Dual HDMI Receiver, Multiformat SDTV/HDTV
Video Decoder, and RGB Graphics Digitizer
Data Sheet
ADV7441A
Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved.
FEATURES
Dual HDMI® 1.3 receiver
HDMI support
Deep color support
xvYCC Enhanced colorimetry
Gamut metadata
225 MHz HDMI receiver
Repeater support
High-bandwidth digital content protection (HDCP 1.3)
S/PDIF (IEC60958-compatible) digital audio output
Multichannel I2S audio output (up to 8 channels)
Adaptive equalizer for cable lengths up to 30 meters
Internal EDID RAM
DVI 1.0
Multiformat decoder
Four 10-bit analog-to-digital converters (ADCs)
ADC sampling rates up to 170 MHz
Mux with 12 analog input channels
SCART fast blank sampling support
NTSC/PAL/SECAM color standards support
525p-/625p-component progressive scan formats support
720p-/1080i-/1080p-component HD formats support
Digitizes RGB graphics from VGA to UXGA rates
(up to 1600 × 1200 at 60 Hz)
VBI data slicer (including teletext)
Analog-to-HDMI fast switching mode
General
Highly flexible output interface
STDI function support standard identification
2 any-to-any, 3 × 3 color-space conversion matrices
Programmable interrupt request output pins
APPLICATIONS
Advanced TVs
PDP HDTVs
LCD TVs (HDTV ready)
LCD/DLP® rear projection HDTVs
CRT HDTVs
LCoS® HDTVs
Audio/video receivers (AVR)
LCD/DLP front projectors
HDTV STBs with PVR
DVD recorders with progressive scan input support
GENERAL DESCRIPTION
The ADV7441A is a high quality multiformat video decoder and
graphics digitizer with an integrated 2:1 multiplexed HDMI receiver.
The ADV7441A contains two main processing sections. The
first section is the standard definition processor (SDP), which
processes all types of PAL, NTSC, and SECAM signals. The second
section is the component processor (CP), which processes YPrPb
and RGB component formats, including RGB graphics. The
CP also processes the video signals from the HDMI receiver. The
ADV7441A can keep the HDCP link between a HDMI source
and the selected HDMI port active in analog mode operation. This
allows for fast switching between the analog and HDMI modes.
As a decoder, the ADV7441A can convert PAL, NTSC, and
SECAM composite or S-Video signals into a digital ITU-R
BT.656 format. It can also decode a component RGB or YPrPb
video signal into a digital YCrCb or RGB pixel output stream.
The ADV7441A supports the 525i, 625i, 525p, 625p, 720p, 1080i,
1080p, and 1250i component video standards, as well as many
other HD and SMPTE standards. SCART and overlay functionality
are enabled by the ability of the ADV7441A to process CVBS
and standard definition RGB signals simultaneously. As a
graphics digitizer, the ADV7441A can digitize RGB graphics
signals from VGA to UXGA rates and convert them to a digital
RGB or YCrCb pixel output stream.
The ADV7441A incorporates a dual-input HDMI-compatible
receiver that supports HDTV formats up to 1080p and display
resolutions up to UXGA. The reception of encrypted video is
possible with the inclusion of HDCP. The inclusion of adaptive
equalization in the HDMI receiver ensures robust operation of the
interface with cable lengths up to 30 meters. The HDMI receiver
has advanced audio functionality, including a mute controller
that prevents audible extraneous noise in the audio output.
To facilitate professional applications, where HDCP processing
and decryption is not required, a derivative part of the ADV7441A
is available. This allows users who are not HDCP adopters to pur-
chase the ADV7441A (see the Ordering Guide section for details).
Fabricated using an advanced CMOS process, the ADV7441A
is available in a space-saving, 144-lead, surface-mount, RoHS-
compliant, plastic LQFP and is specified over the −40°C to
+85°C temperature range.
ADV7441A Data Sheet
Rev. H | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications ..................................................................................... 4
Electrical Characteristics ............................................................. 4
Video Specifications ..................................................................... 6
Analog and HDMI Specifications .............................................. 7
Timing Characteristics ................................................................ 8
Absolute Maximum Ratings .......................................................... 10
Thermal Resistance .................................................................... 10
Package Thermal Performance ................................................. 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Functional Overview ...................................................................... 14
Analog Front End ....................................................................... 14
HDMI Receiver ........................................................................... 14
Standard Definition Processor Pixel Data Output Modes .... 14
Component Processor Pixel Data Output Modes .................. 14
Composite and S-Video Processing ......................................... 14
Component Video Processing .................................................. 15
RGB Graphics Processing ......................................................... 15
General Features ......................................................................... 15
Theory of Operation ...................................................................... 16
Analog Front End ....................................................................... 16
HDMI Receiver ........................................................................... 16
Standard Definition Processor ................................................. 16
Component Processor (CP) ...................................................... 17
VBI Data Processor .................................................................... 17
Pixel Output Formatting................................................................ 18
Register Map Architecture ........................................................ 21
Typical Connection Diagram........................................................ 22
Recommended External Loop Filter Components ................ 23
ADV7441A Evaluation Platform .................................................. 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
2/12—Rev. G to Rev. H
Deleted EVA L -ADV7441AFEZ_2 .................................... Universal
Changes to ADV7441A Evaluation Platform Section ............... 24
5/11—Rev. F to Rev. G
Added Endnote 10 (Table 1) ........................................................... 4
11/10—Rev. E to Rev. F
Changes to Product Title and Features Section ............................ 1
Changes to Analog Front End Section......................................... 14
Changes to Ordering Guide .......................................................... 25
7/09—Rev. D to Rev. E
Change to Pin No. Order for AIN1 to AIN12 Pins (Table 7) .......... 12
4/09—Rev. C to Rev. D
Changes to Package Thermal Performance Section .................. 10
Changes to VBI Data Processor Section ...................................... 17
1/09—Rev. B to Rev. C
Change to Figure 1 ............................................................................ 3
Changes to Static Performance Parameter and Power
Requirements Parameter, Table 1 .................................................... 4
Changes to HDMI Specifications Parameter, Table 3 ................... 7
Change to Maximum Junction Temperature (TJ_MAX), Table 5 ....... 10
Changes to Package Thermal Performance Section .................. 10
Changes to ADV7441A Evaluation Platform Section ............... 24
Changes to Table 13 ....................................................................... 24
Changes to Figure 11 ...................................................................... 24
Changes to Ordering Guide .......................................................... 25
7/08—Revision B: Initial Version
Data Sheet ADV7441A
Rev. H | Page 3 of 28
FUNCTIONAL BLOCK DIAGRAM
RXA_0
ALSB
SDA
SCL
FB
SOG
YC AND
CVBS
YPrPb
RGB
CVBS
SOY
HS_IN/CS_IN
VS_IN
RXA_1
RXA_2
RXA_C
RXB_C
RXB_0
RXB_1
RXB_2
DDCB_SCL
DDCB_SDA
DDCA_SDA
DDCA_SCL MUX
SAMPLER
SAMPLER
PLL
MUX
EQUALIZER EQUALIZER
LLC
GENERATION
ADC 3
CLAMP
SYNC PROCESSING
AND CLOCK
GENERATION
CONTROL
INTERFACE
I2C
CONTROLAND DATA
CONTROL
FILTER
CONTROL
CONTROL
HS/CS, VS
ADC 2
CLAMP
ADC 1
CLAMP
ADC 0
CLAMP
ANALOG INTERFACE 10
10
10
10
DATA RE COVERY
ALIGNMENT
HDMI DE CODE
DE
XOR
VS
HS
4:2:2 TO 4: 4: 4
CONVERSION
EDID/REPEATER
CONTROLLER
HDCP
ENGINE
HDCP
EEPROM
PACKET
PROCESSOR
MUX
INPUT
MATRIX
DATA
PROCESSOR
CHA
CHB
CHC
CHA
CHB
CHC
C Y
CHD
EMBEDDED
SYNC
COLOR-SPACE
CONVERTER
DECIMATION AND
DOWNSAMPLING
FILTERS
PACKET/
INFOFRAME
MEMORY
AUDIO
PROCESSING
LRCLK
SCLK
I2S
SPDIF
MACROVISION
DETECTION STANDARD
AUTODETECTION FREE RUN
OUTPUT CONTROL
VBI DATA
RECOVERY GLOBAL
CONTROL SYNTHESIZED
LLC CONTROL
GAIN
CONTROLCHROMA
RE-
SAMPLE
CHROMA
2D COM B
(0x04 MAX )
CHROMA
FILTER
CHROMA
DEMOD
CHROMA
DIGITAL
FINE
CLAMP
FAS T BL ANK OVERLAY CONT RO L
G
B
R
FB
SYNC
EXTRACT LINE
LENGTH
PREDICTOR
RE-
SAMPLE
CONTROL
AV
CODE
INSERTION
CTI
C-DNR
FSC
RECOVERY
STANDARD DEFINITION P ROCESS OR
OUTPUT FORMATTER
GAIN
CONTROLLUMA
RE-
SAMPLE
LUMA
2D COM B
(0x04 MAX )
LUMA
FILTER
LUMA
DIGITAL
FINE
CLAMP
10
10
10
PIXEL
DATA
P10 TO P19
INT1
HS/CS
VS/FIELD
DE/FIELD
LLC
SFL/
SYNC_OUT/
INT2
P20 TO P29
P0 TO P9
DIGITAL PROCE S S ING BLOCK
COMPONENT PROCESSOR
SYNC S OURCE
AND
POLARITY DETECT
PROGRAM
DELAY
NOISE AND
CALIBRATION ACTIVE PEAK AND
HSYNC DE P TH
GAIN
CONTROL
DIGITIAL
FINE
CLAMP
MACROVISION AND
CGMS DETECTION
OFFSET
ADDER
AV
CODE
INSERTION
STANDARD
IDENTIFICATION
SYNC E X TRACT
VBI
DECODER ANCILLARY
DATA
FORMATTER
ANCILLARY
DATA
VBI DATA PROCESSOR
06914-001
MCLKOUT
MDA
MCL
Figure 1.
ADV7441A Data Sheet
Rev. H | Page 4 of 28
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V,
CVDD = 1.71 V to 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter1 Symbol Test Conditions Min Typ Max Unit
STATIC PERFORMANCE2
Resolution (Each ADC) N 10 Bits
Integral Nonlinearity INL BSL 27 MHz (@ a 10-bit level) −0.5/+2 LSB
BSL 54 MHz (@ a 10-bit level) −0.5/+2 LSB
BSL 74 MHz (@ a 10-bit level) −0.5/+1.5 LSB
BSL 110 MHz (@ a 10-bit level) −0.7/+2 LSB
BSL 170 MHz (@ an 8-bit level) −0.25/+0.5 LSB
Differential Nonlinearity DNL At 27 MHz (@ a 10-bit level) −0.5/+0.5 LSB
At 54 MHz (@ a 10-bit level) ±0.5 LSB
At 74 MHz (@ a 10-bit level) ±0.5 LSB
At 110 MHz (@ a 10-bit level) ±0.5 LSB
At 170 MHz (@ an 8-bit level) −0.25/+0.2 LSB
DIGITAL INPUTS
Input High Voltage 3 VIH 2 V
HS_IN/CS_IN, VS_IN low trigger mode 0.7 V
Input Low Voltage3 VIL 0.8 V
HS_IN/CS_IN, VS_IN low trigger mode 0.3 V
Input Current IIN Pin 21 (RESET) −60 +60 µA
All input pins other than Pin 21 −10 +10 µA
Input Capacitance4 CIN 10 pF
DIGITAL OUTPUTS
Output High Voltage5 VOH ISOURCE = 0.4 mA 2.4 V
Output Low Voltage5 VOL ISINK = 3.2 mA 0.4 V
High Impedance Leakage Current ILEAK 10 µA
Output Capacitance4 COUT 20 pF
POWER REQUIREMENTS4
Digital Core Power Supply DVDD 1.62 1.8 1.98 V
Digital I/O Power Supply
DVDDIO
2.97
3.3
3.63
V
PLL Power Supply PVDD 1.71 1.8 1.89 V
Analog Power Supply AVDD 1.71 1.8 1.89 V
Terminator Power Supply TVDD 3.135 3.3 3.465 V
Comparator Power Supply CVDD 1.71 1.8 1.89 V
Digital Core Supply Current IDVDD CVBS input sampling @ 54 MHz6, 7 140 198 mA
Graphics RGB sampling @ 108 MHz6, 7 141 290 mA
SCART RGB fast blank sampling @ 54 MHz6, 7 152 218 mA
YPrPb 1080p sampling @ 148.5 MHz6, 7 203 305 mA
HDMI RGB sampling @ 165 MHz7, 8, 9 242 358 mA
HDMI RGB sampling @ 225 MHz7, 8, 9 242 414 mA
Digital I/O Supply Current IDVDDIO CVBS input sampling @ 54 MHz6, 7 16 48 mA
Graphics RGB sampling @ 108 MHz6, 7 17 80 mA
SCART RGB fast blank sampling @ 54 MHz6, 7 16 50 mA
YPrPb 1080p sampling @ 148.5 MHz6, 7 42 136 mA
HDMI RGB sampling @ 165 MHz7, 8, 9 17 192 mA
HDMI RGB sampling @ 225 MHz7, 8, 9, 10 20 151 mA
Data Sheet ADV7441A
Rev. H | Page 5 of 28
Parameter1 Symbol Test Conditions Min Typ Max Unit
HDMI Comparators ICVDD CVBS input sampling @ 54 MHz6, 7 56 83 mA
TMDS PLL and Equalizer Graphics RGB sampling @ 108 MHz6, 7 56 83 mA
Supply Current SCART RGB fast blank sampling @ 54 MHz6, 7 56 83 mA
YPrPb 1080p sampling @ 148.5 MHz6, 7 56 83 mA
7, 8, 9
86
111
mA
HDMI RGB sampling @ 225 MHz7, 8, 9 95 125 mA
Analog Supply Current11 IAVDD CVBS input sampling @ 54 MHz6, 7 63 115 mA
Graphics RGB sampling @ 108 MHz6, 7 174 312 mA
SCART RGB fast blank sampling @ 54 MHz6, 7 225 388 mA
YPrPb 1080p sampling @ 148.5 MHz6, 7 180 318 mA
HDMI RGB sampling @ 165 MHz7, 8, 9 0 2 mA
HDMI RGB sampling @ 225 MHz7, 8, 9 0 2 mA
Terminator Supply Current ITVDD CVBS input sampling @ 54 MHz6, 7 12 20 mA
Graphics RGB sampling @ 108 MHz6, 7 12 20 mA
SCART RGB fast blank sampling @ 54 MHz6, 7 12 20 mA
YPrPb 1080p sampling @ 148.5 MHz6, 7 12 20 mA
HDMI RGB sampling @ 165 MHz7, 8, 9, 12 42 97 mA
HDMI RGB sampling @ 225 MHz7, 8, 9, 12 63 100 mA
Audio and Video PLL Supply Current IPVDD CVBS input sampling @ 54 MHz6, 7 18 24 mA
Graphics RGB sampling @ 108 MHz6, 7 14 22 mA
SCART RGB fast blank sampling @ 54 MHz6, 7 17 24 mA
6, 7
19
25
mA
HDMI RGB sampling @ 165 MHz7, 8, 9 10 20 mA
HDMI RGB sampling @ 225 MHz7, 8, 9 15 21 mA
Power-Down Current IPWRDN 11.6 mA
Power-Up Time tPWRUP 25 ms
1 The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range (TMIN to TMAX).
2 All ADC linearity tests were performed at input range full scale − 12.5% and at zero scale + 12.5%.
3 Pin 1, Pin 105, Pin 106, and Pin 144 are 5 V tolerant.
4 Guaranteed by characterization.
5 The VOH and VOL levels were obtained using the default drive strength value (0x15) in User Map Register 0xF4.
6 Current measurements for analog inputs were made with HDMI/analog simultaneous mode disabled (User Map Register 0xBA, Bit 7, programmed with Value 0) and
with no HDMI sources connected to the part.
7 Typical current measurements were taken with nominal voltage supply levels and an SMPTE bar video pattern input. Maximum current measurements were taken
with maximum rating voltage supply levels and a MoiréX video pattern input.
8 Current measurements for HDMI inputs were made with a source connected to the active HDMI port and with no source connected to the inactive HDMI port.
9 Audio stream is an uncompressed stereo audio sampling frequency of fS = 48 kHz, and MCLKOUT = 256 fS.
10 The maximum IDVDDIO value for the HDMI RGB sampling @ 225 MHz appears lower than expected. This is due to the 1080p 12-bit deep color mode input used during
evaluation. In this mode, the input HDMI TMDS clock has a frequency of 222.75 MHz; however, the output pixel clock is stepped down to 148.5 MHz to account for the
extra bits of data. DVDDIO power is proportional to the output pixel clock, therefore the stepping down of the output pixel clock data in 1080p 12-bit deep color
mode results in lower than expected IDVDDIO.
11 Analog current measurements for CVBS were made with only ADC0 powered up; for RGB, with only ADC0, ADC1, and ADC2 powered up; for SCART FB, with all ADCs
powered up; and for HDMI mode, with all ADCs powered off.
12 The terminator supply current may vary with the HDMI source in use.
ADV7441A Data Sheet
Rev. H | Page 6 of 28
VIDEO SPECIFICATIONS
AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V,
CVDD = 1.71 V to 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter1, 2 Symbol Test Conditions Min Typ Max Unit
NONLINEAR SPECIFICATIONS
Differential Phase DP CVBS input, modulated in five steps 0.3 Degrees
Differential Gain DG CVBS input, modulated in five steps 0.6 %
Luma Nonlinearity LNL CVBS input, five steps 0.8 %
NOISE SPECIFICATIONS
SNR Unweighted Luma ramp 61.8 dB
Luma flat field 63.1 dB
Analog Front-End Crosstalk 60 dB
LOCK TIME SPECIFICATIONS
Horizontal Lock Range −5 +5 %
Vertical Lock Range 40 70 Hz
FSC Subcarrier Lock Range ±1.3 kHz
Color Lock-In Time 60 Lines
Synchronization Depth Range3 20 200 %
Color Burst Range 5 200 %
Vertical Lock Time 2 Fields
Horizontal Lock Time 100 Lines
CHROMA SPECIFICATIONS
Hue Accuracy HUE 1 Degrees
Color Saturation Accuracy CL_AC 1 %
Color AGC Range 5 400 %
Chroma Amplitude Error 0.5 %
Chroma Phase Error
0.1
Degrees
Chroma Luma Intermodulation 0.3 %
LUMA SPECIFICATIONS
Luma Brightness Accuracy CVBS, 0.5 V input 1 %
Luma Contrast Accuracy CVBS, 0.5 V input 1 %
1 The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range (TMIN to TMAX).
2 Guaranteed by characterization.
3 Nominal synchronization depth is 300 mV at 100% of the synchronization depth range.
Data Sheet ADV7441A
Rev. H | Page 7 of 28
ANALOG AND HDMI SPECIFICATIONS
AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V,
CVDD = 1.71 V to 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted.
Table 3.
Parameter1, 2 Test Conditions Min Typ Max Unit
CLAMP CIRCUITRY
External Clamp Capacitor 0.1 µF
Input Impedance (Except Pin 74) Clamps switched off 10 MΩ
Input Impedance of Pin 74 20 kΩ
Common-Mode Level (CML)
0.88
V
ADC Full-Scale Level CML + 0.5 V
ADC Zero-Scale Level CML − 0.5 V
ADC Dynamic Range 1 V
Clamp Level (When Locked) CVBS input CML – 0.122 V
SCART RGB input (R, G, B signals) CML – 0.167 V
S-Video input (Y signal) CML– 0.122 V
S-Video input (C signal) CML V
Component input (Y signal) CML − 0.120 V
Component input (Pr signal) CML V
Component input (Pb signal) CML V
PC RGB input (R, G, B signals) CML − 0.120 V
Large Clamp Source Current SDP only 8 mA
Large Clamp Sink Current SDP only 8 mA
Fine Clamp Source Current SDP only 0.25 µA
Fine Clamp Sink Current SDP only 0.4 µA
HDMI SPECIFICATIONS3
Intrapair (Positive-to-Negative) Differential
Input Skew4, 5
0.4 tbit
Channel-to-Channel Differential Input Skew5, 6 0.2 tpixel + 1.78 ns
1 The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range (TMIN to TMAX).
2 Guaranteed by characterization.
3 Guaranteed by design.
4 tbit is 1/10 the pixel period tpixel.
5 The unit of measurement depends on the video applied and the TMDS clock frequency.
6 tpixel is the period of the TMDS clock.
ADV7441A Data Sheet
Rev. H | Page 8 of 28
TIMING CHARACTERISTICS
AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V,
CVDD = 1.71 V to 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted.
Table 4.
Parameter1, 2 Symbol Test Conditions Min Typ Max Unit
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency 28.6363 MHz
Crystal Frequency Stability ±50 ppm
Horizontal Sync Input Frequency 14.8 110 kHz
LLC Frequency Range 12.825 170 MHz
I2C PORTS (FAST MODE)3
xCL Frequency4 400 kHz
xCL Minimum Pulse Width High4 t1 0.6 µs
xCL Minimum Pulse Width Low4 t2 1.3 µs
Hold Time (Start Condition) t3 0.6 µs
Setup Time (Start Condition) t4 0.6 µs
xDA Setup Time4 t5 100 ns
xCL and xDA Rise Times4 t6 300 ns
xCL and xDA Fall Times4 t7 300 ns
Setup Time for Stop Condition t8 0.6 µs
I2C PORTS (NORMAL MODE)3
xCL Frequency4 100 kHz
xCL Minimum Pulse Width High4 t1 4 µs
xCL Minimum Pulse Width Low4 t2 4.7 µs
Hold Time (Start Condition) t3 4 µs
Setup Time (Start Condition) t4 4.7 µs
xDA Setup Time4 t5 250 ns
xCL and xDA Rise Times4 t6 1000 ns
xCL and xDA Fall Times4 t7 300 ns
Setup Time for Stop Condition t8 4 µs
RESET FEATURE
Reset Pulse Width 5 ms
CLOCK OUTPUTS
LLC Mark-Space Ratio t9:t10 45:55 55:45 % duty cycle
DATA AND CONTROL OUTPUTS
Data Output Transition Time SDR (SDP)5 t11 Negative clock edge to start of valid data 3.4 ns
t12 End of valid data to negative clock edge 2.4 ns
Data Output Transition Time SDR (CP)6 t13 End of valid data to negative clock edge 2 ns
t14 Negative clock edge to start of valid data 0.5 ns
I2S PORT (MASTER MODE)
SCLK Mark-Space Ratio t15:t16 45:55 55:45 % duty cycle
LRCLK Data Transition Time t17 End of valid data to negative SCLK edge 10 ns
t18 Negative SCLK edge to start of valid data 10 ns
I2Sx Data Transition Time7 t19 End of valid data to negative SCLK edge 5 ns
t20 Negative SCLK edge to start of valid data 5 ns
MCLKOUT Frequency 4.096 24.576 MHz
1 The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range (TMIN to TMAX).
2 Guaranteed by characterization.
3 Refers to all I2C pins (DDC and control port).
4 The prefix x refers to pin names beginning with S, DDCA_S, and DDCB_S.
5 SDP timing figures were obtained using the default drive strength value (0x15) in User Map Register 0xF4.
6 CP timing figures were obtained using the maximum drive strength value (0x3F) in User Map Register 0xF4.
7 The suffix x refers to pin names ending with 0, 1, 2, and 3.
Data Sheet ADV7441A
Rev. H | Page 9 of 28
Timing Diagrams
xDA
xCL
t
5
t
3
t
4
t
8
t
6
t
7
t
2
t
1
t
3
NOTES
1. THE PRE FIX x RE FERS TO P IN NAMES BE GINNING WITH S, DDCA_S , AND DDCB_S.
06914-002
Figure 2. I2C Timing
LLC
P0 TO P29, VS,
HS, DE/FIELD,
SFL/SYNC_OUT
t
9
t
11
t
12
t
10
06914-003
Figure 3. Pixel Port and Control SDR Output Timing (SDP Core)
t
9
LLC
P0 TO P29, VS,
HS, DE/FIELD
t
13
t
14
t
10
06914-004
Figure 4. Pixel Port and Control SDR Output Timing (CP Core)
SCLK
LRCLK
I2Sx
LEFT-JUSTIFIED
MODE
I2Sx
RIGHT-JUSTIFIED
MODE
I2Sx
I2S MODE
MSB MSB – 1
t15
t16
t17
t19
t20
t18
MSB MSB – 1
LSBMSB
t19
t20 t19
t20
NOTES
1. THE SUFFIX x REFERS TO P IN NAMES E NDING WITH 0, 1, 2, AND 3.
06914-007
Figure 5. I2S Timing
ADV7441A Data Sheet
Rev. H | Page 10 of 28
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
AVDD to AGND 2.2 V
DVDD to DGND 2.2 V
PVDD to PGND 2.2 V
DVDDIO to DGND 4 V
CVDD to CGND 2.2 V
TVDD to TGND 4 V
DVDDIO to AVDD −0.3 V to +3.6 V
DVDDIO to TVDD
−3.6 V to +3.6 V
DVDDIO to DVDD −2 V to +2 V
CVDD to DVDD −2 V to +0.3 V
PVDD to DVDD −2 V to +0.3 V
AVDD to CVDD −2 V to +2 V
AVDD to PVDD
−2 V to +2 V
AVDD to DVDD −2 V to +0.3 V
AVDD to TVDD −3.6 V to +0.3 V
TVDD to DVDD −2 V to +2 V
Digital Inputs
Voltage to DGND DGND − 0.3 V to DVDDIO + 0.3 V
Digital Outputs
Voltage to DGND DGND − 0.3 V to DVDDIO + 0.3 V
Analog Inputs
Voltage to AGND AGND − 0.3 V to AVDD + 0.3 V
Maximum Junction
Temperature (TJ_MAX)
119°C
Storage Temperature Range −65°C to +150°C
Infrared Reflow,
Soldering (20 sec)
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 6.
Package Type ΨJT1 Unit
144-Lead LQFP (ST-144) 1.62 °C/W
1 Junction-to-package surface thermal resistance.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption during ADV7441A operation,
turn off unused ADCs.
On a 4-layer PCB that includes a solid ground plane, the value
of θJA is 25.3°C/W. However, due to variations within the PCB
metal and, therefore, variations in PCB heat conductivity, the
value of θJA may differ for various PCBs.
The most efficient measurement technique is to use the surface
temperature of the package to estimate the die temperature
because it is not affected by the variance associated with the
value of θJA.
The maximum junction temperature (TJ_MAX) of 119°C must not
be exceeded. The following equation calculates the junction
temperature using the measured surface temperature of the
package and applies only when no heat sink is used on the
device under test:
TJ_MAX = TS + (ΨJT × WTOTAL)
where:
TS is the surface temperature of the package expressed in degrees
Celsius.
ΨJT is the junction-to-package surface thermal resistance.
WTOTAL = {(AV D D × IAV D D ) + (DVDD × IDVDD) + (DVDDIO ×
IDVDDIO) + (PVDD × IPVDD) + (CVDD × ICVDD) + (TVDD × ITVDD)}.
The ADV7441A can be operated in ambient temperatures of
up to +85°C. However, in video modes where highest power
is consumed and there is higher than nominal power supply
voltages and worst-case video data, operation at these ambient
temperatures may cause the junction temperature to exceed its
maximum allowed value (119°C). One way to avoid this is to
restrict the ambient temperature to be below +79°C. However, even
if the ambient temperature is kept below +79°C, the user still needs
to observe the thermally efficient PCB design recommendations
outlined in this section to ensure that the maximum allowed
junction temperature is not exceeded in any video mode.
Contact an Analog Devices, Inc., sales representative or a field
applications engineer (FAE) for more information on package
thermal performance.
ESD CAUTION
Data Sheet ADV7441A
Rev. H | Page 11 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
1
DDCB_SDA
2
SPDIF
3
I2S0
4
I2S1
5
I2S2
6
I2S3
7
LRCLK
8
SCLK
9
MCLKOUT
10
EXT_CLAMP
11
SDA
12
SCL
13
ALSB
14
DGND
15
DVDDIO
16
DE/FIELD
17
HS/CS
18
VS/FIELD
19
INT1
20
SFL/SYNC_OUT/INT2
21
RESET
22
DGND
23
DVDD
24
P0
25
P1
26
P2
27
P3
28
P4
29
P5
30
P6
31
P7
32
P8
33
P9
34
DGND
35
DVDDIO
36
P10
73
TEST0
74
FB
75
SOG
76
AIN7
77
AIN1
78
AIN8
79
AIN2
80
AIN9
81
AIN3
82
AGND
83
AGND
84
AVDD
85
REFOUT
86
CML
87
AGND
88
AVDD
89
TEST2
90
REFN
91
TEST3
92
REFP
93
AIN10
94
AIN4
95
AIN11
96
AIN5
97
SOY
98
AIN12
99
AIN6
100
PGND
101
PVDD
102
AUDIO_ELPF
103
CGND
104
CVDD
105
DDCA_SCL
106
DDCA_SDA
107
TEST4
108
TEST5
109
CVDD
110
CGND
111
TVDD
112
RXA_CN
113
RXA_CP
114
TGND
115
RXA_0N
116
RXA_0P
117
TGND
118
RXA_1N
119
RXA_1P
120
TGND
121
RXA_2N
122
RXA_2P
123
TVDD
124
RTERM
125
CVDD
126
CGND
127
TVDD
128
RXB_CN
129
RXB_CP
130
TGND
131
RXB_0N
132
RXB_0P
133
TGND
134
RXB_1N
135
RXB_1P
136
TGND
137
RXB_2N
138
RXB_2P
139
TVDD
140
CGND
141
CVDD
142
DVDD
143
DGND
144
DDCB_SCL
37
P11
38
P12
39
P13
40
P14
41
P15
42
P16
43
P17
44
P18
45
P19
46
P20
47
P21
48
EXT_CLK
49
DGND
50
DVDDIO
51
LLC
52
P22
53
P23
54
P24
55
P25
56
DGND
57
DVDD
58
P26
59
P27
60
P28
61
P29
62
VS_IN
63
HS_IN/CS_IN
64
DGND
65
XTAL1
66
XTAL
67
DVDDIO
68
PVDD
69
PGND
70
ELPF
71
PVDD
72
PGND
ADV7441A
TOP VI EW
(No t t o Scal e)
06914-005
Figure 6. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
14, 22, 34, 49, 56,
64, 143
DGND G Digital Ground.
82, 83, 87 AGND G Analog Ground.
69, 72, 100 PGND G PLL Ground.
103, 110, 126, 140 CGND G Comparator Ground.
114, 117, 120,
130, 133, 136
TGND G Terminator Ground.
15, 35, 50, 67 DVDDIO P Digital I/O Supply Voltage (3.3 V).
23, 57, 142 DVDD P Digital Core Supply Voltage (1.8 V).
84, 88 AVDD P Analog Supply Voltage (1.8 V).
68, 71, 101 PVDD P Audio and Video PLL Supply Voltage (1.8 V).
104, 109, 125, 141 CVDD P HDMI Comparator, TMDS PLL, and Equalizer Supply Voltage (1.8 V).
111, 123, 127, 139 TVDD P Terminator Supply Voltage (3.3 V).
74 FB I Fast Blank. Fast switch overlay between CVBS and RGB analog signals.
73, 91, 108 TEST0, TEST3, TEST5 I Test Pins. Do not connect.
89 TEST2 O Test Pin. Do not connect.
ADV7441A Data Sheet
Rev. H | Page 12 of 28
Pin No. Mnemonic Type1 Description
107 TEST4 I/O Test Pin. Do not connect.
77, 79, 81, 94, 96,
99, 76, 78, 80, 93,
95, 98
AIN1 to AIN12 I Analog Video Input Channels.
24 to 33, 36 to 47,
52 to 55, 58 to 61
P0 to P29
O
Video Pixel Output Port.
19 INT1 O Interrupt Signal. Can be active low or active high. The set of events that triggers an
interrupt is under user control.
20 SFL/SYNC_OUT/INT2 O Subcarrier Frequency Lock (SFL). Contains a serial output stream that can be used to
lock the subcarrier frequency when this decoder is connected to any Analog Devices
digital video encoder.
Sliced Synchronization Output Signal (SYNC_OUT). Available only in CP mode.
Interrupt Signal (INT2).
17 HS/CS O Horizontal Synchronization Output Signal (HS). Output by the SDP and CP.
Composite Synchronization (CS). A single signal containing both horizontal and
vertical synchronization pulses.
18 VS/FIELD O Vertical Synchronization Output Signal (VS). Output by the SDP and CP.
Field Synchronization Output Signal (FIELD). Field synchronization output signal in all
interlaced video modes.
16 DE/FIELD O Data Enable Signal (DE). Indicates active pixel data.
Field Synchronization Output Signal (FIELD). Field synchronization output signal in all
interlaced video modes.
11 SDA I/O I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
12 SCL I I2C Port Serial Clock Input. (Maximum clock rate of 400 kHz.) SCL is the clock line for
the control port.
13 ALSB I This pin sets the second LSB of the slave address for each ADV7441A register map.
21 RESET I System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required
to reset the ADV7441A circuitry.
51 LLC O Line-Locked Output Clock for Pixel Data. Range is 13.5 MHz to 170 MHz.
65 XTAL1 O This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an
external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7441A. In
crystal mode, the crystal must be a fundamental crystal.
66
XTAL
I
Input Pin for the 28.63636 MHz Crystal. This pin can be overdriven by an external 3.3 V
28.63636 MHz clock oscillator source to clock the ADV7441A.
70 ELPF O The recommended external loop filter must be connected to this ELPF pin.
102 AUDIO_ELPF O The recommended external loop filter must be connected to this AUDIO_ELPF pin.
85 REFOUT O Internal Voltage Reference Output.
86 CML O Common-Mode Level for the Internal ADCs.
90
REFN
O
Internal Voltage Reference Output.
92 REFP O Internal Voltage Reference Output.
63 HS_IN/CS_IN I HS Input Signal. Used in analog mode for 5-wire timing mode.
CS Input Signal. Used in analog mode for 4-wire timing mode.
For optimal performance, a 100 Ω series resistor is recommended on the
HS_IN/CS_IN pin.
62 VS_IN I VS Input Signal. Used in analog mode for 5-wire timing mode. For optimal performance,
a 100 Ω series resistor is recommended on the VS_IN pin.
75 SOG I Synchronization-on-Green Input. This pin is used in embedded synchronization mode.
97 SOY I Synchronization-on-Luma Input. This pin is used in embedded synchronization mode.
112 RXA_CN I Digital Input Clock Complement of Port A in the HDMI Interface.
113
RXA_CP
I
Digital Input Clock True of Port A in the HDMI Interface.
115 RXA_0N I Digital Input Channel 0 Complement of Port A in the HDMI Interface.
116 RXA_0P I Digital Input Channel 0 True of Port A in the HDMI Interface.
118 RXA_1N I Digital Input Channel 1 Complement of Port A in the HDMI Interface.
119 RXA_1P I Digital Input Channel 1 True of Port A in the HDMI Interface.
121 RXA_2N I Digital Input Channel 2 Complement of Port A in the HDMI Interface.
122 RXA_2P I Digital Input Channel 2 True of Port A in the HDMI Interface.
Data Sheet ADV7441A
Rev. H | Page 13 of 28
Pin No. Mnemonic Type1 Description
128 RXB_CN I Digital Input Clock Complement of Port B in the HDMI Interface.
129 RXB_CP I Digital Input Clock True of Port B in the HDMI Interface.
131 RXB_0N I Digital Input Channel 0 Complement of Port B in the HDMI Interface.
132 RXB_0P I Digital Input Channel 0 True of Port B in the HDMI Interface.
134
RXB_1N
I
Digital Input Channel 1 Complement of Port B in the HDMI Interface.
135 RXB_1P I Digital Input Channel 1 True of Port B in the HDMI Interface.
137 RXB_2N I Digital Input Channel 2 Complement of Port B in the HDMI Interface.
138 RXB_2P I Digital Input Channel 2 True of Port B in the HDMI Interface.
106 DDCA_SDA I/O HDCP Slave Serial Data Port A.
1 DDCB_SDA I/O HDCP Slave Serial Data Port B.
105 DDCA_SCL I HDCP Slave Serial Clock Port A.
144 DDCB_SCL I HDCP Slave Serial Clock Port B.
2 SPDIF O SPDIF Digital Audio Output.
3 I2S0 O I2S Audio for Channel 1 and Channel 2.
4 I2S1 O I2S Audio for Channel 3 and Channel 4.
5 I2S2 O I2S Audio for Channel 5 and Channel 6.
6 I2S3 O I2S Audio for Channel 7 and Channel 8.
7 LRCLK O Data Output Clock for Left and Right Audio Channels.
8 SCLK O Audio Serial Clock Output.
9 MCLKOUT O Audio Master Clock Output.
10 EXT_CLAMP I External Clamp Signal Input for External Clock and Clamp Mode. This is an optional
mode of operation for the ADV7441A.
48 EXT_CLK I Clock Input for External Clock and Clamp Mode. This is an optional mode of operation
for the ADV7441A.
124 RTERM I Sets internal termination resistance. Connect this pin to TGND using a 500 Ω resistor.
1 G = ground, P = power, I = input, O = output.
ADV7441A Data Sheet
Rev. H | Page 14 of 28
FUNCTIONAL OVERVIEW
The following overview provides a brief description of the
functionality of the ADV7441A. More details are available in
the Theory of Operation section.
ANALOG FRONT END
The analog front end of the ADV7441A provides four high quality
10-bit ADCs to enable 10-bit video decoding, a multiplexer with
12 analog input channels to enable multisource connection
without the requirement of an external multiplexer, and four
current and voltage clamp control loops to ensure that dc offsets
are removed from the video signal. SCART functionality and
standard definition RGB overlay with CVBS are controlled by
the FB input.
HDMI RECEIVER
The ADV7441A is compatible with the HDMI specification.
The ADV7441A supports all HDTV formats up to 1080p and
all display resolutions up to UXGA (1600 × 1200 at 60 Hz).
The device includes the following features:
• Adaptive front-end equalization for HDMI operation with
cable lengths up to 30 meters
• Synchronization conditioning for higher performance in
strenuous conditions
• Audio mute for removing extraneous noise
• Programmable data island packet interrupt generator
STANDARD DEFINITION PROCESSOR PIXEL DATA
OUTPUT MODES
The ADV7441A features the following SDP output modes:
• 8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time
codes and/or HS, VS, and FIELD
• 16-/20-bit YCrCb 4:2:2 with embedded time codes and/or
HS, VS, and FIELD
• 24-/30-bit YCrCb 4:4:4 with embedded time codes and/or
HS, VS, and FIELD
COMPONENT PROCESSOR PIXEL DATA OUTPUT
MODES
The ADV7441A features single data rate outputs as follows:
• 8-/10-bit 4:2:2 YCrCb for 525i and 625i
• 16-/20-bit 4:2:2 YCrCb for all standards
• 24-/30-bit 4:4:4 YCrCb/RGB for all standards
COMPOSITE AND S-VIDEO PROCESSING
The ADV7441A supports NTSC (M/J/4.43), PAL (B/D/I/G/H/
M/N/Nc/60), and SECAM (B/D/G/K/L) standards for CVBS
and S-Video formats. Superadaptive 2D, 5-line comb filters for
NTSC and PAL provide superior chrominance and luminance
separation for composite video.
The composite and S-Video processing functionalities also
include fully automatic detection of switching among
worldwide standards (PAL/NTSC/SECAM); automatic gain
control (AGC) with white peak mode to ensure that the video
is processed without compromising the video processing range;
Adaptive Digital Line Length Tracking (ADLLT™); and proprietary
architecture for locking to weak, noisy, and unstable sources
from VCRs and tuners. The IF filter block compensates for high
frequency luma attenuation due to the tuner SAW filter.
The ADV7441A also features chroma transient improvement
(CTI) and luminance digital noise reduction (DNR), as well as
teletext, closed captioning (CC), extended data service (EDS), and
wide-screen signaling (WSS). It offers certified Macrovision® copy
protection detection on composite and S-Video for all worldwide
formats (PAL/NTSC/SECAM), and a copy generation management
system (CGMS). Other features include 4× oversampling (54 MHz)
for CVBS, S-Video, and YUV modes; line-locked clock output
(LLC); vertical interval time codes (VITC); support for letterbox
detection; a free-run output mode for stable timing when no
video input is present; clocking from a single 28.63636 MHz
crystal; and subcarrier frequency lock (SFL) output for downstream
video encoders.
In addition, the device has color controls for hue, brightness,
saturation, and contrast and controls for Cr and Cb offsets. The
ADV7441A also incorporates a vertical blanking interval data
processor and a video programming system (VPS) on the device.
The differential gain of the ADV7441A is 0.6% typical, and the
differential phase is 0.3° typical.
Data Sheet ADV7441A
Rev. H | Page 15 of 28
COMPONENT VIDEO PROCESSING
The ADV7441A supports 525i, 625i, 525p, 625p, 720p, 1080i,
1080p, and many other HDTV formats. It provides automatic
adjustments for gain (contrast) and offset (brightness), as well
as manual adjustment controls. Furthermore, the ADV7441A
not only supports analog component YPrPb/RGB video formats
with embedded synchronization or with separate HS, VS, and CS,
but also supports YCrCb-to-RGB and RGB-to-YCrCb conversions
by any-to-any, 3 × 3 color-space conversion matrices.
In addition, the ADV7441A features brightness, saturation, and
hue controls. Standard identification (STDI) enables detection
of the component format at the system level, and a synchroniza-
tion source polarity detector (SSPD) determines the source and
polarity of the synchronization signals that accompany the
input video.
Certified Macrovision copy protection detection is available on
component formats (525i, 625i, 525p, and 625p).
When no video input is present, free-run output mode provides
stable timing.
The ADV7441A supports user-defined pixel sampling for
nonstandard video sources and arbitrary pixel sampling
for nonstandard video sources.
RGB GRAPHICS PROCESSING
The ADV7441A provides 170 MSPS conversion rate support of
RGB input resolutions up to 1600 × 1200 at 60 Hz (UXGA) and
automatic or manual clamp and gain controls for graphics models.
The RGB graphics processing functionality features contrast
and brightness controls, automatic detection of synchronization
source and polarity by the SSPD block, standard identification
enabled by the STDI block, and user-defined pixel sampling
support for nonstandard video sources.
Additional RGB graphics processing features of the ADV7441A
include the following:
• Sampling PLL clock with 500 ps p-p jitter at 170 MSPS.
• 32-phase DLL support of optimum pixel clock sampling.
• Color-space conversion of RGB to YCrCb and decimation
to a 4:2:2 format for videocentric back-end IC interfacing.
• Data enable (DE) output signal supplied for direct
connection to the HDMI/DVI transmitter IC.
GENERAL FEATURES
The ADV7441A features HS, VS, and FIELD output signals with
programmable position, polarity, and width. It also includes
programmable interrupt request output pins, INT1 and INT2.
The part offers low power consumption—1.8 V digital core,
1.8 V analog, and 3.3 V digital input/output—and a low power
power-down mode.
The ADV7441A operates over a temperature range of −40°C
to +85°C and is available in a 144-lead, 20 mm × 20 mm, RoHS-
compliant LQFP.
ADV7441A Data Sheet
Rev. H | Page 16 of 28
THEORY OF OPERATION
ANALOG FRONT END
The ADV7441A analog front end comprises four 10-bit ADCs that
digitize the analog video signal before applying it to the SDP or CP.
The analog front end uses differential channels connected to each
ADC to ensure high performance in mixed-signal applications.
The analog front end also includes a 12-channel input mux that
enables multiple video signals to be applied to the ADV7441A.
Current and voltage clamps are positioned in front of each ADC
to ensure that the video signal remains within the range of the
converter. Fine clamping of the video signals is performed
downstream by digital fine clamping in either the CP or SDP.
The ADCs are configured to run in 4× oversampling mode
when decoding composite and S-Video inputs. For component
525i, 625i, 525p, and 625p sources, 2× oversampling is performed,
but 4× oversampling is available for component 525i and 625i.
All other video standards are 1× oversampled. Oversampling
the video signals reduces the cost and complexity of external
antialiasing (AA) filters, with the additional benefit of
increasing the signal-to-noise ratio (SNR).
The ADV7441A supports simultaneous processing of CVBS and
RGB standard definition signals to enable SCART compatibility
and overlay functionality. A combination of CVBS and RGB inputs
can be mixed and output, as controlled by the I2C registers and
the FB pin.
HDMI RECEIVER
The HDMI receiver on the ADV7441A incorporates active
equalization of the HDMI data signals. This equalization compen-
sates for the high frequency losses inherent in HDMI and DVI
cables, especially those with long lengths and high frequencies.
Because the ADV7441A can provide equalization compensation
for cable lengths up to 30 meters, it is capable of achieving robust
receiver performance at even the highest HDMI data rates.
With the inclusion of HDCP, displays can receive encrypted
video content. The HDMI interface of the ADV7441A allows
for authentication of a video receiver, decryption of encoded
data at the receiver, and renewability of that authentication
during transmission as specified by the HDCP 1.3 protocol.
The HDMI receiver also offers advanced audio functionality.
The receiver contains an audio mute controller that can detect
a variety of selectable conditions that may result in audible
extraneous noise in the audio output. Upon detection of these
conditions, the audio data can be ramped to prevent audio
clicks and pops.
STANDARD DEFINITION PROCESSOR
The SDP section is capable of decoding a large selection of
baseband video signals in composite, S-Video, and YUV
formats. The video standards supported by the SDP include
PAL (B/D/I/G/H/60/M/N/Nc), NTSC (M/J/4.43), and SECAM
(B/D/G/K/L). The ADV7441A automatically detects the video
standard and processes it accordingly. The SDP has a five-line,
superadaptive, 2D comb filter that provides superior chrominance
and luminance separation when decoding a composite video signal.
This highly adaptive filter automatically adjusts its processing
mode according to the video standard and signal quality
without requiring user intervention. The SDP has an IF filter
block that compensates for attenuation in the high frequency
luma spectrum due to a tuner SAW filter.
The SDP has specific luminance and chrominance parameter
control for brightness, contrast, saturation, and hue.
The ADV7441A implements the patented ADLLT algorithm
to track varying video line lengths from sources such as VCRs.
ADLLT enables the ADV7441A to track and decode poor
quality video sources, such as VCRs, and noisy sources, such
as tuner outputs, VCD players, and camcorders. The SDP also
contains a CTI processor. This processor increases the edge rate
on chroma transitions, resulting in a sharper video image.
The SDP can process a variety of VBI data services, such as
teletext, closed captioning (CC), wide-screen signaling (WSS), a
video programming system (VPS), vertical interval time codes
(VITC), a copy generation management system (CGMS), and
an extended data service (XDS). The ADV7441A SDP section has
a Macrovision 7.1 detection circuit that allows it to detect Type I,
Type II, and Type III protection levels. The decoder is fully robust
to all Macrovision signal inputs.
Data Sheet ADV7441A
Rev. H | Page 17 of 28
COMPONENT PROCESSOR (CP)
The component processor section is capable of decoding and
digitizing a wide range of component video formats in any color
space. Component video standards supported by the CP are
525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, VGA up to
UXGA at 60 Hz, and many other standards.
The CP section of the ADV7441A contains an AGC block. This
block is followed by a digital clamp circuit that ensures that the
video signal is clamped to the correct blanking level. Automatic
adjustments within the CP include gain (contrast) and offset
(brightness); however, manual adjustment controls are also
supported. If no embedded synchronization is present, the
video gain can be set manually.
A fully programmable, any-to-any, 3 × 3 color-space converter is
placed before the CP section. This enables YPrPb-to-RGB and
RGB-to-YCrCb conversions. Many other standards of color
space can be implemented using the color-space converter.
A second fully programmable, any-to-any, 3 × 3 color-space
converter is placed in the back end of the CP core. This color-
space converter features advanced color controls, such as
contrast, saturation, brightness, and hue controls.
The output section of the CP is highly flexible. It can be configured
in single data rate (SDR) mode with one data packet per clock
cycle. In SDR mode, a 16-/20-bit 4:2:2 or 24-/30-bit 4:4:4 output
is possible. In these modes, HS/CS, VS/FIELD, and DE/FIELD
(where applicable) timing reference signals are provided.
The CP section contains circuitry to enable the detection of
Macrovision-encoded YPrPb signals for 525i, 625i, 525p, and
625p. It is designed to be fully robust when decoding these
types of signals.
VBI DATA PROCESSOR
VBI extraction of CGMS data is performed by the VBI data
processor (VDP) section of the AD7441A for interlaced,
progressive, and high definition scanning rates. The data
extracted is read back over the I2C interface.
For more detailed product information about the ADV7441A,
contact a local Analog Devices sales representative or field
applications engineer (FAE).
ADV7441A Data Sheet
Rev. H | Page 18 of 28
PIXEL OUTPUT FORMATTING
Note that unused pins of the pixel output port are driven with a low voltage.
Table 8. Standard Definition Pixel Port Modes (P19 to P0)
Processor Mode Format
Data Port Pins P[19:0]
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDP Mode 1 Video output
8-bit 4:2:2
YCrCb[7:0]
SDP Mode 2 Video output
10-bit 4:2:2
YCrCb[9:0]
SDP Mode 3 Video output
16-bit 4:2:2
Y[7:0] CrCb[7:0]
SDP Mode 4 Video output
20-bit 4:2:2
Y[9:0] Cb[9:0]
SDP Mode 5 Video output
24-bit 4:4:4
Y[7:0] Cb[7:0]
SDP Mode 6 Video output
30-bit 4:4:4
Y[9:0] Cb[9:0]
Table 9. Standard Definition Pixel Port Modes (P29 to P20)
Processor Mode Format
Data Port Pins P[29:20]
29 28 27 26 25 24 23 22 21 20
SDP Mode 1 Video output
8-bit 4:2:2
SDP Mode 2 Video output
10-bit 4:2:2
SDP Mode 3 Video output
16-bit 4:2:2
SDP Mode 4 Video output
20-bit 4:2:2
SDP Mode 5 Video output
24-bit 4:4:4
Cr[7:0]
SDP Mode 6 Video output
30-bit 4:4:4
Cr[9:0]
Data Sheet ADV7441A
Rev. H | Page 19 of 28
Table 10. Component Processor Pixel Output Pin Map (P19 to P0)
Processor1 Mode Format
Output of Data Port Pins P[19:0]
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP Mode 1 Video output
8-bit 4:2:22
YCrCb[7:0]
CP
Mode 2
Video output
10-bit 4:2:22
YCrCb[9:0]
CP Mode 3 Video output
12-bit 4:2:22
YCrCb[11:2]
CP Mode 4 Video output
12-bit 4:2:22
YCrCb[11:4]
CP Mode 5 Video output
12-bit 4:2:22
YCrCb[11:4] YCrCb[3:0]
CP Mode 6 Video output
16-bit 4:2:23, 4
CHA[7:0] (default data is Y[7:0]) CHB/CHC[7:0] (default data is
Cr/Cb[7:0])
CP Mode 7 Video output
20-bit 4:2:23, 4
CHA[9:0] (default data is Y[9:0]) CHB/CHC[9:0] (default data is Cr/Cb[9:0])
CP Mode 8 Video output
20-bit 4:2:223, 4
CHA[9:2] (default data is Y[9:2]) CHB/CHC[9:2] (default data is
Cr/Cb[9:2])
CP Mode 9 Video output
24-bit 4:2:23, 4
Y[11:2] CrCb[11:2]
CP Mode 10 Video output
24-bit 4:2:23, 4
Y[11:4] CrCb[11:4]
CP Mode 11 Video output
24-bit 4:2:23, 4
Y[11:4] Y[3:0] CrCb[3:0]
CP Mode 12 Video output
24-bit 4:4:43, 4
CHA[7:0] (default data is G[7:0] or Y[7:0]) CHB[7:0] (default data is R[7:0]
or Cr[7:0])
CP Mode 13 Video output
24-bit 4:4:43, 4
CHA[7:0] (default data is G[7:0] or Y[7:0]) CHC[7:0] (default data is B[7:0]
or Cb[7:0])
CP Mode 14 Video output
24-bit 4:4:43, 4
CHC[7:0] (default data is B[7:0] or Cb[7:0]) CHA[7:0] (default data is G[7:0]
or Y[7:0])
CP Mode 15 Video output
24-bit 4:4:43, 4
CHC[7:0] (default data is B[7:0] or Cb[7:0]) CHB[7:0] (default data is R[7:0]
or Cr[7:0])
CP Mode 16 Video output
30-bit 4:4:43, 4
CHA[9:0] (default data is G[9:0] or Y[9:0]) CHB[9:0] (default data is R[9:0] or Cr[9:0])
CP
Mode 17
Video output
30-bit 4:4:43, 4
CHA[9:0] (default data is G[9:0] or Y[9:0])
CHC[9:0] (default data is B[9:0] or
Cb[9:0])
CP Mode 18 Video output
30-bit 4:4:43, 4
CHC[9:0] (default data is B[9:0] or Cb[9:0]) CHA[9:0] (default data is G[9:0] or Y[9:0])
CP Mode 19 Video output
30-bit 4:2:23, 4
CHC[9:0] (default data is B[9:0] or Cb[9:0]) CHB[9:0] (default data is R[9:0] or Cr[9:0])
1 The CP processor uses the digitizer or HDMI as input.
2 Maximum pixel clock rate of 54 MHz.
3 Maximum pixel clock rate of 170 MHz for analog digitizer.
4 Maximum pixel clock rate of 165 MHz for HDMI.
ADV7441A Data Sheet
Rev. H | Page 20 of 28
Table 11. Component Processor Pixel Output Pin Map (P29 to P20)
Processor1 Mode Format
Output of Data Port Pins P[29:20]
29 28 27 26 25 24 23 22 21 20
CP Mode 1 Video output
8-bit 4:2:22
CP
Mode 2
Video output
10-bit 4:2:22
CP Mode 3 Video output
12-bit 4:2:22
YCrCb[1:0]
CP Mode 4 Video output
12-bit 4:2:22
YCrCb[3:0]
CP Mode 5 Video output
12-bit 4:2:2
2
CP Mode 6 Video output
16-bit 4:2:23, 4
CP Mode 7 Video output
20-bit 4:2:23, 4
CP Mode 8 Video output
20-bit 4:2:23, 4
Y[1:0] CrCb[1:0]
CP Mode 9 Video output
24-bit 4:2:23, 4
CrCb[1:0] Y[1:0]
CP Mode 10 Video output
24-bit 4:2:23, 4
CrCb[3:0] Y[3:0]
CP Mode 11 Video output
24-bit 4:2:23, 4
CrCb[11:4]
CP Mode 12 Video output
24-bit 4:4:43, 4
CHC[7:0] (for example, B[7:0] or Cb[7:0])
CP Mode 13 Video output
24-bit 4:4:43, 4
CHB[7:0] (for example, R[7:0] or Cr[7:0])
CP Mode 14 Video output
24-bit 4:4:43, 4
CHB[7:0] (for example, R[7:0] or Cr[7:0])
CP Mode 15 Video output
24-bit 4:4:43, 4
CHA[7:0] (for example, G[7:0] or Y[7:0])
CP Mode 16 Video output
30-bit 4:4:43, 4
CHC[9:0] (for example, B[9:0] or Cb[9:0])
CP Mode 17 Video output
30-bit 4:4:43, 4
CHB[9:0] (for example, R[9:0] or Cr[9:0])
CP Mode 18 Video output
30-bit 4:4:43, 4
CHB[9:0] (for example, R[9:0] or Cr[9:0])
CP Mode 19 Video output
30-bit 4:2:23, 4
CHA[9:0] (for example, G[9:0] or Y[9:0])
1 The CP processor uses the digitizer or HDMI as input.
2 Maximum pixel clock rate of 54 MHz.
3 Maximum pixel clock rate of 170 MHz for analog digitizer.
4 Maximum pixel clock rate of 165 MHz for HDMI.
Data Sheet ADV7441A
Rev. H | Page 21 of 28
REGISTER MAP ARCHITECTURE
The ADV7441A registers are controlled via a 2-wire serial (I2C-compatible) interface. The ADV7441A has eight maps, each with a unique
I2C address. The state of the ALSB pin (Pin 13) sets Bit 2 of each register map address in Table 12.
Table 12. Register Map Addresses
Register Map
Default Address
with ALSB = Low
Default Address
with ALSB = High Programmable Address
Location Where Address
Can Be Programmed
User Map 0x40 0x42 Not programmable N/A
User Map 1 0x44 0x46 Programmable User Map 2, Register 0xEB
User Map 2
0x60
0x62
Programmable
User Map, Register 0x0E
VDP Map 0x48 0x4A Programmable User Map 2, Register 0xEC
Reserved Map 0x4C 0x4E Programmable User Map 2, Register 0xEA
HDMI Map 0x68 0x6A Programmable User Map 2, Register 0xEF
Repeater KSV Map 0x64 0x66 Programmable User Map 2, Register 0xED
EDID Map 0x6C 0x6E Programmable User Map 2, Register 0xEE
SCL
SDA
SA:
PROGRAMMABLE
SA:
PROGRAMMABLE
SA:
PROGRAMMABLE
SA:
PROGRAMMABLE SA:
PROGRAMMABLE SA:
PROGRAMMABLE
SA:
PROGRAMMABLE
RESERVED MAP
REPEATER
KSV MAP
EDI D M APHDMI M AP
SA: 0x40
VDP MAPUSER MAP 2USER MAP 1USER M AP
06914-008
Figure 7. Register Map Access Through the Main I2C Port
ADV7441A Data Sheet
Rev. H | Page 22 of 28
TYPICAL CONNECTION DIAGRAM
06914-009
Figure 8. Typical Connection Diagram
Data Sheet ADV7441A
Rev. H | Page 23 of 28
RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS
Note that the external loop filter components for the ELPF and AUDIO_ELPF pins should be placed as close as possible to the respective
pins. The recommended component values are specified in Figure 9 and Figure 10.
1.69kΩ
82nF
10nF
PVDD = 1.8V
ELPF 70
06914-010
Figure 9. ELPF Components
1.5kΩ
80nF
8nF
PVDD = 1.8V
AUDIO_ELPF 102
06914-011
Figure 10. AUDIO_ELPF Components
ADV7441A Data Sheet
Rev. H | Page 24 of 28
ADV7441A EVALUATION PLATFORM
Analog Devices has developed an advanced TV (ATV) evaluation
platform for the ADV7441A decoder. The evaluation platform
consists of a motherboard and two daughterboards. The mother-
board features a Xilinx FPGA for digital processing and muxing
functions. The motherboard also features three AD9742 devices
(12-bit DACs) from Analog Devices. This allows the user to drive a
VGA monitor with just the motherboard and front-end board.
The back end of the platform can be connected to a specially
developed video output board from Analog Devices. This
modular board features an Analog Devices encoder and an
Analog Devices HDMI transmitter.
The front end of the platform consists of an ADV7441 eval-
uation board (EVAL-ADV7441AFEZ_1). This evaluation board
contains an ADV7441A decoder (see Table 13 for details). The
evaluation board feeds the digital outputs from the ADV7441A
decoder to the FPGA on the motherboard.
Table 13. Front-End Modular Board Details
Front-End Modular Board Model On-Board Decoder HDCP License Required
EVAL-ADV7441AFEZ_1
ADV7441ABSTZ-170
Yes
VIDEO INPUT BOARD
EVAL-ADV7441AFEZ_x
ADV7441A
DECODER
ANALOG AND DIGITAL VIDEO INPUTS
ATV MOTHERBOARD
VIDEO OUTPUT BO ARD
Xilinx FPGA VGA
OUTPUT
AVI 168- P IN CONNE CTOR
AVO 168- P IN CONNE CTOR
HDMI
Y/C
CVBS
YPrPb
AD9889B ADV7341
AUDIO 96-PIN CONNE CTOR
06914-012
Figure 11. Functional Block Diagram of Evaluation Platform
Data Sheet ADV7441A
Rev. H | Page 25 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JE DE C S TANDARDS MS-026-BFB
051706-A
0.27
0.22
0.17
1
36
37
73
72
108
144 109
TOP VIEW
(PINS DO W N)
0.50
BSC
LEAD P ITCH
1.60
MAX
0.75
0.60
0.45
VIEW A
PIN 1
1.45
1.40
1.35
0.15
0.05
0.20
0.09
0.08
COPLANARITY
VIEW A
ROTAT E D 90° CCW
SEATING
PLANE
7°
3.5°
0°
22.20
22.00 SQ
21.80
20.20
20.00 SQ
19.80
Figure 12. 144-Lead Low Profile Quad Flat Package [LQFP]
(ST-144)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Notes
Temperature Range
Package Description
Package Option
ADV7441ABSTZ-170
2
−40°C to +85°C
144-Lead Low Profile Quad Flat Package [LQFP]
ST-144
ADV7441ABSTZ-110
2
−40°C to +85°C
144-Lead Low Profile Quad Flat Package [LQFP]
ST-144
ADV7441ABSTZ-5P 3, 4 −40°C to +85°C 144-Lead Low Profile Quad Flat Package [LQFP] ST-144
EVAL-ADV7441AFEZ_1 2, 5, 6 Front-End Evaluation Board
1 Z = RoHS Compliant Part.
2 This part is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection, LLC, for licensing requirements) to
purchase any components with internal HDCP keys.
3 Speed grade: 5 = 170 MHz. HDCP functionality: P = no HDCP functionality (professional version).
4 Professional version for non-HDCP encrypted applications. Purchaser is not required to be an HDCP adopter.
5 Front-end board for the ATV evaluation platform, fitted with ADV7441ABSTZ-170 decoder. See the ADV7441A Evaluation Platform section for details on the evaluation
platform.
6 An ATV motherboard is also required to process the ADV7441A digital outputs and achieve video output. An ATV video output board is optional to evaluate
performance through an HDMI Tx and video encoder.
ADV7441A Data Sheet
Rev. H | Page 26 of 28
NOTES
Data Sheet ADV7441A
Rev. H | Page 27 of 28
NOTES
ADV7441A Data Sheet
Rev. H | Page 28 of 28
NOTES
I2C refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors).
HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other
countries.
©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06914-0-2/12(H)