Ericsson Internal
PRODUCT SPECIFICATION 6 (18)
Prepared (also subject responsible if other) No.
EAB/FJB/GMD EHOSMIR 30/1301-BMR 464 Uen
Approved Checked Date Rev Reference
EAB/FJB/GMF (Ksenia Harrisen) (EKRIROB) 2014-05-02 E
Synchronization
Synchronization is a feature that allows multiple products to be
synchronized to a common frequency. Synchronized pr oducts
powered from the same bus eliminate beat frequencies
reflected back to the input supply, and also reduces EMI
filtering requirements. Eliminating the slow beat frequencies
(usually <10 kHz) allows the EMI filter to be designed to
attenuate only the synchronization freq uency. Synchronization
can also be utilized for phase spreading, described in section
Phase Spreading.
The products can be synchronize d with an external oscillator or
one product can be configur ed with the SYNC pin as a SYNC
Output working as a master driving the synchronization. All
others on the same synchronization bus must be configured
with SYNC Input. Default configuration is us ing the internal
clock, independently of signal at the SYNC pin.
See application note AN309 for further information.
Phase Spreading
When multiple products share a common DC input supply,
spreading of the switching clock phase between the products
can be utilized. T his dramatically reduces input capacitance
requirements and efficiency losses, since the peak curre nt
drawn from the input supply is effectively spread out over the
whole switch period. This requires that the products are
synchronized. Up to 16 different phases can be used.
The phase spreading of the product can be configured using
the PMBus interface.
See application note AN309 for further information.
Parallel Operation (Current Sharing)
Paralleling multiple products can be used to i ncrease the
output current capability of a single power rail. By connecting
the GCB pins of each device and configuring the devices as a
current sharing rail, the units will share the c urrent equally,
enabling up to 100% utiliz ation of the current capability for
each device in the current shar ing rail. The product uses a low-
bandwidth, first-order digital current sharing by aligning the
output voltage of the slave dev ices to del iver the same current
as the master device. Artificial droop resistance is added to the
output voltage path to control the slope of the loa d lin e curve,
calibrating out the phys ical parasitic mismatches due to power
train components and PWB layout. Up to 7 devices can be
configured in a given current shari ng group.
In order to avoid interference with other algorithms executing
during parallel operation, the dead-time algorithm should be
turned off and fixed dead-times be used. See application note
N307 for further information.
Phase Adding and Shedding fo r Parallel Operation
During periods of light load ing, it may be beneficial to disable
one or more phases (modules) in order to el iminate the current
drain and switching losses associated with those phases,
resulting in higher efficiency. The product offers the ability to
add and drop phases (modules) using a PMBus command in
response to an observed load current chan ge. All phases
(modules) in a current share rail ar e considered active prior to
the current sharing rail ramp to power-good. Phases can be
dropped after power-good is reached. An y member of the
current sharing rail can be dropped. If the reference module is
dropped, the remaining active module with the lowest member
position will become the ne w referenc e. Additionally, any
change to the number of members of a current sharing rail will
precipitate autonomous phase distribution within the rail where
all active phases realign their phase position based on their
order within the number of active members. If the members of
a current sharing rail are forced to shut down due to an
observed fault, all members of the rail will attempt to re-start
simultaneously after the fault has cleared.
See application note AN307 for further information.
Efficiency Optimized Dead Time Control
The product utilizes a closed l oop algorithm to optimize the
dead-time applied between the gate drive signals for the switch
and synch FETs. The algorithm constantly adjusts the
deadtime non-overlap to minimize the duty cycle, thus
maximizing efficiency. This algorithm will null out deadtime
differences due to component variation, temperature and
loading effects. The algorithm can be configured via the
PMBus interface.
Over Current Protection (OCP)
The product includes current limiting circuitry for protection at
continuous overload. The following OCP response options a r e
available:
1. Initiate a shutdown and attempt to restart an infinite number
of times with a preset delay period between attempts.
3. Initiate a shutdown and attempt to restart a preset number
of times with a preset delay period between attempts.
4. Continue operating for a given delay period, followed by
shutdown if the fault still exists.
5. Continue operating thro ugh the fault (this could result in
permanent damage to the power sup pl y).
6. Initiate an immediate shutdo wn.
The default response from an over current fault is an
immediate shutdo wn of the device. The device will
continuously check for the presence of the fault condition, and
if the fault condition no longer exists the device will be re-
enabled. The load distribution should be designed for the
maximum output short circuit current specified. The OCP limit
and response of the product can be reconfigured using the
PMBus interface.
Initialization Procedure
The product follows a specific internal initialization procedure
after power is applied to the VIN pin:
1. Status of the address and output voltage pin-strap pins are
checked and values associated with the pin settings are
loaded to RAM.
2. Values stored in the Ericsson default non-v ol atile memory
are loaded to RAM. This overwrites any previously loade d
E
BMR464 series PoL Regulators
Input 4.5-14 V, Output up to 50 A / 165 W EN/LZT 146 435 R4B May 2014
© Ericsson AB
Technical Specification