2732A 32K (4K x 8) UV ERASABLE PROM @ 200ns (2732A-2) Maximum Access @ Pin Compatible to 2764 EPROM Time ... HMOS*-E Technology Compatible to High Speed 8mHz o dustry Standard Pinout .. . JEDEC 8086-2 MPU .. .Zero WAIT State pprove @ Two Line Control @ Low Standby Current ... 35mA Max. The Intel 2732A is a 5V only, 32,768 bit ultraviolet erasable and electrically programmable read-only memory (EPROM). It is pin compatible to Intels 450ns 2732. The standard 2732As access time is 250ns with speed selection (2732A-2) available at 200ns. The access time is compatible to high performance microprocessors, such as the 8mHz 8086-2. In these systems, the 2732A allows the microprocessor to operate without the addition of WAIT states. An important 2732A feature is the separate output control, Output Enable (OE), from the Chip Enable control (CE). The OE control eliminates bus contention in multiple bus microprocessor systems. Intels Application Note AP-72 describes the microprocessor system implementation of the OE and CE controls on Intels EPROMs. AP-72 is available from Intels Literature Department. The 2732A has a standby mode which reduces the power dissipation without increasing access time. The maximum active current is 150mA, while the maximum standby current is only 35mA, a 75% saving. The standby mode is achieved by applying a TTL-high signal to the CE input. The 2732A is fabricated with HMOS*-E technology, Intel's high speed N-channel MOS Silicon Gate Technology. 2764 MODE SELECTION PIN CONFIGURATION 2732A PINS CE | SE/Vpp Vec OUTPUTS PIN CONFIGURATION owe: wed vcc MODE (18) | (20) (24) | (9-11,13-17) Av CJ2 a7 [Pom ar] 26] Nc Read Vie Vit +5 Dout aeC]s 25 [7] As Standby Vin {Don't Care +5 High Z Ass 24] Ag Pp Vv + aaCle ws Elan rogram IL Vpp 5 Din aC? 22 f] OE Program Verify | Vit Vit +5 Dout ae(]e asf) Ato Program Inhibit] Vi4 Vpp +5 High Z aiC]9 20(] cE Aq LJ 10 19) o7 oo (11 18 [_] 6 0112 170) os As "He BLOCK DIAGRAM ano [7] 14 15[_] 03 DATA OUTPUTS (1For total compatibility trom Voc o- 00-07 2732A provide a trace to pin 26 GNO oO q vero HT oF ANO PIN NAMES c-|_ GE voaic OUTPUT SUFFERS = Y I Aa-Ai1_| ADDRESSES Ao-at, | ==|_oecopern |? Y-GATING 7 ADORESS ts ce CHIP ENABLE ieuTs | l 7 oe OUTPUT ENABLE = x 3 32,768-B1T Qy-0, OUTPUTS ==] OECODER : CELL MATRIX | HMOS is a patented process of Intel Corporation.PROGRAMMING 2732A The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions Section. Absolute Maximum Ratings* Temperature Under Bias............ =10Cto +80C Storage Temperature ............. -65Cto +125C All Input or Output Voltages with Respect to Ground ............-.0.. +6Vto -0.3V Vpp Supply Voltage with Respect to Ground During Programming .............- +22V to 0.3V *COMMENT: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress tating onty and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC and AC Operating Conditions During Read 2732A 2732A:2 2732A-3 Operating Temperature Range oc 70C oc 70C oc 70C Voc Power Supply 5V+5% 5V+5% 5V+5% READ OPERATION D.C. and Operating Characteristics Symbol Parameter Min. Wel Max. Unit Conditions he Input Load Current 10 BA | Viy =5.25V lLo Output Leakage Current 10 vA | Vout =5.25V lees Voc Current (Standby) 35 mA | CE=Vy,, OF = Vy lece Veco Current (Active) 150 mA | OF=CE=Vy. Vit Input Low Voltage -0.1 0.8 v Vi Input High Voltage 2.0 Veco +1 Vv Vor Output Low Voltage 0.45 Vie] Ion =2.1mA Vow Output High Voltage 2.4 Vv lon = 400nA NOTES: 1. Typical values are for Ty = 25C and nominal supply voltages. 2-122732A PRELIMINARY A.C. Characteristics Symbol Parameter 2732A Limits 2732A-2 Limits 2732A-3 Limits Unit Test Min Typltl Max) Min Typlll Max| Min Typl] Max Conditions tacc _ | Address to Output Delay 250 200 300 | ns | CE=OE=Vy, toe CE to Output Delay 250 200 300 | ns | OE=Vy tog Output Enable to Output 10 100} 10 70 | 10 150 | ns | CE=Vi Delay tor Output Enable High to Output | 0 90 0 60 0 130 | ns | CE=Vy Float tou Output Hold from Addresses, | 0 4) ) ns | CE=OE=Vi, CE or OE Whichever Occurred First CAPACITANCE 1) 1, = 25C, f= 4MHz A.C. TEST CONDITIONS Symbol Parameter Typ. | Max. | Unit | Conditions Output Load: 1 TTL gate and C_ = 100pF Cina Input Capacitance Input Rise and Fallt Times: <= 20ns Except OE/Vpp 4 6 pF | Vin = 0V Input Pulse Levels: 0.8V to 2.2V = Timing Measurement Reference Level: Cinz2 | OE/Vee Input Inputs 1V and 2v Capacitance 20 pF [Vin = 0V Outputs 0.8V and 2V Cout Output Capacitance 12 pF | Vout = 0V A. C. Waveforms / ee N ADDRESSES ADDRESSES VALID N eee j CE fo @eensee ] te OE /f tol] a tor!) hn tacc!3! toH ~ OUTPUT un LLL VALID OUTPUT NOTE: 1. Typical values are for Ta = 25C and nominal supply voltages. 2. This parameter is only sampled and is not 100% tested. 3. OE may be delayed up to tacc tog after the falling edge of CE without impact on taco. 4. tpg Is specified trom OE or CE, whichever occurs first. , HIGH Z 2-132732A PROGRAMMING"! D.C. PROGRAMMING CHARACTERISTICS: T, = 25245C, Vog =5V+5%, Vpp=21V + 0.5V Limits Symbol Parameter Min. Typ. Max. Unit Test Conditions to Input Current (All Inputs) 10 pA Vin= Vic or Vin VoL Output Low Voltage During Verify 0.45 Vv lol = 2.1 mA Von Output High Voltage During Verify 2.4 Vv lon = 400 pA loc Voc Supply Current 85 150 mA Vit Input Low Level (All Inputs) -0.1 0.8 Vv Vin Input High Level (All Inputs Except OE/Vpp) 2.0 Vect1 Vv Ipp Vpp Supply Current 30 mA | CE=Vi,, GE=Vpp A.C, PROGRAMMING CHARACTERISTICS: T, =25+5C, Vog = 5V + 5%, Vpp=21V +0,5V Limits Symbo! Parameter Min. Typ. Max. Unit Test Conditions* tas Address Setup Time 2 ys toes GE Setup Time 2 us tos Data Setup Time 2 us tay Address Hold Time 0 us toe QE Hold Time 2 | us toy Data Hold Time 2 us tor Chip Enable to Output Float Delay 0 130 ns toy Data Valid from TE 1 us | CE=V,, OE=Vy, tpw TE Pulse Width During Programming 45 50 55 ms tert OE Pulse Rise Time During Programming 50 ns tyr Vpp Recovery Time 2 us NOTE: 1. When programming the 2723A, a 0.1uF capacitor is required across OEMNVpp and ground to suppress spurious voltage transients which may damage the device. *A.C. CONDITIONS OF TEST Input Rise and Fall Times (10% to 90%) ......... 20ns Input Pulse Levels .......... 0... e eee 0.8V to 2.2V Input Timing Reference Level .............. 1V and 2V Output Timing Reference Level ........... 0.8V and 2V2732A ERASURE CHARACTERISTICS The erasure characteristics of the 2732A are such that erasure begins to occur when exposed to light with wave- lengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000A range. Data show that constant exposure to room level fluorescent lighting could erase the typical 2732A in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sun- light. If the 2732A Is to be exposed to these types of light- ing conditions for extended periods of time, opaque labels are available from Intel which should be placed over the 2732A window to prevent unintentional erasure. The recommended erasure procedure for the 2732A is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity X exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000,.Wicm? power rating. The 2732A should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. DEVICE OPERATION The five modes of operation of the 2732A are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels except for OE/Vpp during programming. In the program mode the OE/Vpp input is pulsed from a TTL level to 21V. TABLE 1. Mode Selection PINS cE OE/Vpp Voc OUTPUTS MODE (18) (20) (24) (9-11,13-17) Read Vit Vit +5 Dout Standby Vi Dont Care +5 High Z Program Vie Vpp +5 Din Program Verify Vit Vin +5 Dout Program Inhibit Vin Vpp +5 High Z Read Mode The 2732A has two control functions, both of which must be logically satisfied in order to obtain data at the out- puts. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be usec! to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (taco) is equal to the delay from CE to output (tc). Data_is available at the outputs after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tacc toe- Standby Mode The 2732A has a standby mode which reduces the active power current by 75%, from 150mA to 35mA. The 2732A is placed in the standby mode by applying a TTL high signal to the CE input. When in standby mode, the out- puts are in a high impedance state, independent of the OE input. Output OR-Tieing Becaus@ EPROMs are usually used in larger memory arrays, Intel has provided a 2 line control function that accomodates this use of multiple memory connection. The two line contro! function allows for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recommended that CE (pin 18) be decoded and used as the primary device selecting function, while OE (pin 20) be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is desired from a particular memory device. PROGRAMMING (See Programming Instruction Section for Waveforms.) Programming is the same as Intels 450ns 2732 except for the programming voltage. In the program mode the 2732A OE/Vpp input is pulsed from a TTL low level to 21V (25V for the 2732). Exceeding 21.5V will damage the 2732A. Initially, and after each erasure, all bits of the 2732A are in the 1 state. Data is introduced by selectively pro- gramming 0s into the desired bit locations. Although only 0s will be programmed, both 1s and 0s can be present in the data word. The only way to change a 0 to a 1 is by ultraviolet light erasure. The 27324 is in the programming mode when the OE/Vpp input is at 21V. It is required that a 0.1nF capacitor be placed across OE/Vpp and ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, a 50msec, active low, TTL program pulse is applied to the CE input. A pro- gram pulse must be applied at each address location to be programmed. You can program any location at any time either individually, sequentially, or at random. The program pulse has a maximum width of 55msec. The 2732A must not be programmed with a DC signal applied to the CE input. Programming of mulitple 2732As in parallel with the same data can be easily accomplished due to the simpli- city of the programming requirements. Like inputs of the paralleled 2732As may be connected together when they are programmed with the same data. A low level TTL pulse applied to the CE input programs the paralleled 2732As. 2-152732A Program Inhibit Programming of mulitple 2732As In parallel with differ- ent data is also easily accomplished. Except for CE, all like inputs (including OE) of the parallel 2732As may be common. A TTLlevel program pulse applied to. a 2732As CE input with OE/Vpp at 21V will program that 2732A. A high level CE input inhibits the other 2732As from being programmed. Program Verify A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with OE/Vpp and CE at V,. Data should be verified tpy after the falling edge of cE 2-16 -