TPS65580
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SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
4.5V to 18V Input 1.5A, 2.5A, 1.5A Triple Synchronous Step-Down Converter
Check for Samples: TPS65580
1FEATURES APPLICATIONS
2• Advanced D-CAP2™ Control Mode • Point-of-Load Regulation in Low Power
Systems for Wide Range of Applications
– Fast Transient Response – Digital TV Power Supply
– No External Parts Required For Loop
Compensation – Networking Home Terminal
– Compatible with Ceramic Output – Digital Set Top Box (STB)
Capacitors – DVD Player/Recorder
• Wide Input Voltage Range : 4.5 V to 18 V – Gaming Consoles and Other
• Output Voltage Range : 0.76 V to 7.0 V DESCRIPTION
• Highly Efficient Integrated FETs Optimized for The TPS65580 is a triple, advanced D-CAP2™ mode
Low Duty Cycle Applications synchronous buck converter. The TPS65580 enables
– 160 mΩ(High Side) and 130 mΩ(Low Side) system designers to complete the suite of various
for 2.5A end equipment’s power bus regulators with a cost
– 250mΩ(High Side) and 230mΩ(Low Side) effective, low component count, and low standby
for 1.5A current solution. The main control loops of the
TPS65580 uses the advanced D-CAP2™ mode
• High Initial Reference Accuracy control which provides a fast transient response with
• Low-Side RDS(on) Loss-Less Current Sensing no external compensation components. The
• Fixed 1.2 ms Soft Start TPS65580 is able to adapt to both low equivalent
series resistance (ESR) output capacitors such as
• Non-Sinking Pre-Biased Soft Start POSCAP or SP-CAP, and ultra-low ESR, ceramic
• 700 kHz Switching Frequency capacitors. The device provides convenient and
• Cycle-by-Cycle Over-Current Limiting Control efficient operation with input voltages from 4.5V to
18V.
• OCL, OVP, UVP, UVLO, TSD Protections
• Hiccup Timer for Over Load Protection The TPS65580 is available in 4.4mm × 6.5mm 20 pin
TSSOP (PWP) package, and is specified from –40°C
• PowerGood to 85°C ambient temperature range.
• Adaptive Gate Drivers with Integrated Boost
PMOS Switch
• OCP Constant Due To Thermally Compensated
rds(on) with 4000ppm/℃℃
• 20-Pin HTSSOP
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2D-CAP2, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Input Voltage
C21
C11
L11 C31
VO2
R21
R1１R13
R23
C22
PGND
PGND
VO1
C4
L12C32
PGND
SGND SGND
SGND
R12
R22
SGND
L13
C33
VO3
C23
PGND
SW1
VIN
VBST1
EN1
VFB2
EN3
GND
VREG5
PGND1
6
VBST2
SW2
EN2
5
1
3
11
2
4
7
13
12
TPS65580
HTSSOP20
14
8
15
16
(PowerPAD)
VFB1 VFB3
VBST3
SW3
10
9
17
18
19
20
PGND2
PGND3
PG
VIN
TPS65580
SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
HTSSOP APPLICATION DIAGRAM
ORDERING INFORMATION
TAPACKAGE(1) ORDERING PART NUMBER PINS OUTPUT SUPPLY ECO PLAN
TPS65580PWPR Tape-and-Reel Green (RoHS & no Sb/Br)
–40℃to 85℃PWP 20
TPS65580PWP Tube
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com
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SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)(2)
VALUE UNIT
MIN MAX
VIN, EN1, EN2, EN3 –0.3 20
VBST1, VBST2, VBST3 –0.3 26
VBST1, VBST2, VBST3 (10ns transient) –0.3 28
Input voltage range VBST1–SW1, VBST2–SW2, VBST3–SW3 –0.3 6.5 V
VFB1, VFB2, VFB3 –0.3 6.5
SW1, SW2, SW3 –2 20
SW1, SW2, SW3 (10ns transient) –3 22
VREG5, PG –0.3 6.5
Output voltage range V
PGND1, PGND2, PGND3 –0.3 0.3
Human Body Model (HBM) 2 kV
Electrostatic discharge Charged Device Model (CDM) 500 V
TAOperating ambient temperature range –40 85 °C
TSTG Storage temperature range –55 150 °C
TJJunction temperature range –40 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to IC GND terminal.
THERMAL INFORMATION TPS65580
THERMAL METRIC(1) UNITS
PWP (20) PINS
θJA Junction-to-ambient thermal resistance 40.0
θJCtop Junction-to-case (top) thermal resistance 24.8
θJB Junction-to-board thermal resistance 21.3 °C/W
ψJT Junction-to-top characterization parameter 0.8
ψJB Junction-to-board characterization parameter 21.1
θJCbot Junction-to-case (bottom) thermal resistance 1.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report,SPRA953.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) VALUES UNIT
MIN MAX
Supply input voltage range VIN 4.5 18 V
VBST1, VBST2, VBST3 –0.1 24
VBST1, VBST2, VBST3 (10ns transient) –0.1 27
VBST1–SW1, VBST2–SW2, VBST3–SW3 –0.1 5.7
Input voltage range VFB1, VFB2, VFB3 –0.1 5.7 V
EN1, EN2, EN3 –0.1 18
SW1, SW2, SW3 –1.0 18
SW1, SW2, SW3 (10ns transient) –3 21
VREG5, PG –0.1 5.7
Output voltage range V
PGND1, PGND2, PGND3 –0.1 0.1
TAOperating free-air temperature –40 85 °C
TJOperating Junction Temperature –40 150 °C
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ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
TA= 25°C, EN1 = EN2 = EN3 = 5 V,
IIN VIN supply current 2.9 3.6 mA
VFB1 = VFB2 = VFB3 = 1.0 V, Non-
switching
IVINSDN VIN shutdown current TA= 25°C, EN1 = EN2 = EN3 = 0 V 1.8 3 µA
VFB VOLTAGE
TA= 25°C, VO1=3.3V, VO2=1.2V,
VVFBTHLx VFBx threshold voltage(1) 752 764 776 mV
VO3=1.5V
TCVFBx Temperature coefficient On the basis of 25°C(2) –180 180 ppm/℃
VREG5 OUTPUT
VREG5 Rising 4.0
VUVREG5 VREG5 UVLO Threshold V
Hysteresis 0.3
VVREG5 VREG5 output voltage TA= 25°C, VIN = 12 V, IVREG = 5 mA 5.5 V
IVREG5 Output current VIN = 6 V, TA= 25°C 20 mA
MOSFETs
rDS(on)H2 High side switch resistance for 2.5A TA= 25℃, VBST2-SW2 = 5.5 V (2) , CH2 160 mΩ
rDS(on)L2 Low side switch resistance for 2.5A TA= 25℃(2), CH2 130 mΩ
TA= 25℃, VBSTx-SWx = 5.5 V (2) , CH1,
rDS(on)Hx High side switch resistance for 1.5A 250 mΩ
CH3
rDS(on)Lx Low side switch resistance for 1.5A TA= 25℃(2), CH1, CH3 230 mΩ
MIN ON/OFF TIME and SWfrequency
TONminx Min On Time TA= 25℃, VOUT = 0.8V(2) 80 ns
TOFFminx Min Off Time TA= 25℃, VFBx = 0.7 V(2) 220 ns
Fsw SW-frequency TA= 25℃700 kHz
SOFT START
TSS Soft-start time Internal soft-start time 1.2 ms
(1) x means either 1 or 2 or 3, that is, VFBx means VFB1, VFB2 or VFB3.
(2) Specified by design. Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
POWER GOOD
PG from lower VOx (going high) 84%
VPGTH PGx threshold PG from higher VOx (going low) 116%
RPG PGx pull-down resistance VPGx = 0.5 V 50 85 130 Ω
Delay for PGx going high 1.5 ms
TPGDLY PGx delay time Delay for PGx going low 2 µs
TPGCOMPSS PGOOD comparator start-up delay PGx comparator wake-up delay 2.8 ms
LOGIC THRESHOLD
VENH ENx H-level threshold voltage 2.0 V
VENL ENx L-level threshold voltage 0.4 V
RENx_IN ENx input resistance ENx = 12 V 225 400 900 kΩ
CURRENT LIMIT
IOCL1 Lout = 3.3 µH(3), VOUT = 3.3 V 1.7 2.0 3.4 A
IOCL2 Current limit Lout = 2.2 µH(3) VOUT = 1.2 V 2.9 3.5 4.9 A
IOCL3 Lout = 2.2 µH(3) VOUT = 1.5 V 1.8 2.2 3.6 A
OVER / UNDER VOLTAGE PROTECTION
VOVP Output OVP trip threshold measured on VFBx 120%
VUVP Output UVP trip threshold measured on VFBx 63% 68% 73%
TUVPDEL Output UVP delay time 0.5 ms
TUVPEN Output UVP enable delay UVP Enable Delay 2.8 ms
THERMAL SHUTDOWN
Shutdown temperature(3) 155
TSD Thermal shutdown threshold °C
Hysteresis(3) 30
(3) Specified by design. Not production tested.
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SW1
VIN
VBST1
EN1
VFB2
EN3
GND
VREG5
PGND1
6
VBST2
SW2
EN2
5
1
3
11
2
4
7
13
12
TPS65580
HTSSOP20
14
8
15
16
(PowerPAD)
VFB1 VFB3
VBST3
SW3
10
9
17
18
19
20
PGND2
PGND3
PG
VIN
TPS65580
SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
www.ti.com
DEVICE INFORMATION
HTSSOP PACKAGE
(TOP VIEW)
PIN FUNCTIONS(1)
PIN I/O DESCRIPTION
NAME TSSOP20
VIN 1,2 I Power input and connects to both high side NFET drains. Supply Input for 5.5V linear regulator.
VBST1, VBST2, Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor between
3, 14, 20 I
VBST3 VBSTx and SWx pins. An internal diode is connected between VREG5 and VBSTx
SW1, SW2, Switch node connections for both the high-side NFETs and low–side NFETs. Input of current
4,15,19 I/O
SW3 comparator.
PGND1,
PGND2, 5,16,18 I/O Ground returns for low-side MOSFETs. Input of current comparator.
PGND3 Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at least
VREG5 6 O 1.0µF. VREG5 is active when ENx is high level.
PG 7 O Open drain power good output. Low means the output voltage is out of regulation.
EN1, EN2, EN3 8,13,17 I Enable. Pull High to according converter.
VFB1, VFB2, 9,11,12 I D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
VFB3
GND 10 I/O Signal GND. Connect sensitive VFBx returns to GND at a single point.
Exposed Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be
Back side I/O
Thermal Pad connected to GND.
(1) x means either 1, 2 or 3, VFBx means VFB1, VFB2 or VFB3.
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SWx
VBSTx
ENx
VFBx
GND VREG5
PGNDx
.
VOx
.
VIN
VREG5
EN
Logic Control
and
Protection
Logic
UVx
OVx
Refx SSx
Fixed
SoftStart
Bandgap
UVLO
TSD
VBG
-32
+20
SSx
PGND
Err
Comp
CHx Min-off timer
VIN
VIN
SWx
Ref_OCL
OCPx
Circuitry for single channel, x = 1,2 or 3
Common Circuitry
ENintx
ENSSx
ENSSx
UVLO
TSD
UVLO
TSD
OVx
UVx
Refx
PGx
/
+16%
-16%
PG1
PG2
PG3
PG
TPS65580
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SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
FUNCTIONAL BLOCK DIAGRAM
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TPS65580
SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
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OVERVIEW
The TPS65580 is a 1.5A/2.5A/1.5A triple synchronous step-down (buck) converter with two integrated N-channel
MOSFETs for each channel. It operates using Advanced D-CAP2™ control mode. The fast transient response of
Advanced D-CAP2™ control reduces the required output capacitance to meet a specific level of performance.
Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer
types.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS65580 is a fixed switching frequency pulse width modulation (PWM) controller
that supports a proprietary advanced D-CAP2™ mode control. Advanced D-CAP2™ mode control combines
constant switching frequency with an internal compensation circuit and low external component count
configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the
output.
PWM Frequency and Adaptive On-Time Control
TPS65580 uses a advanced D-CAP2 mode control scheme and have a dedicated on board oscillator. The
TPS65580 runs with fixed frequency of 700 kHz.
Soft Start and Pre-Biased Soft Start
The TPS65580 has an internal, 1.2ms, soft-start for each channel. When the ENx pin becomes high, an internal
DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is
maintained during start up.
The TPS65580 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than internal feedback voltage VFB), the controller slowly activates synchronous rectification by
starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VOx)
starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation.
Overvoltage Protection
TPS65580 detects overvoltage conditions by monitoring the feedback voltage (VFB). When the feedback voltage
becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit drives as
the high-side MOSFET driver turns off and the low-side MOSFET turns off.
This is a non-latch function.
Current Protection
The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit and
using HICCUP mode over current protection. The switch current is monitored by measuring the low-side FET
switch voltage between the SWx pin and PGNDx. This voltage is proportional to the switch current and the on-
resistance of the FET. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iox. If the sensed voltage on the
low side FET is above the voltage proportional to the current limit, the converter keeps the low-side switch on
until the measured voltage falls below the voltage corresponding to the current limit and a new switching cycle
begins. In subsequent switching cycles, the on-time is set to the value determined for CCM and the current is
monitored in the same manner.
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<Start up>
TPS65580
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SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
Following are some important considerations for this type of over-current protection. The load current one half of
the peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited,
the output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. When the over current condition is removed, the output voltage returns to the regulated value. This
protection is non-latching.
Load current less than 1.5 A for CH1 and CH3 is required at VOUT setting in high on-duty because overcurrent
limit function causes degradation of load transient response.
Hiccup Mode
Hiccup mode of operation protects the power supply from being damaged during an over-current fault condition.
The operation of hiccup is as follows. If the OCL comparator circuit detects an over-current event the output
voltage falls. When the feedback voltage falls below 68% of the reference voltage, the UVP comparator output
goes high and an internal UVP delay counter begins counting. After counting UVP delay time, the TPS65580
shuts off the power supply for a given time (7x UVP Enable Delay Time) and then tries to re-start the power
supply. If the over-load condition has been removed, the power supply starts and operates normally; otherwise,
the TPS65580 detects another over-current event and shuts off the power supply again, repeating the previous
cycle. Excess heat due to overload lasts for only a short duration in the hiccup cycle, therefore the junction
temperature of the power devices is much lower.
POWERGOOD
The TPS65580 has power-good output that are measured on VFBx. The power-good function is activated after
the soft-start has finished. If the all output voltages of 3 channels are within 16% of the target voltage, the
internal comparator detects the power good state and the power good signal becomes high after 1.5ms delay.
During start-up, this internal delay starts after 1.5ms of the UVP Enable delay time to avoid a glitch of power-
good signal. Even if at least one of the feedback voltages of 3 channels goes outside of ±16% of target value,
the power-good signal becomes low after 2µs.
Figure 1. Start up
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<Power Down>
<Vout Transient>
TPS65580
SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
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Figure 2. VOUT Transient
Figure 3. Power Down
UVLO Protection
Under voltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is
lower than UVLO threshold voltage, the TPS65580 is shut down. As soon as the voltage increases above the
UVLO threshold, the converter starts again.
Thermal Shutdown
TPS65580 monitors its temperature of itself. If the temperature exceeds the threshold value (typically 155°C), the
device is shut down. When the temperature falls below the threshold, the IC starts again. When VIN starts up
and VREG5 output voltage is below its nominal value, the thermal shutdown threshold is lower than 155℃. As
long as VIN and VREG5 rise, TJmust be kept below 110℃.
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3.2
3.22
3.24
3.26
3.28
3.3
3.32
3.34
3.36
3.38
3.4
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
VOUT - Output Voltage (V)
IOUT - Output Current (A)
C004
VIN = 6 V
VIN = 12 V VIN = 18 V
1.15
1.16
1.17
1.18
1.19
1.2
1.21
1.22
1.23
1.24
1.25
0 0.5 1 1.5 2 2.5
VOUT - Output Voltage (V)
IOUT - Output Current (A)
C005
VIN = 18 V
VIN = 12 V
VIN = 5 V
0
5
10
15
20
25
30
35
40
45
50
0 5 10 15 20
EN Input Current (uA)
EN Input Voltage (V)
EN1
EN2
EN3
C003
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
±50 0 50 100 150
Ivinsdn - VIN Shutdown Current (A)
TJ Junction Temperature (C)
C002
VIN = 12 V
0
5
10
15
20
25
30
±50 0 50 100 150
IIN - VIN Supply Current (mA)
TJ Junction Temperature (C)
C001
VIN = 12 V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
±50 0 50 100 150
IIN - VIN Supply Current (mA)
TJ Junction Temperature (C)
C019
VIN = 12 V
TPS65580
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SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS
VIN = 12 V, TA= 25°C (unless otherwise noted)
Figure 4. VIN Current vs Junction Temperature Figure 5. VIN Current vs Junction Temperature
(VIN Current at ALL Channels Switching with IO= 0A) (VIN Current at ALL Channels Non-switching EN = H)
Figure 6. VIN Shutdown Current vs Junction Temperature Figure 7. EN Current vs EN Voltage
Figure 8. VOUT1 = 3.3V Output Voltage vs Output Current Figure 9. VOUT2 = 1.2V Output Voltage vs Output Current
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Vout(50mV/div)
Iout2(1A/div)
Vo=1.2V
100us/div
Vo=3.3V VOUT(50mV/div)
IOUT1(1A/div)
100us/div
1.15
1.16
1.17
1.18
1.19
1.2
1.21
1.22
1.23
1.24
1.25
0 2 4 6 8 10 12 14 16 18 20
VOUT - Output Voltage (V)
VIN - Input Voltage (V)
Io=0A
Io=1A
C008
IOUT = 0 A
IOUT = 1 A
1.45
1.46
1.47
1.48
1.49
1.5
1.51
1.52
1.53
1.54
1.55
0 2 4 6 8 10 12 14 16 18 20
VOUT - Output Voltage (V)
VIN - Input Voltage (V)
Io=0A
Io=1A
C009
IOUT = 0 A
IOUT = 1 A
3.2
3.22
3.24
3.26
3.28
3.3
3.32
3.34
3.36
3.38
3.4
0 2 4 6 8 10 12 14 16 18 20
VOUT - Output Voltage (V)
VIN - Input Voltage (V)
Io=0A
Io=1A
C007
IOUT = 0 A
IOUT = 1 A
1.45
1.46
1.47
1.48
1.49
1.5
1.51
1.52
1.53
1.54
1.55
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
VOUT - Output Voltage (V)
IOUT - Output Current (A)
C006
VIN = 18 V
VIN = 12 V
VIN = 5 V
TPS65580
SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
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TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA= 25°C (unless otherwise noted)
Figure 10. VOUT3 = 1.5V Output Voltage vs Output Voltage Figure 11. VOUT1 = 3.3V Output Voltage vs Input Voltage
Figure 12. VOUT2 = 1.2V Output Voltage vs Input Voltage Figure 13. VOUT3 = 1.5V Output Voltage vs Input Voltage
Figure 14. VOUT1 = 3.3V, 0A to 1.5A Load Transient Figure 15. VOUT2 = 1 .2V, 0A to 2.5A Load Transient
Response Response
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400
450
500
550
600
650
700
750
800
850
900
0 2 4 6 8 10 12 14 16 18 20
fsw - Switching Frequency (kHz)
VIN - Input Voltage (V)
C013
IOUT = 1 A
400
450
500
550
600
650
700
750
800
850
900
0 2 4 6 8 10 12 14 16 18 20
fsw - Switching Frequency (kHz)
VIN - Input Voltage (V)
C014
IOUT = 1 A
40
50
60
70
80
90
100
0 0.5 1 1.5 2 2.5
Efficiency (%)
IOUT - Output Current (A)
VIN=6V
VIN=12V
VIN=18V
C011
VIN = 5 V
VIN = 12 V
VIN = 18 V
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Efficiency (%)
IOUT - Output Current (A)
VIN=6V
VIN=12V
VIN=18V
C012
VIN = 5 V
VIN = 12 V
VIN = 18 V
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Efficiency (%)
IOUT - Output Current (A)
VIN=6V
VIN=12V
VIN=18V
C010
VIN = 6 V
VIN = 12 V
VIN = 18 V
VOUT(50mV/div)
IOUT3(1A/div)
Vo=1.5V
100us/div
TPS65580
www.ti.com
SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA= 25°C (unless otherwise noted)
Figure 16. VOUT3 = 1.5V, 0A to 1.5A Load Transient Figure 17. VOUT1 = 3.3V Light Load Efficiency vs Output
Response Current
Figure 18. VOUT2 = 1.2V Light Load Efficiency vs Output Figure 19. VOUT3=1.5V, Light Load Efficiency vs Output
Current Current
Figure 20. VOUT1 = 3.3V Switching Frequency vs Input Figure 21. VOUT2 = 1.2V Switching Frequency vs Input
Voltage Voltage
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 13
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400 ns/div
VO2 (10mV/div)
VO = 1.2V
SW2 (5V/div)
400 ns/div
VO = 3.3V
SW1 (5V/div)
VO1 (10mV/div)
400
450
500
550
600
650
700
750
800
850
900
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
fsw - Switching Frequency (kHz)
IO - Output Current (A)
C018
VIN = 12 V
400
450
500
550
600
650
700
750
800
850
900
0 0.5 1 1.5 2 2.5
IO- Output Current (A) C005
V
IN = 12 V
fsw - Switching Frequency (kHz)
400
450
500
550
600
650
700
750
800
850
900
0 2 4 6 8 10 12 14 16 18 20
fsw - Switching Frequency (kHz)
VIN - Input Voltage (V)
C015
IOUT = 1 A
400
450
500
550
600
650
700
750
800
850
900
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
fsw - Switching Frequency (kHz)
IO - Output Current (A)
C016
VIN = 12 V
TPS65580
SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA= 25°C (unless otherwise noted)
Figure 22. VOUT3 = 1.5V Switching Frequency vs Input Figure 23. VOUT1 = 3.3V Switching Frequency vs Output
Voltage current
Figure 24. VOUT2 = 1.2V, Switching Frequency vs Output Figure 25. VOUT3 = 1.5V, Switching Frequency vs Output
Current Current
Figure 26. VOUT1 = 3.3V, VO1 Ripple Voltage at IOUT1 = Figure 27. VOUT2 = 1.2V, Ripple Voltage at IOUT2 = 2.5A
1.5A
14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS65580
VOUT2 (0.5V/div)
EN2 (10V/div)
1 ms/div
VREG5 (5V/div)
PG (5V/div)
VOUT1 (1V/div)
EN1 (10V/div)
1 ms/div
VREG5 (5V/div)
PG (5V/div)
VIN (50mV/div)
SW3(5V/div)
VO = 1.5V
400ns/div
VIN(50mV/div)
SW2(5V/div)
VO = 1.2V
400ns/div
400 ns/div
VO3 (10mV/div)
VO = 1.5V
SW3 (5V/div)
VIN(50mV/div)
SW1(5V/div)
VO = 3.3V
400ns/div
TPS65580
www.ti.com
SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA= 25°C (unless otherwise noted)
Figure 28. VOUT3 = 1.2V, Ripple Voltage at IOUT3 = 1.5A Figure 29. VOUT1 = 3.3V, VIN Ripple Voltage at IOUT1 =
1.5A
Figure 30. VOUT2 = 1.2V VIN Ripple at IOUT2 = 2.5A Figure 31. VOUT3 = 1.5V VIN Ripple at IOUT3 = 1.5A
Figure 32. VOUT1 = 3.3V Soft-Start IOUT1 = 1.5A Figure 33. VOUT2 = 1.2V Soft-Start IOUT2 = 2.5A
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS65580
VOUT3 (0.5V/div)
EN3 (10V/div)
1 ms/div
VREG5 (5V/div)
PG (5V/div)
TPS65580
SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA= 25°C (unless otherwise noted)
Figure 34. VOUT3 = 1.5V Soft-Start IOUT3 = 1.5A
16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS65580
P
1X 2X
1
F
2 L C
=
p ´
OX
R1x
V 0.764 1
R2x
æ ö
= ´ +
ç ÷
è ø
Input Voltage
C21
C11
L11 C31
VO2
R21
R1１R13
R23
C22
PGND
PGND
VO1
C4
L12C32
PGND
SGND SGND
SGND
R12
R22
SGND
L13
C33
VO3
C23
PGND
SW1
VIN
VBST1
EN1
VFB2
EN3
GND
VREG5
PGND1
6
VBST2
SW2
EN2
5
1
3
11
2
4
7
13
12
TPS65580
HTSSOP20
14
8
15
16
(PowerPAD)
VFB1 VFB3
VBST3
SW3
10
9
17
18
19
20
PGND2
PGND3
PG
VIN
TPS65580
www.ti.com
SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
DESIGN GUIDE
Step By Step Design Procedure
To begin the design process, you must know a few application parameters:
• Input voltage range
• Output voltage
• Output current
Figure 35. Schematic Diagram for the Design Example at Vin=12V
Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFBx pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 1 to calculate VOx.
To improve efficiency at very light loads consider using larger value resistors; although, resistance values too
high cause more susceptibility to noise and voltage errors due to the VFBx input current being more noticeable.
(1)
Output Filter Selection
The output filter used with the TPS65580 is an LC circuit. This LC filter has double pole at:
(2)
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPS65580
( )
OX IN OX
C2X(RMS)
IN IX SW
V V V
I12 V L ƒ
´ -
=´ ´ ´
2 2
L1X(RMS) OX L1X
1
I I I
12
= + D
L1X
L1XPEAK OX
I
I I
2
D
= +
IN(MAX) OX
OX
L1X
IN(MAX) SW
V V
V
IV L1x ƒ
-
D = ´
´
TPS65580
SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
www.ti.com
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS65580. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. Advanced D-CAP2™ introduces a high frequency
zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade
above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the
double pole of Equation 2 is located below the high frequency zero but close enough that the phase boost
provided by the high frequency zero provides adequate phase margin for a stable circuit. To meet this
requirement use the values recommended in Table 1.
Table 1. Recommended Component Values
OUTPUT VOLTAGE (V) R1x (kΩ) R2x (kΩ) L1x (µH) C2x (µF)
1 0.68 2.2 1.5 to 3.3 22 - 68
1.05 0.82 2.2 1.5 to 3.3 22 - 68
1.2 1.27 2.2 1.5 to 3.3 22 - 68
1.5 2.15 2.2 1.5 to 3.3 22 - 68
1.8 3.00 2.2 1.5 to 3.3 22 - 68
2.5 4.98 2.2 2.2 to 4.7 22 - 68
3.3 7.36 2.2 2.2 to 4.7 22 - 68
5 12.4 2.2 2.2 to 4.7 22 - 68
6.5 16.5 2.2 2.2 to 4.7 22 - 68
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 3,
Equation 4 and Equation 5. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
For the calculations, use 700 kHz as the switching frequency, fSW. Make sure the chosen inductor is rated for the
peak current of Equation 4 and the RMS current of Equation 5.
(3)
(4)
(5)
For the above design example, the calculated peak current is 2.46 A and the calculated RMS current is 2.02 A.
for Vo1. The inductor used is a TDK CLF7045-1R5N with a rated current of 7.3 A based on the inductance
change and of 4.9A based on the temperature rise.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS65580 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22µF to 68µF. Use Equation 6 to
determine the required RMS current rating for the output capacitor(s).
(6)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩeach.
The calculated RMS current is 0.19A and each output capacitor is rated for 4A.
Input Capacitor Selection
The TPS65580 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10µF × 2 is recommended for the decoupling capacitor. Accordingly, 0.1 µF
ceramic capacitors from pin 1 to ground is recommended to improve the stability and reduce the SWx node
overshoots. The capacitor voltage rating needs to be greater than the maximum input voltage.
18 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS65580
TPS65580
www.ti.com
SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
Bootstrap Capacitor Selection
A 0.1 µF ceramic capacitors must be connected between the VBSTx and SWx pins for proper operation. It is
recommended to use ceramic capacitors with a dielectric of X5R or better.
VREG5 Capacitor Selection
A 1 µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. It is
recommended to use a ceramic capacitor with a dielectric of X5R or better.
Thermal Information
This 20-pin PWP package incorporates an exposed thermal pad that is designed to be directly to an external
heartsick. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heartsick structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, refer to the Technical Brief, PowerPAD™Thermally Enhanced Package, Texas Instruments Literature
No. SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
Figure 36. Thermal Pad Dimensions
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TPS65580
VBST1
VIN
VIN
PGND1
PG
EN1 EN3
SW1
6
VBST2
EN2
SW2
VREG5
5
1
3
13
14
15
PGND3
2
4
7
17
16
18
8
19
20
VIN
VIN HIGH
FREQUENCY
BYPASS
CAPACITOR
～0.1µF
VIN INPUT
BYPASS
CAPACITOR
10µFx2
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
GND PLANE
TO ENABLE
CONTROL
BOOST
CAPACITOR
Keep
distance more
than 1 inch
Recommend to keep
distance more than 3-4mm.
(to avoid noise scattering,
especially GND plane.)
VO2
Feedback
resisters
GND
PLANE
2,3 or bottom
layer
Break Line * Flow of
switching noise.
Switching noise
flows through IC
and Cin.
VFB1
GND
9
10 11
12 VFB3
VBST3
SW3
PGND2
VFB2
OUTPUT
FILTER
CAPACITOR
VO1
OUTPUT
INDUCTOR
VO1
OUTPUT
INDUCTOR
TO ENABLE
CONTROL
Feedback
resisters
Feedback
resisters
VO2
VO3
VO3
GND PLANE
OUTPUT
FILTER
CAPACITOR
TPS65580
SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
www.ti.com
Layout Considerations
1. Keep the input current loop as small as possible. And avoid the input switching current through the thermal
pad.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching currents to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder.
8. VREG5 capacitor should be placed near the device, and connected to PGND.
9. Output capacitors should be connected with a broad pattern to the PGND.
10. Voltage feedback loops should be as short as possible, and preferably with ground shield.
11. Kelvin connections should be brought from the output to the feedback pin of the device.
12. Providing sufficient vias is preferable for VIN, SW and PGND connection.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. VIN Capacitor should be placed as near as possible to the device.
Figure 37. TPS65580 Layout
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TPS65580
www.ti.com
SLVSC29B –SEPTEMBER 2013–REVISED DECEMBER 2013
REVISION HISTORY
Page numbers of current version may differ from previous versions.
Changes from Original (September 2013) to Revision A Page
• Added text to Current Protection section for clarification. ..................................................................................................... 9
• Added text to Output Voltage Resistors Selection for clarification. .................................................................................... 17
• Corrected resistor R1x (kΩ) values in Table 1. .................................................................................................................. 18
Changes from Revision A (September 2013) to Revision B Page
• Added VOVP specification to ELEC CHARA, OVER / UNDER VOLTAGE PROTECTION ................................................... 5
• Added Overvoltage Protection description. .......................................................................................................................... 8
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 21
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PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS65580PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS65580
TPS65580PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS65580
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2017
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS65580PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Dec-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS65580PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Dec-2013
Pack Materials-Page 2
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