www.chipinfo.ru intel. MCS 51 8-BIT CONTROL-ORIENTED MICROCONTROLLERS Commercial/Express 803 1AH/8051AH/8051AHP 8032AH/8052AH 8751H/8751H-8 8751BH/8752BH High Performance HMOS Process m@ Booiean Processor Internal Timers/Event Counters m@ Bit-Addressable RAM 2-Level Interrupt Priority Structure 32 I/O Lines (Four 8-Bit Ports) Programmable Full Duplex Serial Channel 64K External Program Memory Space @ 111 Instructions (64 Single-Cycle) Security Feature Protects EPROM Parts 64K External Data Memory Space Against Software Piracy m@ Extended Temperature Range ( 40C to + 85C) The MCS 51 controllers are optimized for control applications, Byte-processing and numerical operations on small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instruc- tions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit manipulation and testing in control and logic systems that require Boolean processing. The 8751H is an EPROM version of the 8051AH. It has 4 Kbytes of electrically programmable ROM which can be erased with ultraviolet light. It is fully compatible with the 8051AH but incorporates one additional feature: a Program Memory Security bit that can be used to protect the EPROM against unauthorized readout. The 8751H-8 is identical to the 8751H but only operates up to 8 MHz. The 8051AHP is identical to the 8051AH with the exception of the Protection Feature. To incorporate this Protection Feature, program verification has been disabled and external memory accesses have been limited to 4K. The 8052AH is an enhanced version of the 8051AH. It is backwards compatible with the 8051AH and is fabricated with HMOS |! technology. The 8052AH enhancements are listed in the table below. Also refer to this table for the ROM, ROMless and EPROM versions of each product. Internal Memory Timers/ Device prooram Data Event Counters interrupts 8031AH none 128 x 8 RAM 2 x 16-Bit 5 8051AH 4K x8 ROM 128 x 8 RAM 2x 16-Bit 5 8051 AHP 4K x8 ROM 128 x 8 RAM 2x 16-Bit 5 8751H 4K x8 EPROM 128 x8 RAM 2x 16-Bit 5 8751H-8 4K x 8 EPROM 128 x 8 RAM 2x 16-Bit 5 8751BH 4K x8 EPROM 128 x 8 RAM 2x 16-Bit 5 8032AH none 256 x 8 RAM 3x 16-Bit 6 8052AH BK x 8 ROM 256 x 8 RAM 3x 16-Bit 6 8752BH BK x 8 EPROM 256 x 8 RAM 3x 16-Bit 6 October 1993 Order Number: 272318-001 2-21 Be sure to visit CHIPINFO web site for more information.MCS 51 CONTROLLER L rk PO0.0-Po.7 P2.0-P2 7 ab beaS Shannen PORT 0 PORT 2 ORIVERS ORIVERS ee eh | [gs | a RAM | ge PORT PORT 2 EPROM | LATCH LATCH ROM i ifpit ut Yt | 177 i ig: | PROGRAM ace STACK 'ADDA | POINTER REGISTER | it | af 8 ' BUFFER | | necister rwr2 TP! K_) | | Mw PCON [SCON]TMOD] TCON ALU T2con | To ] mo fT PC | - INCREMENTER ! TL | TH2 | TL2" [RCAPSH ACAPaL | seur| t | [ow | INTERRUPT, SERIAL PROGRAM PORT AND TIMER BLOCKS counter = g it it ALE =} THANG i _ AND ? g K opta EA CONTROL eT o | PORT 1 PORT 3 | LATCH LATCH | | osc | PORT 1 PORT 3 L RIVERS ORIVERS xtact Lia, mans TT rn THI TO C] everer P10-F17 P30-PI.7 272318-1 Figure 1. MCS 51 Controller Block Diagram PROCESS INFORMATION The 8031AH/8051AH and 8032AH/8052AH devic- es are manufactured on P414.1, an cess. The 8751H/8751H-8 devices HMOS II pro- are manufac- tured on P421.X, an HMOS-E process. The 8751BH and 8752BH devices are manufactured on P422. Additional process and reliability information is avail- able in Intel's Components Quality and Reliability Handbook, Order No. 210997. 2-22 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.B intel : MCS 51 CONTROLLER PACKAGES Part Prefix Package Type Oia Ae 8051AH P 40-Pin Plastic DIP 45C/W 16C/W 8031AH D 40-Pin CERDIP 45C/W 15C/W 8052AH N 44-Pin PLCC 46C/W 16C/W 8032AH 8752BH* 8751H D 40-Pin CERDIP 45C/W 15C/W 8751H-8 8051 AHP P 40-Pin Plastic DIP 45C/W 16C/W D 40-Pin CERDIP 45C/W 15C/W 8751BH P 40-Pin Plastic DIP 36C/W 12C/W N 44-Pin PLCC 47C/W 16C/W NOTE: 2 *8752BH is 36/10 for D, and 38/22 for N. All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number 240800) for a description of Intels thermal impedance test methodology. . www.chipinfo.ru Be sure to visit CHIPINFO web site for more information. 8052/8032 ONLY 7 T2 POC 40 Veg a 8588 T2EX P11 O)2 39] P0.0 ADO INDEX cb c < = s P1203 3617 P01 aD1 CORNER PS SSS 8S 5 Pi3C4 377) Po.2 apz face Seeee Pras 36 [> P0.3 ADS OPitia sos eee P1516 35 [F Po.4 ADS PIs [7 38] P0.4 (AD4) P16()7 34D P05 ADS P16 | [4] P06 (ADS) P1L7Cle8 33 [2 P0.6 A06 P17 [83 <37] PO.6 (ADS) RST C9 325 0.7 AD7 AST fis? 136] PO.7 (AD?) RXD P3.0 C10 8X5X 31[7 EA/Vpp" (RXD) P3.0 Fi; [34] EA/Vpp* THO P3.1 C14 5 30[F ALE/-PROG' Reserved** [1:7 BX5X (# ] Reeerved** INTO P3.2 C) 12 29 (7) PSEN (TXD) Pat bia: 33] ALE/PROG" INT1 P3.3 CQ 13 a) P27 Als (INTO) P32 ia} 03] PSEN TO P3.4 CJ 14 277) p2. gate (INT1) Pag {3 3] 2.7 (ats) Ti P3. 1115 267 P2.s aia 2: oa (To) P3.e [337 136] P26 (A14) WR P3.6 Cl] 16 2517) P2.4 ai2 (72) Pas fas: 36] P25 (A13 AD P3.7. C17 2475 P23 At Os ect yet en re en eg ght] PABA) XTAL2 Cl 18 2315 P2.2 A10 FE RR aa MTALi C19 22(F P2.1 ag sada 8:85 * Vss Cj 20 217 p20 as gees sages @a2eoerew ze SS225 272318-2 DIP PLCC *EPROM only **Do not connect reserved pins. Figure 2. MCS 51 Controller Connections 2-23www.chipinfo.ru MCS 51 CONTROLLER PIN DESCRIPTIONS Vec: Supply voltage. Vgs: Circuit ground. Port 0: Port 0 is an 8-bit open drain bidirectional |/O port. As an output port each pin can sink 8 LS TTL inputs. Port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong inter- nal pultups when emitting 1's and can source and sink 8 LS TTL inputs. Port 0 also receives the code bytes during program- ming of the EPROM parts, and outputs the code bytes during program verification of the ROM and EPROM parts. External pullups are required during program verification. Port 1: Port 1 is an 8-bit bidirectional 1/O port with internal pullups. The Port 1 output buffers can sink/ source 4 LS TTL inputs. Port 1 pins that have 1's written to them are pulled high by the internal puil- ups, and in that state can be used as inputs. As inputs, Pert 1 pins that are externally pulled low will source current (Ij, on the data sheet) because of the internal pullups. Port 1 also receives the low-order address bytes during programming of the EPROM parts and during program verification of the ROM and EPROM parts. in the 8032AH, 8052AH and 8752BH, Port 1 pins P1.0 and P1.1 also serve the T2 and T2EX func- tions, respectively. intel. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX @DPTR). in this application it uses strong internal pullups when emitting 1s. Dur- ing accesses to external Data Memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits dur- ing programming of the EPROM parts and during program verification of the ROM and EPROM parts. The protection feature of the 8051AHP causes bits P2.4 through P2.7 to be forced to 0, effectively limit- ing externat Data and Code space to 4K each during external accesses. Port 3: Port 3 is an 8-bit bidirectional 1/O port with internal pullups. The Port 3 output buffers can sink/ source 4 LS TTL inputs. Port 3 pins that have 1s written to them are pulled high by the internal pull- ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled low witl source current (lj, on the data sheet) because of the pullups. Port 3 also serves the functions of various special features of the MCS 51 Family, as listed below: Port Alternative Function Pin P3.0 | RXD (serial input port) P3.1 TXD (serial output port) P3.2 | INTO (external interrupt 0) P3.3 | iNT? (external interrupt 1) P3.4 TO (Timer 0 external input) P3.5 T1 (Fimer 1 external input) P3.6 | WR (external data memory write strobe) P3.7 | RD (external data memory read strobe) Port Alternative Function Pin P1.0 T2 (Timer/Counter 2 External Input) P1.4 T2EX (Timer/Counter 2 Capture/Reload Trigger) Port 2: Port 2 is an 8-bit bidirectional |1/O port with internal pullups. The Port 2 output buffers can sink/ source 4 LS TTL inputs. Port 2 pins that have 1s written to them are pulled high by the internal pull- ups, and in that state can be used as inputs. As inputs, Port 2 pins that are externaily pulled low will source current (Ij_ on the data sheet) because of the internal puilups. 2-24 Be sure to visit CHIPINFO web site for more information. RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the de- vice. ALE/PROG: Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during programming of the EPROM parts. In normal operation ALE is emitted at a constant rate of 1% the oscillator frequency, and may be used for external timing or clocking purposes. Note, how- ever, that one ALE pulse is skipped during each ac- cess to external Data Memory.www.chipinfo.ru a intel. PSEN: Program Store Enable is the read strobe to external Program Memory. When the device is executing code from external Program Memory, PSEN is activated twice each ma- chine cycle, except that two PSEN activations are skipped during each access to external Data Memo- ry. EA/Vpp: External Access enable EA must be strapped to Vgg in order to enable any MCS 51 de- vice to fetch code from external Program memory locations starting at OOOOH up to FFFFH. EA must be strapped to Vcc for internal program execution. Note, however, that if the Security Bit in the EPROM devices is programmed, the device will not fetch code from any location in external Program Memory. This pin also receives the programming supply volt- age (VPP) during programming of the EPROM parts. c2 T_ XTAL2 Cc) _I | XTALt C1 vSS 272918-3 C1, C2 = 30 pF +10 pF for Crystals For Ceramic Resonators contact resonator manufacturer. Figure 3. Oscillator Connections XTAL1: Input to the inverting oscillator amplifier. XTAL2: Output from the inverting oscillator amplifi- er. OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respec- tively, of an inverting amplifier which can be config- ured for use as an on-chip oscillator, as shown in Figure 3. Either a quartz crystal or ceramic resonator may be used. More detailed information concerning the use of the on-chip oscillator is available in Appli- cation Note AP-155, Oscillators for Microcontrol- lers, Order No. 230659. MCS 51 CONTROLLER To drive the device from an external clock source, XTAL1 should be grounded, while XTAL2 is driven, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. EXTERNAL OSCILLATOR 4._ x Tai 2 SIGNAL XTAL1 272318-4 Figure 4, External Drive Configuration EXPRESS Version The Intel EXPRESS system offers enhancements to the operational specifications of the MCS 51 family of microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose operating requirements exceed commercial standards. The EXPRESS program includes the commercial standard temperature range with burn-in, and an ex- tended temperature range with or without burn-in. With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of OC to + 70C. With the ex- tended temperature range option, operational char- acteristics are guaranteed over a range of 40C to + 85C. The optional burn-in is dynamic, for a minimum time of 160 hours at 125C with Vcc = 5.5V +0.25V, following guidelines in MIL-STD-883, Method 1015. Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The prefixes are listed in Table 1. For the extended temperature range option, this data sheet specifies the parameters which deviate from their commercial temperature range limits. 2-25 Be sure to visit CHIPINFO web site for more information.MCS 51 CONTROLLER intel. Table 1, EXPRESS Prefix identification Prefix Package Type Temperature Range Burn-in P Plastic Commercial No D Cerdip Commercial! No N PLCC Commercial! No TD Cerdip Extended No TP Plastic Extended No TN PLCC Extended No QP Plastic Commercial Yes QD Cerdip Commercial Yes LO Cerdip Extended Yes LP Plastic Extended Yes NOTE: Contact distributor or local sales office to match EXPRESS prefix with proper device. DESIGN CONSIDERATIONS If an 8751BH or 8752BH is replacing an 8751H in a future design, the user should carefully com- pare both data sheets for DC or AC Characteris- tic differences. Note that the Vj and |) specifi- cations for the EA pin differ significantly between the devices. Exposure to light when the EPROM device is in operation may cause logic errors. For this reason, it is suggested that an opaque label be placed over the window when the die is exposed to am- bient light. 2-26 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information. The 8051AHP cannot access external Program or Data memory above 4K. This means that the following instructions that use the Data Pointer only read/write data at address locations below OFFFH: MOVX A,@DPTR MOVX @DPTR, A When the Data Pointer contains an address above the 4K limit, those locations will not be ac- cessed. To access Data Memory above 4K, the MOVX @Ri,A or MOVX A,@Ri instructions must be used.a intel MCS 51 CONTROLLER ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. It is valid for ; ; the devices indicated in the revision history. The Ambient Temperature Under Bias . 40C to + 85C specifications are subject to change without notice. Storage Temperature .......... 65C to + 150C = * WARNING: Stressing the device beyond the Absolute Voltage on EA/Vpp Pin to Vss Maximum Ratings may cause permanent damage. 8751H 05V to + These are stress ratings only. Operation beyond the Torres r esses seen es 0.5V to +21.5V Operating Conditions is not recommended and ex- 8751BH/8752BH ............ ~0.5V to +13.0V tended exposure beyond the Operating Conditions Voltage on Any Other Pinto Vgg ....0.5Vto +7V. '4Y affect device reliability. Power Dissipation.........: eee caer e eee 1.5W OPERATING CONDITIONS Symbol Description Min Max Units Ta Ambient Temperature Under Bias Commercial 0 +70 C Express -40 +85 C Voc Supply Voltage 45 5.5 v Fosc Oscillator Frequency 3.5 12 MHz DC CHARACTERISTICS (Over Operating Conditions) All parameter values apply to all devices unless otherwise indicated Symbol Parameter Min Max Units | Test Conditions ViL Input Low Voltage (Except EA Pin of 0.5 0.8 V 8751H and 8751H-8) Vind Input Low Voltage to EA Pin of 0 0.7 V 8751H and 8751H-8 Vid Input High Voltage (Except XTAL2, RST) 2.0 | Voc + 0.5 Vv View Input High Voltage to XTAL2, RST 2.5 | Vcc +05] V_ | XTAL1 = Vgg Vine input High Voltage to EA pin 4.5 5.5V of 8751BH and 8752BH VoL Output Low Voltage (Ports 1, 2, 3)* 0.45 Vv lo. = 1.6mA Voui Output Low Voltage (Port 0, ALE, PSEN)* 8751H, 8751H-8 0.60 Vv lo. = 3.2 mA 0.45 Vv lol = 2.4mA All Others 0.45 Vv lo. = 3.2 mA Vou Output High Voltage (Ports 1, 2, 3, ALE, PSEN) 2.4 Vv lon = 80 pA Von Output High Voltage (Port 0 in 2.4 Vv lon = 400 pA External Bus Mode) Hie Logical 0 Input Current (Ports 1, 2, 3, and RST) 500 BHA | Vin = 0.45V hua Logical 0 Input Current (EA) 8751H and 8751H-8 15 mA | Vin = 0.45V 8751BH ~10 mA | Vin = Vss 8752BH 10 mA | Vin = Vss 0.5 mA 2-27 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.MCS 51 CONTROLLER intel DC CHARACTERISTICS (Over Operating Conditions) All parameter values apply to ail devices unlass otherwise indicated (Continued) Symbol Parameter Min | Max | Units | Test Conditions lite Logical 0 Input Current (XTAL2) -3.2 |} mA | Vin = 0.45V iu Input Leakage Current (Port 0) 8751H and 8751H-8 100 | pA | 0.45<Vin< Voc All Cthers 10 BA | 0.45 < Vin = Voc hy Logical 1 Input Current (EA) 8751H and 8751H-8 500 pA | Vin = 2.4V 8751BH/8752BH 1 mA | 4.5V < Vin < 5.5V lie Input Current to RST to Activate Reset 500 HA | Vin < (Voc 1.5) loc Power Suppty Current: 8031AH/8051AH/8051AHP 125 mA _ | All Outputs 8032AH/8052AH/8751BH/8752BH 176 mA | Disconnected; 8751H/8751H-8 250 mA | EA= Vcc Cio Pin Capacitance 40 pF | Test freq = 1 MHz NOTES: 1. Capacitive loading on Ports and 2 may cause spurious noise pulses to be superimposed on the Vo_s of ALE/PROG and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE/PROG pin may exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 2. ALE/PROG refers to a pin on the 8751BH. ALE refers to a timing signal that is output on the ALE/PROG pin. 3. Under steady state (non-transient) conditions, Io, must be externally limited as follows: Maximum Io, per port pin: 10 mA Maximum Io, per 8-bit port - Port 0: 26 mA Ports 1, 2, and 3: 15 mA Maximum total Io for all output pins: 71 mA If Io, exceeds the test condition, Vo, may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2-28 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.intel. EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters. The first char- acter is always a T (stands for time). The other characters, depending on their positions, stand for the name of a signal or the fogical status of that signal. The following is a list of all the characters and what they stand for. A: Address C: Clock D: Input Data H: Logic level HIGH I: Instruction (program memory contents) MCS 51 CONTROLLER L: Logic level LOW, or ALE P: PSEN Q: Output data R: RD signal T: Time V: Valid W: WR signal X: No longer a valid logic level 2: Float TAVLL TLLPL For example, Ho ime from Address Valid to ALE Low. ime from ALE Low to PSEN Low. a AC CHARACTERISTICS (Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF) EXTERNAL PROGRAM MEMORY CHARACTERISTICS Symbol Parameter 12 MHz Oscillator Variable Oscillator Units Min Max Min Max 1/TCLCL | Oscillator Frequency 3.5 12.0 MHz TLHLL ALE Pulse Width 127 2TCLCL40 ns TAVLL Address Valid to ALE Low 43 TCLCL 40 ns TLLAX Address Hold after ALE Low 48 TCLCL35 ns TLLIV ALE Low to Valid Instr In 8751H 183 4TCLCL 150 ns All Others 233 4TCLCL 100 ns TLLPL ALE Low to PSEN Low 58 TCLCL 25 ns TPLPH PSEN Pulse Width 8751H 190 3TCLCL60 ns All Others 215 3TCLCL35 ns TPLIV PSEN Low to Valid Instr In 8751H 100 3TCLCL 150 ns All Others 125 3TCLCL 125 ns TPXIX Input Instr Hold after PSEN 0 0 ns TPXIZ input Instr Float after PSEN 63 TCLCL 20 ns TPXAV PSEN to Address Valid 75 TCLCL-8 ns TAVIV Address to Valid Instr In 8751H 267 5TCLCL 150 ns All Others 302 5TCLCL 115 ns TPLAZ PSEN Low to Address Float 20 20 ns TRLRH RD Pulse Width 400 6TCLCL 100 ns TWLWH_| WR Pulse Width 400 6TCLCL 100 ns TRLDV RD Low to Valid Data In 252 5TCLCL 165 ns TRHDX Data Hold after RO 0 0 ns TRHDZ Data Float after RD 97 2TCLCL-70 ns TLLDV ALE Low to Valid Data In 517 8TCLCL 150 ns TAVDV Address to Valid Data In 585 9TCLOL 165 ns www.chipinfo.ru Be sure to visit CHIPINFO web site for more information. 2-29MCS 51 CONTROLLER EXTERNAL PROGRAM MEMORY CHARACTERISTICS (Continued) in tel. Symbol Parameter 12 MHz Oscillator Variable Osclilator Units Min Max Min Max TLLWL | ALE Low to RD or WR Low 200 300 3TCLCL50 | 3TCLCL+50 ns TAVWL | Address to RD or WR Low 203 4TCLCL 130 ns TQVWX | Data Vatid to WR Transition 8751H 13 TCLCL70 ns All Others 23 TCLCL60 ns TQVWH | Data Vaiid to WR High 433 7TCLCL 150 ns TWHOQX | Data Hold after WR 33 TCLCL 50 ns TRLAZ | RD Low to Address Float 20 20 ns TWHLH | RD or WR High to ALE High 8751H 33 133 TCLCL-50 TCLCL + 50 ns All Others 43 123 TCLCL 40 TCLOL + 40 ns NOTE: The 8751H-8 is identical to the 8751H but only operates up to 8 MHz. When calculating the AC Characteristics for the 8751H-8, use the 8751H formula for variable oscillators. 2-30 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.J intel MCS 51 CONTROLLER EXTERNAL PROGRAM MEMORY READ CYCLE TLHLL ALE TLLPL TAVLL TPLPH TELLIV PSEN TPLIV TPXAV TPXIZ TPLAZ TPXIX PORT 0 INSTR IN PORT 2 2723918~-E EXTERNAL DATA MEMORY READ CYCLE ALE PSEN TLLDV RO TRHDZ TLLAX TRHDX PORT 0 AO-A7 FROM RI OR DPL DATA IN AQ-A7 FROM PCL INSTR. IN TAVWL TAYDV PORT 2 P2.0-P2.7 OR AB-A1S FROM DPH AB-A15 FROM PCH 272318-6 EXTERNAL DATA MEMORY WRITE CYCLE ALE PSEN TWHOX TQVWH PORTO DATA OUT AQ-A7 FROM PCL INSTR. IN TAVWL PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A8-A1S FROM PCH 272318-7 2-31 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.MCS 51 CONTROLLER SERIAL PORT TIMINGSHIFT REGISTER MODE Test Conditions: Over Operating Conditions; Load Capacitance = 80 pF intel. Symbol Parameter 12 MHz Oscillator Variable Oscillator Units Min Max Min Max TXLXL | Serial Port Clock Cycle Time 1.0 12TCLCL BS TQVXH | Output Data Setup to Clock Rising 700 {OFCLCL 133 ns Edge TXH@X | Output Data Hold after Clock 50 2TCLCL117 ns Rising Edge TXHDX | input Data Hold after Clock Rising 0 0 ns Edge TXHDV | Clock Rising Edge to Input Data 700 JOTCLCL133] ns Valid SHIFT REGISTER MODE TIMING WAVEFORMS INSTRUCTION | 2 Os 1 } 2 | 3 | 4 5 | 6 | 7 8 | [oT TXLXL-y clock LI LI ! LT LT 1 L_/f Lf tava | pe TXHOX | OUTPUT DATA Xo 1% + 1K 2 KX 3 4 xX 5 X 6 7 f am wl He TXHDX 4 WRITE TO SBUF TXHDV SET TI INPUT OATA aco (vatio) ALD TD) DLT) GD TT) GD TE t CLEAR RI SET RI 272318-8 2-32 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.intel. EXTERNAL CLOCK DRIVE MCS 51 CONTROLLER Symbol Parameter Min Max Units 1/TCLCL Oscillator Frequency (except 8751H-8) 3.5 12 MHz 8751H-8 3.5 8 MHz TCHCX High Time 20 ns TCLCOX Low Time 20 ns TCLGH Rise Time 20 ns TCHCL Fall Time 20 ns EXTERNAL CLOCK DRIVE WAVEFORM TCHCX TOLCH ~> p= he} ee TCHCL 2.5 J 2.5 / 2.5 0.8 0.8 q p* TCLOX } a TCLCL > 272318-9 AC TESTING INPUT, OUTPUT WAVEFORM 4 2.0 20 x > TEST POTS < 0.8 08 0.45 272318-10 AC Tasting: Inputs are driven at 2.4V for a Logic '1" and 0.45V for a Logic O". Timing measurements are made at 2.0V for a Logic 1 and 0.8V for a Logic 0. 2-33 | www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.www.chipinfo.ru MCS 51 CONTROLLER EPROM CHARACTERISTICS Table 3. EPROM Programming Modes Mode RST PSEN ALE EA P2.7 P2.6 P2.5 P2.4 Program 1 0 o* VPP 1 0 x Xx Verity 1 0 1 1 0 0 x x Security Set 4 0 0* VPP 1 1 x x NOTE: 1 = logic high for that pin VPP = +21V +0.5V 0 = Ingic low for that pin *ALE is pulsed low for 50 ms. xX = dont care PROGRAMMING THE 8751H Note that the EA/VPP pin must not be allowed to go To be programmed, the part must be running with a 4 to 6 MHz oscillator. (The reason the oscillator needs to be running is that the internal bus is being used to transfer address and program data to appro- priate internal registers.) The address of an EPROM location to be programmed is applied to Port 1 and pins P2.0-P2.3 of Port 2, while the code byte to be programmed into that location is applied to Port 0. The other Port 2 pins, and RST, PSEN, and EA/Vpp should be held at the Program levels indicated in Table 3. ALE/PROG is pulsed low for 50 ms to pro- gram the code byte into the addressed EPROM lo- cation. The setup is shown in Figure 5. Normally EA/Vpp is held at a logic high until just before ALE/PROG is to be pulsed. Then EA/Vpp is raised to +21V, ALE/PROG is pulsed, and then EA/Vpp is returned to a logic high. Waveforms and detailed timing specifications are shown in later sec- tions of this data sheet. +5V vec J AQ-AT Pi OOOOH-OFFFH e Po; PGM DATA 2.0 AB-A11 P23 8751H KX w] P24 X = DON'T CARE __ Kw] P25 ALE ALE PROG Vi ] P26 50 ms PULSE TO GND Vi ewd P27 KTAL2 EA b EA VPP a 3 XTALI RST ee VIH1 H vss PSEN Py a ot a-emnz } L4 272318-11 Figure 5. Programming Configuration 2-34 Be sure to visit CHIPINFO web site for more information. above the maximum specified VPP level of 21.5V for any amount of time. Even a narrow glitch above that voltage level can cause permanent damage to the device. The VPP source should be well regulated and free of glitches. Program Verification If the Security Bit has not been programmed, the on- chip Program Memory can be read out for verifica- tion purposes, if desired, either during or after the programming operation. The address of the Program Memory location to be read is applied to Port 1 and pins P2.0P2.3. The other pins should be held at the Verify levels indicated in Table 3. The contents of the addressed location will come out on Port 0. Ex- ternal pullups are required on Port 0 for this opera- tion. The setup, which is shown in Figure 6, is the same as for programming the EPROM except that pin P2.7 is held at a logic low, or may be used as an active- iow read strobe. vcc J PI PGM Po r\. pata P20 my {USE 10K 623 PULLUPS) e7S5iH Xe] Pe X= "DON'T CARE x e] P2 @LE VEL ] P26 o VIM ENABLE * P27 EA XTAL2 a ae 4-6Hz (C3 TA RST Po VIHI a E | XTALI r SS PSEN al 272318-12 Figure 6. Program Verificationwww.chipinfo.ru intel. EPROM Security The security feature consists of a locking bit which when programmed denies electrical access by any external means to the on-chip Program Memory. The bit is programmed as shown in Figure 7. The setup and procedure are the same as for normal EPROM programming, except that P2.6 is held ata logic high. Port 0, Port 1 and pins P2.0-P2.3 may be in any state. The other pins should be held at the Security levels indicated in Table 3. Once the Security Bit has been programmed, it can be cleared only by full erasure of the Program Mem- ory. While it is programmed, the internal Program Memory can not be read out, the device can not be further programmed, and it can not execute out of external program memory. Erasing the EPROM, thus clearing the Security Bit, restores the devices full functionality. It can then be reprogrammed. Erasure Characteristics Erasure of the EPROM begins to occur when the device is exposed to light with wavelengths shorter than approximately 4,000 Angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an ex- tended time (about 1 week in sunlight, or 3 years in room-levei fluorescent lighting) could cause inadver- tent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. MCS 51 CONTROLLER +5 X = "DON'T CARE vec J _ PI Po Ko x P2.0- x = P23 eysiM ] P24 ALE 7= ALE PROG 50 ms PULSE TO GNO i P25 P26 woe Lg P27 EA - EA vp XTAL2 ci RST -o Vint XTAL1 vss PSEN r] 272318-13 Figure 7. Programming the Security Bit The recommended erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to an integrat- ed dose of at least 15 W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000 4W/cm2 rating for 20 to 30 minutes, at a distance of about 1 inch, should be sufficient. Erasure leaves the array in an all 1s state. EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS Ta = 21C to 27C; VCC = 5V +10%; VSS = OV | Symbol Parameter Min Max Units VPP Programming Supply Voltage 20.5 21.5 Vv IPP Programming Supply Current 30 mA 1/TCLCL Oscillator Frequency 4 6 MHz TAVGL Address Setup to PROG Low 48TCLCL TGHAX Address Hold after PROG 48TCLCL TDVGL Data Setup to PROG Low 48TCLCL TGHDX Data Hold after PROG 48TCLCL TEHSH P2.7 (ENABLE) High to VPP 48TCLCL TSHGL VPP Setup to PROG Low 10 us TGHSL VPP Hold after PROG 10 pS TGLGH PROG Width 45 55 ms TAVQV Address to Data Valid 48TCLCL TELQV ENABLE Low to Data Valid 48TCLCL TEHQZ Data Float after ENABLE 0 48TCLCL 2-35 Be sure to visit CHIPINFO web site for more information.MCS 51 CONTROLLER EPROM PROGRAMMING AND VERIFICATION WAVEFORMS PROGRAMMING VERIFICATION P1.0-P1.7 2.0-62.3 ADDRESS ADDRESS Tavay PORT 0 * DATA IN \. DATA OUT y , TOVGL -a} +| TGHOX TAVGL > <} TGHAX ALE/PROG rn \ TS + + >| TGHSL NGL TGLGH 21V = SV _ TTL HIGH TTL HIGH TTL HIGH TTL HIGH EA/vep TENSH <a - TELQV -w] ee ye TET P27 (ENABLE) \ A Fer programming conditions see Figure 5. 272318-14 For verification conditions see Figure 6. 2-36 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.intel. Programming the 8751BH/8752BH To be programmed, the 875XBH must be running with a 4 to 6 MHz oscillator. (The reason the oscilla- tor needs to be running is that the internal bus is being used to transfer address and program data to appropriate internal registers.) The address of an EPROM location to be programmed is applied to Port 1 and pins P2.0 - P2.4 of Port 2, while the code byte to be programmed into that location is applied to Port 0. The other Port 2 and 3 pins, and RST, PSEN, and EA/Vpp should be held at the Program levels indicated in Table 1. ALE/PROG is pulsed low to program the code byte into the addressed MCS 51 CONTROLLER Normally EA/Vpp is held at a logic high until just before ALE/ PROG is to be pulsed. Then EA/Vpp is raised to Vpp, ALE/PROG is pulsed low, and then EA/Vpp is returned to a valid high voitage. The volt- age on the EA/Vpp pin must be at the valid EA/Vpp high level before a verify is attempted. Waveforms and detailed timing specifications are shown in later sections of this data sheet. Note that the EA/Vpp pin must not be allowed to go above the maximum specified Vpp level for any amount of time. Even a narrow glitch above that volt- age level can cause permanent damage to the de- vice. The Vpp source should be well regulated and EPROM location. The setup is shown in Figure 8. free of glitches. +5 Yee AQTA7 yt Po KFarpara 1 py RST EA/Vpp [= + 12.759 ALE/PROG w= 25 100 us PULSES TO GND 1p} P3.6 f * a75xBH SEN }+-9 {pl P37 P2.7 [nee Ta XTALZ P2.6 }_0 P2.0 Ce XTAL 1 Poa AS-AtZ 272318-15 Figure 8. Programming the EPROM Table 4. EPROM Programming Modes for 875XBH ALE/ EA/ MODE RST PSEN PROG Vpp P2.7 P2.6 P3.6 P3.7 Program Code Data 1 0 0 Vpp 1 0 1 1 Verify Code Data 1 0 1 1 0 0 1 1 Program Encryption Tabie 1 0 of Vpp 1 0 0 1 Use Addresses 0-1FH Program Lock x=1 1 0 0 Vpp 1 1 1 1 Bits (LBx) x=2 1 0 0* Vpp 1 1 Read Signature 1 0 1 1 0 0 0 0 NOTES: " = Vaiid high for that pin QO = Valid low for that pin Vpp" = +12.75V +0.25V *ALE/PROG is pulsed low for 100 uS for programming. (Quick-Pulse Programming) 2-37 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.www.chipinfo.ru MCS 51 CONTROLLER QUICK-PULSE PROGRAMMING ALGORITHM The 875XBH can be programmed using the Quick- Pulse Programming Algorithm for microcontrollers. The features of the new programming method are a lower Vpp (12.75 volts as compared to 21 volts) and a shorter programming pulse. For example, it is pos- sible to program the entire 8 Kbytes of 875XBH EPROM memory in less than 25 seconds with this algorithm! To program the part using the new algorithm, Vpp must be 12.75 +0.25 Volts. ALE/PROG is pulsed low for 100 pseconds, 25 times as shown in Figure 9. Then, the byte just programmed may be verified. After programming, the entire array should be verified. The Program Lock features are pro- grammed using the same method, but with the setup as shown in Table 4. The only difference in program- ming Lock features is that the Lock features cannot be directly verified. Instead, verification of program- ming is by observing that their features are enabled. intel. PROGRAM VERIFICATION lf the Lock Bits have not been programmed, the on- chip Program Memory can be read out for verifica- tion purposes, if desired, either during or after the programming operation. The address of the Program Memory location to be read is applied to Port + and pins P2.0 - P2.4. The other pins should be held at the Verify levels indicated in Table 1. The con- tents of the addressed location will come out on Port 0. External pullups are required on Port 0 for this operation. (if the Encryption Array in the EPROM has been programmed, the data present at Port 0 will be Code Data XNOR Encryption Data. The user must know the Encryption Array contents to manual- ly unencrypt the data during verify.) The setup, which is shown in Figure 10, is the same as for programming the EPROM except that pin P2.7 is held at a logic low, or may be used as an active low read strobe. ALE/PROG : ALE/PROG : LU ULL | | {|:-- 100 ps 10 ys MIN us *| 10 us 1 rT mes | | 272318-16 Figure 9. PROG Waveforms +5 1Okn Voc 18 7 PGM AO-A7 Pt PO DATA 1$p] RST EA/Vpp }+- 1 ALE/PROG 1] P3.6 a7sxen PSEN ft-- 0 1 PEPS.7 P2.7 he0 (ENABLE) rr XTAL 2 P2.6 h 0 4-6 MHz C bh Lr P2.0 - + XTAL 1 opp AB-AIZ ss 7 272318-17 Figure 10. Verifying the EPROM 2-38 Be sure to visit CHIPINFO web site for more information.intel. PROGRAM MEMORY LOCK The two-level Program Lock system consists of 2 Lock bits and a 32-byte Encryption Array which are used to protect the program memory against soft- ware piracy. ENCRYPTION ARRAY Within the EPROM array are 32 bytes of Encryption Array that are initially unprogrammed (all 1s). Every time that a byte is addressed during a verify, 5 ad- dress lines are used to select a byte of the Encryp- tion Array. This byte is then exclusive-NORed (XNOR) with the code byte, creating an Encrypted Verify byte. The algorithm, with the array in the un- programmed state (all 1s), will return the code in its original, unmodified form. It is recommended that whenever the Encryption Ar- ray is used, at least one of the Lock Bits be pro- grammed as well. LOCK BITS Also included in the EPROM Program Lock scheme are two Lock Bits which function as shown in Table 5. Erasing the EPROM also erases the Encryption Ar- ray and the Lock Bits, returning the part to full un- locked functionality. To ensure proper functionality of the chip, the inter- nally latched value of the EA pin must agree with its external state. www.chipinfo.ru MCS 51 CONTROLLER Table 5. Lock Bits and their Features Lock Bits Logic Enabled LB1 LB2 U U {Minimum Program Lock features enabled. (Code Verify will still be encrypted by the Encryption Array) MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the EPROM is disabled P P |Same as above, but Verify is also disabled U P Reserved for Future Definition P = Programmed U = Unprogrammed READING THE SIGNATURE BYTES The signature bytes are read by the same procedure as a normal verification of locations O30H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values returned are: (030H) = 89H indicates manufactured by Intel (031H) = 51H indicates 8751BH 52H indicates 8752BH 2-39 Be sure to visit CHIPINFO web site for more information.MCS 51 CONTROLLER ERASURE CHARACTERISTICS Erasure of the EPROM begins to occur when the 8752BH is exposed to light with wavelengths shorter than approximately 4,000 Angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an ex- tended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadver- tent erasure. If an application subjects the device to intel. this type of exposure, it is suggested that an opaque label be placed over the window. The recommended erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to an integrat- ed dose of at lease 15 W-sec/cm. Exposing the EPROM to an ultraviolet lamp of 12,000 W/cm rat- ing for 30 minutes, at a distance of about 1 inch, should be sufficient. Erasure leaves the array in an all 1s state. EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS (Ta = 21C to 27C, Vog = 5.0V +10%, Vgg = OV) Symbol Parameter Min Max Units Vpp Programming Supply Voltage 12.5 13.0 Vv Ipp Programming Supply Current 50 mA 1/TCLCL Oscillator Frequency 4 6 MHz TAVGL Address Setup to PROG Low 48TCLCL TGHAX Address Hold After PROG 48TCLCL TDVGL Data Setup to PROG Low 48TCLCL TGHDX Data Hold After PROG 48TCLCL TEHSH P2.7 (ENABLE) High to Vpp 48TCLCL TSHGL Vpp Setup to PROG Low 10 us TGHSL Vpp Hold After PROG 10 LS TGLGH PROG Width 90 110 MS TAVOQV Address to Data Valid 48TCLCL TELQV ENABLE Low to Data Valid 48TCLCL TEHQZ Data Float After ENABLE 0 48TCLCL TGHGL PROG High to PROG Low 10 ps EPROM PROGRAMMING AND VERIFICATION WAVEFORMS PROGRAMMING VERIFICATION raped noone ee i TAVYOY PORT 9 DATA nS DATA OUT Savas of iulSes Lr ALE /PROG TTT J oa +4. TGHSL FA/Vpp aaa ~\ EA/HIGH TEHSH TELQV he TEHOZ > = 272318-18 2-40 www.chipinfo.ru Be sure to visit CHIPINFO web site for more information.intel. DATA SHEET REVISION HISTORY This datasheet (272318-001) replaces the tcllowing datasheets: MCS 51 Controllers (270048-007) B051AHP (270279-004) 8751BH (270248-005) 8751BH EXPRESS (270708-001) 8752BH (270429-004) 8752BH EXPRESS (270650-002) www.chipinfo.ru Be sure to visit CHIPINFO web site for more information. MCS 51 CONTROLLER 2-44