SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
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SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
3.3-V FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS
Check for Samples: SN65HVD30-EP,SN65HVD31-EP,SN65HVD32-EP,SN65HVD33-EP,SN65HVD34-EP,SN65HVD35-EP
1FEATURES APPLICATIONS
• 1/8 Unit-Load Option Available (up to 256 • Utility Meters
Nodes on the Bus) • DTE/DCE Interfaces
• Bus-Pin ESD Protection Exceeds 15-kV HBM • Industrial, Process, and Building Automation
• Optional Driver Output Transition Times for • Point-of-Sale (POS) Terminals and Networks
Signaling Rates (1) of 1 Mbps, 5 Mbps, and
25 Mbps SUPPORTS DEFENSE, AEROSPACE,
• Low-Current Standby Mode: <1 μAAND MEDICAL APPLICATIONS
• Glitch-Free Power-Up and Power-Down • Controlled Baseline
Protection for Hot-Plugging Applications • One Assembly/Test Site
• 5-V-Tolerant Inputs • One Fabrication Site
• Bus Idle, Open, and Short-Circuit Fail Safe • Available in Military (–55°C/125°C)
• Driver Current Limiting and Thermal Shutdown Temperature Range
• Meet or Exceed the Requirements of ANSI • Extended Product Life Cycle
TIA/EIA-485-A and RS-422 Compatible • Extended Product-Change Notification
(1) The signaling rate of a line is the number of voltage • Product Traceability
transitions that are made per second expressed in the units
bps (bits per second).
DESCRIPTION
The SN65HVD3x devices are 3-state differential line drivers and differential-input line receivers that operate with
3.3-V power supply.
Each driver and receiver has separate input and output pins for full-duplex bus communication designs. They are
designed for balanced transmission lines and interoperation with ANSI TIA/EIA-485A, TIA/EIA-422-B, ITU-T v.11,
and ISO 8482:1993 standard-compliant devices.
The SN65HVD30, SN65HVD31, and SN65HVD32 are fully enabled with no external enabling pins.
The SN65HVD33, SN65HVD34, and SN65HVD35 have active-high driver enables and active-low receiver
enables. A low (less than 1 μA) standby current can be achieved by disabling both the driver and receiver.
All devices are characterized for operation from –55°C to 125°C.
IMPROVED REPLACEMENT FOR:
Part Number Replace With
xxx3491 SN65HVD33: Better ESD protection (15 kV vs 2 kV or not specified), higher signaling rate (25 Mbps vs 20 Mbps),
xxx3490 SN65HVD30: fractional unit load (64 nodes vs 32)
MAX3491E SN65HVD33: Higher signaling rate (25 Mbps vs 12 Mbps), fractional unit load (64 nodes vs 32)
MAX3490E SN65HVD30:
MAX3076E SN65HVD33: Higher signaling rate (25 Mbps vs 16 Mbps), lower standby current (1 μA vs 10 μA)
MAX3077E SN65HVD30:
MAX3073E SN65HVD34: Higher signaling rate (5 Mbps vs 500 kbps), lower standby current (1 μA vs 10 μA)
MAX3074E SN65HVD31:
MAX3070E SN65HVD35: Higher signaling rate (1 Mbps vs 250 kbps), lower standby current (1 μA vs 10 μA)
MAX3071E SN65HVD32:
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
R
D
B
A
Z
Y
7
8
6
5
2
3
DP
(TOP VIEW)
ACKAGE
1
2
3
4
8
7
6
5
R
D
VCC
B
A
Z
Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
R
RE
DE
D
GND
GND
VCC
VCC
A
B
Z
Y
NC
NC-Nointernalconnection
DP
(TOP VIEW)
ACKAGE
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
xxx SN65HVD30, SN65HVD31, SN65HVD32 SN65HVD33, SN65HVD34, SN65HVD35
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SN65HVD35-EP
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
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SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
AVAILABLE OPTIONS(1)
BASE SIGNALING RECEIVER
UNIT LOADS ENABLES SOIC MARKING
PART NUMBER RATE EQUALIZATION
SN65HVD30MDREP 25 Mbps 1/2 No No HVD30EP
SN65HVD31MDREP(2) 5 Mbps 1/8 No No PREVIEW
SN65HVD32MDREP(2) 1 Mbps 1/8 No No PREVIEW
SN65HVD33MDREP 25 Mbps 1/2 No Yes HVD33EP
SN65HVD34MDREP(2) 5 Mbps 1/8 No Yes PREVIEW
SN65HVD35MDREP(2) 1 Mbps 1/8 No Yes PREVIEW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Product Preview
Absolute Maximum Ratings(1) (2)
over operating free-air temperature range (unless otherwise noted) UNIT
VCC Supply voltage range –0.3 V to 6 V
V(A), V(B), V(Y), V(Z) Voltage range at any bus terminal (A, B, Y, Z) –9 V to 14 V
V(TRANS) Voltage input, transient pulse through 100 Ω(see Figure 12) (A, B, Y, Z)(3) –50 V to 50 V
VIInput voltage range (D, DE, RE) –0.5 V to 7 V
PD(cont) Continuous total power dissipation Internally limited(4)
IOOutput current (receiver output only, R) 11 mA
TJJunction temperature 165°C
TSTG Storage temperature range –65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) This tests survivability only and the output state of the receiver is not specified.
(4) The thermal shutdown protection circuit internally limits the continuous total power dissipation. Thermal shutdown typically occurs when
the junction temperature reaches 165°C.
Copyright © 2006–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP
SN65HVD35-EP
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
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Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
VCC Supply voltage 3 3.6 V
VIor VIC Voltage at any bus terminal (separately or common mode) –7(1) 12 V
'HVD30, 'HVD33 25
1/tUI Signaling rate 'HVD31, 'HVD34 5 Mbps
'HVD32, 'HVD35 1
RLDifferential load resistance 54 60 Ω
VIH High-level input voltage D, DE, RE 2 VCC V
VIL Low-level input voltage D, DE, RE 0 0.8 V
VID Differential input voltage –12 12 V
Driver –60
IOH High-level output current mA
Receiver –8
Driver 60
IOL Low-level output current mA
Receiver 8
TAAmbient still-air temperature –55 125(2) °C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
(2) Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
Electrostatic Discharge Protection
PARAMETER TEST CONDITIONS TYP(1) UNIT
Human-Body Model Bus terminals and GND ±16
Human-Body Model(2) All pins ±4 kV
Charged-Device Model(3) All pins ±1
(1) All typical values at 25°C with 3.3-V supply
(2) Tested in accordance with JEDEC Standard 22, Test Method A114-A
(3) Tested in accordance with JEDEC Standard 22, Test Method C101
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SN65HVD35-EP
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
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SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
Driver Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VI(K) Input clamp voltage II= –18 mA –1.5 V
VCC +
IO= 0 2.3 0.1
RL= 54 Ω, See Figure 1 (RS-485) 1.5 2
|VOD(SS)| Steady-state differential output voltage V
RL= 100 Ω, See Figure 1 (RS-422) 2 2.3
Vtest = –7 V to 12 V, See Figure 2 1.5
Change in magnitude of steady-state
Δ|VOD(SS)| differential output voltage between RL= 54 Ω, See Figure 1 and Figure 2 –0.2 0.2 V
states
Differential output voltage overshoot RL= 54 Ω, CL= 50 pF, See Figure 5 and
VOD(RING) 10%(2) V
and undershoot Figure 3
'HVD30, 'HVD33 0.5
Peak-to-peak
VOC(PP) common-mode See Figure 4 V
'HVD31, 'HVD32, 0.25
output voltage 'HVD34, 'HVD35
Steady-state common-mode output
VOC(SS) See Figure 4 1.6 2.3 V
voltage
Change in steady-state common-mode
ΔVOC(SS) See Figure 4 –0.05 0.05 V
output voltage VCC = 0 V, VZor VY= 12 V, 90
Other input at 0 V
'HVD30, 'HVD31,
'HVD32 VCC = 0 V, VZor VY= –7 V, –10
High-impedance Other input at 0 V
IZ(Z) or state output μA
IY(Z) VCC = 3 V or 0 V, DE = 0 V,
current 90
VZor VY= 12 V
'HVD33, 'HVD34, Other input
'HVD35 at 0 V
VCC = 3 V or 0 V, DE = 0 V, –10
VZor VY= –7 V
VZor VY= –7 V
IZ(S) or Other input
Short-circuit output current ±250 mA
IY(S) at 0 V
VZor VY= 12 V
IIInput current D, DE 0 100 μA
C(OD) Differential output capacitance VOD = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 16 pF
(1) All typical values at 25°C with 3.3-V supply
(2) 10% of the peak-to-peak differential output voltage swing, per TIA/EIA-485
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SN65HVD35-EP
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
www.ti.com
Driver Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
'HVD30, 'HVD33 4 10 23
Propagation delay time,
tPLH 'HVD31, 'HVD34 25 38 65 ns
low- to high-level output 'HVD32, 'HVD35 120 175 305
'HVD30, 'HVD33 4 9 23
Propagation delay time,
tPHL 'HVD31, 'HVD34 25 38 65 ns
high- to low-level output 'HVD32, 'HVD35 120 175 305
'HVD30, 'HVD33 2.5 5 18
Differential output signal RL= 54 Ω, CL= 50 pF,
tr'HVD31, 'HVD34 20 37 60 ns
rise time See Figure 5
'HVD32, 'HVD35 120 185 300
'HVD30, 'HVD33 2.5 5 18
Differential output signal
tf'HVD31, 'HVD34 20 35 60 ns
fall time 'HVD32, 'HVD35 120 180 300
'HVD30, 'HVD33 0.6
tsk(p) Pulse skew (|tPHL – tPLH|) 'HVD31, 'HVD34 2.0 ns
'HVD32, 'HVD35 5.1
'HVD33 45
Propagation delay time, high-
tPZH1 'HVD34 235 ns
impedance to high-level output RL= 110 Ω, RE at 0 V,
'HVD35 490
D = 3 V and S1 = Y, or
D = 0 V and S1 = Z,
'HVD33 25
See Figure 6
Propagation delay time, high-
tPHZ 'HVD34 65 ns
level to high-impedance output 'HVD35 165
'HVD33 35
Propagation delay time, high-
tPZL1 'HVD34 190 ns
impedance to low-level output RL= 110 Ω, RE at 0 V,
'HVD35 490
D = 3 V and S1 = Z, or
D = 0 V and S1 = Y,
'HVD33 30
See Figure 7
Propagation delay time, low-
tPLZ 'HVD34 120 ns
level to high-impedance output 'HVD35 290
'HVD30 RL= 110 Ω, RE at 3 V, 4000
Propagation delay time, standby D = 3 V and S1 = Y, or
tPZH2 ns
to high-level output D = 0 V and S1 = Z,
'HVD33 5000
See Figure 6
'HVD30 RL= 110 Ω, RE at 3 V, 4000
Propagation delay time, standby D = 3 V and S1 = Z, or
tPZL2 ns
to low-level output D = 0 V and S1 = Y,
'HVD33 5000
See Figure 7
(1) All typical values at 25°C with 3.3-V supply
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SN65HVD35-EP
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SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
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SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
Receiver Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
Positive-going differential input threshold
VIT+ IO= –8 mA –0.02 V
voltage
Negative-going 'HVD30 –0.15
VIT– differential input IO= 8 mA V
'HVD33 -0.2
threshold voltage
Vhys Hysteresis voltage (VIT+ – VIT–) 50 mV
VIK Enable-input clamp voltage II= –18 mA –1.5 V
VID = 200 mV, IO= –8 mA, See Figure 8 2.4
VOOutput voltage V
VID = –200 mV, IO= 8 mA, See Figure 8 0.4
IO(Z) High-impedance-state output current VO= 0 or VCC, RE at VCC –1 1 μA
VAor VB= 12 V 0.05 0.1
VAor VB= 12 V, VCC = 0 V 0.06 0.1
'HVD31, 'HVD32, Other input
'HVD34, 'HVD35 at 0 V
VAor VB= –7 V –0.10 –0.04
VAor VB= –7 V, VCC = 0 V –0.10 –0.03
IAor Bus input current mA
IBVAor VB= 12 V 0.20 0.35
VAor VB= 12 V, VCC = 0 V 0.24 0.4
Other input
'HVD30, 'HVD33 at 0 V
VAor VB= –7 V –0.35 –0.18
VAor VB= –7 V, VCC = 0 V –0.25 –0.13
IIH Input current, RE VIH = 0.8 V or 2 V –60 μA
CID Differential input capacitance VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 15 pF
Supply Current
'HVD30 2.1
D at 0 V or VCC and no load
'HVD31, 'HVD32 6.4 mA
'HVD33 RE at 0 V, D at 0 V or VCC, DE at 0 V, 1.8
No load (receiver enabled and driver
'HVD34, 'HVD35 2.2
disabled)
RE at VCC, D at VCC, DE at 0 V,
'HVD33, 'HVD34, No load (receiver disabled and driver 0.022 1.5 μA
'HVD35
ICC Supply current disabled)
'HVD33 RE at 0 V, D at 0 V or VCC, DE at VCC, 2.1
No load (receiver enabled and driver
'HVD34, 'HVD35 6.5
enabled) mA
'HVD33 RE at VCC, D at 0 V or VCC, DE at VCC 1.8
No load (receiver disabled and driver
'HVD34, 'HVD35 6.2
enabled)
(1) All typical values at 25°C with 3.3-V supply
Receiver Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
'HVD30, 'HVD33 26 60
Propagation delay time,
tPLH ns
low- to high-level output 'HVD31, 'HVD32, 'HVD34, 'HVD35 47 70
'HVD30, 'HVD33 29 60
Propagation delay time,
tPHL ns
high- to low-level output 'HVD31, 'HVD32, 'HVD34, 'HVD35 49 70
VID = –1.5 V to 1.5 V,
'HVD30, 'HVD33 12
CL= 15 pF, See Figure 9
tsk(p) Pulse skew (|tPHL – tPLH|) ns
'HVD31, 'HVD34, 'HVD32, 'HVD35 10
'HVD30 10
trOutput signal rise time ns
'HVD33 18
tfOutput signal fall time 12.5 ns
(1) All typical values 25°C with 3.3-V supply
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SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
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Receiver Switching Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tPHZ Output disable time from high level 20 ns
DE at 3 V
tPZH1 Output enable time to high level 20 ns
CL= 15 pF,
See Figure 10
'HVD30 4000
Propagation delay time,
tPZH2 DE at 0 V ns
standby to high-level output 'HVD33 5000
tPLZ Output disable time from low level 20 ns
DE at 3 V
tPZL1 Output enable time to low level 20 ns
CL= 15 pF,
See Figure 11
'HVD30 4000
Propagation delay time,
tPZL2 DE at 0 V ns
standby to low-level output 'HVD33 5000
Receiver Equalization Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS DEVICE MIN TYP(1) MAX UNIT
100 m 'HVD33(2) PREVIEW
25 Mbps 150 m 'HVD33(2) PREVIEW
200 m 'HVD33(2) PREVIEW
200 m 'HVD33(2) PREVIEW
Pseudo-random NRZ code 10 Mbps 250 m 'HVD33(2) PREVIEW
Peak-to-peak
tj(pp) with a bit pattern length of ns
eye-pattern jitter 300 m 'HVD33(2) PREVIEW
216 – 1, Belden 3105A cable 5 Mbps 500 m 'HVD34(2) PREVIEW
'HVD33(2) PREVIEW
3 Mbps 500 m 'HVD34(2) PREVIEW
1 Mbps 1000 m 'HVD34(2) PREVIEW
(1) All typical values are at VCC = 5 V and temperature = 25°C.
(2) The SN65HVD33 and the SN65HVD34 do not have receiver equalization, but are specified for comparison.
Device Power Dissipation – PD
DEVICE TEST CONDITIONS MIN MAX UNIT
'HVD30 (25 Mbps) 197
RL= 60 Ω, CL= 50 pF,
'HVD31 (5 Mbps) 213 mW
Input to D a 50% duty cycle square wave at indicated signaling rate, TA= 85°C
'HVD32 (1 Mbps) 193
'HVD33 (25 Mbps) 197
RL= 60 Ω, CL= 50 pF, DE at VCC, RE at 0 V,
'HVD34 (5 Mbps) 193 mW
Input to D a 50% duty cycle square wave at indicated signaling rate, TA= 85°C
'HVD35 (1 Mbps) 248
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IY
VOD RL
0or3V
VY
VZ
IZ
DE
VCC
II
VI
Y
Z
60 Ω±1%
VOD
0or3V
_
+−7V<V(test) <12V
DE
VCC
Y
Z
D
375 Ω±1%
375 Ω±1%
VOD(RING)
VOD(RING)
–VOD(SS)
VOD(SS)
0VDifferential
VOC
27 Ω ±1%
Input
Y
Z
VY
VZ
VOC(PP) ∆VOC(SS)
VOC
27 Ω ±1%
CL=50pF ±20%
DY
Z
DE
VCC
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
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SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
PARAMETER MEASUREMENT INFORMATION
Figure 1. Driver VOD Test Circuit and Voltage and Current Definitions
Figure 2. Driver VOD With Common-Mode Loading Test Circuit
Figure 3. VOD(RING) Waveform and Definitions
VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from
the VOD(H) and VOD(L) steady state values.
Input: PRR = 500 kHz, 50% Duty Cycle, tr< 6 ns, tf< 6 ns, ZO= 50 Ω
Figure 4. Test Circuit and Definitions for Driver Common-Mode Output Voltage
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Y
Z
W
W
»
»
VI
VO
tPZH(1&2)
50 W
D
DS1
3V Y
0VZ Y
Z
VI
RL=110 W
±1%
CL=50 pF
±20%
VO
3V
1.5V
1.5V
tPHZ
2.3V
DE
Input
Generator
~0V
VOH
0.5V 0V
S1
VID
VA
VB
IO
A
B
IBVO
R
RE
IA
VIC
VA+VB
2IIVI
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
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PARAMETER MEASUREMENT INFORMATION (continued)
A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr< 6 ns, tf< 6 ns, ZO= 50 Ω
Figure 5. Driver Switching Test Circuit and Voltage Waveforms
A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr< 6 ns, tf< 6 ns, ZO= 50 Ω
B. CLIncludes Fixture and Instrumentation Capacitance
Figure 6. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr< 6 ns, tf< 6 ns, ZO= 50 Ω
Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
Figure 8. Receiver Voltage and Current Definitions
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Input
Generator 50 Ω
VO
1.5V
0V
1.5V 1.5V
3V
VOH
VOL
1.5V
10%
1.5V
tPLH tPHL
trtf
90%
VI
VO
CL=15pF
±20%
A
B
RE
VI
R0V
90%
10%
B
A
RVO
50 W
VI
Input
Generator
CL=15 pF
±20%
RE
S1
1k W±1%
A
B
VCC
VI
tPZH(1&2)
3V
1.5V
1.5V
tPHZ
0V
VO
1.5V
~0V
VOH
0.5V
1.5V
0V
B
A
RVO
50 W
VI
Input
Generator
CL=15 pF
±20%
RE
S1
1k W±1%
A
B
VCC
VI
VO
3V
1.5V
1.5V
VCC
VOL
0.5V
0V
1.5V
tPZL(1&2) tPLZ
0V
1.5V
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
www.ti.com
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
PARAMETER MEASUREMENT INFORMATION (continued)
A. CLIncludes Fixture and Instrumentation Capacitance
B. Generator: PRR = 500 kHz, 50% Duty Cycle, tr< 6 ns, tf< 6 ns, ZO= 50 Ω
Figure 9. Receiver Switching Test Circuit and Voltage Waveforms
A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr< 6 ns, tf< 6 ns, ZO= 50 Ω
Figure 10. Receiver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr< 6 ns, tf< 6 ns, ZO= 50 Ω
Figure 11. Receiver Enable Time From Standby (Driver Disabled)
Copyright © 2006–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP
SN65HVD35-EP
B
A
R
100 W
±1%
+
-
PulseGenerator
15 msduration
1%DutyCycle
t ,t 100ns
r f £
Z
Y
D
100 W
±1%
+
-
DE
0Vor3V
0Vor3V
RE
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 12. Test Circuit, Transient Over Voltage Test
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Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP
SN65HVD35-EP
4
5
9
10
Y
Z
D
DE
A
B
12
11
2
R
3
RE
Low-Power
Standby
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
www.ti.com
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
DEVICE INFORMATION
Low-Power Standby Mode
When both the driver and receiver are disabled (DE low and RE high), the device is in standby mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against
inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs are held in this
state for 300 ns or more, the device is assured to be in standby mode. In this low-power standby mode, most
internal circuitry is powered down, and the supply current is typically less than 1 nA. When either the driver or the
receiver is re-enabled, the internal circuitry becomes active.
Figure 13. Low-Power Standby Logic Diagram
If only the driver is re-enabled (DE transitions to high), the driver outputs are driven according to the D input after
the enable times given by tPZH2 and tPZL2 in the driver switching characteristics. If the D input is open when the
driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver fail-safe feature.
If only the receiver is re-enabled (RE transitions to low), the receiver output is driven according to the state of the
bus inputs (A and B) after the enable times given by tPZH2 and tPZL2 in the receiver switching characteristics. If
there is no valid state on the bus, the receiver responds as described in the fail-safe operation section.
If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state
of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the
active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver
outputs are valid.
Copyright © 2006–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP
SN65HVD35-EP
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
www.ti.com
FUNCTION TABLES
Table 1. SN65HVD33, SN65HVD34, SN65HVD35
DRIVER(1)
INPUTS OUTPUTS
D DE Y Z
H H H L
L H L H
X L or open Z Z
Open H L H
(1) H = high level, L = low level, Z = high impedance, X = irrelevant
Table 2. SN65HVD33, SN65HVD34, SN65HVD35
RECEIVER(1)
DIFFERENTIAL INPUTS ENABLE OUTPUT
VID = V(A) – V(B) RE R
VID ≤ −0.2 V L L
−0.2 V < VID <−0.02 V L ?
−0.02 V ≤VID L H
X H or open Z
Open circuit L H
Idle circuit L H
Short circuit, V(A) = V(B) L H
(1) H = high level, L = low level, Z = high impedance, X = irrelevant,
? = indeterminate
Table 3. SN65HVD30, SN65HVD31, SN65HVD32
DRIVER(1)
OUTPUTS
INPUT
DY Z
H H L
L L H
Open L H
(1) H = high level, L = low level
Table 4. SN65HVD30, SN65HVD31, SN65HVD32
RECEIVER(1)
DIFFERENTIAL INPUTS OUTPUT
VID = V(A) – V(B) R
VID ≤ −0.15 V L
−0.15 V < VID <−0.02 V ?
−0.02 V ≤VID H
Open circuit H
Idle circuit H
Short circuit, V(A) = V(B) H
(1) H = high level, L = low level, ? = indeterminate
14 Submit Documentation Feedback Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP
SN65HVD35-EP
VCC
Input
470 W
130 kW
VCC
5W
Output
ROutput
9 V
9 V
R3
22 V
22 V
Input
R2
R1
VCC
A Input
R3
22 V
22 V
Input
R2
R1
VCC
BInput
16 V
16 V
Y andZOutputs
Output
VCC
RE Input
VCC
Input
470 W
125 kW
9 V
DandDEInput
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
www.ti.com
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
R1/R2 R3
SN65HVD30, SN65HVD33 9 kΩ45 kΩ
SN65HVD31, SN65HVD32, SN65HVD34, SN65HVD35 36 kΩ180 kΩ
Copyright © 2006–2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP
SN65HVD35-EP
30
35
40
45
50
55
0 5 10 15 20 25
SignalingRate-Mbps
I -RMSSupplyCurrent-mA
CC
T =25°CR =54
=V C =50pF
DE=V
AL
CC L
CC
W
RE
V =3.3V
CC
30
35
40
45
50
55
60
0 1 2 3 4 5
SignalingRate-Mbps
I -RMSSupplyCurrent-mA
CC
T =25°CR =54
=V C =50pF
DE=V
AL
CC L
CC
W
RE
V =3.3V
CC
30
35
40
45
50
55
60
0 0.2 0.4 0.6 0.8 1
SignalingRate-Mbps
I -RMSSupplyCurrent-mA
CC
T =25°CR =54
=V C =50pF
DE=V
AL
CC L
CC
W
RE
V =3.3V
CC
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS
'HVD30, 'HVD33 'HVD31, 'HVD34
RMS SUPPLY CURRENT RMS SUPPLY CURRENT
vs vs
SIGNALING RATE SIGNALING RATE
Figure 14. Figure 15.
'HVD32, 'HVD35
RMS SUPPLY CURRENT
vs
SIGNALING RATE
Figure 16.
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Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP
SN65HVD35-EP
–200
–150
–100
–50
50
0
100
150
200
250
–7 –4 –1 2 5 8 11 14
V -BusInputVoltage-V
I
I -BusInputCurrent- A
Im
T =25°C
=0V
DE=0V
A
RE
V =3.3V
CC
-60
-40
-20
20
40
0
60
-7 -4 -1 2 5 8 11 14
V -BusInputVoltage-V
I
I -BusInputCurrent-uA
I
T =25°C
=0V
DE=0V
A
RE
V =3.3V
CC
–0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0 0.5 1 1.5 2 2.5 3 3.5
V -Low-LevelOutputVoltage-V
OL
I -DriverLow-LevelOutputCurrent- A
OL
V =3.3V
DE=V
D=0V
CC
CC
–0.13
–0.11
–0.09
–0.07
–0.05
–0.03
–0.01
0.01
0 0.5 1 1.5 2 2.5 3 3.5
V -High-LevelOutputVoltage-V
OH
I -DriverHigh-LevelOutputCurrent- A
OH
V =3.3V
DE=V
D=0V
CC
CC
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
www.ti.com
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
TYPICAL CHARACTERISTICS (continued)
'HVD30, 'HVD33 'HVD31, 'HVD32, 'HVD34, 'HVD35
BUS INPUT CURRENT BUS INPUT CURRENT
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 17. Figure 18.
DRIVER LOW-LEVEL OUTPUT CURRENT DRIVER HIGH-LEVEL OUTPUT CURRENT
vs vs
LOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE
Figure 19. Figure 20.
Copyright © 2006–2012, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP
SN65HVD35-EP
1.8
1.9
2.0
2.1
2.2
–40 –15 10 35 60 85
T -Free-AirTemperature-°C
A
V -DriverDifferentialOutputVoltage-V
OD
V =3.3V
DE=V
D=
CC
CC
VCC
0
5
10
15
20
25
30
35
40
0 0.5 1 1.5 2 2.5 3 3.5
V SupplyVoltage-V
CC
I -DriverOutputCurrent-mA
O
T =25°C
R =54
D=V
DE=V
A
L
CC
CC
W
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
DRIVER DIFFERENTIAL OUTPUT VOLTAGE DRIVER OUTPUT CURRENT
vs vs
FREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 21. Figure 22.
18 Submit Documentation Feedback Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP
SN65HVD35-EP
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65HVD30MDREP ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD30MDREPG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD33MDREP ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD33MDREPG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/06634-01XE ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/06634-04YE ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD30-EP, SN65HVD33-EP :
•Catalog: SN65HVD30,SN65HVD33
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 22-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65HVD30MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD33MDREP SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD30MDREP SOIC D 8 2500 367.0 367.0 35.0
SN65HVD33MDREP SOIC D 14 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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