SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP www.ti.com SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 3.3-V FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS Check for Samples: SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP, SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP FEATURES APPLICATIONS * * * * * 1 * * * * * * * * (1) 1/8 Unit-Load Option Available (up to 256 Nodes on the Bus) Bus-Pin ESD Protection Exceeds 15-kV HBM Optional Driver Output Transition Times for Signaling Rates (1) of 1 Mbps, 5 Mbps, and 25 Mbps Low-Current Standby Mode: <1 A Glitch-Free Power-Up and Power-Down Protection for Hot-Plugging Applications 5-V-Tolerant Inputs Bus Idle, Open, and Short-Circuit Fail Safe Driver Current Limiting and Thermal Shutdown Meet or Exceed the Requirements of ANSI TIA/EIA-485-A and RS-422 Compatible The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). Utility Meters DTE/DCE Interfaces Industrial, Process, and Building Automation Point-of-Sale (POS) Terminals and Networks SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS * * * * * * * Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Military (-55C/125C) Temperature Range Extended Product Life Cycle Extended Product-Change Notification Product Traceability DESCRIPTION The SN65HVD3x devices are 3-state differential line drivers and differential-input line receivers that operate with 3.3-V power supply. Each driver and receiver has separate input and output pins for full-duplex bus communication designs. They are designed for balanced transmission lines and interoperation with ANSI TIA/EIA-485A, TIA/EIA-422-B, ITU-T v.11, and ISO 8482:1993 standard-compliant devices. The SN65HVD30, SN65HVD31, and SN65HVD32 are fully enabled with no external enabling pins. The SN65HVD33, SN65HVD34, and SN65HVD35 have active-high driver enables and active-low receiver enables. A low (less than 1 A) standby current can be achieved by disabling both the driver and receiver. All devices are characterized for operation from -55C to 125C. IMPROVED REPLACEMENT FOR: Part Number Replace With xxx3491 xxx3490 SN65HVD33: SN65HVD30: Better ESD protection (15 kV vs 2 kV or not specified), higher signaling rate (25 Mbps vs 20 Mbps), fractional unit load (64 nodes vs 32) MAX3491E MAX3490E SN65HVD33: SN65HVD30: Higher signaling rate (25 Mbps vs 12 Mbps), fractional unit load (64 nodes vs 32) MAX3076E MAX3077E SN65HVD33: SN65HVD30: Higher signaling rate (25 Mbps vs 16 Mbps), lower standby current (1 A vs 10 A) MAX3073E MAX3074E SN65HVD34: SN65HVD31: Higher signaling rate (5 Mbps vs 500 kbps), lower standby current (1 A vs 10 A) MAX3070E MAX3071E SN65HVD35: SN65HVD32: Higher signaling rate (1 Mbps vs 250 kbps), lower standby current (1 A vs 10 A) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2006-2012, Texas Instruments Incorporated SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. xxx SN65HVD30, SN65HVD31, SN65HVD32 SN65HVD33, SN65HVD34, SN65HVD35 D PACKAGE (TOP VIEW) D PACKAGE (TOP VIEW) VCC R D GND 1 8 2 7 3 6 4 5 A B Z Y 8 2 R A 7 NC R RE DE D GND GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC VCC A B Z Y NC B NC - No internal connection 5 3 D Y 6 Z 2 Submit Documentation Feedback Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP www.ti.com SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 AVAILABLE OPTIONS (1) (1) (2) BASE PART NUMBER SIGNALING RATE UNIT LOADS RECEIVER EQUALIZATION ENABLES SOIC MARKING SN65HVD30MDREP 25 Mbps 1/2 No No HVD30EP SN65HVD31MDREP (2) 5 Mbps 1/8 No No PREVIEW SN65HVD32MDREP (2) 1 Mbps 1/8 No No PREVIEW SN65HVD33MDREP 25 Mbps 1/2 No Yes HVD33EP SN65HVD34MDREP (2) 5 Mbps 1/8 No Yes PREVIEW SN65HVD35MDREP (2) 1 Mbps 1/8 No Yes PREVIEW For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Product Preview Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) UNIT VCC Supply voltage range V(A), V(B), V(Y), V(Z) Voltage range at any bus terminal (A, B, Y, Z) V(TRANS) Voltage input, transient pulse through 100 (see Figure 12) (A, B, Y, Z) VI Input voltage range (D, DE, RE) PD(cont) Continuous total power dissipation IO Output current (receiver output only, R) TJ Junction temperature TSTG Storage temperature range (1) (2) (3) (4) -0.3 V to 6 V -9 V to 14 V (3) -50 V to 50 V -0.5 V to 7 V Internally limited (4) 11 mA 165C -65C to 150C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. This tests survivability only and the output state of the receiver is not specified. The thermal shutdown protection circuit internally limits the continuous total power dissipation. Thermal shutdown typically occurs when the junction temperature reaches 165C. Copyright (c) 2006-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP 3 SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 www.ti.com Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VCC Supply voltage VI or VIC Voltage at any bus terminal (separately or common mode) NOM MAX 3 3.6 V -7 (1) 12 V 'HVD30, 'HVD33 25 'HVD31, 'HVD34 5 1/tUI Signaling rate RL Differential load resistance VIH High-level input voltage D, DE, RE VIL Low-level input voltage D, DE, RE VID Differential input voltage 'HVD32, 'HVD35 IOH High-level output current IOL Low-level output current TA Ambient still-air temperature (1) (2) UNIT Mbps 1 54 Driver 60 2 VCC V 0 0.8 V -12 12 V -60 Receiver mA -8 Driver 60 Receiver 8 -55 125 (2) mA C The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet. Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging. Electrostatic Discharge Protection PARAMETER Human-Body Model Bus terminals and GND Human-Body Model (2) Charged-Device Model (1) (2) (3) 4 TEST CONDITIONS (3) TYP (1) UNIT 16 All pins 4 All pins 1 kV All typical values at 25C with 3.3-V supply Tested in accordance with JEDEC Standard 22, Test Method A114-A Tested in accordance with JEDEC Standard 22, Test Method C101 Submit Documentation Feedback Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP www.ti.com SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 Driver Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VI(K) Input clamp voltage TEST CONDITIONS II = -18 mA MAX -1.5 IO = 0 |VOD(SS)| MIN TYP (1) V VCC + 0.1 2.3 Steady-state differential output voltage RL = 54 , See Figure 1 (RS-485) RL = 100 , See Figure 1 (RS-422) Vtest = -7 V to 12 V, See Figure 2 UNIT 1.5 2 2 2.3 V 1.5 |VOD(SS)| Change in magnitude of steady-state differential output voltage between states RL = 54 , See Figure 1 and Figure 2 VOD(RING) Differential output voltage overshoot and undershoot RL = 54 , CL = 50 pF, See Figure 5 and Figure 3 VOC(PP) Peak-to-peak common-mode output voltage VOC(SS) Steady-state common-mode output voltage See Figure 4 1.6 2.3 V VOC(SS) Change in steady-state common-mode See Figure 4 output voltage -0.05 0.05 V 'HVD30, 'HVD33 'HVD31, 'HVD32, 'HVD34, 'HVD35 'HVD30, 'HVD31, 'HVD32 IZ(Z) or IY(Z) High-impedance state output current 'HVD33, 'HVD34, 'HVD35 IZ(S) or IY(S) Short-circuit output current II Input current C(OD) Differential output capacitance (1) (2) -0.2 0.2 V 10% (2) V 0.5 See Figure 4 V 0.25 VCC = 0 V, VZ or VY = 12 V, Other input at 0 V 90 VCC = 0 V, VZ or VY = -7 V, Other input at 0 V VCC = 3 V or 0 V, DE = 0 V, VZ or VY = 12 V VCC = 3 V or 0 V, DE = 0 V, VZ or VY = -7 V VZ or VY = -7 V VZ or VY = 12 V -10 A Other input at 0 V 90 -10 Other input at 0 V D, DE 250 0 VOD = 0.4 sin (4E6t) + 0.5 V, DE at 0 V mA 100 16 A pF All typical values at 25C with 3.3-V supply 10% of the peak-to-peak differential output voltage swing, per TIA/EIA-485 Copyright (c) 2006-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP 5 SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 www.ti.com Driver Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER Propagation delay time, low- to high-level output tPLH Propagation delay time, high- to low-level output tPHL TEST CONDITIONS 'HVD30, 'HVD33 4 10 'HVD31, 'HVD34 25 38 65 'HVD32, 'HVD35 120 175 305 'HVD30, 'HVD33 4 9 23 25 38 65 'HVD32, 'HVD35 120 175 305 2.5 5 18 tr Differential output signal fall time tf tsk(p) tPZH1 Pulse skew (|tPHL - tPLH|) Propagation delay time, highimpedance to high-level output 'HVD31, 'HVD34 20 37 60 'HVD32, 'HVD35 120 185 300 'HVD30, 'HVD33 2.5 5 18 'HVD31, 'HVD34 20 35 60 'HVD32, 'HVD35 120 180 300 'HVD30, 'HVD33 0.6 'HVD31, 'HVD34 2.0 'HVD32, 'HVD35 5.1 45 'HVD34 235 'HVD33 Propagation delay time, highlevel to high-impedance output 'HVD34 RL = 110 , RE at 0 V, D = 3 V and S1 = Y, or D = 0 V and S1 = Z, See Figure 6 Propagation delay time, highimpedance to low-level output 65 35 190 'HVD34 RL = 110 , RE at 0 V, D = 3 V and S1 = Z, or D = 0 V and S1 = Y, See Figure 7 tPZL2 (1) 6 ns ns ns 490 30 120 'HVD35 tPZH2 ns 165 'HVD34 'HVD33 Propagation delay time, lowlevel to high-impedance output tPLZ ns 25 'HVD33 'HVD35 ns 490 'HVD35 tPZL1 ns ns 'HVD33 'HVD35 tPHZ RL = 54 , CL = 50 pF, See Figure 5 UNIT 23 'HVD31, 'HVD34 'HVD30, 'HVD33 Differential output signal rise time MIN TYP (1) MAX ns 290 'HVD30 Propagation delay time, standby to high-level output 'HVD33 RL = 110 , RE at 3 V, D = 3 V and S1 = Y, or D = 0 V and S1 = Z, See Figure 6 4000 'HVD30 Propagation delay time, standby to low-level output 'HVD33 RL = 110 , RE at 3 V, D = 3 V and S1 = Z, or D = 0 V and S1 = Y, See Figure 7 4000 5000 5000 ns ns All typical values at 25C with 3.3-V supply Submit Documentation Feedback Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP www.ti.com SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 Receiver Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP (1) TEST CONDITIONS VIT+ Positive-going differential input threshold voltage IO = -8 mA VIT- Negative-going differential input threshold voltage IO = 8 mA Vhys Hysteresis voltage (VIT+ - VIT-) VIK Enable-input clamp voltage 'HVD30 'HVD33 IO(Z) High-impedance-state output current 50 V 2.4 0.4 VO = 0 or VCC, RE at VCC -1 VA or VB = 12 V, VCC = 0 V VA or VB = -7 V Other input at 0 V VA or VB = -7 V, VCC = 0 V Bus input current VA or VB = 12 V, VCC = 0 V VA or VB = -7 V Other input at 0 V VA or VB = -7 V, VCC = 0 V IIH Input current, RE VIH = 0.8 V or 2 V CID Differential input capacitance VID = 0.4 sin (4E6t) + 0.5 V, DE at 0 V 1 0.05 0.1 0.06 0.1 -0.10 -0.04 -0.10 -0.03 VA or VB = 12 V 'HVD30, 'HVD33 mV -1.5 VA or VB = 12 V IA or IB V V VID = -200 mV, IO = 8 mA, See Figure 8 'HVD31, 'HVD32, 'HVD34, 'HVD35 -0.02 -0.2 VID = 200 mV, IO = -8 mA, See Figure 8 Output voltage UNIT -0.15 II = -18 mA VO MAX 0.20 0.35 0.24 0.4 -0.35 -0.18 -0.25 -0.13 V A mA A -60 15 pF Supply Current 'HVD30 'HVD31, 'HVD32 'HVD33 'HVD34, 'HVD35 ICC 'HVD33, 'HVD34, 'HVD35 Supply current 'HVD33 'HVD34, 'HVD35 'HVD33 'HVD34, 'HVD35 (1) 2.1 D at 0 V or VCC and no load 6.4 RE at 0 V, D at 0 V or VCC, DE at 0 V, No load (receiver enabled and driver disabled) 1.8 mA 2.2 RE at VCC, D at VCC, DE at 0 V, No load (receiver disabled and driver disabled) 0.022 1.5 RE at 0 V, D at 0 V or VCC, DE at VCC, No load (receiver enabled and driver enabled) 2.1 RE at VCC, D at 0 V or VCC, DE at VCC No load (receiver disabled and driver enabled) 1.8 A 6.5 mA 6.2 All typical values at 25C with 3.3-V supply Receiver Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 26 60 tPLH Propagation delay time, low- to high-level output 'HVD30, 'HVD33 'HVD31, 'HVD32, 'HVD34, 'HVD35 47 70 tPHL Propagation delay time, high- to low-level output 'HVD30, 'HVD33 29 60 'HVD31, 'HVD32, 'HVD34, 'HVD35 49 70 tsk(p) Pulse skew (|tPHL - tPLH|) tr Output signal rise time tf Output signal fall time (1) 'HVD30, 'HVD33 VID = -1.5 V to 1.5 V, CL = 15 pF, See Figure 9 12 'HVD31, 'HVD34, 'HVD32, 'HVD35 10 'HVD30 10 'HVD33 18 12.5 UNIT ns ns ns ns ns All typical values 25C with 3.3-V supply Copyright (c) 2006-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP 7 SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 www.ti.com Receiver Switching Characteristics (continued) over recommended operating conditions (unless otherwise noted) PARAMETER tPHZ Output disable time from high level tPZH1 Output enable time to high level Propagation delay time, standby to high-level output 'HVD33 tPLZ Output disable time from low level tPZL1 Output enable time to low level Propagation delay time, standby to low-level output MIN TYP (1) MAX DE at 3 V CL = 15 pF, See Figure 10 'HVD30 tPZH2 tPZL2 TEST CONDITIONS CL = 15 pF, See Figure 11 ns ns 20 ns 20 ns 4000 DE at 0 V 'HVD33 ns 20 5000 DE at 3 V 'HVD30 20 4000 DE at 0 V UNIT 5000 ns Receiver Equalization Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS DEVICE 25 Mbps tj(pp) Peak-to-peak eye-pattern jitter Pseudo-random NRZ code with a bit pattern length of 216 - 1, Belden 3105A cable 10 Mbps 5 Mbps 3 Mbps 1 Mbps (1) (2) TYP (1) MIN 100 m 'HVD33 (2) PREVIEW 150 m 'HVD33 (2) PREVIEW 200 m 'HVD33 (2) PREVIEW 200 m 'HVD33 (2) PREVIEW 250 m 'HVD33 (2) PREVIEW 300 m 'HVD33 (2) PREVIEW 500 m 'HVD34 (2) PREVIEW 'HVD33 (2) PREVIEW 'HVD34 (2) PREVIEW (2) PREVIEW 500 m 1000 m 'HVD34 MAX UNIT ns All typical values are at VCC = 5 V and temperature = 25C. The SN65HVD33 and the SN65HVD34 do not have receiver equalization, but are specified for comparison. Device Power Dissipation - PD DEVICE TEST CONDITIONS MIN MAX 'HVD30 (25 Mbps) 'HVD31 (5 Mbps) RL = 60 , CL = 50 pF, Input to D a 50% duty cycle square wave at indicated signaling rate, TA = 85C 'HVD32 (1 Mbps) mW 197 RL = 60 , CL = 50 pF, DE at VCC, RE at 0 V, Input to D a 50% duty cycle square wave at indicated signaling rate, TA = 85C 'HVD35 (1 Mbps) 8 213 193 'HVD33 (25 Mbps) 'HVD34 (5 Mbps) UNIT 197 Submit Documentation Feedback 193 mW 248 Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP www.ti.com SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 PARAMETER MEASUREMENT INFORMATION VCC DE II Y IY VOD 0 or 3 V Z RL IZ VI VZ VY Figure 1. Driver VOD Test Circuit and Voltage and Current Definitions 375 1% VCC DE D Y VOD 0 or 3 V 60 1% + _ -7 V < V(test) < 12 V Z 375 1% Figure 2. Driver VOD With Common-Mode Loading Test Circuit VOD(SS) VOD(RING) 0 V Differential VOD(RING) -VOD(SS) Figure 3. VOD(RING) Waveform and Definitions VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from the VOD(H) and VOD(L) steady state values. VCC DE Input D 27 1% Y Y VY Z VZ VOC(PP) Z 27 1% CL = 50 pF 20% VOC VOC(SS) VOC Input: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Figure 4. Test Circuit and Definitions for Driver Common-Mode Output Voltage Copyright (c) 2006-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP 9 SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Y W Z W A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Figure 5. Driver Switching Test Circuit and Voltage Waveforms D 3V 0V 3V S1 Y Z Y S1 D VO 1.5 V 1.5 V VI 0.5 V t PZH(1 & 2) Z 0V V OH DE Input Generator VI RL = 110 W 1% CL = 50 pF 20% 50 W VO 2.3 V ~0V tPHZ A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 B. CL Includes Fixture and Instrumentation Capacitance Figure 6. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms D 3V 0V VCC S1 Z Y RL = 110 1% Y A. 1.5 V VO DE VI 1.5 V VI S1 D Input Generator 3V 0V Z t PZL(1&2) t PLZ VCC CL = 50 pF 20% 50 0.5 V CL Includes Fixture and Instrumentation Capacitance VO 2.3 V VOL Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms IA VA VA + VB 2 VIC A R VID IO B VB IB RE II VO VI Figure 8. Receiver Voltage and Current Definitions 10 Submit Documentation Feedback Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP www.ti.com SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 PARAMETER MEASUREMENT INFORMATION (continued) 3V A R Input Generator VI 50 1.5 V 0V B 1.5 V 0V CL = 15 pF 20% RE 1.5 V VI VO t PLH VO t PHL 90% 90% 1.5 V 10% tr A. CL Includes Fixture and Instrumentation Capacitance B. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 VOH 1.5 V 10% V OL tf Figure 9. Receiver Switching Test Circuit and Voltage Waveforms 1.5 V V CC A R 0V B VI S1 C L = 15 pF 20% RE Input Generator 1 k W 1% VO 3V A VI 1.5V 1.5V 0V B t PHZ t PZH(1 & 2) V OH 50 W 1.5 V VO 0.5V ~0 V A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Figure 10. Receiver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms 0V V CC A R 1.5 V V O 1 k W 1% B RE Input V Generator I 50 W C L = 15 pF 20% S1 3V A VI 1.5V 1.5V B 0V t PZL(1 & 2) VO t PLZ 1.5 V V CC 0.5 V V OL A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Figure 11. Receiver Enable Time From Standby (Driver Disabled) Copyright (c) 2006-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP 11 SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 0 V or 3 V DE A Y D R Z 100 W 1% + - Pulse Generator 15 ms duration 1% Duty Cycle tr, tf 100 ns 100 W 1% B RE 0 V or 3 V + - Figure 12. Test Circuit, Transient Over Voltage Test 12 Submit Documentation Feedback Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP www.ti.com SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 DEVICE INFORMATION Low-Power Standby Mode When both the driver and receiver are disabled (DE low and RE high), the device is in standby mode. If the enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs are held in this state for 300 ns or more, the device is assured to be in standby mode. In this low-power standby mode, most internal circuitry is powered down, and the supply current is typically less than 1 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active. 12 R RE 2 11 A B 3 Low-Power Standby DE 4 9 D 5 10 Y Z Figure 13. Low-Power Standby Logic Diagram If only the driver is re-enabled (DE transitions to high), the driver outputs are driven according to the D input after the enable times given by tPZH2 and tPZL2 in the driver switching characteristics. If the D input is open when the driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver fail-safe feature. If only the receiver is re-enabled (RE transitions to low), the receiver output is driven according to the state of the bus inputs (A and B) after the enable times given by tPZH2 and tPZL2 in the receiver switching characteristics. If there is no valid state on the bus, the receiver responds as described in the fail-safe operation section. If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver outputs are valid. Copyright (c) 2006-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP 13 SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 www.ti.com FUNCTION TABLES Table 1. SN65HVD33, SN65HVD34, SN65HVD35 DRIVER (1) INPUTS (1) OUTPUTS D DE Y Z H H H L L H L H X L or open Z Z Open H L H H = high level, L = low level, Z = high impedance, X = irrelevant Table 2. SN65HVD33, SN65HVD34, SN65HVD35 RECEIVER (1) DIFFERENTIAL INPUTS VID = V(A) - V(B) ENABLE RE OUTPUT R VID -0.2 V L L -0.2 V < VID < -0.02 V L ? -0.02 V VID L H X H or open Z Open circuit L H Idle circuit L H Short circuit, V(A) = V(B) L H (1) H = high level, L = low level, Z = high impedance, X = irrelevant, ? = indeterminate Table 3. SN65HVD30, SN65HVD31, SN65HVD32 DRIVER (1) (1) OUTPUTS INPUT D Y H H L L L H Open L H Z H = high level, L = low level Table 4. SN65HVD30, SN65HVD31, SN65HVD32 RECEIVER (1) (1) 14 DIFFERENTIAL INPUTS VID = V(A) - V(B) OUTPUT R VID -0.15 V L -0.15 V < VID < -0.02 V ? -0.02 V VID H Open circuit H Idle circuit H Short circuit, V(A) = V(B) H H = high level, L = low level, ? = indeterminate Submit Documentation Feedback Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP www.ti.com SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS D and DE Input RE Input VCC VCC 130 kW Input 470 W Input 470 W 9V 9V 125 kW A Input B Input VCC VCC R1 22 V 22 V R3 R3 Input R1 Input 22 V R2 22 V R2 R Output Y and Z Outputs VCC VCC 16 V 5W Output 16 V Output 9V R1/R2 R3 SN65HVD30, SN65HVD33 9 k 45 k SN65HVD31, SN65HVD32, SN65HVD34, SN65HVD35 36 k 180 k Copyright (c) 2006-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP 15 SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS 'HVD30, 'HVD33 RMS SUPPLY CURRENT vs SIGNALING RATE 'HVD31, 'HVD34 RMS SUPPLY CURRENT vs SIGNALING RATE 60 55 TA = 25C RL = 54 W RE = VCC CL = 50 pF DE = VCC 55 ICC - RMS Supply Current - mA 50 ICC - RMS Supply Current - mA TA = 25C RL = 54 W RE = VCC CL = 50 pF DE = VCC 45 VCC = 3.3 V 40 35 50 VCC = 3.3 V 45 40 35 30 30 0 5 10 15 20 0 25 1 2 3 4 5 Signaling Rate - Mbps Signaling Rate - Mbps Figure 14. Figure 15. 'HVD32, 'HVD35 RMS SUPPLY CURRENT vs SIGNALING RATE 60 TA = 25C RL = 54 W RE = VCC CL = 50 pF DE = VCC ICC - RMS Supply Current - mA 55 50 VCC = 3.3 V 45 40 35 30 0 0.2 0.4 0.6 0.8 1 Signaling Rate - Mbps Figure 16. 16 Submit Documentation Feedback Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP www.ti.com SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) 'HVD30, 'HVD33 BUS INPUT CURRENT vs INPUT VOLTAGE 'HVD31, 'HVD32, 'HVD34, 'HVD35 BUS INPUT CURRENT vs INPUT VOLTAGE 250 60 TA = 25C RE = 0 V DE = 0 V 200 TA = 25C RE = 0 V DE = 0 V 40 100 II - Bus Input Current - uA II - Bus Input Current - mA 150 50 VCC = 3.3 V 0 -50 -100 20 0 VCC = 3.3 V -20 -40 -150 -200 -7 -60 -4 -1 2 5 8 11 14 -7 -4 -1 VI - Bus Input Voltage - V 5 8 11 Figure 17. Figure 18. DRIVER LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE DRIVER HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 14 0.01 0.14 VCC = 3.3 V DE = VCC D=0V 0.12 IOH - Driver High-Level Output Current - A IOL - Driver Low-Level Output Current - A 2 VI - Bus Input Voltage - V 0.1 0.08 0.06 0.04 0.02 0 -0.02 VCC = 3.3 V DE = VCC D=0V -0.01 -0.03 -0.05 -0.07 -0.09 -0.11 -0.13 0 0.5 1 1.5 2 2.5 VOL - Low-Level Output Voltage - V Figure 19. Copyright (c) 2006-2012, Texas Instruments Incorporated 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 VOH - High-Level Output Voltage - V Figure 20. Submit Documentation Feedback Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP 17 SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP SGLS367D - SEPTEMBER 2006 - REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE DRIVER OUTPUT CURRENT vs SUPPLY VOLTAGE 40 VCC = 3.3 V DE = VCC D = VCC 2.1 2.0 1.9 30 25 20 15 10 5 1.8 0 -40 -15 10 35 TA - Free-Air Temperature - C Figure 21. 18 TA = 25C RL = 54 W D = VCC DE = VCC 35 IO - Driver Output Current - mA VOD - Driver Differential Output Voltage - V 2.2 Submit Documentation Feedback 60 85 0 0.5 1 1.5 2 2.5 3 3.5 VCC Supply Voltage - V Figure 22. Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP SN65HVD35-EP PACKAGE OPTION ADDENDUM www.ti.com 22-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65HVD30MDREP ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD30MDREPG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD33MDREP ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD33MDREPG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/06634-01XE ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/06634-04YE ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF SN65HVD30-EP, SN65HVD33-EP : * Catalog: SN65HVD30, SN65HVD33 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65HVD30MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65HVD33MDREP SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65HVD30MDREP SOIC SN65HVD33MDREP SOIC D 8 2500 367.0 367.0 35.0 D 14 2500 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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