March 1998 Revision 1.0 data sheet PDC2UV6484A-(75/102/103)T-S 16MByte (2M x 64) CMOS, PC/100 Synchronous DRAM Module General Description The PDC2UV6484A-(75/102/103)T-S is a high performance, 16-megabyte synchronous, dynamic RAM module organized as 2M words by 64 bits, in a 168-pin, dual-in-line memory module (DIMM) package. The module utilizes eight Fujitsu MB81F16822B-(75/102/103) FN CMOS 2Mx8 synchronous dynamic RAMs in surface mount package (TSOP) on an epoxy laminated substrate. Each device is accompanied by a decoupling capacitor for improved noise immunity. A 256 Byte Serial EEPROM contains the module configuration information. Features * High Density: 16MByte * Cycle Time: 7.5ns (-75), 10ns (-102), 10ns (-103) * Low Power: Active 4.3W (-75), 4.0W (-102), 3.7W (-103) * LVTTL-compatible inputs and outputs * Separate power and ground planes to improve noise immunity * Single power supply of 3.3V0.3V * Height: 1.250 inch ABSOLUTE MAXIMUM RATINGS Item Symbol Ratings Unit Voltage on any pin relative to VSS VT -0.5 to +4.6 V Power Dissipation PT 10.4 W Operating Temperature Topr 0 to +70 C Storage Temperate Tstg -55 to +125 C Short Circuit Output Current IOS 50 mA RECOMMENDED DC OPERATING CONDITIONS (TA = 0 to +70 C) Symbol Parameter VCC Supply Voltage VSS Ground Min Typ Max Unit 3.0 3.3 3.6 V 0 0 0 V V V VIH Input High voltage 2.0 - VCC+0.5 VIL Input Low voltage -0.5 - 0.8 Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH 1 March 1998 Revision 1.0 PDC2UV6484A-(75/102/103)T-S Functional Diagram DQMB6 DQMB7 DQMB2 DQMB3 CS2* DQMB4 DQMB5 DQMB0 DQM DQM DQM DQM DQM DQM DQM DQM WE* WE* WE* WE* WE* RAS* RAS* RAS* RAS* RAS* CAS* CAS* CAS* CAS* CAS* CLK0 CLK CLK CKE0 CKE DQMB1 CS0* A0-A10, BA0 2M X 16 SDRAM CKE CLK2 CLK CLK 2M X 16 SDRAM CKE 2M X 16 SDRAM CKE 2M X 16 SDRAM CS* CS* CS* CS* A0-A10, BA0 A0-A10, BA0 A0-A10, BA0 A0-A10, BA0 DQ32~DQ39 DQ40~DQ47 DQ0~DQ7 DQ8~DQ15 DQ16~DQ23 DQ24~DQ31 DQ48~DQ55 DQ56~DQ63 DQ0~DQ63 SA0-SA2 A0~A2 SDA SCL SCL EEPROM Two 0.1 F SDA VCC WP 47K VSS Decoupling capacitors to all devices (All specifications of the device are subject to change without notice.) Notes: 1. Data and CLKs are terminated using 10 ohm series resistors. 2. Two 2Mx8 devices compose each 2Mx16 block. 3. DQMs vs Data I/Os 4. Clock Wiring DQMB0 controls DQMB1 controls DQMB2 controls DQMB3 controls DQMB4 controls DQMB5 controls DQMB6 controls DQMB7 controls 10 CLK0, CLK2 SDRAM1 SDRAM2 SDRAM3 SDRAM4 3.3pF 2 DQ0 ~ DQ7 DQ8 ~ DQ15 DQ16 ~ DQ23 DQ24 ~ DQ31 DQ32 ~ DQ39 DQ40 ~ DQ47 DQ48 ~ DQ55 DQ56 ~ DQ63 10 CLK1, CLK3 10pF Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH March 1998 Revision 1.0 PDC2UV6484A-(75/102/103)T-S Pin Name A0~A10 BA0 DQ0~DQ63 CLK0~CLK3 RAS* CAS* CKE0 DQMB0-DQMB7 Pin No. 1 Addresses Bank Select Address Data Inputs/Outputs Clock Inputs Row Address Strobes Column Address Strobes Clock Enables DQ Mask Enables Pin Designation VSS Pin No. 43 Pin Designation VSS CS0*, CS2* WE* SA0-SA2 SCL SDA WP VCC VSS NC Pin No. 85 Pin Designation VSS Chip Select Write Enable Decode Input Serial Clock Serial Data Input/Output Write Protect Power Supply Ground No Connection Pin No. 127 Pin Designation VSS 2 DQ0 44 NC 86 DQ32 128 CKE0 3 DQ1 45 CS2* 87 DQ33 129 NC 4 DQ2 46 DQMB2 88 DQ34 130 DQMB6 5 DQ3 47 DQMB3 89 DQ35 131 DQMB7 6 VCC 48 NC 90 VCC 132 NC 7 DQ4 49 VCC 91 DQ36 133 VCC 8 DQ5 50 NC 92 DQ37 134 NC 9 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 NC 94 DQ39 136 NC 11 DQ8 53 NC 95 DQ40 137 NC 12 VSS 54 VSS 96 VSS 138 VSS 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 VCC 101 DQ45 143 VCC 18 VCC 60 DQ20 102 VCC 144 DQ52 19 DQ14 61 NC 103 DQ46 145 NC 20 DQ15 62 NC 104 DQ47 146 NC 21 NC 63 NC 105 NC 147 NC 22 NC 64 VSS 106 NC 148 VSS 23 VSS 65 DQ21 107 VSS 149 DQ53 24 NC 66 DQ22 108 NC 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 VCC 68 VSS 110 VCC 152 VSS 27 WE* 69 DQ24 111 CAS* 153 DQ56 28 DQMB0 70 DQ25 112 DQMB4 154 DQ57 29 DQMB1 71 DQ26 113 DQMB5 155 DQ58 30 CS0* 72 DQ27 114 NC 156 DQ59 31 NC 73 VCC 115 RAS* 157 VCC 32 VSS 74 DQ28 116 VSS 158 DQ60 33 A0 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78 VSS 120 A7 162 VSS 37 A8 79 CLK2 121 A9 163 CLK3 38 A10 80 NC 122 BA0 164 NC 39 NC 81 WP 123 NC 165 SA0 40 VCC 82 SDA 124 VCC 166 SA1 41 VCC 83 SCL 125 CLK1 167 SA2 42 CLK0 84 VCC 126 NC 168 VCC Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH 3 March 1998 Revision 1.0 PDC2UV6484A-(75/102/103)T-S SERIAL PD INFORMATION Byte# Function Supported 75 102 103 75 103 # Bytes Written into serial memory at module mfr Total # bytes of SPD memory device Fundamental memory type # Row Address on this assembly # Column Addresses on this assembly # Module Banks on this assembly Data Width of this assembly Data Width of this assembly (continued) Voltage interface standard of this assembly SDRAM cycle time at CL=3 (tCLK) SDRAM Access from Clock at CL=3 (tAC) DIMM configuration type Refresh Rate/Type SDRAM Width Primary DRAM ECC SDRAM Data Width Min. clock delay, Back to Back Random Column Addresses (ICCD) Burst Length Supported # Banks on each SDRAM device CAS# Latency CS# Latency Write Latency SDRAM Module Attribute SDRAM Device Attribute Min Clock cycle Time at CL=2 (tCLK) Max. Data Access Time from clock at CL=2 (tAC) Min Clock cycle Time at CL=1 (tCLK) Max. Data Access Time from clock at CL=1 (tAC) Min. Row Precharge Time (tRP) Min. Row Active Delay (tRRD) Min. RAS to CAS Delay (tRCD) Min. RAS Pulse Width (tRAS) Module Bank Density Address and Command Signal Input Setup Time before clock (tSI) 20h 80h 08h 04h 0Bh 09h 01h 40h 00h 01h A0h 60h 00h 80h 08h 00h 01h 8Fh 02h 06h 01h 01h 00h 0Eh A0h 60h FFh FFh 14h 14h 14h 32h 04h 20h 33 Address and Command Signal Input Hold Time after clock (tHI) 1ns 1ns 1ns 10h 10h 10h 34 Data Signal Input Setup Time before clock (tSI) 2ns 2ns 2ns 20h 20h 20h 35 Data Signal Input Hold Time after clock (tHI) 1ns 1ns 1ns 10h 10h 10h Superset Information SPD Revision Checksum for bytes 0-62 128 bytes 256 bytes SDRAM 11 9 1 64 bits Hex Value 102 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 36-61 62 63 4 Function Described LVTTL 10ns 10ns 6ns 6ns Non-Parity S/R, Normal 15.6 ms x8 N/A 1CLK 1, 2, 4, 8 & Full 2 2,3 0 0 Non-Buffered/Registered Vcc, B/R, S/W, P/A, A/P 11.5ns 10ns 12ns 7ns 6ns 7ns N/A N/A 22.5ns 20ns 20ns 15ns 20ns 20ns 22.5ns 20ns 20ns 45ns 50ns 50ns 16MB 2ns 2ns 2ns 7.5ns 6ns Rev. 2 JEDEC Calculation 75h 60h B5h 70h 17h 0Fh 17h 2Dh A0h 60h C0h 70h 14h 14h 14h 32h 20h FFh 02h JEDEC Calculation Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH March 1998 Revision 1.0 PDC2UV6484A-(75/102/103)T-S SERIAL PD INFORMATION (CONTINUED) Function Supported Byte# 64 65 66-71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95-98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128-255 Function Described Manufacturers JEDEC ID code per JEP-106E Manufacturers JEDEC ID code per JEP-106E Manufacturers JEDEC ID code per JEP-106E Manufacturing location Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Revision Code Revision Code Manufacturing Date Manufacturing Date Assembly Serial Number Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Open for CPQ Use for Read & Write Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH 75 102 Continuation code SMART's ID None Mfr Specific Data P D C 2 U V 6 4 8 4 A 7 1 5 0 T 2 S T None S None None Mfr Specific Data None DATE DATE Serial Number S M A R T M o d u l a r T e c h n o l o g i e s None None None None None None Hex Value 103 75 102 103 7Fh 94h FFh 1 0 3 T S 37h 35h 54h 53h FFh 50h 44h 43h 32h 55h 56h 36h 34h 38h 34h 41h 31h 30h 32h 54h 53h FFh FFh Mfr Specific Data FFh DATE DATE S.No. 53h 4Dh 41h 52h 54h 4Dh 6Fh 64h 75h 6Ch 61h 72h 54h 65h 63h 68h 6Eh 6Fh 6Ch 6Fh 67h 69h 65h 73h FFh FFh FFh FFh FFh FFh 31h 30h 33h 54h 53h 5 March1998 Revision 1.0 PDC2UV6484A-(75/102/103)T-S DC CHARACTERISTICS (At recommended operating conditions unless otherwise noted) Notes 1,2 Value Parameter Symbol Conditions Unit Min. Max. Output High Voltage VOH(DC) IOH = -2mA 2.4 - V Output Low Voltage VOL(DC) IOL = 2mA - 0.4 V Input Leakage Current (Any Input) ILI 0V VIN VCC; All other pins not under test = 0V -40 40 A Output Leakage Current ILO 0V VIN VCC Dout = Disable -5 5 A 75 102 ICC1S Burst: Length=4, tRC = min for BL=4, tCK = min. One bank- active, Outputs open, Addresses changed up to 3-times during tRC (min), 800 - 800 103 0V Vin VCC 720 75 Burst: Length=4 (each bank), tRC = min for BL=4 (each bank), tCK = min. All banks active, Output open, Addresses changed up to 3-times during tRC (min), 1200 mA Operating Current (Average Power Supply Current) 102 ICC1D 0V Vin VCC 103 - ICC2PS CKE=VIL, All banks idle, CLK=H or L, Power down mode, 0V Vin VCC - 3.2 - 216 - 160 - 160 - 120 ICC2N 103 Precharge Standby Current (Power Supply Current) 6 ICC2NS CKE=VIH, All banks idle, tCK=min, NOP commands only, Input signals (except to CMD) are changed one time during 3 clock cycles, 0V Vin VCC CKE=VIH, All banks idle, CLK=H or L, Input signals are stable, 0V Vin VCC mA 1040 ICC2P 75 102 1120 CKE=VIL, All banks idle, tCK=min, Power down mode, 0V Vin VCC Precharge Standby Current (Power Supply Current) Precharge Standby Current (Power Supply Current) - 3.2 mA mA Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH March 1998 Revision 1.0 PDC2UV6484A-(75/102/103)T-S (Continued) Value Parameter Symbol ICC3P Max. - 40 mA - 24 mA - 432 mA - 320 mA - 320 mA - 200 mA CKE=VIL, Any bank active, tCK=min, ICC3PS CKE=VIL, Any bank active, CLK = H or L, 0V Vin VCC ICC3N CKE=VIH, Any bank active, tCK=min, NOP commands only, Input signals (except to CMD) are changed one time during 3 clock cycles, 0V Vin VCC 75 102 103 ICC3NS Active Standby Current (Power Supply Current) 75 Burst mode Current (Average Power supply current) Unit Min. 0V Vin VCC Active Standby Current (Power Supply Current) Active Standby Current (Power Supply Current) Test Condition 102 ICC4 CKE=VIH, Any bank active, CLK = H or L, 0V Vin VCC tCK=min, Burst length=4, Outputs open, Multiple-banks active, Gapless data, 0V Vin VCC 1200 - 103 102 ICC5 Refresh Current #2 (Average Power Supply Current) Auto-refresh; tCK=min, tRC=min, 800 - 0V Vin VCC 103 Refresh Current #2 (Average Power Supply Current) mA 960 75 Refresh Current #1 (Average Power Supply Current) 960 ICC6 ICC6A Self-refresh; tCK=min, CKE 0.2V, 0V Vin VCC Asynchronous Self-refresh (by CLK stop); CKE 0.2V, CLK = VIL, 640 mA 640 - 3.2 mA - 3.2 mA 0V Vin VCC CL = CAS* Latency Notes: 1. ICC depends on the output termination or load conditions, clock cycle rate, and signal clocking rate; The specified values are obtained with the output open and no termination register. 2. An initial pause (DESL or NOP) of 200 s is required after power-up followed by a minimum of eight Auto-refresh cycles. Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH 7 March 1998 Revision 1.0 PDC2UV6484A-(75/102/103)T-S CAPACITANCE (TA =+25C, VCC = 3.3V0.3V) Parameter Symbol Max. Unit Notes Input Capacitance (Address, WE*, CKE, RAS*, CAS*) CI1 45 pF 1 Input Capacitance (DQMBs) CI2 10 pF 1 Input Capacitance (CS0*, CS2*) CI3 25 pF 1 Input Capacitance (CLK0, CLK2) CI4 25 pF 1 Input Capacitance (CLK1, CLK3) CI5 15 pF 1 Input/Output Capacitance (DQ0~DQ63) CI/O 12 pF 1, 2 Notes: 1. Capacitance is measured with Boonton Meter or effective capacitance method. 2. CAS* - VIH to disable Dout. AC CHARACTERISTICS: MB81F16822B-(75/102/103) (At recommended operating conditions unless otherwise noted) Parameter Clock Period Symbol CAS Latency=2 tCK2 CAS Latency=3 tCK3 -75 -102 -103 Min. Max. Min. Max. Min. Max. 11.5 - 10 - 12 - 7.5 - 10 - 10 - tCH ns 2.5 - 3 - 3 - Clock Low Time tCL ns 2.5 - 3 - 3 - Input Setup Time tSI ns 2 - 2 - 2 - tHI ns 1 - 1 - 1 - - 7 - 6 - 7 - 6 - 6 - 6 0 - 0 - 0 - 3 7 3 6 3 7 2 6 3 6 3 6 3 - 3 - 3 - 2 - 3 - 3 - Access time from Clock (tCK=min) CAS Latency=2 tAC2 CAS Latency=3 tAC3 Output in High-Z Output Hold Time ns tLZ Output In Low-Z CAS Latency=2 tHZ2 CAS Latency=3 tHZ3 CAS Latency=2 CAS Latency=3 ns 5,6 ns tOH 7 ns Time between Auto-Refresh command Interval tREFI s - 15.6 - 15.6 - 15.6 CKE Low (or CLK Low) Hold Time for Asynchronous Self-Refresh Entry tASE s 100 200 100 200 100 200 tT ns 0.5 2 0.5 2 0.5 2 tCKSP ns 3 - 3 - 3 - Transition Time CKE Set Up time for Power Down Exit Notes ns Clock High Time Input Hold Time 8 Unit Notes 2,3,4 Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH March1998 Revision 1.0 PDC2UV6484A-(75/102/103)T-S BASE VALUES FOR CLOCK COUNT/LATENCY: MB81F16822B-(75/102/103) Parameter Symbol Unit tRC RAS Precharge Time RAS Active Time RAS to CAS Delay Time -75 -102 -103 Min. Max. Min. Max. Min. Max. ns 67.5 - 70 - 70 - tRP ns 22.5 - 20 - 20 - tRAS ns 45 110000 50 110000 50 110000 tRCD ns 22.5 - 20 - 20 - Write Recovery Time tWR ns 7.5 - 10 - 10 - Data-in to Precharge Lead Time tDPL ns 7.5 - 10 - 10 - 1cyc+tRP - 1cyc+tRP - 1cyc+tRP - 2cyc+tRP - 2cyc+tRP - 2cyc+tRP - RAS Cycle Time Data-in to Active/Refresh command period CAS Latency=2 tDAL2 CAS Latency=3 tDAL3 Notes 8 9 ns Mode Register set cycle Time tRSC ns 15 - 20 - 20 - RAS to RAS Bank Active Delay Time tRRD ns 15 - 20 - 20 - CLOCK COUNT FORMULA (Note 10) Clock > Base Value Clock Period (Round off a whole number) LATENCY-FIXED VALUES: MB81F16822B-(75/102/103) (The latency values on these parameters are fixed regardless of clock period) Parameter Symbol Unit -75 -102 -103 ICKE cycle 1 1 1 DQM to Output in High-Z IDQZ cycle 2 2 2 DQM to Input Data Delay IDQD cycle 0 0 0 Last Output to Write Command Delay IOWD cycle 2 2 2 IDWD cycle 0 0 0 2 2 2 3 3 3 CKE to Clock Disable Write Command to Input Data Delay Precharge to Output in High-Z Delay Burst Stop Command to Output in High-Z Delay CL = 2 IROH2 CL = 3 IROH3 CL = 2 IBSH2 CL = 3 IBSH3 cycle cycle 2 2 2 3 3 3 CAS to CAS Delay (min) ICCD cycle 1 1 1 CAS Bank Delay (min) ICBD cycle 1 1 1 Notes: 1. Notes ICC depends on the output termination or load conditions, clock cycle rate, and signal clocking rate; The specified values are obtained with the output open and no termination register. 2. An initial pause (DESL or NOP) of 200 s is required after power-up followed by a minimum of eight Auto-refresh cycles. 3. AC characteristics assume tT = 1 ns and 50 pF of capacitive load. 4. 1.4 V is the reference level for measuring timing of input signals. Transition times are measured between VIH (min) and VIL (max). 5. Assumes tRCD is satisfied. 6. tAC also specifies the access time at burst mode. 7. Specified where output buffer is no longer driven. 8. Actual clock count of tRC (IRC) will be sum of clock count of tRAS (IRAS) and tRP (IRP). 9. Operation within the(tRCD) (min) ensures that access time is determined by (tRCD) (min) + (tAC) (max); If tRCD is greater than the specified tRCD (min), access time is determined by tAC. 10. All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off a whole number). Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH 9 March 1998 Revision 1.0 PDC2UV6484A-(75/102/103)T-S Fig. 4 - EXAMPLE OF AC TEST LOAD CIRCUIT R1 = 50 1.4V Output CL = 50pF LVTTL Note: AC characteristics are measured in this condition. This load circuits are not applicable for VOH and VOL. 10 Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH March 1998 Revision 1.0 PDC2UV6484A-(75/102/103)T-S Physical Dimensions 168-pin (84x2) DIMM 5.250 0.102 (max.) 5.171 5.014 0.088 0.175 0.158 0.700 0.118 1.250 0.324 "A" 1 11 0.450 40 "A" 41 84 2.150 1.450 0.250 1.700 2.507 0.118 0.250 0.050 +0.004/-0.003 4.550 (Ref.) 5.014 0.123 0.350 Front View Notes: 1. All dimensions are in inches. 2. Pin 85 is behind pin 1 on the back side. Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH 0.079 Detail "A" 11 March 1998 Revision 1.0 PDC2UV6484A-(75/102/103)T-S Ordering Information P D C 2 U V 64 8 4 A - 102 T - S (1) (1) (2) (3) (4) . (5) 12 (2) (3) (4) (5) (6) (7) (8) (9) (10) Memory Type S : SDRAM (PC/66) G : SGRAM P : SDRAM-Fast (PC/100) Module Shape S : SIMM D : DIMM O : Small Outline DIMM Module Pin Count A : 72-pin B : 144-pin C : 168-pin D : 200-pin Word Depth 1 : 1M 2 : 2M 4 : 4M 8 : 8M 16 : 16M 256 : 256K 512 : 512K (11) (10) (12) (13) Module Revision / Applied "Standard" Blank : Rev. 0 A : Rev. 1 B : Rev. 2 (etc.) *1 *1 When DRAM device or PCB is revised, the revision is changed (11) Clock Frequency SDRAM (PC/66) 100 : 100Mhz SDRAM-Fast (100Mhz, PC/100) 75 : 133 Mhz (CL=3; tRCD=3; tRP=3) 102 : 100 Mhz (CL=2; tRCD=2; tRP=2) 103 : 100 Mhz (CL=3; tRCD=2; tRP=2) 10 : 100 Mhz (CL=3; tRCD=3; tRP=3) (12) Package of Component T : TSOP (13) Assembly & Test Site S : Smart Modular Technologies Buffer Type B : Buffered U : Unbuffered R : Registered (6) Operating Voltage & Power Consumption V : 3.3V & LVTTL & Standard Power L : 3.3V & LVTTL & Low Power S : 3.3V & SSTL & Standard Power (7) Data Width (ex. 64=x64, 72=x72 etc.) (8) Device Configuration 4 : x4 8 : x8 1 : x16 3 : x32 (9) Refresh 2 : 2krf 4 : 4krf 8 : 8krf Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH March 1998 Revision 1.0 PDC2UV6484A-(75/102/103)T-S FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Memory Marketing Dept. 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki 211-88, Japan Tel: +81-44-754-3767 Fax: +81-44-754-3343 Internet: http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street San Jose, CA 95134-1804, USA. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center (Mon-Fri: 7am-5pm (PST)) Tel: +1-800-866-8608 Fax: +1-408-922-9179 Internet: http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 Internet: http://www.fujitsu-ede.com/ Asia FUJITSU MICROELECTRONICS ASIA PTE LIMITED #05-08, 151 Lorong Chuan NewTechPark Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 Internet: http://www.fsl.com.sg/ FUJITSU LIMITED 1998 Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information given in this document have been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any licence under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support. MP-DS-SDRAMM-20692-3/98 13