PDC2UV6484A-75T-S - Fujitsu Quantum Devices Limited

data sheet March 1998

Revision 1.0

1Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH

PDC2UV6484A-(75/102/103)T-S

16MByte (2M x 64) CMOS, PC/100

Synchronous DRAM Module

General Description

The PDC2UV6484A-(75/102/103)T-S is a high performance, 16-megabyte synchronous, dynamic RAM module organized as 2M

words by 64 bits, in a 168-pin, dual-in-line memory module (DIMM) package.

The module utilizes eight Fujitsu MB81F16822B-(75/102/103) FN CMOS 2Mx8 synchronous dynamic RAMs in surface mount

package (TSOP) on an epoxy laminated substrate. Each device is accompanied by a decoupling capacitor for improved noise

immunity.

A 256 Byte Serial EEPROM contains the module configuration information.

Features

•High Density:16MByte

•Cycle Time: 7.5ns (-75), 10ns (-102), 10ns (-103)

•Low Power: Active 4.3W (-75), 4.0W (-102), 3.7W (-103)

•LVTTL-compatible inputs and outputs

•Separate power and ground planes to improve noise immunity

•Single power supply of 3.3V±0.3V

•Height: 1.250 inch

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED DC OPERATING CONDITIONS

(TA = 0 to +70 °C)

Item Symbol Ratings Unit

Voltage on any pin relative to VSS VT-0.5 to +4.6 V

Power Dissipation PT10.4 W

Operating Temperature Topr 0 to +70 °C

Storage Temperate Tstg -55 to +125 °C

Short Circuit Output Current IOS ±50 mA

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage 3.0 3.3 3.6 V

VSS Ground 0 0 0 V

VIH Input High voltage 2.0 - VCC+0.5 V

VIL Input Low voltage -0.5 - 0.8 V

PDC2UV6484A-(75/102/103)T-S

March 1998

Revision 1.0

2 Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH

Functional Diagram

Notes: 1. Data and CLKs are terminated using 10 ohm series resistors.

2. Two 2Mx8 devices compose each 2Mx16 block.

3. DQMs vs Data I/Os DQMB0 controls DQ0 ~ DQ7

DQMB1 controls DQ8 ~ DQ15

DQMB2 controls DQ16 ~ DQ23

DQMB3 controls DQ24 ~ DQ31

DQMB4 controls DQ32 ~ DQ39

DQMB5 controls DQ40 ~ DQ47

DQMB6 controls DQ48 ~ DQ55

DQMB7 controls DQ56 ~ DQ63

4. Clock Wiring

(All specifications of the device are subject to change without notice.)

DQMB6

DQMB7

DQMB2

DQMB3

DQMB4

DQMB5

DQMB0

DQMB1 DQM

DQM

WE*

RAS*

CAS*

CLK

CKE

CS*

A0-A10, BA0

WE*

RAS*

CAS*

CLK0

CKE0

CS0*

A0-A10, BA0

DQM

WE*

RAS*

CAS*

CLK

CKE

CS*

A0-A10, BA0

DQM

WE*

RAS*

CAS*

CLK

CKE

CS*

A0-A10, BA0

2M X 16

SDRAM

DQM

WE*

RAS*

CAS*

CLK

CKE

CS*

A0-A10, BA0

CS2*

DQ0~DQ7

DQ0~DQ63

SA0-SA2

SCL A0~A2

SCL SDA

EEPROM

SDA

VCC VSS

Decoupling capacitors

to all devices

DQ8~DQ15 DQ16~DQ23

DQ24~DQ31

DQ32~DQ39

DQ40~DQ47 DQ48~DQ55

DQ56~DQ63

CLK2

Two 0.1 µF

2M X 16

SDRAM 2M X 16

SDRAM

47KΩ

CLK0, CLK2 CLK1, CLK3

SDRAM1

SDRAM2

10pF

SDRAM3

SDRAM4

10Ω

3.3pF

March 1998

Revision 1.0

PDC2UV6484A-(75/102/103)T-S

3Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH

Pin Name

A0~A10 Addresses CS0*, CS2* Chip Select

BA0 Bank Select Address WE* Write Enable

DQ0~DQ63 Data Inputs/Outputs SA0-SA2 Decode Input

CLK0~CLK3 Clock Inputs SCL Serial Clock

RAS* Row Address Strobes SDA Serial Data Input/Output

CAS* Column Address Strobes WP Write Protect

CKE0 Clock Enables VCC Power Supply

DQMB0-DQMB7 DQ Mask Enables VSS Ground

NC No Connection

Pin No. Pin Designation Pin No. Pin Designation Pin No. Pin Designation Pin No. Pin Designation

1 VSS 43 VSS 85 VSS 127 VSS

2 DQ0 44 NC 86 DQ32 128 CKE0

3 DQ1 45 CS2* 87 DQ33 129 NC

4 DQ2 46 DQMB2 88 DQ34 130 DQMB6

5 DQ3 47 DQMB3 89 DQ35 131 DQMB7

6 VCC 48 NC 90 VCC 132 NC

7 DQ4 49 VCC 91 DQ36 133 VCC

8 DQ5 50 NC 92 DQ37 134 NC

9 DQ6 51 NC 93 DQ38 135 NC

10 DQ7 52 NC 94 DQ39 136 NC

11 DQ8 53 NC 95 DQ40 137 NC

12 VSS 54 VSS 96 VSS 138 VSS

13 DQ9 55 DQ16 97 DQ41 139 DQ48

14 DQ10 56 DQ17 98 DQ42 140 DQ49

15 DQ11 57 DQ18 99 DQ43 141 DQ50

16 DQ12 58 DQ19 100 DQ44 142 DQ51

17 DQ13 59 VCC 101 DQ45 143 VCC

18 VCC 60 DQ20 102 VCC 144 DQ52

19 DQ14 61 NC 103 DQ46 145 NC

20 DQ15 62 NC 104 DQ47 146 NC

21 NC 63 NC 105 NC 147 NC

22 NC 64 VSS 106 NC 148 VSS

23 VSS 65 DQ21 107 VSS 149 DQ53

24 NC 66 DQ22 108 NC 150 DQ54

25 NC 67 DQ23 109 NC 151 DQ55

26 VCC 68 VSS 110 VCC 152 VSS

27 WE* 69 DQ24 111 CAS* 153 DQ56

28 DQMB0 70 DQ25 112 DQMB4 154 DQ57

29 DQMB1 71 DQ26 113 DQMB5 155 DQ58

30 CS0* 72 DQ27 114 NC 156 DQ59

31 NC 73 VCC 115 RAS* 157 VCC

32 VSS 74 DQ28 116 VSS 158 DQ60

33 A0 75 DQ29 117 A1 159 DQ61

34 A2 76 DQ30 118 A3 160 DQ62

35 A4 77 DQ31 119 A5 161 DQ63

36 A6 78 VSS 120 A7 162 VSS

37 A8 79 CLK2 121 A9 163 CLK3

38 A10 80 NC 122 BA0 164 NC

39 NC 81 WP 123 NC 165 SA0

40 VCC 82 SDA 124 VCC 166 SA1

41 VCC 83 SCL 125 CLK1 167 SA2

42 CLK0 84 VCC 126 NC 168 VCC

PDC2UV6484A-(75/102/103)T-S

March 1998

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SERIAL PD INFORMATION

Function Supported Hex Value

Byte# Function Described 75 102 103 75 102 103

0 # Bytes Written into serial memory at module mfr 128 bytes 80h

1 Total # bytes of SPD memory device 256 bytes 08h

2 Fundamental memory type SDRAM 04h

3 # Row Address on this assembly 11 0Bh

4 # Column Addresses on this assembly 9 09h

5 # Module Banks on this assembly 1 01h

6 Data Width of this assembly 64 bits 40h

7 Data Width of this assembly (continued) 00h

8 Voltage interface standard of this assembly LVTTL 01h

9 SDRAM cycle time at CL=3 (tCLK) 7.5ns 10ns 10ns 75h A0h A0h

10 SDRAM Access from Clock at CL=3 (tAC) 6ns 6ns 6ns 60h 60h 60h

11 DIMM configuration type Non-Parity 00h

12 Refresh Rate/Type S/R, Normal 15.6 ms 80h

13 SDRAM Width Primary DRAM x8 08h

14 ECC SDRAM Data Width N/A 00h

15 Min. clock delay, Back to Back Random Column Addresses (ICCD) 1CLK 01h

16 Burst Length Supported 1, 2, 4, 8 & Full 8Fh

17 # Banks on each SDRAM device 2 02h

18 CAS# Latency 2,3 06h

19 CS# Latency 0 01h

20 Write Latency 0 01h

21 SDRAM Module Attribute Non-Buffered/Registered 00h

22 SDRAM Device Attribute Vcc, B/R, S/W, P/A, A/P 0Eh

23 Min Clock cycle Time at CL=2 (tCLK) 11.5ns 10ns 12ns B5h A0h C0h

24 Max. Data Access Time from clock at CL=2 (tAC) 7ns 6ns 7ns 70h 60h 70h

25 Min Clock cycle Time at CL=1 (tCLK) N/A FFh

26 Max. Data Access Time from clock at CL=1 (tAC) N/A FFh

27 Min. Row Precharge Time (tRP) 22.5ns 20ns 20ns 17h 14h 14h

28 Min. Row Active Delay (tRRD) 15ns 20ns 20ns 0Fh 14h 14h

29 Min. RAS to CAS Delay (tRCD) 22.5ns 20ns 20ns 17h 14h 14h

30 Min. RAS Pulse Width (tRAS) 45ns 50ns 50ns 2Dh 32h 32h

31 Module Bank Density 16MB 04h

32 Address and Command Signal Input Setup Time before clock (tSI) 2ns 2ns 2ns 20h 20h 20h

33 Address and Command Signal Input Hold Time after clock (tHI) 1ns 1ns 1ns 10h 10h 10h

34 Data Signal Input Setup Time before clock (tSI) 2ns 2ns 2ns 20h 20h 20h

35 Data Signal Input Hold Time after clock (tHI) 1ns 1ns 1ns 10h 10h 10h

36-61 Superset Information FFh

62 SPD Revision Rev. 2 02h

63 Checksum for bytes 0-62 JEDEC Calculation JEDEC Calculation

March 1998

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SERIAL PD INFORMATION (CONTINUED)

Function Supported Hex Value

Byte# Function Described 75 102 103 75 102 103

64 Manufacturers JEDEC ID code per JEP-106E Continuation code 7Fh

65 Manufacturers JEDEC ID code per JEP-106E SMART’s ID 94h

66-71 Manufacturers JEDEC ID code per JEP-106E None FFh

72 Manufacturing location Mfr Specific Data

73 Manufacturer’s Part Number P 50h

74 Manufacturer’s Part Number D 44h

75 Manufacturer’s Part Number C 43h

76 Manufacturer’s Part Number 2 32h

77 Manufacturer’s Part Number U 55h

78 Manufacturer’s Part Number V 56h

79 Manufacturer’s Part Number 6 36h

80 Manufacturer’s Part Number 4 34h

81 Manufacturer’s Part Number 8 38h

82 Manufacturer’s Part Number 4 34h

83 Manufacturer’s Part Number A 41h

84 Manufacturer’s Part Number 7 1 1 37h 31h 31h

85 Manufacturer’s Part Number 5 0 0 35h 30h 30h

86 Manufacturer’s Part Number T 2 3 54h 32h 33h

87 Manufacturer’s Part Number S T T 53h 54h 54h

88 Manufacturer’s Part Number None S S FFh 53h 53h

89 Manufacturer’s Part Number None FFh

90 Manufacturer’s Part Number None FFh

91 Revision Code Mfr Specific Data Mfr Specific Data

92 Revision Code None FFh

93 Manufacturing Date DATE DATE

94 Manufacturing Date DATE DATE

95-98 Assembly Serial Number Serial Number S.No.

99 Manufacturer Specific Data S 53h

100 Manufacturer Specific Data M 4Dh

101 Manufacturer Specific Data A 41h

102 Manufacturer Specific Data R 52h

103 Manufacturer Specific Data T 54h

104 Manufacturer Specific Data M 4Dh

105 Manufacturer Specific Data o 6Fh

106 Manufacturer Specific Data d 64h

107 Manufacturer Specific Data u 75h

108 Manufacturer Specific Data l 6Ch

109 Manufacturer Specific Data a 61h

110 Manufacturer Specific Data r 72h

111 Manufacturer Specific Data T 54h

112 Manufacturer Specific Data e 65h

113 Manufacturer Specific Data c 63h

114 Manufacturer Specific Data h 68h

115 Manufacturer Specific Data n 6Eh

116 Manufacturer Specific Data o 6Fh

117 Manufacturer Specific Data l 6Ch

118 Manufacturer Specific Data o 6Fh

119 Manufacturer Specific Data g 67h

120 Manufacturer Specific Data i 69h

121 Manufacturer Specific Data e 65h

122 Manufacturer Specific Data s 73h

123 Manufacturer Specific Data None FFh

124 Manufacturer Specific Data None FFh

125 Manufacturer Specific Data None FFh

126 Manufacturer Specific Data None FFh

127 Manufacturer Specific Data None FFh

128-255 Open for CPQ Use for Read & Write None FFh

PDC2UV6484A-(75/102/103)T-S

March1998

Revision 1.0

6 Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH

DC CHARACTERISTICS

(At recommended operating conditions unless otherwise noted) Notes 1,2

Parameter Symbol Conditions Value Unit

Min. Max.

Output High Voltage VOH(DC) IOH = -2mA 2.4 - V

Output Low Voltage VOL(DC) IOL = 2mA - 0.4 V

Input Leakage Current (Any Input) ILI 0V ≤ VIN ≤ VCC;

All other pins not under test = 0V -40 40 µA

Output Leakage Current ILO 0V ≤ VIN ≤ VCC

Dout = Disable -5 5 µA

Operating Current

(Average Power Supply Current)

ICC1S

Burst: Length=4,

tRC = min for BL=4,

tCK = min.

One bank- active,

Outputs open,

Addresses changed up to

3-times during tRC (min),

0V ≤ Vin ≤ VCC

800

mA102 800

103 720

ICC1D

Burst: Length=4 (each bank),

tRC = min for BL=4 (each bank),

tCK = min.

All banks active,

Output open,

Addresses changed up to

3-times during tRC (min),

0V ≤ Vin ≤ VCC

1200

mA102 1120

103 1040

Precharge Standby Current

(Power Supply Current)

ICC2P

CKE=VIL,

All banks idle,

tCK=min,

Power down mode,

0V ≤ Vin ≤ VCC

- 3.2

ICC2PS

CKE=VIL,

All banks idle,

CLK=H or L,

Power down mode,

0V ≤ Vin ≤ VCC

- 3.2

Precharge Standby Current

(Power Supply Current)

ICC2N

CKE=VIH,

All banks idle,

tCK=min,

NOP commands only,

Input signals (except to CMD) are

changed one time during 3 clock

cycles,

0V ≤ Vin ≤ VCC

- 216

102 - 160

103 - 160

Precharge Standby Current

(Power Supply Current) ICC2NS

CKE=VIH,

All banks idle,

CLK=H or L,

Input signals are stable,

0V ≤ Vin ≤ VCC

- 120

March 1998

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7Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH

(Continued)

†CL = CAS* Latency

Notes: 1. ICC depends on the output termination or load conditions, clock cycle rate, and signal clocking rate;

The specified values are obtained with the output open and no termination register.

2. An initial pause (DESL or NOP) of 200 µs is required after power-up followed by a minimum of eight Auto-refresh cycles.

Parameter Symbol Test Condition Value Unit

Min. Max.

Active Standby Current (Power Supply Current)

ICC3P

CKE=VIL,

Any bank active,

tCK=min,

0V ≤ Vin ≤ VCC

- 40 mA

ICC3PS

CKE=VIL,

Any bank active,

CLK = H or L,

0V ≤ Vin ≤ VCC

- 24 mA

Active Standby Current (Power Supply Current)

ICC3N

CKE=VIH,

Any bank active,

tCK=min,

NOP commands only,

Input signals (except to CMD) are

changed one time during 3 clock

cycles,

0V ≤ Vin ≤ VCC

- 432 mA

102 - 320 mA

103 - 320 mA

Active Standby Current (Power Supply Current) ICC3NS

CKE=VIH,

Any bank active,

CLK = H or L,

0V ≤ Vin ≤ VCC

- 200 mA

Burst mode Current

(Average Power supply current)

ICC4

tCK=min,

Burst length=4,

Outputs open,

Multiple-banks active,

Gapless data,

0V ≤ Vin ≤ VCC

1200

mA102 960

103 960

Refresh Current #1

(Average Power Supply Current)

ICC5

Auto-refresh;

tCK=min,

tRC=min,

0V ≤ Vin ≤ VCC

800

102 640

103 640

Refresh Current #2 (Average Power Supply Current) ICC6

Self-refresh;

tCK=min,

CKE ≤ 0.2V,

0V ≤ Vin ≤ VCC

- 3.2 mA

Refresh Current #2 (Average Power Supply Current) ICC6A

Asynchronous Self-refresh

(by CLK stop);

CKE ≤ 0.2V,

CLK = VIL,

0V ≤ Vin ≤ VCC

- 3.2 mA

PDC2UV6484A-(75/102/103)T-S

March 1998

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CAPACITANCE

(TA =+25°C, VCC = 3.3V±0.3V)

Notes: 1. Capacitance is measured with Boonton Meter or effective capacitance method.

2. CAS* - VIH to disable Dout.

AC CHARACTERISTICS: MB81F16822B-(75/102/103)

(At recommended operating conditions unless otherwise noted) Notes 2,3,4

Parameter Symbol Max. Unit Notes

Input Capacitance (Address, WE*, CKE, RAS*, CAS*) CI1 45 pF 1

Input Capacitance (DQMBs) CI2 10 pF 1

Input Capacitance (CS0*, CS2*) CI3 25 pF 1

Input Capacitance (CLK0, CLK2) CI4 25 pF 1

Input Capacitance (CLK1, CLK3) CI5 15 pF 1

Input/Output Capacitance (DQ0~DQ63) CI/O 12 pF 1, 2

Parameter Symbol Unit -75 -102 -103 Notes

Min. Max. Min. Max. Min. Max.

Clock Period

CAS

Latency=2 tCK2 ns 11.5 - 10 - 12 -

CAS

Latency=3 tCK3 7.5 - 10 - 10 -

Clock High Time tCH ns 2.5 - 3 - 3 -

Clock Low Time tCL ns 2.5 - 3 - 3 -

Input Setup Time tSI ns 2 - 2 - 2 -

Input Hold Time tHI ns 1 - 1 - 1 -

Access time from Clock (tCK=min)

CAS

Latency=2 tAC2 ns - 7 - 6 - 75,6

CAS

Latency=3 tAC3 - 6 - 6 - 6

Output In Low-Z tLZ ns 0 - 0 - 0 -

Output in High-Z

CAS

Latency=2 tHZ2 ns 3 7 3 6 3 77

CAS

Latency=3 tHZ3 2 6 3 6 3 6

Output Hold Time

CAS

Latency=2 tOH ns 3 - 3 - 3 -

CAS

Latency=3 2 - 3 - 3 -

Time between Auto-Refresh command Interval tREFI µs - 15.6 - 15.6 - 15.6

CKE Low (or CLK Low) Hold Time for

Asynchronous Self-Refresh Entry tASE µs 100 200 100 200 100 200

Transition Time tTns 0.5 2 0.5 2 0.5 2

CKE Set Up time for Power Down Exit tCKSP ns 3 - 3 - 3 -

March1998

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9Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH

BASE VALUES FOR CLOCK COUNT/LATENCY: MB81F16822B-(75/102/103)

CLOCK COUNT FORMULA

(Note 10)

LATENCY-FIXED VALUES: MB81F16822B-(75/102/103)

(The latency values on these parameters are fixed regardless of clock period)

Notes: 1. ICC depends on the output termination or load conditions, clock cycle rate, and signal clocking rate;

The specified values are obtained with the output open and no termination register.

2. An initial pause (DESL or NOP) of 200 µs is required after power-up followed by a minimum of eight Auto-refresh cycles.

3. AC characteristics assume tT = 1 ns and 50 pF of capacitive load.

4. 1.4 V is the reference level for measuring timing of input signals. Transition times are measured between VIH (min) and VIL (max).

5. Assumes tRCD is satisfied.

6. tAC also specifies the access time at burst mode.

7. Specified where output buffer is no longer driven.

8. Actual clock count of tRC (IRC) will be sum of clock count of tRAS (IRAS) and tRP (IRP).

9. Operation within the(tRCD) (min) ensures that access time is determined by (tRCD) (min) + (tAC) (max);

If tRCD is greater than the specified tRCD (min), access time is determined by tAC.

10. All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are

calculated by a simple formula: clock count equals base value divided by clock period (round off a whole number).

Parameter Symbol Unit -75 -102 -103 Notes

Min. Max. Min. Max. Min. Max.

RAS Cycle Time tRC ns 67.5 - 70 - 70 - 8

RAS Precharge Time tRP ns 22.5 - 20 - 20 -

RAS Active Time tRAS ns 45 110000 50 110000 50 110000

RAS to CAS Delay Time tRCD ns 22.5 - 20 - 20 - 9

Write Recovery Time tWR ns 7.5 - 10 - 10 -

Data-in to Precharge Lead Time tDPL ns 7.5 - 10 - 10 -

Data-in to Active/Refresh

command period

CAS

Latency=2 tDAL2 ns 1cyc+tRP - 1cyc+tRP - 1cyc+tRP -

CAS

Latency=3 tDAL3 2cyc+tRP - 2cyc+tRP - 2cyc+tRP -

Mode Register set cycle Time tRSC ns 15 - 20 - 20 -

RAS to RAS Bank Active Delay Time tRRD ns 15 - 20 - 20 -

Parameter Symbol Unit -75 -102 -103 Notes

CKE to Clock Disable ICKE cycle 1 1 1

DQM to Output in High-Z IDQZ cycle 2 2 2

DQM to Input Data Delay IDQD cycle 0 0 0

Last Output to Write Command Delay IOWD cycle 2 2 2

Write Command to Input Data Delay IDWD cycle 0 0 0

Precharge to Output in High-Z Delay CL = 2 IROH2 cycle 2 2 2

CL = 3 IROH3 3 3 3

Burst Stop Command to

Output in High-Z Delay CL = 2 IBSH2 cycle 2 2 2

CL = 3 IBSH3 3 3 3

CAS to CAS Delay (min) ICCD cycle 1 1 1

CAS Bank Delay (min) ICBD cycle 1 1 1

>Base Value

Clock Period

Clock (Round off a whole number)

PDC2UV6484A-(75/102/103)T-S

March 1998

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10 Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH

Output

CL = 50pF

R1 = 50Ω

Fig. 4 - EXAMPLE OF AC TEST LOAD CIRCUIT

1.4V

LVTTL

Note: AC characteristics are measured in this condition. This load circuits are not applicable for VOH and VOL.

March 1998

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PDC2UV6484A-(75/102/103)T-S

11Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH

Physical Dimensions

168-pin (84x2) DIMM

Notes: 1. All dimensions are in inches.

2. Pin 85 is behind pin 1 on the back side.

5.250

5.171

5.014

1.250

0.700

0.118

0.158

∅0.118

2.507 4.550 (Ref.)

5.014

1.700

1.450 2.150

0.450 0.250

0.250

0.350

0.102

(max.)

0.050

+0.004/-0.003

Front View

0.123

0.079

Detail “A”

“A”

1 11 40 41 84

0.088

0.175

0.324

PDC2UV6484A-(75/102/103)T-S

March 1998

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12 Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH

(1) Memory Type

S: SDRAM (PC/66)

G: SGRAM

P: SDRAM-Fast (PC/100)

(2) Module Shape

S: SIMM

D: DIMM

O: Small Outline DIMM

(3) Module Pin Count

A: 72-pin

B: 144-pin

C: 168-pin

D: 200-pin

(4) Word Depth

1 :1M

2 :2M

4 :4M

8 :8M

16: 16M

256:256K

512:512K

(5) Buffer Type

B: Buffered

U: Unbuffered

R: Registered

(6) Operating Voltage & Power Consumption

V: 3.3V & LVTTL & Standard Power

L: 3.3V & LVTTL & Low Power

S: 3.3V & SSTL & Standard Power

(7) Data Width

(ex. 64=x64, 72=x72 etc.)

(8) Device Configuration

4: x4

8: x8

1: x16

3: x32

(9) Refresh

2: 2krf

4: 4krf

8: 8krf

P D C 2U V 64 8 4 A- 102 T -S

(1) (2) (3) (4) (5) (6) (7) (8)(9)(10) (11) (12) (13)

Ordering Information

(10) Module Revision / Applied “Standard” *1

Blank: Rev. 0

A : Rev. 1

B : Rev. 2 (etc.)

*1 When DRAM device or PCB is

revised, the revision is changed

(11)Clock Frequency

SDRAM (PC/66)

100 : 100Mhz

SDRAM-Fast (100Mhz, PC/100)

75 : 133 Mhz (CL=3; tRCD=3; tRP=3)

102 : 100 Mhz (CL=2; tRCD=2; tRP=2)

103 : 100 Mhz (CL=3; tRCD=2; tRP=2)

10 : 100 Mhz (CL=3; tRCD=3; tRP=3)

(12)Package of Component

T : TSOP

(13)Assembly & Test Site

S : Smart Modular Technologies

March 1998

Revision 1.0

PDC2UV6484A-(75/102/103)T-S

13Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH

FUJITSU LIMITED 1998 MP-DS-SDRAMM-20692-3/98

Japan

North and South America

Europe

Asia

FUJITSU MICROELECTRONICS, INC.

3545 North First Street

San Jose, CA 95134-1804, USA.

Tel:+1-408-922-9000

Fax:+1-408-922-9179

Customer Response Center (Mon-Fri: 7am-5pm (PST))

Tel:+1-800-866-8608

Fax:+1-408-922-9179

Internet: http://www.fujitsumicro.com/

FUJITSU MICROELECTRONICS ASIA PTE LIMITED

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Tel: +65-281-0770

Fax:+65-281-0220

Internet: http://www.fsl.com.sg/

FUJITSU MIKROELEKTRONIK GmbH

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Tel:+49-6103-690-0

Fax:+49-6103-690-122

Internet: http://www.fujitsu-ede.com/

FUJITSU LIMITED

Memory Marketing Dept.

4-1-1, Kamikodanaka Nakahara-ku,

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Tel:+81-44-754-3767

Fax:+81-44-754-3343

Internet: http://www.fujitsu.co.jp/

For further information please contact:

FUJITSU LIMITED

Circuit diagrams utilizing Fujitsu products are included

as a means of illustrating typical semiconductor appli-

cations. Complete information sufficient for construc-

tion purposes is not necessarily given.

The information given in this document have been

carefully checked and is believed to be reliable. How-

ever, Fujitsu assumes no responsibility for inaccura-

cies.

The information contained in this document does not

convey any licence under the copyrights, patent rights

or trademarks claimed and owned by Fujitsu.

Fujitsu reserves the right to change products or specifi-

cations without notice.

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The information contained in this document are not

intended for use with equipments which require

extremely high reliability such as aerospace equip-

ments, undersea repeaters, nuclear control systems or

medical equipments for life support.