 
  
EN1
FB1/NC
EN2
FB2/NC
NR
10
9
8
7
6
IN
NC
OUT1
OUT2
GND
1
2
3
4
5
DRC PACKAGE
3mm x 3mm SON
(TOP VIEW)
80
70
60
50
40
30
20
10
0
PSRR (dB)
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
PSRR (RIPPLE REJECTION) vs FREQUENCY
VOUT = 2.8 V
COUT = 2.2 µF
CNR = 0.01 µF
IOUT = 1 mA
IOUT = 250 mA
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049D –MAY 2004–REVISED AUGUST 2010
Dual 250 mA Output, UltraLow Noise, High PSRR,
Low-Dropout Linear Regulator
Check for Samples: TPS71202,TPS71219,TPS71229,TPS71247,TPS71256,TPS71257
1FEATURES DESCRIPTION
• Dual 250 mA High-Performance RF LDOs The TPS712xx family of low-dropout (LDO) voltage
regulators is tailored to noise-sensitive and RF
• Available in Fixed and Adjustable applications. These products feature dual 250 mA
Voltage Options (1.2 V to 5.5 V) LDOs with ultralow noise, high power-supply rejection
• High PSRR: 65 dB at 10 kHz ratio (PSRR), and fast transient and start-up
• UltraLow Noise: 32 mVrms response. Each regulator output is stable with
low-cost 2.2 mF ceramic output capacitors and
• Fast Start-Up Time: 60 msfeatures very low dropout voltages (125 mV typical at
• Stable with 2.2 mF Ceramic Capacitor 250 mA). Each regulator achieves fast start-up times
• Excellent Load/Line Transient Response (approximately 60 ms with a 0.001 mF bypass
capacitor) while consuming very low quiescent
• Very Low Dropout Voltage: 125 mV at 250 mA current (300 mA typical with both outputs enabled).
• Independent Enable Pins When the device is placed in standby mode, the
• Thermal Shutdown and Independent Current supply current is reduced to less than 0.3 mA typical.
Limit Each regulator exhibits approximately 32 mVrms of
output voltage noise with VOUT = 2.8 V and a 0.01 mF
• Available in Thermally-Enhanced SON noise reduction (NR) capacitor. Applications with
Package: 3mm x 3mm x 1mm analog components that are noise-sensitive, such as
portable RF electronics, will benefit from high PSRR,
APPLICATIONS low noise, and fast line and load transient features.
• Cellular and Cordless Phones The TPS712 family is offered in a thin 3mm x 3mm
• Wireless PDA/Handheld Products SON package and is fully specified from -40°C to
• PCMCIA/Wireless LAN Applications +125°C (TJ).
• Digital Camera/Camcorder/Internet Audio
• DSP/FPGA/ASIC/Controllers and Processors
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
SBVS049D –MAY 2004–REVISED AUGUST 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
VOLTAGE (V) PACKAGE- SPECIFIED
LEAD TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT VOUT1 VOUT2 (DESIGNATOR) RANGE (TJ) MARKING NUMBER MEDIA, QUANTITY
TPS71202DRCT Tape and Reel, 250
TPS71202 Adjustable Adjustable SON-10 (DRC) -40°C to +125°C ARQ TPS71202DRCR Tape and Reel, 3000
TPS71219DRCT Tape and Reel, 250
TPS71219 1.8 V Adjustable SON-10 (DRC) -40°C to +125°C ARW TPS71219DRCR Tape and Reel, 3000
TPS71229DRCT Tape and Reel, 250
TPS71229 2.8 V Adjustable SON-10 (DRC) -40°C to +125°C ARU TPS71229DRCR Tape and Reel, 3000
TPS71247DRCT Tape and Reel, 250
TPS71247 1.8 V 2.85 V SON-10 (DRC) -40°C to +125°C ARS TPS71247DRCR Tape and Reel, 3000
TPS71256DRCT Tape and Reel, 250
TPS71256 2.8 V 2.8 V SON-10 (DRC) -40°C to +125°C ARV TPS71256DRCR Tape and Reel, 3000
TPS71257DRCT Tape and Reel, 250
TPS71257 2.85 V 2.85 V SON-10 (DRC) -40°C to +125°C ART TPS71257DRCR Tape and Reel, 3000
(1) For the most current package and ordering information, see the Package Ordering Addendum located at the end of this data sheet.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted(1)
TPS712xx UNIT
VIN range -0.3 to 6.0 V
VEN1, VEN2 range -0.3 to VIN + 0.3 V
VOUT range -0.3 to 6.0 V
Peak output current Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation See Dissipation Ratings Table
Junction temperature range, TJ-40 to +150 °C
Storage temperature range -65 to +150 °C
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION TPS712xx
THERMAL METRIC(1)(2) UNITS
DRC (10 PINS)
qJA Junction-to-ambient thermal resistance 49.6
qJCtop Junction-to-case (top) thermal resistance 70.0
qJB Junction-to-board thermal resistance 17.8 °C/W
yJT Junction-to-top characterization parameter 0.6
yJB Junction-to-board characterization parameter 15.2
qJCbot Junction-to-case (bottom) thermal resistance 5.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
2Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049D –MAY 2004–REVISED AUGUST 2010
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ= -40°C to +125°C), VIN = highest VOUT(nom) + 1.0 V or 2.7 V (whichever is greater),
IOUT = 1 mA, VEN1, 2 = 1.2 V, COUT = 10 mF, CNR = 0.01 mF, and adjustable LDOs are tested at VOUT = 3.0 V, unless otherwise
noted. Typical values are at TJ= +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range(1) 2.7 5.5 V
VFB Internal reference (adjustable LDOs) 1.200 1.225 1.250 V
Output voltage range VFB 5.5 - VDO V
(adjustable LDOs)
VOUT Nominal TJ= +25°C, IOUT = 0 mA -1.5 +1.5
Accuracy(1) %
Over VIN, VOUT + 1.0 V ≤VIN ≤5.5 V, -3 ±1 +3
IOUT, and T 0 mA≤IOUT ≤250 mA
ΔVOUT%/ΔVIN Line regulation(1) VOUT + 1.0 V ≤VIN ≤5.5 V 0.05 %/V
ΔVOUT%/ΔIOU Load regulation 0 mA≤IOUT ≤250 mA 0.8 %/mA
T2.8 V,
Dropout voltage(2)
VDO 2.85 V IOUT1 = IOUT2 = 250 mA 125 230 mV
(VIN = VOUT(nom) - 0.1V) Adjustable
ICL Output current limit VOUT = 0.9 × VOUT(nom) 400 600 800 mA
One LDO IOUT = 1 mA (enabled channel) 190 250
enabled
IGND Ground pin current mA
Both LDOs IOUT1 = IOUT2 = 1 mA to 250 mA 300 600
enabled
ISHDN Shutdown current(3) VEN ≤0.4 V, 0 V ≤VIN ≤5.5 V 0.3 2.0 mA
IFB FB pin current (adjustable LDOs) 0.1 1 mA
No CNR, IOUT = 250 mA 80.0 × VOUT
Output noise voltage,
VnmVrms
BW = 10 Hz - 100 kHz CNR = 0.01 mF, IOUT = 250 mA 11.8 × VOUT
f = 100 Hz, IOUT = 250 mA 65
Power-supply rejection ratio
PSRR dB
(ripple rejection) f = 10 kHz, IOUT = 250 mA 65
tSTR Startup time VOUT = 2.85 V, RL= 30Ω, CNR = 0.001 mF 60 ms
VIH Enable threshold high (EN1, EN2) 1.2 VIN V
VIL Enable threshold low (EN1, EN2) 0 0.4 V
IEN Enable pin current (EN1, EN2) VIN = VEN = 5.5 V -1 1 mA
Shutdown Temp increasing +160
TSD Thermal shutdown temperature °C
Reset Temp decreasing +140
Undervoltage lockout threshold VIN rising 2.25 2.65 V
UVLO Undervoltage lockout hysteresis VIN falling 100 mV
(1) Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater.
(2) VDO is not measured for 1.8 V regulators since minimum VIN = 2.7 V.
(3) For the adjustable version, this applies only after VIN is applied; then VEN transitions from high to low.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
Current
Limit
Thermal
Shutdown
VREF
1.225 V
UVLO
30 µA
EN1
OUT1IN
Current
Limit
OUT2
NR
EN2
250 kΩ
Quickstart 5 pF TPS712xx
Fixed/Fixed
30 µA
VREF
1.225 V
UVLO
EN1
OUT1IN
OUT2
FB1
FB2
NR
EN2
250 kΩ
Quickstart 5 pF TPS712xx
Adj/Adj
Current
Limit
Thermal
Shutdown
Current
Limit
90 kΩ
90 kΩ
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
SBVS049D –MAY 2004–REVISED AUGUST 2010
www.ti.com
FUNCTIONAL BLOCK DIAGRAM — FUNCTIONAL BLOCK DIAGRAM —
FIXED VERSION ADJUSTABLE VERSION
Table 1. TERMINAL FUNCTIONS
TERMINAL DESCRIPTION
NAME DRC
IN 1 Unregulated input supply. A small 0.1 mF capacitor should be connected from IN to GND.
GND 5, Pad Ground
Output of the regulator. A small 2.2 mF ceramic capacitor is required from this pin to ground to assure
OUT1 3 stability.
OUT2 4 Same as OUT1 but for LDO2.
Driving the enable pin (EN) high turns on LDO1. Driving this pin low puts LDO1 into shutdown mode,
EN1 10 reducing operating current. The enable pin should be connected to IN if not used.
EN2 8 Same as EN1 but controls LDO2.
FB1/NC 9 Feedback for CH1 adjustable version; no connection for non-adjustable CH1.
FB2/NC 7 Feedback for CH2 adjustable version; no connection for non-adjustable CH2.
NR 6 Noise reduction pin; connect an external bypass capacitor to reduce LDO output noise.
NC 2 No connection.
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1.0
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1.0
VOUT (%)
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VIN (V)
+25_C
+125_C
−40_C
1.0
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1.0
VOUT (%)
0 50 100 150 200 250
IOUT (mA)
+25_C
−40_C
+125_C
1.0
0.5
0
−0.5
−1.0
−1.5
VOUT (%)
Junction Temperature (_C)
−40 −25 −10 5 20 35 50 65 80 95 110 125
IOUT = 10 mA
IOUT = 250 mA
IOUT = 125 mA
200
180
160
140
120
100
80
60
40
20
0
Dropout Voltage (mV)
2.7 3.1 3.3 3.5 3.9 4.1 4.3 4.5 4.7 4.9
VIN (V)
TJ=−40_C
TJ= +25_C
TJ= +125_C
3.72.9
200
150
100
50
0
Dropout Voltage (mV)
0 50 100 150 200 250
IOUT (mA)
TJ= +25_CTJ=−40_C
TJ= +125_C
250
200
150
100
50
0
Dropout Voltage (mV)
−40 −25 −10 5 20 35 50 65 80 95 110 125
IOUT = 250 mA
Junction Temperature (°C)
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049D –MAY 2004–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 mF, and CNR = 0.01 mF,
unless otherwise noted.
OUTPUT VOLTAGE vs INPUT VOLTAGE OUTPUT VOLTAGE vs OUTPUT CURRENT
Figure 1. Figure 2.
DROPOUT VOLTAGE vs INPUT VOLTAGE
OUTPUT VOLTAGE vs TEMPERATURE (ADJUSTABLE VERSION)
Figure 3. Figure 4.
TPS71256 TPS71256
DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs JUNCTION TEMPERATURE
Figure 5. Figure 6.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
400
375
350
325
300
275
250
225
200
IGND (µA)
2.7 3.2 3.7 4.2 4.7 5.2 5.7
VIN (V)
+25_C−40_C
+125_C
400
375
350
325
300
275
250
225
200
IGND (µA)
0 50 100 150 200 250
IOUT (mA)
+25_C
−40_C
+125_C
400
375
350
325
300
275
250
225
200
IGND (µA)
Junction Temperature (_C)
−40 −25 −10 5 20 35 50 65 80 95 110 125
VEN1 = VEN2 = 1.2V
VIN = 3.8 V
VOUT1
VOUT2
VIN
3.8 V
3.2 V
10 mV/div
10 mV/div
100 µs/div
IOUT = 250 mA
IOUT = 1 mA
COUT1 = COUT2 = 10µF
800
750
700
650
600
550
500
450
400
Current Limit (mA)
Junction Temperature (_C)
−40 −25 −10 5 20 35 50 65 80 95 110 125
VIN = 3.8 V
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
SBVS049D –MAY 2004–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 mF, and CNR = 0.01 mF,
unless otherwise noted.
GROUND PIN CURRENT vs INPUT VOLTAGE GROUND PIN CURRENT vs IOUT
Figure 7. Figure 8.
GROUND PIN CURRENT vs JUNCTION TEMPERATURE
GROUND PIN CURRENT vs JUNCTION TEMPERATURE (DISABLED)
Figure 9. Figure 10.
TPS71256
CURRENT LIMIT vs JUNCTION TEMPERATURE LINE TRANSIENT RESPONSE
Figure 11. Figure 12.
6Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
VOUT2
VOUT1
IOUT1
2 mV/div
100 mV/div
200 mA/div
20 µs/div
250 mA
10 mA
COUT2 = 10 µF
COUT1 = 10 µF
60
50
40
30
20
10
0
Channel Isolation (dB)
0.1 1 10 100 1k
Frequency (Hz)
COUT1 = COUT2 = 10 µF
IOUT1 = 0 mA to 500 mA Sinusoidal Load
IOUT2 = 25 mA
1 V/div
50 ms/div
VIN
VOUT1
VOUT2
IOUT1 = IOUT2 = 250 mA
20 mV/div
1 V/div
VOUT2
VOUT1
VEN1
50 µs/div
CNR = 0.001 µF
CNR = 0.01 µFIOUT1 = IOUT2 = 250 mA
COUT1 = COUT 2 = 10 µF
250
200
150
100
50
0
Total Noise (µVrms)
1 10 100 1k 10k 100k
CNR (pF)
COUT = 2.2 µF
IOUT = 250 mA
COUT = 10 µF
IOUT = 250 mA
COUT = 2.2 µF
IOUT = 0 mA
COUT = 10 µF
IOUT = 0 mA
VOUT = 2.8 V
350
300
250
200
150
100
50
0100 1k 10k 100k
Frequency (Hz)
Spectral Noise Density (nV/√Hz)
IOUT = 250 mA
CNR = 0.1 µF
VOUT = 2.8 V
IOUT = 1 mA
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049D –MAY 2004–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 mF, and CNR = 0.01 mF,
unless otherwise noted. TPS71256
LOAD TRANSIENT RESPONSE TPS71256
AND VOUT2 CROSSTALK CHANNEL-TO-CHANNEL ISOLATION vs FREQUENCY
Figure 13. Figure 14.
TPS71256
TURN-ON/OFF RESPONSE TPS71229
AND VOUT2 CROSSTALK POWER-UP/POWER-DOWN
Figure 15. Figure 16.
NOISE SPECTRAL DENSITY
TOTAL NOISE vs CNR COUT = 2.2 mF
Figure 17. Figure 18.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
350
300
250
200
150
100
50
0100 1k 10k 100k
Frequency (Hz)
Spectral Noise Density (nV/√Hz)
IOUT = 250 mA
CNR = 0.1 µF
VOUT = 2.8 V
IOUT = 10 mA
2.0
1.75
1.5
1.25
1.0
0.75
0.5
0.25
0100 1k 10k 100k
Frequency (Hz)
Spectral Noise Density (µV/√Hz)
0.001 µF
0.047 µF
0.01 µF
0.1 µF
COUT = 10 µF
IOUT = 250 mA
VOUT = 2.8 V
80
70
60
50
40
30
20
10
0
PSRR (dB)
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
VOUT = 2.8 V
COUT = 2.2 µF
CNR = 0.01 µF
IOUT = 1 mA
IOUT = 250 mA
80
70
60
50
40
30
20
10
0
PSRR (dB)
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
VOUT = 2.8 V
COUT = 10 µF
CNR = 0.01 µF
IOUT = 1 mA
IOUT = 250 mA
80
70
60
50
40
30
20
10
0
PSRR (dB)
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VIN −VOUT (V)
f = 1 kHz
f = 10 kHz
f = 100 kHz VOUT = 2.8 V
IOUT = 250 mA
COUT = 10 µF
CNR = 0.01 µF
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
SBVS049D –MAY 2004–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 mF, and CNR = 0.01 mF,
unless otherwise noted.
NOISE SPECTRAL DENSITY
COUT = 10 mF NOISE SPECTRAL DENSITY vs CNR
Figure 19. Figure 20.
PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs FREQUENCY
Figure 21. Figure 22.
PSRR (RIPPLE REJECTION) vs VIN - VOUT
Figure 23.
8Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
TPS712xx
GND
EN2 NR
IN OUT1
EN1 OUT2
VIN VOUT1
VOUT2
0.1 µF
2.2 µF
2.2 µF
0.01 µF
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049D –MAY 2004–REVISED AUGUST 2010
APPLICATION INFORMATION
1.8 V or less is chosen, the minimum recommended
The TPS712xx family of dual low-dropout (LDO) output capacitor is 4.7 mF. Any ceramic capacitor that
regulators has been optimized for use in meets the minimum output capacitor requirements is
noise-sensitive battery-operated equipment. The suitable. Capacitors with higher ESR may be used,
device features extremely low dropout, high PSRR, provided the ESR is less than 1Ω.
ultralow output noise, and low quiescent current
(190 mA typical per channel). When both outputs are OUTPUT NOISE
disabled, the supply currents are reduced to less than
2mA. A typical application circuit is shown in The internal voltage reference is a key source of
Figure 24.noise in an LDO regulator. The TPS712xx has an NR
pin that is connected to the voltage reference through
a 250 kΩinternal resistor. The 250 kΩinternal
resistor, in conjunction with an external ceramic
bypass capacitor connected to the NR pin, creates a
low-pass filter to reduce the voltage reference noise
and, therefore, the noise at the regulator output. To
achieve a fast startup, the 250 kΩinternal resistor is
shorted for 400 ms after the device is enabled.
Because the primary noise source is the internal
voltage reference, the output noise will be greater for
higher output voltage versions. For the case where
no noise reduction capacitor is used, the typical noise
Figure 24. Typical Application Circuit (mVrms) over 10 Hz to 100 kHz is 80 times the output
(fixed-voltage versions) voltage. If a 0.01 mF capacitor is used from the NR
pin to ground, the noise (mVrms) drops to 11.8 times
INPUT AND OUTPUT CAPACITOR the output voltage. For example, the TPS71256
REQUIREMENTS exhibits only 33 mVrms of output voltage noise using
a 0.01 mF ceramic bypass capacitor and a 2.2 mF
A 0.1 mF or larger ceramic input bypass capacitor, ceramic output capacitor.
connected between IN and GND and located close to
the TPS712xx, is required for stability. It improves STARTUP CHARACTERISITCS
transient response, noise rejection, and ripple
rejection. A higher-value input capacitor may be To minimize startup overshoot, the TPS712xx will
necessary if large, fast-rise-time load transients are initially target an output voltage that is approximately
anticipated and the device is located several inches 80% of the final value. To avoid a delayed startup
from the power source. time, noise reduction capacitors of 0.01 mF or less
are recommended. Larger noise reduction capacitors
The TPS712xx requires an output capacitor will cause the output to hold at 80% until the voltage
connected between the outputs and GND to stabilize on the noise reduction capacitor exceeds 80% of the
the internal control loops. The minimum bandgap voltage. The typical startup time with a
recommended output capacitor is 2.2 mF. If an output 0.001 mF noise reduction capacitor is 60 ms. Once
voltage of one of the output voltages is present, the startup time
of the other output will not be affected by the noise
reduction capacitor.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
C1 +(3 105) (R1 )R2)
(R1 R2)(pF)
VOUT +VREF ǒ1)R1
R2Ǔ
R1 +ǒVOUT
VREF *1Ǔ R2
VOUT
1.225 V
1.5 V
2.5 V
3.0 V
3.3 V
4.75 V
R1/R3
Short
7.15 kΩ
31.6 kΩ
43.2 kΩ
49.9 kΩ
86.6 kΩ
R2/R4
Open
30.1 kΩ
30.1 kΩ
30.1 kΩ
30.1 kΩ
30.1 kΩ
Output Voltage Programming Guide
C1/C2
Open
100 pF
22 pF
15 pF
15 pF
15 pF
TPS71202
GND
EN2
FB2NR
IN OUT1
FB1
EN1
OUT2
VIN VOUT1
VOUT2
0.1 µF
2.2 µF
2.2 µF
0.01 µF
C1
R1
C2
R3
R2
R4
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
SBVS049D –MAY 2004–REVISED AUGUST 2010
www.ti.com
PROGRAMMING THE TPS71202
ADJUSTABLE LDO REGULATOR (3)
The output voltage of the TPS71202 dual adjustable blank
regulator is programmed using an external resistor The suggested value of this capacitor for several
divider, as shown in Figure 25. The output voltage is resistor ratios is shown in Figure 25. If this capacitor
calculated using Equation 1:is not used (such as in a unity-gain configuration) or if
an output voltage ≤1.8 V is chosen, then the
(1) minimum recommended output capacitor is 4.7 mF
instead of 2.2 mF.
where VREF = 1.225 V (the internal reference
voltage). DROPOUT VOLTAGE
Resistors R2 and R4 should be chosen for The TPS712xx uses a PMOS pass transistor to
approximately a 40 mA divider current. Lower value achieve extremely low dropout. When (VIN - VOUT) is
resistors can be used for improved noise less than the dropout voltage (VDO), the PMOS pass
performance, but will consume more power. Higher device is in its linear region of operation and the
values should be avoided because leakage current at input-to-output resistance is the RDS, ON of the PMOS
FB increases the output voltage error. The pass element. Dropout voltages at lower currents can
recommended design procedure is to choose R2 = be approximated by calculating the effective RDS, ON30.1 kΩto set the divider current at 40 mA, and then of the pass element and multiplying that resistance by
calculate R1 using Equation 2:the load current. RDS, ON of the pass element can be
obtained by dividing the dropout voltage by the rated
output current. For the TPS71256, the RDS, ON of the
(2) pass element is 84 mΩ. The dropout voltage of the
To improve the stability and noise performance of the TPS712xx will be less for higher output voltage
adjustable version, a small compensation capacitor versions. This is because the PMOS pass element
can be placed between OUT and FB. will have lower on-resistance due to increased gate
drive.
For voltages ≤1.8 V, the value of this capacitor
should be 100 pF. For voltages > 1.8 V, the
approximate value of this capacitor can be calculated
as Equation 3:
Figure 25. TPS71202 Adjustable LDO Regulator Programming
10 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
PD+(VIN *VOUT) IOUT
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049D –MAY 2004–REVISED AUGUST 2010
TRANSIENT RESPONSE enabled. Depending on power dissipation, thermal
resistance, and ambient temperature, the thermal
As with any regulator, increasing the size of the protection circuit may cycle on and off. This limits the
output capacitor will reduce over/undershoot dissipation of the regulator, protecting it from damage
magnitude but increase duration of the transient due to overheating.
response. In the adjustable version, the addition of a
capacitor, CFB, from the output to the feedback pin Any tendency to activate the thermal protection circuit
will also improve stability and transient response. The indicates excessive power dissipation or an
transient response of the TPS712xx is enhanced with inadequate heatsink. For reliable operation, junction
an active pull-down that engages when the output is temperature should be limited to +125°C maximum.
over-voltaged. The active pull-down decreases the To estimate the margin of safety in a complete design
output recovery time when the load is removed. (including heatsink), increase the ambient
Figure 13 in the Typical Characteristics section shows temperature until the thermal protection is triggered;
the output transient response. use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
SHUTDOWN condition of your application. This produces a
Both enable pins are active high and are compatible worst-case junction temperature of +125°C at the
with standard TTL-CMOS levels. The device is only highest expected ambient temperature and
completely disabled when both EN1 and EN2 are worst-case load.
logic low. In this state, the LDO is completely off and The internal protection circuitry of the TPS712xx was
the ground pin current drops to approximately 100 designed to protect against overload conditions. It
nA. With one output disabled, the ground pin current was not intended to replace proper heatsinking.
is slightly greater than half the nominal value. When Continuously running the TPS712xx into thermal
shutdown capability is not required, the enable pins shutdown will degrade device reliability.
should be connected to the input supply.
POWER DISSIPATION
INTERNAL CURRENT LIMIT The ability to remove heat from the die is different for
The TPS712xx internal current limit helps protect the each package type, presenting different
regulator during fault conditions. During current limit, considerations in the PCB layout. The PCB area
the output will source a fixed amount of current that is around the device that is free of other components
largely independent of the output voltage. moves the heat from the device to the ambient air.
The TPS712xx PMOS-pass transistors have a built-in Performance data for a JEDEC high-K board is
back diode that conducts reverse current when the shown in the Dissipation Ratings table. Using heavier
input voltage drops below the output voltage (that is, copper will increase the effectiveness in removing
during power-down). Current is conducted from the heat from the device. The addition of plated
output to the input and is not internally limited. If through-holes to heat-dissipating layers will also
extended reverse voltage operation is anticipated, improve the heat-sink effectiveness.
external limiting may be appropriate. Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
THERMAL PROTECTION product of the output current times the voltage drop
Thermal protection disables both outputs when the across the output pass element (VIN to VOUT):
junction temperature of either channel rises to (4)
approximately +160°C, allowing the device to cool.
When the junction temperature cools to Power dissipation can be minimized by using the
approximately +140°C, the output circuitry is again lowest possible input voltage necessary to assure the
required output voltage.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
SBVS049D –MAY 2004–REVISED AUGUST 2010
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July, 2005) to Revision D Page
• Replaced the Dissipation Ratings table with the Thermal Information table ........................................................................ 3
12 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS71202 TPS71219 TPS71229 TPS71247 TPS71256 TPS71257
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS71202DRCR ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71202DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71202DRCT ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71202DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71219DRCR ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71219DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71219DRCT ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71219DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71229DRCR ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71229DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71229DRCT ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71229DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71247DRCR ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71247DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71247DRCT ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71247DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71256DRCR ACTIVE SON DRC 10 TBD Call TI Call TI
TPS71256DRCRG4 ACTIVE SON DRC 10 TBD Call TI Call TI
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS71256DRCT ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71256DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71257DRCR ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71257DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71257DRCT ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS71257DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 3
OTHER QUALIFIED VERSIONS OF TPS71202 :
•Enhanced Product: TPS71202-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS71202DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS71202DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS71219DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS71219DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS71229DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS71229DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS71247DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS71247DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS71256DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS71257DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS71257DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS71202DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS71202DRCT SON DRC 10 250 210.0 185.0 35.0
TPS71219DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS71219DRCT SON DRC 10 250 210.0 185.0 35.0
TPS71229DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS71229DRCT SON DRC 10 250 210.0 185.0 35.0
TPS71247DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS71247DRCT SON DRC 10 250 210.0 185.0 35.0
TPS71256DRCT SON DRC 10 250 210.0 185.0 35.0
TPS71257DRCR SON DRC 10 3000 367.0 367.0 35.0
TPS71257DRCT SON DRC 10 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 2
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