T-Ma xTM
TO-264
N-Channel MOSFET
Absolute Maximum Ratings
Thermal and Mechanical Characteristics
G
D
S
Single die MOSFET
Unit
A
V
mJ
A
Unit
W
°C/W
°C
oz
g
in·lbf
N·m
Ratings
60
38
210
±30
1580
28
Min Typ Max
1040
0.12
0.11
-55 150
300
0.22
6.2
10
1.1
Parameter
Continuous Drain Current @ TC = 25°C
Continuous Drain Current @ TC = 100°C
Pulsed Drain Current 1
Gate-Source Voltage
Single Pulse Avalanche Energy 2
Avalanche Current, Repetitive or Non-Repetitive
Characteristic
Total Power Dissipation @ TC = 25°C
Junction to Case Thermal Resistance
Case to Sink Thermal Resistance, Flat, Greased Surface
Operating and Storage Junction Temperature Range
Soldering Temperature for 10 Seconds (1.6mm from case)
Package Weight
Mounting Torque ( TO-264 Package), 4-40 or M3 screw
Symbol
ID
IDM
VGS
EAS
IAR
Symbol
PD
RθJC
RθCS
TJ,TSTG
TL
WT
Torque
TYPICAL APPLICATIONS
• PFC and other boost converter
• Buck converter
• Two switch forward (asymmetrical bridge)
• Single switch forward
• Flyback
• Inverters
FEATURES
• Fast switching with low EMI/RFI
• Low RDS(on)
• Ultra low Crss for improved noise immunity
• Low gate charge
• Avalanche energy rated
• RoHS compliant
APT56M60B2
APT56M60L
600V, 60A, 0.11Ω Max
APT56M60B2 APT56M60L
Power MOS 8™ is a high speed, high voltage N-channel switch-mode power MOSFET.
A proprietary planar stripe design yields excellent reliability and manufacturability. Low
switching loss is achieved with low input capacitance and ultra low Crss "Miller" capaci-
tance. The intrinsic gate resistance and capacitance of the poly-silicon gate structure
help control slew rates during switching, resulting in low EMI and reliable paralleling,
even when switching at very high frequency. Reliability in fl yback, boost, forward, and
other circuits is enhanced by the high avalanche energy capability.
Microsemi Website - http://www.microsemi.com
050-8086 Rev F 8-2011
Static Characteristics TJ = 25°C unless otherwise specifi ed
Source-Drain Diode Characteristics
Dynamic Characteristics TJ = 25°C unless otherwise specifi ed
1 Repetitive Rating: Pulse width and case temperature limited by maximum junction temperature.
2 Starting at TJ = 25°C, L = 4.03mH, RG = 25Ω, IAS = 28A.
3 Pulse test: Pulse Width < 380μs, duty cycle < 2%.
4 Co(cr) is defi ned as a fi xed capacitance with the same stored charge as COSS with VDS = 67% of V(BR)DSS.
5 Co(er) is defi ned as a fi xed capacitance with the same stored energy as COSS with VDS = 67% of V(BR)DSS. To calculate Co(er) for any value of
V
DS less than V(BR)DSS, use this equation: Co(er) = -1.10E-7/VDS^2 + 4.60E-8/VDS + 1.72E-10.
6 RG is external gate resistance, not including internal gate resistance or gate driver impedance. (MIC4452)
Microsemi reserves the right to change, without notice, the specifi cations and information contained herein.
G
D
S
Unit
V
V/°C
Ω
V
mV/°C
μA
nA
Unit
A
V
ns
μC
V/ns
Unit
S
pF
nC
ns
Min Typ Max
600
0.57
0.09 0.11
3 4 5
-10
100
500
±100
Min Typ Max
60
210
1.0
745
19
8
Min Typ Max
55
11300
115
1040
550
285
280
60
120
65
75
190
60
Test Conditions
VGS = 0V, ID = 250μA
Reference to 25°C, ID = 250μA
VGS = 10V, ID = 28A
VGS = VDS, ID = 2.5mA
V
DS = 600V TJ = 25°C
V
GS = 0V TJ = 125°C
VGS = ±30V
Test Conditions
MOSFET symbol
showing the
integral reverse p-n
junction diode
(body diode)
ISD = 28A, TJ = 25°C, VGS = 0V
ISD = 28A 3
diSD/dt = 100A/μs, TJ = 25°C
ISD ≤ 28A, di/dt ≤1000A/μs, VDD = 100V,
TJ = 125°C
Test Conditions
VDS = 50V, ID = 28A
VGS = 0V, VDS = 25V
f = 1MHz
VGS = 0V, VDS = 0V to 400V
VGS = 0 to 10V, ID = 28A,
VDS = 300V
Resistive Switching
VDD = 400V, ID = 28A
RG = 2.2Ω 6 , VGG = 15V
Parameter
Drain-Source Breakdown Voltage
Breakdown Voltage Temperature Coeffi cient
Drain-Source On Resistance 3
Gate-Source Threshold Voltage
Threshold Voltage Temperature Coeffi cient
Zero Gate Voltage Drain Current
Gate-Source Leakage Current
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 1
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Peak Recovery dv/dt
Parameter
Forward Transconductance
Input Capacitance
Reverse Transfer Capacitance
Output Capacitance
Effective Output Capacitance, Charge Related
Effective Output Capacitance, Energy Related
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Current Rise Time
Turn-Off Delay Time
Current Fall Time
Symbol
VBR(DSS)
∆VBR(DSS)/∆TJ
RDS(on)
VGS(th)
∆VGS(th)/∆TJ
IDSS
IGSS
Symbol
IS
ISM
VSD
trr
Qrr
dv/dt
Symbol
gfs
Ciss
Crss
Coss
Co(cr)
4
Co(er)
5
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
050-8086 Rev F 8-2011
APT56M60B2_L
VGS= 7&8V
4.5V
TJ = 125°C
TJ = 25°C
TJ = -55°C
VGS = 10V
5.5V
5V
VDS> ID(ON) x RDS(ON) MAX.
250μSEC. PULSE TEST
@ <0.5 % DUTY CYCLE
NORMALIZED TO
VGS = 10V @ 28A
TJ = 125°C
TJ = 25°C
TJ = -55°C
Coss
Ciss
ID = 28A
VDS = 480V
VDS = 120V
VDS = 300V
TJ = 125°C
TJ = 25°C
TJ = -55°C
TJ = 150°C
TJ = 25°C
TJ = 125°C
TJ = 150°C
Crss
6V
V
GS, GATE-TO-SOURCE VOLTAGE (V) gfs, TRANSCONDUCTANCE RDS(ON), DRAIN-TO-SOURCE ON RESISTANCE ID, DRAIN CURRENT (A)
I
SD, REVERSE DRAIN CURRENT (A) C, CAPACITANCE (pF) ID, DRAIN CURRENT (A) ID, DRIAN CURRENT (A)
V
DS(ON), DRAIN-TO-SOURCE VOLTAGE (V) VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 1, Output Characteristics Figure 2, Output Characteristics
TJ, JUNCTION TEMPERATURE (°C) VGS, GATE-TO-SOURCE VOLTAGE (V)
Figure 3, RDS(ON) vs Junction Temperature Figure 4, Transfer Characteristics
ID, DRAIN CURRENT (A) VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 5, Gain vs Drain Current Figure 6, Capacitance vs Drain-to-Source Voltage
Qg, TOTAL GATE CHARGE (nC) VSD, SOURCE-TO-DRAIN VOLTAGE (V)
Figure 7, Gate Charge vs Gate-to-Source Voltage Figure 8, Reverse Drain Current vs Source-to-Drain Voltage
0 5 10 15 20 25 30 0 5 10 15 20 25 30
-55 -25 0 25 50 75 100 125 150 0 1 2 3 4 5 6 7 8
0 10 20 30 40 50 60 70 0 100 200 300 400 500 600
0 50 100 150 200 250 300 350 400 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
250
200
150
100
50
0
3.0
2.5
2.0
1.5
1.0
0.5
0
100
80
60
40
20
0
16
14
12
10
8
6
4
2
0
90
80
70
60
50
40
30
20
10
0
200
180
160
140
120
100
80
60
40
20
0
20,000
10,000
1000
100
10
200
180
160
140
120
100
80
60
40
20
0
APT56M60B2_L
050-8086 Rev F 8-2011
TO-264 (L) Package Outline
T-MAX™ (B2) Package Outline
15.49 (.610)
16.26 (.640)
5.38 (.212)
6.20 (.244)
4.50 (.177) Max.
19.81 (.780)
20.32 (.800)
20.80 (.819)
21.46 (.845)
1.65 (.065)
2.13 (.084)
1.01 (.040)
1.40 (.055)
5.45 (.215) BSC
2.87 (.113)
3.12 (.123)
4.69 (.185)
5.31 (.209)
1.49 (.059)
2.49 (.098)
2.21 (.087)
2.59 (.102)
0.40 (.016)
Drai
n
Source
Gate
These dimensions are equal to the TO-247 without the mounting hole.
Drai n
2-Plcs.
19.51 (.768)
20.50 (.807)
19.81 (.780)
21.39 (.842)
25.48 (1.003)
26.49 (1.043)
2.29 (.090)
2.69 (.106)
0.76 (.030)
1.30 (.051)
3.10 (.122)
3.48 (.137)
4.60 (.181)
5.21 (.205)
1.80 (.071)
2.01 (.079)
2.59 (.102)
3.00 (.118)
0.48 (.019)
0.84 (.033)
Drain
Source
Gate
Drai n
2.29 (.090)
2.69 (.106)
5.79 (.228)
6.20 (.244)
2.79 (.110)
3.18 (.125)
5.45 (.215) BSC
2-Plcs.
Dimensions in Millimeters (Inches)
1.016(.040)
Dimensions in Millimeters (Inches)
e3 100% Sn Plated
1ms
100ms
Rds(on)
0.5
SINGLE PULSE
0.1
0.3
0.7
0.05
D = 0.9
Scaling for Different Case & Junction
Temperatures:
ID = ID(TC = 25°C)*(TJ - TC)/125
Peak T
J
= P
DM
x Z
θJC + TC
Duty Factor D = t1/t2
t2
t1
P
DM
Note:
t1 = Pulse Duration
DC line
100μs
IDM
10ms
13μs
100μs
IDM
100ms
10ms
13μs
Rds(on)
DC line
TJ = 150°C
TC = 25°C
1ms
ID, DRAIN CURRENT (A)
V
DS, DRAIN-TO-SOURCE VOLTAGE (V) VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 9, Forward Safe Operating Area Figure 10, Maximum Forward Safe Operating Area
ZθJC, THERMAL IMPEDANCE (°C/W)
10-5 10-4 10-3 10-2 10-1 1.0
RECTANGULAR PULSE DURATION (seconds)
Figure 11. Maximum Effective Transient Thermal Impedance Junction-to-Case vs Pulse Duration
ID, DRAIN CURRENT (A)
1 10 100 800 1 10 100 800
250
100
10
1
0.1
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
250
100
10
1
0.1
APT56M60B2_L
TJ = 125°C
TC = 75°C
050-8086 Rev F 8-2011
