November 2, 2004 © Cypress MicroSystems, Inc. 2004 — Document No. 38-12028 Rev. *C 1
PSoC™ Mixed-Signal Array Final Dat a Sheet
CY8C24123A,
CY8C24223A, and CY8C24423A
PSoC™ Functional Overview
The PSoC™ family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
The PSoC a rchi tec ture, as illustrat ed on the l ef t , is com pri se d of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system . The PSoC C Y8C2 4x23A f amily ca n have up t o three IO
port s that c onnec t to the gl obal di git al and a nalog i ntercon nect s,
providing access to 4 digital blocks and 6 analog blocks.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture se t . Th e co re in cl ud es a C PU , memo r y, clocks, an d c on fig -
urable GPIO (General Purpose IO).
The M8C CP U core is a po werful proce ssor with speeds up to
24 MHz, providi ng a four MI PS 8-bit Harvard arc hitect ure mic ro-
Features
■Powerful Harvard Architecture Processor
❐M8C Processor Speeds to 24 MHz
❐8x8 Multiply, 32-Bit Accumulate
❐Low Power at High S peed
❐2.4 to 5.25V Operating Voltage
❐Operating Voltages Down to 1.0V Using On-
Chip Switch Mode Pump (SMP)
❐Industrial Temperature Range: -40°C to +85°C
■Advanced Peripherals (PSoC Blocks)
❐6 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
❐4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
❐Complex Peripherals by Combining Blocks
■Precis ion, Programmable C locking
❐Internal ±2.5% 24/48 MHz Oscillator
❐High-Accuracy 24 MHz with Optional 32 kHz
Crystal and PLL
❐Optional External Oscillator, up to 24 MHz
❐Internal Oscillator for Watchdog and Sleep
■Flexible On-Chip Memory
❐4K Bytes Flash Program Storage 50,000
Erase/ Write Cycles
❐256 Bytes SRAM Data Storage
❐In-System Serial Programmi ng (I SSP™)
❐Partial Flash Updates
❐Flexible Protection Modes
❐EEPROM Emulation in Flash
■Programmable Pin Configurations
❐25 mA Sink on all GPIO
❐Pull Up, Pull Down, High Z, Strong, or Open
Drain Dri ve Modes on all GPIO
❐Up to 10 Analog Inputs on GPIO
❐Two 30 mA Analog Outputs on GPIO
❐Configurable Interrupt on all GPIO
■New CY8C24x23A PSoC Device
❐Derived from the CY8C24x23 Device
❐Low Power and Low Voltage (2.4V)
■Additio n al System Resources
❐I2C™ Slave, Master, and Multi-Master to
400 kHz
❐Watchdog and Sleep Timers
❐User-Configurable Low Voltage Detection
❐Integrated Supervisory Circuit
❐On-Chip Precision Voltage Reference
■Complete Development Tools
❐Free Development Software
(PSoC™ Designer)
❐Full-Featured, In-Circuit Emulator and
Programmer
❐Full Speed Emulation
❐Complex Breakpoint Structure
❐128K Bytes Trace Memory
DIGITAL SYSTEM
SRAM
256 Bytes
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
Global Digital Interconnect Global Analog Interconnect
PSoC CORE
CPU Core (M8C)
SROM Flash 4K
Digital
Block
Array
Multiply
Accum.
Sw itch
Mode
Pump
Internal
Voltage
Ref.
Digital
Clocks POR and LVD
System Resets
Decimator
SYSTEM RESOURCES
ANALO G SYST EM
Analog
Ref
A nalog
Input
Muxing
I2C
Port 2 Port 1 Port 0 Analog
Drivers
System Bus
Analog
Block
Array
November 2, 2004 Document No. 38-12028 Rev. *C 2
CY8C24x23A Final Data Sheet PSoC™ Over view
processor. The CPU utilizes an interrupt controller with 11 vec-
tors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watchdog Timers (WDT).
Memory encompasses 4 KB of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash utilizes four protec-
tion levels on blocks of 64 bytes, allowing customized software
IP protection.
The PSoC device incorporates flexible internal clock genera-
tors, including a 24 MHz IMO (internal main oscillator) accurate
to 2.5% over temperature and voltage. The 24 MHz IMO can
also be doubled to 48 MHz for use by the digital system. A low
power 32 kHz ILO (internal low speed oscillator) is provided for
the Sleep timer and WDT. If crystal accuracy is desired, the
ECO (32.768 kHz external crystal oscillator) is available for use
as a Real T ime Clock (R T C) and can optiona lly ge nerat e a crys -
tal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the P SoC device.
PSoC GPIO s pro vid e co nne ct ion to the CPU , di gital an d ana lo g
resour ces of th e devi ce. Each pin’ s dri ve mod e may b e selec ted
from eight options, allowing great flexibility in external interfac-
ing. Every pin al so has the c apa bility to gen erate a syste m inter-
rupt on high level, low level, and change from last read.
The Digital System
The Digital System is composed of 4 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other b lock s to form 8 , 16, 2 4, and 32-bit p eriphe rals, wh ich
are called user module references.
Digital System Block Diagram
Digital peripheral configurations include those listed below.
■PWMs (8 to 32 bit)
■PWMs with Dead band (8 to 24 bit)
■Counters (8 to 32 bit)
■Timers (8 to 32 bit)
■UART 8 bit with selectable parity
■SPI master and slave
■I2C slave and multi-master (1 available as a System
Resource)
■Cyclical R edundancy Checker/Gener ator ( 8 to 32 bit)
■IrDA
■Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operat ion s. Th is configura bil ity free s y our d esi gn s fro m th e con-
straints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the opti-
mum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Charac-
teristics” on page 3.
The Analog System
The Analog Syst em is c om pos ed of 6 co nfi gura bl e blo ck s, eac h
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and
can be cus t o mi zed to support s pec ifi c ap pl ica t io n req uire me nt s .
Some of the more common PSoC analog functions (most avail-
able as user modules) are listed below.
■Analog-to-digital converters (up to 2, with 6- to 14-bit resolu-
tion, selec t ab le as Inc r emental, Delta Sigma, and SAR)
■Filters (2 and 4 pole band-pass, low-pass, and notch)
■Amplifiers (up to 2, with selectable gain to 48x)
■Instrumentation amplifiers (1 with selectable gain to 93x)
■Comparators (up to 2, with 16 selectable thresholds)
■DACs (up to 2, with 6- to 9-bit resolution)
■Multiplying DACs (up to 2, with 6- to 9-bit resolution)
■High current output drivers (two with 30 mA drive as a PSoC
Core resource)
■1.3V reference (as a System Resourc e)
■DTMF Dialer
■Modulators
■Correlators
■Peak Detectors
■Many other topologies possible
DIGITAL SYSTEM
To System Bus
Digital Clocks
From Core
Digital PSoC Block Array
To Analog
System
8
Row Input
Configuration
Row Output
Configuration
88
8Row 0
DBB00 DBB01 DCB02 DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digit al
Interconnect
Port 2
Port 1
Port 0
November 2, 2004 Document No. 38-12028 Rev. *C 3
CY8C24x23A Final Data Sheet PSoC™ Over view
Analog blocks are arranged in a column of three, which
includes one CT (Continuous Time) and two SC (Switched
Capacitor) blocks, as shown in the figure below.
Analog System Block Diagram
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems. Addi-
tional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Brief state-
ments describing the merits of each system resource are pre-
sen ted below.
■Digital clock dividers provide three customizable clock fre-
quencie s for use in applic ations . The clo cks can be route d to
both the di git al and ana log syste ms. Additiona l clock s can be
generated using digital PSoC blocks as clock dividers.
■A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bi t acc umula te, to assi st in both genera l math as well
as digital filters.
■The decimator provides a custom hardware filter for digital
signal proce ss ing a ppl ic ati ons i nc lud ing the creati on of D e lt a
Sigma ADCs.
■The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
■Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, w hile the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■An interna l 1.3V referenc e provides an absolute re ference for
the analog system, including ADCs and DACs.
■An integrated sw it ch mode pum p (S MP) gene rate s norm al
operating volt ages f rom a single 1.2V b attery c ell, provi ding a
low cost boo st con ve r ter.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources
available for specific PSoC device groups. The PSoC device
covered by this data sheet is highlighted below.
ACB00 ACB01
Block Array
Arra y Input Configuration
ACI1[1:0]
ASD20
ACI0[1:0]
P0[6]
P0[4]
P0[2]
P0[0]
P2[2]
P2[0]
P2[6]
P2[4]
RefIn
AGNDIn
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Reference
Generators AGNDIn
RefIn
Bandga
p
RefHi
RefLo
AGND
ASD11
ASC21
ASC10
Interface to
Digital System
M8C Interface (Addr ess Bus, Dat a Bus, Etc. )
Analog Reference
PSoC Device Characteristics
PSoC Device
Group
Digital IO (max)
Digital Rows
Digital Blocks
Analog Inputs
Anal og Outputs
Analog Columns
Analog Blocks
Amount of SRAM
Amount of Flash
CY8C29x66 64 416 12 4 4 12 2K 32K
CY8C27x43 44 2 8 12 4 4 12 256 Bytes 16K
CY8C24794 56 1 4 48 2 2 6 1K 16K
CY8C24x23A 24 1 4 12 226256 Bytes 4K
CY8C24x23 24 1 4 12 226256 By tes 4K
CY8C21x34 28 1 4 28 0 2 4a
a. Limited analog functionality.
512 By tes 8K
CY8C21x23 16 1 4 8 0 2 4a256 Bytes 4K
November 2, 2004 Document No. 38-12028 Rev. *C 4
CY8C24x23A Final Data Sheet PSoC™ Over view
Getting Started
The quick es t p a t h to und ers t an din g the PSoC sili con is by rea d-
ing this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an over-
view of the PSoC integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC™ Mixed-Signal Array Technical Reference Manual.
For up-to- date Or dering, Packag ing, an d Electri cal Specificatio n
information, reference the latest PSoC device data sheets on
the web at http://www.cypress.com/psoc.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
at http://www.onfulfillment.com/cypressstore/ contains develop-
ment kits, C compilers, and all accessories for PSoC develop-
ment. Click on PSoC (Programmable System-on-Chip) to view
a current list of available items.
Tele-Training
Free PSoC "Tele-training" is available for beginners and taught
by a marketing or application engineer over the phone. Five
training classes are available to accelerate the learning curve
including introduction, designing, debugging, advanced design,
advanced analog, as well as application-specific classes cover-
ing topics like PSoC and the LIN bus. For days and times of the
tele-training, see http://www.cypress.com/support/training.cfm.
Consultants
Certified PSoC Consultants offer everything from technical
assist anc e to com plete d PSoC d esign s. To cont ac t or beco me a
PSoC Consultant, go to the following Cypress support web site:
http://www.cypress.com/support/cypros.cfm.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Application Notes
A long list of application notes will assist you in every aspect of
your design effort. To locate the PSoC application notes, go to
http://www.cypress.com/design/results.cfm.
Development Tools
The Cypress MicroSystems PSoC Designer is a Microsoft®
Windows-based, integrated development environment for the
Programmable System-on-Chip (PSoC) devices. The PSoC
Designer IDE and application runs on Windows NT 4.0, Win-
dows 2000, Windows Millennium (Me), or Windows XP. (Refer-
ence the PSoC Designer Functional Flow diagram below.)
PSoC Designer helps the customer to select an operating con-
figuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
PSoC Designer Subsystems
Commands
Results
PSoCTM
Designer
Core
Engine
PSoC
Configuration
Sheet
Manufacturing
Information
File
Device
Database
Importable
Design
Database
Device
Programmer
Graphical Designer
Interface Context
Sensitive
Help
Emulation
Pod In-Circuit
Emulator
Project
Database
Application
Database
User
Modules
Library
PSoCTM
Designer
November 2, 2004 Document No. 38-12028 Rev. *C 5
CY8C24x23A Final Data Sheet PSoC™ Over view
PSoC Designer Software Subsystems
Device Editor
The De vice Editor sub system allo ws the u ser to sele ct diffe rent
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configu-
ration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer can print out a configuration sheet for
a given project configuration for use during application pro-
gram ming in co nju nctio n w ith t he De vice D ata Sh eet. Once t he
framework is generated, the user can add application-specific
code t o fle sh out the framework . It’s als o po ss ib le to ch ange the
selecte d com pon ents and regenerate the framew or k.
Design Browser
The Design Browser allows users to select and import precon-
figu r ed de si g ns into th e u se r’s pro jec t. Use r s ca n eas il y br o wse
a catalog of preconfigured designs to facilitate time-to-design.
Examples pro vid ed in the tool s includ e a 30 0-baud mod em , LIN
Bus master and slave, fan controller, and magnetic card reader.
Applicati on Ed itor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, com-
pile, link, and build.
Assembler. The macro assembler allows the assembly code
to be merged seamlessly with C code. The link libraries auto-
matical ly us e abso lut e addre ssing or ca n be co mpil ed in re lat ive
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available
that supports Cypress MicroSystems’ PSoC family devices.
Even if you have never worked in the C language before, the
product quickly allows you to create complete C programs for
the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the des ig ner in getting st arte d.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is avail-
able for development support. This hardware has the capability
to program sing le dev ic es .
The emulator consists of a base unit that connects to the PC by
way of the parallel or USB port. The base unit is universal and
will operate with all PSoC devices. Emulation pods for each
device family are available separately. The emulation pod takes
the place of the PSoC device in the target board and performs
full speed (24 MHz) operation.
November 2, 2004 Document No. 38-12028 Rev. *C 6
CY8C24x23A Final Data Sheet PSoC™ Over view
Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture
a unique fle xibil ity tha t p ays divi dends in mana ging s pecifi catio n
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block h as several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Itera tiv e de vel opment cy cl es perm it y ou to ada pt th e hard-
ware as well as the software. This substantially lowers the risk
of having to select a different part to meet the final design
requirements.
To speed the development process, the PSoC Designer Inte-
grated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library con-
tains over 50 common peripherals such as ADCs, DACs Tim-
ers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters
that allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Mod-
ule configures one or more digital PSoC blocks, one for each 8
bits of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides high-
level functions to control and respond to hardware events at
run-time. The API also provides optional interrupt service rou-
tines that you can adapt as needed.
The API functions are documented in user module data sheets
that are vie wed directl y in the PSo C D esigner IDE. Thes e data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of e ac h us er m od ule p ara me ter a nd docum ent s the se t-
ting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by inter-
connecting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configura tio n or move on to develo ping co de for the proj ect, yo u
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the devic e to y our s pe cif ic atio n an d pro vi des the high -le vel us er
module API functions.
User Module and Source Code Development Flows
The next step is to write your main program, and any sub-rou-
tines using PSoC Designer’s Application Editor subsystem.
The Application Editor includes a Project Manager that allows
you to open the project source code files (including all gener-
ated code files) from a hierarchal view. The source code editor
provides syntax coloring and advanced edit features for both C
and assembly language. File search capabilities include simple
string searches and recursive “grep-style” patterns. A single
mouse click invokes the Build Manager. It employs a profes-
sional-strength “makefile” system to automatically analyze all
file dependencies and run the compiler and assembler as nec-
essary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in
a console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The last ste p in the devel opm en t proc es s takes pla ce insi de the
PSoC Designer’s Debugger subsystem. The Debugger down-
loads the HEX image to the In-Circuit Emulator (ICE) where it
runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoi nt ev ents tha t inc lu de m oni tori ng ad dres s and da ta bus
values, memory locations and external signals.
Debugger
Interface
to ICE
Application Editor
Device Editor
Project
Manager
Source
Code
Editor
Storage
Inspector
User
Module
Selection
Placement
and
Parameter-
ization
Generate
Application
Build
All
Event &
Breakpoint
Manager
Build
Manager
Source
Code
Generator
November 2, 2004 Document No. 38-12028 Rev. *C 7
CY8C24x23A Final Data Sheet PSoC™ Over view
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this doc-
ument.
Units of Measure
A units of measure table is located in the Electrical Specifica-
tions section. Table 3-1 on page 15 lists all the abbreviations
used to measure the PSoC devices.
Numeric Naming
Hexidecimal numbers are represented with all letters in upper-
case with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah ’ ). H exi d ec im al nu mber s ma y al so be re p res en t ed by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Table of Conte nts
For an in depth discussion and more information on your PSoC
device, obtain the PSoC Mixed-Signal Array Technical Refer-
ence Manual. This document encompasses and is organized
into the following chapters and sections.
1. Pin Information ....... ...... ................. ..... ................. ...... ... 8
1.1 Pinouts ................................................................... 8
1.1.1 8-Pin Part Pinout ........................................ 8
1.1.2 20-Pin Part Pinout ....... ..... ...... ................. ... 9
1.1.3 28-Pin Part Pinout ....... ..... ...... ................. . 10
1.1.4 32-Pin Part Pinout ....... ..... ...... ................. . 11
2. Register Reference ..................................................... 12
2.1 Register Conventions ........................................... 12
2.1.1 Abbreviations Used .................................. 12
2.2 Register Mapping Tables ..................................... 12
3. Electrical Specifications ............................................ 15
3.1 Absolute Ma xi mum Ratings ................... ............. 16
3.2 Operating Temperature ....................................... 16
3.3 DC Electrical Characteristics ................................ 17
3.3.1 DC Chip-Level Specifications ................... 17
3.3.2 DC General Purpose IO Specifications .... 18
3.3.3 DC Operational Amplifier Specifications ... 19
3.3.4 DC Analog Output Buffer Specifications ... 22
3.3.5 DC Switch Mode Pump Specifications ..... 24
3.3.6 DC Analog Reference Specifications ....... 25
3.3.7 DC Analog PSoC Block Specifications ..... 26
3.3.8 DC POR, SMP, and LVD Specifications ... 2 7
3.3.9 DC Programming Specifications ............... 28
3.4 AC Electrical Characteristics ................................ 29
3.4.1 AC Chip-Level Specifications ................... 29
3.4.2 AC General Purpose IO Specifications .... 32
3.4.3 AC Operational Amplifier Specifications ... 33
3.4.4 AC Digital Block Specifications ................. 36
3.4.5 AC Analog Output Buffer Specifications ... 38
3.4.6 AC External Clock Specifications ............. 39
3.4.7 AC Programming Specifications ............... 4 0
3.4.8 AC I2C Specifications ............................... 41
4. Packaging Information ............................................... 42
4.1 Packaging Dimensions ......................................... 42
4.2 Thermal Impedances .......................................... 47
4.3 Capacitance on Crystal Pins ............................... 47
4.4 Solder Reflow Peak Temperature ........................ 48
5. Ordering Information .................................................. 49
5.1 Ordering Code Definitions .................................... 49
6. Sales and Company Information ............................... 50
6.1 Revision History ................................................... 5 0
6.2 Copyrights and Code Protection .......................... 50
Acronym Description
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital-to-analog converter
DC direct current
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only memory
FSR full scale range
GPIO general purpose IO
GUI graphical user interface
HBM human bod y mode l
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
IPOR imprecise power on reset
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PLL phase-locked loop
POR power on reset
PPOR precision power on reset
PSoC™ Programmable System-on-Chip™
PWM pulse width modulator
SC switched capacitor
SLIMO slow IMO
SMP switch mode pump
SRAM static random access memory
November 2, 2004 Document No. 38-12028 Rev. *C 8
1. Pin Information
This chapter describes, lists, and illustrates the CY8C24x23A PSoC device pins and pinout configurations.
1.1 Pinouts
The CY8C24x23A PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every
port pin (labeled with a “P”) is capable of Dig i tal IO. However, Vss, Vdd, SMP, and XRES are not c apable o f Digital IO.
1.1.1 8-Pin Part Pinout
Table 1-1. 8-Pin Part Pinout (PDIP, SOIC)
Pin
No. Type Pin
Name Description CY8C24123A 8-Pin PSoC Device
Digital Analog
1IO IO P0[5] Analog column mux input and column output.
2IO IO P0[3] Analog column mux input and column output.
3IO P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL).
4Power Vss Gr ound connection.
5IO P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA).
6IO IP0[2] Analog column mux input.
7IO IP0[4] Analog column mux input.
8Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
PDIP
SOIC
1
2
3
4
8
7
6
5
Vdd
P0[4], A, I
P0[2], A, I
P1[0], XTALout, I2C SDA
A, IO, P0[5]
A, IO, P0[3]
I2C SCL, XTALin, P1[1]
Vss
November 2, 2004 Document No. 38-12028 Rev. *C 9
CY8C24x23A Final Data Sheet 1. Pin Information
1.1.2 20-Pin Part Pinout
Table 1-2. 20-Pin Part Pinout (PDIP, SSOP, SOIC)
Pin
No. Type Pin
Name Description CY8C24223A 20-Pin PSoC Device
Digital Analog
1IO I P0[7] Anal og colum n mux input.
2IO IO P0[5] Analog col um n mux input and col umn outp ut.
3IO IO P0[3] Analog col um n mux input and col umn outp ut.
4IO I P0[1] Anal og colum n mux input.
5Power SMP Switch Mode Pump (SMP) connection to
external com pon ents requ ired .
6IO P1[7] I2C Serial Clock (SCL).
7IO P1[5] I2C Serial Data (SDA).
8IO P1[3]
9IO P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL).
10 Power Vss Ground conn ect io n.
11 IO P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA).
12 IO P1[2]
13 IO P1[4] Optional External Clock Input (EXTCLK).
14 IO P1[6]
15 Input XRES Active high externa l reset wi th internal pull
down.
16 IO I P0[0] Anal og colum n mux input.
17 IO I P0[2] Anal og colum n mux input.
18 IO I P0[4] Anal og colum n mux input.
19 IO I P0[6] Anal og colum n mux input.
20 Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
PDIP
SSOP
SOIC
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
Vdd
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
November 2, 2004 Document No. 38-12028 Rev. *C 10
CY8C24x23A Final Data Sheet 1. Pin Information
1.1.3 28-Pin Part Pinout
Table 1-3. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
Pin
No. Type Pin
Name Description CY8C24423A 28-Pin PSoC Device
Digital Analog
1IO I P0[7] Analog column mux input.
2IO IO P0[5] Analog column mux input and column output.
3IO IO P0[3] Analog column mux input and column output.
4IO I P0[1] Analog column mux input.
5IO P2[7]
6IO P2[5]
7IO I P2[3] Direct switched capacitor block input.
8IO I P2[1] Direct switched capacitor block input.
9Power SMP Switch Mo de Pu mp (SM P) connection to
external components required.
10 IO P1[7] I2C Serial Clock (SCL).
11 IO P1[5] I2C Serial Data (SDA).
12 IO P1[3]
13 IO P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL).
14 Power Vss Ground connection.
15 IO P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA).
16 IO P1[2]
17 IO P1[4] Optio na l Exter nal C lock Inpu t (EXT CLK ).
18 IO P1[6]
19 Input XRES Active high external reset with internal pull
down.
20 IO I P2[0] Direct switched capacitor block input.
21 IO I P2[2] Direct switched capacitor block input.
22 IO P2[4] External Analog Ground (AGND).
23 IO P2[6] External Voltage Reference (VRef).
24 IO I P0[0] Analog column mux input.
25 IO I P0[2] Analog column mux input.
26 IO I P0[4] Analog column mux input.
27 IO I P0[6] Analog column mux input.
28 Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
Vdd
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
P2[6], External VRef
P2[4], External AGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
PDIP
SSOP
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
November 2, 2004 Document No. 38-12028 Rev. *C 11
CY8C24x23A Final Data Sheet 1. Pin Information
1.1.4 32-Pin Part Pinout
Table 1-4. 32-Pin Part Pinout (MLF*)
Pin
No. Type Pin
Name Description CY8C24423A 32-Pin PSoC Device
Digital Analog
1IO P2[7]
2IO P2[5]
3IO I P2[3] Direct switched capacitor block input.
4IO I P2[1] Direct switched capacitor block input.
5Power Vss Ground connection.
6Power SMP Swit ch Mode Pump (SMP) con nection to
external componen ts required .
7IO P1[7] I2C Serial Clock (SCL).
8IO P1[5] I 2C Se ria l Data (SDA).
9NC No connection. Do not use.
10 IO P1[3]
11 IO P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL).
12 Power Vss Ground connection.
13 IO P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA).
14 IO P1[2]
15 IO P1[4] Optional External Clock Input (EXTCLK).
16 NC No connection. Do not use.
17 IO P1[6]
18 Input XRES Active high external reset with internal pull
down.
19 IO I P2[0] Direct switched capacitor block input.
20 IO I P2[2] Direct switched capacitor block input.
21 IO P2[4] External An alog Ground ( AGND).
22 IO P2[6] Externa l Voltage Reference (VRef).
23 IO I P0[0] Analog column mux input.
24 IO I P0[2] Analog column mux input.
25 NC No connection. Do not use.
26 IO I P0[4] Analog column mux input.
27 IO I P0[6] Analog column mux input.
28 Power Vdd Suppl y voltage.
29 IO I P0[7] Analog column mux input.
30 IO IO P0[5] Analog column mux input and column output.
31 IO IO P0[3] Analog column mux input and column output.
32 IO I P0[1] Analog column mux input.
LEGEND: A = Analog, I = Input, and O = Output.
* The MLF package has a center pad that must be connected to ground (Vss).
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
Vss
SMP
MLF
(Top View)
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
P 0 [1 ], A , I
P 0 [3 ], A , IO
P 0 [5 ], A , IO
P 0 [7 ], A , I
Vdd
P 0 [6 ], A , I
P 0 [4 ], A , I
NC
I2 C S CL , P 1 [7 ]
I2C SDA, P1[5]
P 0 [2 ], A , I
P 0 [0 ], A , I
XRES
P1[6]
NC
P1[3]
I2C SCL, XTALin, P1[1]
Vss
I2C SDA, XTALout, P1[0]
P1[2]
EXT CLK, P1[4]
NC
P2[6], External VRef
P2[4], External AGND
P 2 [2 ], A , I
P 2 [0 ], A , I
November 2, 2004 Document No. 38-12028 Rev. *C 12
2. Register Reference
This chapter lists the registers of the CY8C24x23A PSoC device. For detailed register information, reference the
PSoC™ Mixed-Signal Array Technical Reference Manual.
2.1 Register Conventions
2.1.1 Abbrevi at io ns Use d
The register conventions specific to this section are listed in the
followi ng t ab le.
2.2 Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two ban ks. The XOI bit in the Flag regist er (CPU_F)
determines which bank the user is currently in. When the XOI
bit is set the user is in Bank 1.
Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
Convention Description
R Read register or bit(s)
W Write register or bit(s)
L Log ical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific
November 2, 2004 Document No. 38-12028 Rev. *C 13
CY8C24x23A Final Data Sheet 2. Register Reference
Regi ster Map Bank 0 Ta ble: User Space
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
PRT0DR 00 RW 40 ASC10CR0 80 RW C0
PRT0IE 01 RW 41 ASC10CR1 81 RW C1
PRT0GS 02 RW 42 ASC10CR2 82 RW C2
PRT0DM2 03 RW 43 ASC10CR3 83 RW C3
PRT1DR 04 RW 44 ASD11CR0 84 RW C4
PRT1IE 05 RW 45 ASD11CR1 85 RW C5
PRT1GS 06 RW 46 ASD11CR2 86 RW C6
PRT1DM2 07 RW 47 ASD11CR3 87 RW C7
PRT2DR 08 RW 48 88 C8
PRT2IE 09 RW 49 89 C9
PRT2GS 0A RW 4A 8A CA
PRT2DM2 0B RW 4B 8B CB
0C 4C 8C CC
0D 4D 8D CD
0E 4E 8E CE
0F 4F 8F CF
10 50 ASD20CR0 90 RW D0
11 51 ASD20CR1 91 RW D1
12 52 ASD20CR2 92 RW D2
13 53 ASD20CR3 93 RW D3
14 54 ASC21CR0 94 RW D4
15 55 ASC21CR1 95 RW D5
16 56 ASC21CR2 96 RW I2C_CFG D6 RW
17 57 ASC21CR3 97 RW I2C_SCR D7 #
18 58 98 I2C_DR D8 RW
19 59 99 I2C_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C DC
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F DF
DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW
DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW
DBB00DR2 22 RW 62 A2 INT_VC E2 RC
DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W
DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC
DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC
DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW
DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW
DCB02DR0 28 # 68 A8 MUL_X E8 W
DCB02DR1 29 W 69 A9 MUL_Y E9 W
DCB02DR2 2A RW 6A AA MUL_DH EA R
DCB02CR0 2B # 6B AB MUL_DL EB R
DCB03DR0 2C # 6C AC ACC_DR1 EC RW
DCB03DR1 2D W 6D AD ACC_DR0 ED RW
DCB03DR2 2E RW 6E AE ACC_DR3 EE RW
DCB03CR0 2F # 6F AF ACC_DR2 EF RW
30 ACB00CR3 70 RW RDI0RI B0 RW F0
31 ACB00CR0 71 RW RDI0SYN B1 RW F1
32 ACB00CR1 72 RW RDI0IS B2 RW F2
33 ACB00CR2 73 RW RDI0LT0 B3 RW F3
34 ACB01CR3 74 RW RDI0LT1 B4 RW F4
35 ACB01CR0 75 RW RDI0RO0 B5 RW F5
36 ACB01CR1 76 RW RDI0RO1 B6 RW F6
37 ACB01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD FD
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific.
November 2, 2004 Document No. 38-12028 Rev. *C 14
CY8C24x23A Final Data Sheet 2. Register Reference
Register Map Bank 1 Table: Conf iguration Space
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
PRT0DM0 00 RW 40 ASC10CR0 80 RW C0
PRT0DM1 01 RW 41 ASC10CR1 81 RW C1
PRT0IC0 02 RW 42 ASC10CR2 82 RW C2
PRT0IC1 03 RW 43 ASC10CR3 83 RW C3
PRT1DM0 04 RW 44 ASD11CR0 84 RW C4
PRT1DM1 05 RW 45 ASD11CR1 85 RW C5
PRT1IC0 06 RW 46 ASD11CR2 86 RW C6
PRT1IC1 07 RW 47 ASD11CR3 87 RW C7
PRT2DM0 08 RW 48 88 C8
PRT2DM1 09 RW 49 89 C9
PRT2IC0 0A RW 4A 8A CA
PRT2IC1 0B RW 4B 8B CB
0C 4C 8C CC
0D 4D 8D CD
0E 4E 8E CE
0F 4F 8F CF
10 50 ASD20CR0 90 RW GDI_O_IN D0 RW
11 51 ASD20CR1 91 RW GDI_E_IN D1 RW
12 52 ASD20CR2 92 RW GDI_O_OU D2 RW
13 53 ASD20CR3 93 RW GDI_E_OU D3 RW
14 54 ASC21CR0 94 RW D4
15 55 ASC21CR1 95 RW D5
16 56 ASC21CR2 96 RW D6
17 57 ASC21CR3 97 RW D7
18 58 98 D8
19 59 99 D9
1A 5A 9A DA
1B 5B 9B DB
1C 5C 9C DC
1D 5D 9D OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW
DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW
DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW
23 AMD_CR0 63 RW A3 VLT_CR E3 RW
DBB01FN 24 RW 64 A4 VLT_CMP E4 R
DBB01IN 25 RW 65 A5 E5
DBB01OU 26 RW AMD_CR1 66 RW A6 E6
27 ALT_CR0 67 RW A7 E7
DCB02FN 28 RW 68 A8 IMO_TR E8 W
DCB02IN 29 RW 69 A9 ILO_TR E9 W
DCB02OU 2A RW 6A AA BDG_TR EA RW
2B 6B AB ECO_TR EB W
DCB03FN 2C RW 6C AC EC
DCB03IN 2D RW 6D AD ED
DCB03OU 2E RW 6E AE EE
2F 6F AF EF
30 ACB00CR3 70 RW RDI0RI B0 RW F0
31 ACB00CR0 71 RW RDI0SYN B1 RW F1
32 ACB00CR1 72 RW RDI0IS B2 RW F2
33 ACB00CR2 73 RW RDI0LT0 B3 RW F3
34 ACB01CR3 74 RW RDI0LT1 B4 RW F4
35 ACB01CR0 75 RW RDI0RO0 B5 RW F5
36 ACB01CR1 76 RW RDI0RO1 B6 RW F6
37 ACB01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD FD
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific.
November 2, 2004 Document No. 38-12028 Rev. *C 15
3. Electrical S pecifications
This chapter presents the DC and AC electrical specifications of the CY8C24x23A PSoC device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Specifications for devices running at greater
than 12 MHz are valid for -40oC ≤ TA ≤ 70oC and TJ ≤ 82oC.
Refer to Table 3-20 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
Figure 3-1a. Voltage versus CPU Frequency Figure 3-1b. IMO Frequency Trim Options
The following table lists the units of measure that are used in this chapter.
Table 3-1: Units of Measure
Symbol Unit of Meas ure Symbol Unit of Measure
oCdegree Celsius µWmicrowatts
dB decibels mA milli-ampere
fF femto farad ms milli-second
Hz hertz mV milli-volts
KB 1024 bytes nA nanoampere
Kbit 1024 bits ns nanosecond
kHz kilohertz nV nanovolts
kΩkilohm Ωohm
MHz megahertz pA picoampere
MΩmegaohm pF picofarad
µAmicroampere pp peak-to-peak
µFmicrofarad ppm parts per million
µHmicrohenry ps picosecond
µsmicrosecond sps samples per second
µVmicrovolts σsigma: one standard deviation
µVrms microvolts root-mean-square Vvolts
5.25
4.75
3.00
93 kHz 12 MHz 24 MHz
CP U Frequency
Vdd Voltage
5.25
4.75
3.00
93 kHz 12 MHz 24 MHz
IM O Frequency
Vdd Voltage
3.60
6 MHz
SLIMO Mode = 0
SLIMO
Mode=0
2.40
SLIMO
Mode=1
SLIMO
Mode=1 SLIMO
Mode=1
2.40
3 MHz
Valid
Operating
Region
SLIMO
Mode=1
SLIMO
Mode=0
November 2, 2004 Document No. 38-12028 Rev. *C 16
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.1 Absolute Maximum Ratings
3.2 Operating Temperature
Table 3-2. Absolute Maximum Ratings
Symbol Description Min Typ Max Units Notes
TSTG Storage Temperatur e -55 –+100 oCHigher storage temperatures will reduce data
retention time.
TAAmbient Temperature with Power Applied -40 –+85 oC
Vdd Supply Voltage on Vdd Relative to Vss -0.5 –+6.0 V
VIO DC Input Voltage Vss - 0.5 –Vdd + 0.5 V
VIOZ DC Voltage Applied to T ri-state Vss - 0.5 –Vdd + 0.5 V
IMIO Max imum Current into any Port Pin -25 –+50 mA
ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD.
LU Latch-up Current – – 200 mA
Table 3-3. Operating Temperature
Symbol Description Min Typ Max Units Notes
TAAmbient Temperature -40 –+85 oC
TJJunction Temperature -40 –+100 oCThe temperature rise from ambient to junction is
pa ckage specific. See “Thermal Impedances”
on page 47. The user must limit the power con-
sumption to comply with this requirement.
November 2, 2004 Document No. 38-12028 Rev. *C 17
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.3 DC Electrical Characteristics
3.3.1 DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-4. DC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
Vdd Supply Voltage 2.4 –5.25 VSee DC POR and LVD specifications, Table 3-
18 on page 27.
IDD Supply Current – 5 8 mA Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3
MHz, SYSCLK doubler disabled, VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, ana-
log power = off. SLIMO mode = 0. IMO = 24
MHz.
IDD3 Supply Current –3.3 6.0 mA Conditions are Vdd = 3.3V , TA = 25 oC, CPU = 3
MHz, SYSCLK doubler disabled, VC1 = 1.5
MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, ana-
log power = off. SLIMO mode = 0. IMO = 24
MHz.
IDD27 Supply Current – 2 4 mA Conditions are Vdd = 2.7V, TA = 25 oC, CPU =
0.75 MHz , SYS CLK doubler disabled, VC1 =
0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz,
analog power = off. SLIMO mode = 1. IMO = 6
MHz.
ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, and
WDT.a
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compare d w it h de vic e s t ha t ha ve si m i la r fu n ct i o ns
enabled.
– 3 6.5 µAConditions are with internal slow speed oscilla-
tor, Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC, analog
power = off.
ISBH Sleep (Mode) Current with POR, LVD, Sleep Timer, and
WDT at high temperature.a– 4 25 µAConditions are with internal slow speed oscilla-
tor, Vdd = 3.3V, 55 oC < TA ≤ 85 oC, analog
power = off.
ISBXTL Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and external cryst al.a– 4 7.5 µACondi tions are with properl y lo aded, 1 µW max,
32.768 kHz crystal. Vdd = 3.3V, -40 oC ≤ TA ≤ 55
oC, analog power = off.
ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and external crystal at high temperature.a– 5 26 µAConditions are wit h properly loaded, 1µW max,
32.768 kHz crystal. Vdd = 3.3 V, 55 oC < TA ≤ 85
oC, analog power = off.
VREF Reference Voltage (Bandgap) 1.28 1.30 1.33 VTrimmed for appropriate Vdd. Vdd > 3.0V.
VREF27 Reference Voltage (Bandgap) 1.16 1.30 1.33 VTrimmed for appropriate Vdd. Vdd = 2.4V to
3.0V.
November 2, 2004 Document No. 38-12028 Rev. *C 18
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.3.2 DC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-5. 5V and 3.3V DC GPIO Specifications
Symbol Description Min Typ Max Units Notes
RPU Pull up Resistor 4 5.6 8 kΩ
RPD Pull down Res is tor 4 5.6 8 kΩ
VOH High Output Level Vdd - 1.0 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (maximum
40 mA on even port pins (for example, P0[2],
P1[4]), maximum 40 mA on odd port pins (for
example, P0[3], P1[5])). 80 mA maximum com-
bined IOH budg et.
VOL Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (maximum
100 mA on even port pins (for example, P0[2],
P1[4]), maximum 100 mA on odd port pins (for
example, P0[3], P1[5])). 150 mA maximum com-
bined IOL bud ge t.
VIL Input Low Level – – 0.8 V Vdd = 3.0 to 5.25.
VIH Input High Level 2.1 – V Vdd = 3.0 to 5.25.
VHInput Hysterisis –60 –mV
IIL Input Leakage (Absolute Value) –1–nA Gross tested to 1 µA.
CIN Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent. Temp = 25oC.
COUT Capacitive Load on Pins as Output –3.5 10 pF Package and pin dependent. Temp = 25oC.
Table 3-6. 2.7V DC GPIO Specifications
Symbol Description Min Typ Max Units Notes
RPU Pull up Resistor 4 5.6 8 kΩ
RPD Pull down Res is tor 4 5.6 8 kΩ
VOH High Output Level Vdd - 0.4 – – V IOH = 2 mA (6.25 Typ), Vdd = 2.4 to 3.0V (16
mA maximum, 50 mA Typ combined IOH bud-
get).
VOL Low Output Level – – 0.75 V IOL = 11.25 mA, Vdd = 2.4 to 3.0V (90 mA max-
imum combined IOL budget).
VIL Input Low Level – – 0.75 V Vdd = 2.4 to 3.0.
VIH Input High Level 2.0 – – V Vdd = 2.4 to 3.0.
VHInput Hysteresis – 90 – mV
IIL Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 µA.
CIN Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent. Temp = 25oC.
COUT Capacitive Load on Pins as Output – 3.5 10 pF Package and pin dependent. Temp = 25oC.
November 2, 2004 Document No. 38-12028 Rev. *C 19
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.3. 3 DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guid ance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at
25°C and are for design guidance only.
Table 3-7. 5V DC Operational A mpli fier Sp eci fications
Symbol Description Min Typ Max Units Notes
VOSOA Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–1.6
1.3
1.2
10
8
7.5
mV
mV
mV
–
–
TCVOSOA Average Input Offset Voltage Drift – 7.0 35.0 µV/oC
IEBOA Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 µA.
CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp = 25oC.
VCMOA Common Mode Voltage Range
Common Mode Voltage Range (high power or high
opamp bias)
0.0 – Vdd
Vdd - 0.5 V The common-mode input voltage range is mea-
sured through an analog output buffer. The
specification includes the limitations imposed
by the characteristics of the analog output
buffer.
0.5 –
GOLOA Open Loop Gain
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
60
60
80
– – dB S pecification is applicable at high power. For all
other bias modes (except high power, high
opamp bias), minimum is 60 dB.
VOHIGHOA High Output Voltage Swing (inter nal s ignals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
ISOA Suppl y Curren t (including asso ciated AG ND buffer)
Power = Low, Opamp Bias = High
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
µA
µA
µA
µA
µA
µA
PSRROA Supply Voltage Rejection Ratio 64 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN
≤ Vdd.
November 2, 2004 Document No. 38-12028 Rev. *C 20
CY8C24x23A Final Data Sheet 3. Electrical Specifications
Table 3-8. 3.3V DC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5 Volts Only
–
–1.65
1.32 10
8 mV
mV
TCVOSOA Average Input Offset Voltage Drift – 7.0 35.0 µV/oC
IEBOA Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 µA.
CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp = 25oC.
VCMOA Common Mode Voltage Range 0.2 – Vdd - 0.2 V The common-mode input voltage range is
measured through an analog output buffer.
The specification includes the limitations
imposed by the characteristics of the analog
output buf fer.
GOLOA Open Loop Gain
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
60
60
80
– – dB S pecification is applicable at high power. For
all other bias modes (except high power , high
opamp bias), minimum is 60 dB.
VOHIGHOA High Output Voltage Swing (inter nal s ignals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High is 5V only
Vdd - 0.2
Vdd - 0.2
Vdd - 0.2
–
–
–
–
–
–
V
V
V
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
ISOA Suppl y Curren t (including asso ciated AG ND buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
µA
µA
µA
µA
µA
µA
PSRROA Supply Voltage Rejection Ratio 64 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤
VIN ≤ Vdd..
November 2, 2004 Document No. 38-12028 Rev. *C 21
CY8C24x23A Final Data Sheet 3. Electrical Specifications
Table 3-9. 2.7V DC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5 Volts Only
–
–1.65
1.32 10
8 mV
mV
TCVOSOA Average Input Offset Voltage Drift – 7.0 35.0 µV/oC
IEBOA Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 µA.
CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp = 25oC.
VCMOA Common Mode Voltage Range 0.2 – Vdd - 0.2 V The common-mode input voltage range is
measured through an analog output buffer.
The specification includes the limitations
imposed by the characteristics of the analog
output buf fer.
GOLOA Open Loop Gain
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High
60
60
80
– – dB S pecification is applicable at high power. For
all other bias modes (except high power , high
opamp bias), minimum is 60 dB.
VOHIGHOA High Output Voltage Swing (inter nal s ignals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High is 5V only
Vdd - 0.2
Vdd - 0.2
Vdd - 0.2
–
–
–
–
–
–
V
V
V
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
ISOA Suppl y Curren t (including asso ciated AG ND buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
µA
µA
µA
µA
µA
µA
PSRROA Supply Voltage Rejection Ratio 64 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤
VIN ≤ Vdd.
November 2, 2004 Document No. 38-12028 Rev. *C 22
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.3.4 DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-10. 5V DC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
VOSOB Input Offset Voltage (Absolute Value) – 3 12 mV
TCVOSOB A verage Input Offset Voltage Drift –+6 –µV/°C
VCMOB Common-Mode Input Voltage Range 0.5 –Vdd - 1.0 V
ROUTOB Output Resistance
Power = Low
Power = High –
–1
1–
–
Ω
Ω
VOHIGHOB High Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
Power = High 0.5 x Vdd + 1.1
0.5 x Vdd + 1.1 –
––
–V
V
VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
Power = High –
––
–0.5 x Vdd - 1.3
0.5 x Vdd - 1.3 V
V
ISOB Supply Current Including Bias Cell (No Load)
Power = Low
Power = High –
–1.1
2.6 5.1
8.8 mA
mA
PSRROB Supply Voltage Rejection Ratio 52 64 –dB VOUT > (Vdd - 1.25).
Table 3-11. 3.3V DC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
VOSOB Input Offset Voltage (Absolute Value) – 3 12 mV
TCVOSOB Average Input Offset Voltage Drift –+6 –µV/°C
VCMOB Common-Mode Input Voltage Range 0.5 -Vdd - 1.0 V
ROUTOB Output Resistance
Power = Low
Power = High –
–1
1–
–
Ω
Ω
VOHIGHOB High Output Voltage Swing (Load = 1k ohms to Vdd/2)
Power = Low
Power = High 0.5 x Vdd + 1.0
0.5 x Vdd + 1.0 –
––
–V
V
VOLOWOB Low Output Voltage Swing (Load = 1k ohms to Vdd/2)
Power = Low
Power = High –
––
–0.5 x Vdd - 1.0
0.5 x Vdd - 1.0 V
V
ISOB Supply Current Including Bias Cell (No Load)
Power = Low
Power = High –0.8
2.0 2.0
4.3 mA
mA
PSRROB Supply Voltage Rejection Ratio 52 64 –dB VOUT > (Vdd - 1.25).
November 2, 2004 Document No. 38-12028 Rev. *C 23
CY8C24x23A Final Data Sheet 3. Electrical Specifications
Table 3-12. 2.7V DC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
VOSOB Input Offset Voltage (Absolute Value) – 3 12 mV
TCVOSOB Average Input Offset Voltage Drift –+6 –µV/°C
VCMOB Common-Mode Input Voltage Range 0.5 -Vdd - 1.0 V
ROUTOB Output Resistance
Power = Low
Power = High –
–1
1–
–
Ω
Ω
VOHIGHOB High Output Voltage Swing (Load = 1k ohms to Vdd/2)
Power = Low
Power = High 0.5 x Vdd + 0.2
0.5 x Vdd + 0.2 –
––
–V
V
VOLOWOB Low Output Voltage Swing (Load = 1k ohms to Vdd/2)
Power = Low
Power = High –
––
–0.5 x Vdd - 0.7
0.5 x Vdd - 0.7 V
V
ISOB Supply Current Including Bias Cell (No Load)
Power = Low
Power = High –0.8
2.0 2.0
4.3 mA
mA
PSRROB Supply Voltage Rejection Ratio 52 64 –dB VOUT > (Vdd - 1.25).
November 2, 2004 Document No. 38-12028 Rev. *C 24
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.3.5 DC Switch Mode Pump Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Figure 3-2. Basic Switch Mode Pump Circuit
Table 3-13. DC Switch Mode Pump (SMP) Specifications
Symbol Description Min Typ Max Units Notes
VPUMP 5V 5V Output Voltage from Pum p 4.75 5.0 5.25 V Configuration of footnote.a Average, neglecting
ripple. SMP trip voltage is set to 5.0V.
VPUMP 3V 3.3V Output Voltage from Pump 3.00 3.25 3.60 V Configuration of footnote.a Average, neglecting
ripple. SMP trip voltage is set to 3.25V.
VPUMP 2V 2.6V Output Voltage from Pump 2.45 2.55 2.80 V Configuration of footnote.a Average, neglecting
ripple. SMP trip voltage is set to 2.55V.
IPUMP Availa ble Outp ut C urr en t
VBAT = 1.8V, VPUM P = 5.0V
VBAT = 1.5V, VPUM P = 3.25V
VBAT = 1.3V, VPUM P = 2.55V
5
8
8
–
–
–
–
–
–
mA
mA
mA
Configuration of footno te.a
SMP trip voltage is set to 5.0V.
SMP trip voltage is set to 3.25V.
SMP trip voltage is set to 2.55V.
VBAT5V Input Voltage Range from Battery 1.8 – 5.0 V Confi guration of footnote.a SMP trip voltage is
set to 5.0V.
VBAT3V Input Voltage Range from Battery 1.0 – 3.3 V Confi guration of footnote.a SMP trip voltage is
set to 3.25V.
VBAT2V Input Voltage Range from Battery 1.0 – 3.0 V Confi guration of footnote.a SMP trip voltage is
set to 2.55V.
VBATSTART Minimum Input Voltage from Battery to St art Pump 1.2 – – V Configur ation of footnot e.a 0oC ≤ TA ≤ 100.
1.25V at TA = -40oC.
∆VPUMP_Line Line Regulation (over VBAT range) – 5 – %VO Configuration of footnote.a VO is the “Vdd Value
for PUMP Trip” specified by the VM[2:0] setting
in the DC POR and LVD Specification, Table 3-
18 on page 27.
∆VPUMP_Load Load Regulation – 5 – %VO Configuration of footnote.a VO is the “Vdd V alue
for PUMP Trip” specified by the VM[2:0] setting
in the DC POR and LVD Specification, Table 3-
18 on page 27.
∆VPUMP_Ripple Output Voltage Ripple (depends on capacitor/load) – 100 – mVpp Configuration of foot note.a Load is 5 mA.
a. L1 = 2 µH inductor, C1 = 10 µF capacitor, D1 = Schottky diode. See Figure 3-2.
E3Efficiency 35 50 – % Conf iguration of footnote.a Load is 5 mA. SMP
trip voltage is set to 3.25V.
E2Efficiency
FPUMP Switching Frequency – 1.3 – MHz
DCPUMP Switching Duty Cycle – 50 – %
Battery C1
D1
+PSoCTM
Vdd
Vss
SMP
V
BAT
L1
VPUM
P
November 2, 2004 Document No. 38-12028 Rev. *C 25
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.3.6 DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guid ance only.
The guarant eed spe cific ations are m easure d throug h the Anal og Contin uous Time PSoC block s. The powe r level s for AGND refe r to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 3-14. 5V DC Analog Reference Specifications
Symbol Description Min Typ Max Units
BG Bandg ap Voltage Referenc e 1.28 1.30 1.33 V
–AGND = Vdd/2 Vdd/2 - 0.04 Vdd/2 - 0.01 Vdd/2 + 0.007 V
–AGND = 2 x BandGap 2 x BG - 0.048 2 x BG - 0.030 2 x BG + 0.024 V
–AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.011 P2[4] P2[4] + 0.011 V
–AGND = BandGap BG - 0.009 BG + 0.008 BG + 0.016 V
–AGND = 1.6 x BandGap 1.6 x BG - 0.022 1.6 x BG - 0.010 1.6 x BG + 0.018 V
–AGND Block to Block Variation (AGND = Vdd/2) -0.034 0.000 0.034 V
–RefHi = Vdd/2 + BandGap Vdd/2 + BG - 0.10 Vdd/2 + BG Vdd/2 + BG + 0.10 V
–RefHi = 3 x BandGap 3 x BG - 0.06 3 x BG 3 x BG + 0.06 V
–RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG + P2[6] - 0.113 2 x BG + P2[6] - 0.018 2 x BG + P2[6] + 0.077 V
–RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098 V
–RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] - 0.133 P2[4] + P2[6] - 0.016 P2[4] + P2[6]+ 0.100 V
–RefHi = 3.2 x BandGap 3.2 x BG - 0.112 3.2 x BG 3.2 x BG + 0.076 V
–RefLo = Vdd/2 – Band Gap Vdd/2 - BG - 0.04 Vdd/2 - BG + 0.024 Vdd/2 - BG + 0.04 V
–RefLo = BandGap BG - 0.06 BG BG + 0.06 V
–RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134 V
–RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107 V
–RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] - 0.057 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110 V
Table 3-15. 3.3V DC Anal og Reference Spec ifications
Symbol Description Min Typ Max Units
BG Bandg ap Voltage Referenc e 1.28 1.30 1.33 V
–AGND = Vdd/2 Vdd/2 - 0.03 Vdd/2 - 0.01 Vdd/2 + 0.005 V
–AGND = 2 x BandGap Not Allowed
–AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.008 P2[4] + 0.001 P2[4] + 0.009 V
–AGND = BandGap BG - 0.009 BG + 0.005 BG + 0.015 V
–AGND = 1.6 x BandGap 1.6 x BG - 0.027 1.6 x BG - 0.010 1.6 x BG + 0.018 V
–AGND Column to Column Variation (AGND = Vdd/2) -0.034 0.000 0.034 mV
–RefHi = Vdd/2 + BandGap Not Allowed
–RefHi = 3 x BandGap Not Allowed
–RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed
–RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed
–RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] - 0.075 P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057 V
–RefHi = 3.2 x BandGap Not Allowed
–RefLo = Vdd/2 - BandGap Not Allowed
–RefLo = BandGap Not Allowed
–RefLo = 2 x B andGap - P2[6] (P2[6] = 0.5V) Not Allowed
–RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed
–RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.048 P2[4]- P2[6] + 0.022 P2[4] - P2[6] + 0.092 V
November 2, 2004 Document No. 38-12028 Rev. *C 26
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.3.7 DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-16. 2.7V DC Anal og Reference Spec ifications
Symbol Description Min Typ Max Units
BG Bandg ap Voltage Referenc e 1.16 1.30 1.33 V
–AGND = Vdd/2 Vdd/2 - 0.03 Vdd/2 - 0.01 Vdd/2 + 0.01 V
–AGND = 2 x BandGap Not Allowed
–AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.01 P2[4] P2[4] + 0.01 V
–AGND = BandGap BG - 0.01 BG BG + 0.015 V
–AGND = 1.6 x BandGap Not Allowed
–AGND Column to Column Variation (AGND = Vdd/2) -0.034 0.000 0.034 mV
–RefHi = Vdd/2 + BandGap Not Allowed
–RefHi = 3 x BandGap Not Allowed
–RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed
–RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed
–RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] - 0.08 P2[4] + P2[6] - 0.01 P2[4] + P2[6] + 0.06 V
–RefHi = 3.2 x BandGap Not Allowed
–RefLo = Vdd/2 - BandGap Not Allowed
–RefLo = BandGap Not Allowed
–RefLo = 2 x B andGap - P2[6] (P2[6] = 0.5V) Not Allowed
–RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed
–RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.05 P2[4]- P2[6] + 0.01 P2[4] - P2[6] + 0.09 V
Table 3-17. DC Analog PSoC Block Specifications
Symbol Description Min Typ Max Units Notes
RCT Resistor Unit Value (Continuous Time) –12.2 – kΩ
CSC Capacitor Unit Value (Switch Cap) –80 –fF
November 2, 2004 Document No. 38-12028 Rev. *C 27
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.3.8 DC POR, SMP, and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guid ance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed-Signal Array Technical
Reference Manual for more information on the VLT_CR register.
Table 3-18. DC POR and LVD Specifications
Symbol Description Min Typ Max Units Notes
VPPOR0
VPPOR1
VPPOR2
Vdd Value for PPOR Trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b –2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
Vdd must be greater than or equal to 2.5V
during startup, reset from the XRES pin, or
reset from Watchdog.
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 11 1b
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.450
2.920
3.02
3.13
4.48
4.64
4.73
4.81
2.51a
2.99b
3.09
3.20
4.55
4.75
4.83
4.95
a. Always greater than 50 mV above VPPOR (PORLEV=00) for falling supply.
b. Always greater than 50 mV above V PPOR (PORLEV=01) for falling supply .
V0
V0
V0
V0
V0
V
V
V
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
Vdd Value for SMP Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 11 1b
2.500
2.96
3.03
3.18
4.54
4.62
4.71
4.89
2.550
3.02
3.10
3.250
4.64
4.73
4.82
5.00
2.62c
3.09
3.16
3.32d
4.74
4.83
4.92
5.12
c. Always greater than 50 mV above VLVD0.
d. Always greater than 50 mV above VLVD3.
V
V0
V0
V0
V0
V
V
V
November 2, 2004 Document No. 38-12028 Rev. *C 28
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.3.9 DC Programm i ng Specific at ions
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-19. DC Programming Specifications
Symbol Description Min Typ Max Units Notes
VddIWRITE Supply Voltage for Flash Write Operations 2.70 – – V
IDDP Supply Current During Programming or Verify – 5 25 mA
VILP Input Low Voltage During Programming or Verify – – 0.8 V
VIHP Input High Voltage During Programming or Verify 2.1 – – V
IILP Input Current when Applying Vilp to P1[0] or P1[1] During
Progra mm i ng or Verify – – 0.2 mA Driving internal pull-down resistor.
IIHP Input Current when Applying Vihp to P1[0] or P1[1] During
Progra mm i ng or Verify – – 1.5 mA Driving internal pull-down resistor.
VOLV Output Low Voltage Duri ng Progra m ming or Verify – – Vss + 0.75 V
VOHV Output High Voltage During Programming or Verify Vdd - 1.0 –Vdd V
FlashENPB Flash Endurance (per block) 50,000 – – – E ra se/ write cycles per block.
FlashENT Flash Endu ran c e (total) a
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of
25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than
50,000 cycl es).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to
the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
1,800,000 – – – Erase/ write cycles.
FlashDR Flash Data Retention 10 – – Years
November 2, 2004 Document No. 38-12028 Rev. *C 29
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.4 AC Electrical Characteristics
3.4.1 AC Chip-Level Sp ecifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-20. 5V and 3.3V AC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
FIMO24 Internal Main Oscillator Frequency for 24 MHz 23.4 24 24.6a,b,c MHz Trimmed for 5V or 3.3 V operation using fac-
tory trim values. See Figure 3-1b on
page 15. SLIMO mode = 0.
FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 66.35a,b,c MHz Trimmed for 5V or 3.3 V operation using fac-
tory trim values. See Figure 3-1b on
page 15. SLIMO mode = 1.
FCPU1 CP U Fr equency (5V Nom inal) 0.93 24 24.6a,b
a. 4.75V < Vdd < 5.25V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
MHz
FCPU2 CPU Frequency (3.3V Nominal) 0.93 12 12.3b,c
c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller T rims for Dual V oltage-Range Operation” for information on trimming for operation at 3.3V .
MHz
F48M Digital PSoC Block Frequency 048 49.2a,b,d
d. See the individual user module data sheets for information on maximum frequencies for user modules.
MHz Refer to the AC Digital Block Specifications
below.
F24M Digital PSoC Block Frequency 024 24.6b, d MHz
F32K1 Internal Low Speed Oscillator Frequency 15 32 64 kHz
F32K2 External Crystal Oscillator –32.768 –kHz Accuracy is capacitor and crystal dependent.
50% duty cycle.
FPLL PLL Frequency –23.986 –MHz Is a multiple (x732) of crystal frequency.
Jitter24M2 24 MHz Pe riod Jitter (P LL) – – 600 ps
TPLLSLEW PLL Lock Time 0.5 –10 ms
TPLLSLEWS-
LOW PLL Lock Time for Low Gain Setting 0.5 –50 ms
TOS External Crystal Oscillator Sta rtup to 1% –1700 2620 ms
TOSACC External Crystal Oscillator St artup to 100 ppm –2800 3800 ms The crystal oscillator frequency is within 100
ppm of its final value by the end of the Tosacc
perio d. Corr ect ope ra tion assu me s a prop-
erly loaded 1 uW maximum drive level
32.768 kHz crystal. 3.0V ≤ Vdd ≤ 5.5V, -40 oC
≤ TA ≤ 85 oC.
Jitter32k 32 kHz Period Jitter –100 ns
TXRST External Reset Pulse Width 10 – – µs
DC24M 24 MHz Duty Cycle 40 50 60 %
Step24M 24 MHz Trim Step Size – 50 – kHz
Fout48M 48 MHz Output Frequency 46.8 48.0 49.2a,c MHz Trimmed. Utilizing factory trim values.
Jitter24M1P 24 MHz Period Jitter (IMO) Peak-to-Peak –300 ps
Jitter24M1R 24 MHz Period Jitter (IMO) Root Mean Squared – – 600 ps
FMAX Maximum frequency of signal on row input or row output. – – 12.3 MHz
TRAMP Su ppl y Ram p Time 0 – – µs
November 2, 2004 Document No. 38-12028 Rev. *C 30
CY8C24x23A Final Data Sheet 3. Electrical Specifications
Figure 3-3. PLL Lock Timing Diagram
Figure 3-4. PLL Lock for Low Gain Setting Timing Diagram
Table 3-21. 2.7V AC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
FIMO12 Internal Main Oscillator Frequency for 12 MHz 11.5 12 12.7a,b,c MHz Trimmed for 2.7V operation using factory
trim values. See Figure 3-1b on page 15.
SLIMO mo de = 1.
FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 66.35a,b,c MHz Trimmed for 2.7V operation using factory
trim values. See Figure 3-1b on page 15.
SLIMO mo de = 1.
FCPU1 CPU Frequency (2.7V Nominal)00.930303.15a,b MHz0
FBLK27 Digital PSoC Block Frequency (2.7V Nominal) 012 12.7a,b,c MHz0Refer to the AC Digital Block Specifica-
tions below.
F32K1 Internal Low Speed Oscillator Frequency 832 96 kHz
Jitter32k 32 kHz Period Jitter –150 ns
TXRST External Reset Pulse Width 10 – – µs
DC12M 12 MHz Duty Cycle 40 50 60 %
Jitter12M1P 12 MHz Period Jitter ( IMO) Peak-to-Peak –340 ps
Jitter12M1R 12 MHz Period Jitter (IMO) Root Mean Squared – – 600 ps
FMAX Maximum frequency of signal on row input or row output. – – 12.7 MHz
TRAMP Su ppl y Ramp Time 0 – – µs
a. 2.4V < Vdd < 3.0V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
c. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency for User Modules.
24 MHz
FPLL
PLL
Enable TPLLSLEW
PLL
Gain 0
24 MHz
FPLL
PLL
Enable TPLLSLEWLOW
PLL
Gain 1
November 2, 2004 Document No. 38-12028 Rev. *C 31
CY8C24x23A Final Data Sheet 3. Electrical Specifications
Figure 3-5. External Crystal Oscillator Startup Timing Diagram
Figure 3-6. 24 MHz Period Jitter (IMO) Timing Diagram
Figure 3-7. 32 kHz Period Jitter (ECO) Timing Diagram
32 kHz
F32K2
32K
Select TOS
Jitter24M1
F24M
Jitter32k
F32K2
November 2, 2004 Document No. 38-12028 Rev. *C 32
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.4. 2 A C General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Figure 3-8. GPIO Timing Diagram
Table 3-22. 5V and 3.3V AC GPIO Specifications
Symbol Description Min Typ Max Units Notes
FGPIO GPIO Operat ing Fr equency 0 – 12 MHz Normal Strong Mod e
TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90%
TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90%
TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 10 27 – ns Vdd = 3 to 5.25V, 10% - 90%
TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 10 22 – ns Vdd = 3 to 5.25V, 10% - 90%
Table 3-23. 2.7V AC GPIO Specifications
Symbol Description Min Typ Max Units Notes
FGPIO GPIO Operat ing Fr equency 0 – 3 MHz Normal Strong Mode
TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 6 – 50 ns Vdd = 2.4 to 3.0V, 10% - 90%
TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 6 – 50 ns Vdd = 2.4 to 3.0V, 10% - 90%
TRiseS Rise T ime, Slow Strong Mode, Cload = 50 pF 18 40 120 ns Vdd = 2.4 to 3.0V, 10% - 90%
TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 18 40 120 ns Vdd = 2.4 to 3.0V, 10% - 90%
TFallF
TFallS
TRiseF
TRiseS
90%
10%
GPIO
Pin
Output
Voltage
November 2, 2004 Document No. 38-12028 Rev. *C 33
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.4.3 AC Operational Amplifier Specification s
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guid ance only.
Settlin g time s, sl ew rates , and gain bandw idth are bas ed on the Anal og Conti nu ous Time PSoC block.
Power = High and Opamp Bias = H igh is not supported at 3.3V and 2.7V.
Table 3-24. 5V AC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
TROA Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
3.9
0.72
0.62
µs
µs
µs
TSOA Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
5.9
0.92
0.72
µs
µs
µs
SRROA Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.15
1.7
6.5
–
–
–
–
–
–
V/µs
V/µs
V/µs
SRFOA Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.01
0.5
4.0
–
–
–
–
–
–
V/µs
V/µs
V/µs
BWOA Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.75
3.1
5.4
–
–
–
–
–
–
MHz
MHz
MHz
ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz
Table 3-25. 3.3V AC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
TROA Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High –
––
–3.92
0.72
µs
µs
TSOA Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High –
––
–5.41
0.72
µs
µs
SRROA Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High 0.31
2.7 –
––
–V/µs
V/µs
SRFOA Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High 0.24
1.8 –
––
–V/µs
V/µs
BWOA Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High 0.67
2.8 –
––
–MHz
MHz
ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz
November 2, 2004 Document No. 38-12028 Rev. *C 34
CY8C24x23A Final Data Sheet 3. Electrical Specifications
Table 3-26. 2.7V AC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
TROA Rising Settling Time from 80% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High –
––
–3.92
0.72
µs
µs
TSOA Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High –
––
–5.41
0.72
µs
µs
SRROA Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High 0.31
2.7 –
––
–V/µs
V/µs
SRFOA Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High 0.24
1.8 –
––
–V/µs
V/µs
BWOA Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High 0.67
2.8 –
––
–MHz
MHz
ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz
November 2, 2004 Document No. 38-12028 Rev. *C 35
CY8C24x23A Final Data Sheet 3. Electrical Specifications
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 3-9. Typical AGND Noise with P2[4] Bypass
At low frequ encies, the opam p no is e is proportiona l to 1/f, p ower in de pen dent, and de term ine d by de vic e g eom etry. At high frequen-
cies, increased power level reduces the noise spectrum level.
Figure 3-10. Typical Opamp Noise
100
1000
10000
0.001 0.01 0.1 1 10 100Freq (kHz)
dBV/rtHz
0
0.01
0.1
1.0
10
10
100
1000
10000
0.001 0.01 0.1 1 10 100
Freq (kHz)
nV/rtHz
PH_BH
PH_BL
PM_BL
PL_BL
November 2, 2004 Document No. 38-12028 Rev. *C 36
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.4.4 AC Digital Block Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-27. 5V and 3 .3V AC Digital Block Sp ecifications
Function Description Min Typ Max Units Notes
Timer Ca ptu re Pul se Width 50a
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
– – ns
Maximum Frequency, No Capture – – 49.2 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, With Capture – – 24.6 MHz
Counter Enable Pulse Width 50a– – ns
Maximum Frequency, No Enable Input – – 49.2 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, Enable Input – – 24.6 MHz
Dead Band Kill Pulse Width:
Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode 50a– – ns
Disable Mode 50a– – ns
Maxi mum Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V.
CRCPRS
(PRS Mode) Maximum Input Clock Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V.
CRCPRS
(CRC Mode) Maximum Input Clock Frequency – – 24.6 MHz
SPIM Maximum I nput Clock Frequency – – 8.2 MHz Maxim um data rate at 4.1 MHz due to 2 x ov er
clocking.
SPIS Maximum I nput Clock Frequency – – 4.1 ns
Width of SS_ Negated Between Transmissions 50a– – ns
Transmitter Maxi mum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Receiver Maximum Input Cl ock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz du e to 8 x over
clocking.
November 2, 2004 Document No. 38-12028 Rev. *C 37
CY8C24x23A Final Data Sheet 3. Electrical Specifications
Table 3-28. 2.7V AC Digital Block Specifications
Function Description Min Typ Max Units Notes
All
Functions Maximum Block Clocking Frequency 12.7 MHz 2.4V < Vdd < 3.0V.
Timer Ca ptu re Pul se Width 100a
a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
–0–0ns
Maximum Frequency, With or Without Capture – – 12.7 MHz
Counter Enable Pulse Width 100a–0–0ns
Maximum Frequency, No Enable Input – – 12.7 MHz
Maximum Frequency, Enable Input – – 12.7 MHz
Dead Band Kill Pulse Width:
Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode 100a–0–0ns
Disable Mode0100a–0–0ns
Maxi mum Frequency – – 12.7 MHz
CRCPRS
(PRS Mode) Maximum Input Clock Frequency – – 12.7 MHz
CRCPRS
(CRC Mode) Maximum Input Clock Frequency – – 12.7 MHz
SPIM Maximum I nput Clock Frequency – – 6.35 MHz Maximum data rate at 3.17 MHz due to 2 x over
clocking.
SPIS Maximum I nput Clock Frequency – – 4.23 ns
Width of SS_ Negated Between Transmissions 100a–0–0ns
Transmitter Maxi mum Input Clock Frequency – – 12.7 MHz Maximum data rate at 1.59 MHz due to 8 x over
clocking.
Receiver Maximum Input Cl ock Frequency – – 12.7 MHz Maximum data rate at 1.59 MHz du e to 8 x over
clocking.
November 2, 2004 Document No. 38-12028 Rev. *C 38
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.4.5 AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-29. 5V AC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
TROB Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High –
––
–2.5
2.5
µs
µs
TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High –
––
–2.2
2.2
µs
µs
SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Power = Low
Power = High 0.65
0.65 –
––
–V/µs
V/µs
SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Power = Low
Power = High 0.65
0.65 –
––
–V/µs
V/µs
BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Power = Low
Power = High
0.8
0.8 –
––
–MHz
MHz
BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Power = Low
Power = High
300
300 –
––
–kHz
kHz
Table 3-30. 3.3V AC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
TROB Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High –
––
–3.8
3.8
µs
µs
TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High –
––
–2.6
2.6
µs
µs
SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Power = Low
Power = High 0.5
0.5 –
––
–V/µs
V/µs
SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Power = Low
Power = High 0.5
0.5 –
––
–V/µs
V/µs
BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Power = Low
Power = High
0.7
0.7 –
––
–MHz
MHz
BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Power = Low
Power = High
200
200 –
––
–kHz
kHz
November 2, 2004 Document No. 38-12028 Rev. *C 39
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.4.6 AC External Clock Specification s
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-31. 2.7V AC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
TROB Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High –
––
–4
4
µs
µs
TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High –
––
–3
3
µs
µs
SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Power = Low
Power = High 0.4
0.4 –
––
–V/µs
V/µs
SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Power = Low
Power = High 0.4
0.4 –
––
–V/µs
V/µs
BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Power = Low
Power = High
0.6
0.6 –
––
–MHz
MHz
BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Power = Low
Power = High
180
180 –
––
–kHz
kHz
Table 3-32. 5V AC External Clock Specific ations
Symbol Description Min Typ Max Units Notes
FOSCEXT Frequency 0.093 –24.6MHz
– High Period 20.6 –5300 ns
– Low Period 20.6 ––ns
– Power Up IMO to Switch 150 – – µs
Table 3-33. 3.3V AC External Clock Speci ficat ions
Symbol Description Min Typ Max Units Notes
FOSCEXT Frequency with CPU Clock divide by 1a
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
0.093 –12.3MHz
FOSCEXT Frequency with CPU Clock divide by 2 or greaterb
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty per-
cent duty cycle requirement is met.
0.186 –24.6MHz
– High Period with CPU Clock divide by 1 41.7 –5300 ns
– Low Period with CPU Clock divide by 1 41.7 ––ns
– Power Up IMO to Switch 150 – – µs
November 2, 2004 Document No. 38-12028 Rev. *C 40
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.4. 7 A C Programming Sp ecific ations
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 3-34. 2.7V AC External Clock Speci ficat ions
Symbol Description Min Typ Max Units Notes
FOSCEXT Frequency with CPU Clock divide by 1a0.093 –12.3MHz
FOSCEXT Frequency with CPU Clock divide by 2 or greaterb0.186 –12.3MHz
– High Period with CPU Clock divide by 1 41.7 –5300 ns
– Low Period with CPU Clock divide by 1 41.7 ––ns
– Power Up IMO to Switch 150 – – µs
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty per-
cent duty cycle requirement is met.
Table 3-35. AC Programming Specifications
Symbol Description Min Typ Max Units Notes
TRSCLK Rise Time of SCLK 1 – 20 ns
TFSCLK Fall Time of SCLK 1 – 20 ns
TSSCLK Data Set up Time to Falling Edge of SCLK 40 – – ns
THSCLK Data Hold Time from Falling Edge of SCLK 40 – – ns
FSCLK Frequency of SCLK 0 – 8 MHz
TERASEB Flash Erase Time (Block) –20 –ms
TWRITE Flash Block Write Time –20 –ms
TDSCLK Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6
TDSCLK3 Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6
TDSCLK2 Data Out Delay from Falling Edge of SCLK – – 70 ns 2.4 ≤ Vdd ≤ 3.0
November 2, 2004 Document No. 38-12028 Rev. *C 41
CY8C24x23A Final Data Sheet 3. Electrical Specifications
3.4.8 AC I2C Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3 .0V to 3.6V a nd -40°C ≤ T A ≤ 85 °C, or 2.4V to 3.0V and -40°C ≤ T A ≤ 85 °C, respec tivel y. Ty pica l pa ram eters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Figure 3-11. Definition for Timing for Fast/Standard Mode on the I2C Bus
Table 3-36. AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V
Symbol Description Standard Mode Fast Mode Units NotesMin Max Min Max
FSCLI2C SCL Clock Frequency 0 100 0 400 kHz
THDSTAI2C Hold T ime (repeated) ST AR T Condition. After this period, the
first clock pulse is generated. 4.0 –0.6–µs
TLOWI2C LOW Period of the SCL Clock 4.7 –1.3–µs
THIGHI2C HIGH Period of the SCL Clock 4.0 –0.6–µs
TSUSTAI2C Set-up Time for a Repeated START Condition 4.7 –0.6–µs
THDDATI2C Data Hold Time 0 –0–µs
TSUDATI2C Data Set-up Time 250 –100a
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
–ns
TSUSTOI2C Set-up Time for STOP Condition 4.0 –0.6–µs
TBUFI2C Bus Free Time Between a STOP and START Condition 4.7 –1.3–µs
TSPI2C Pulse Width of spikes are suppressed by the input filter. –– 0 50 ns
Table 3-37. AC Characteristics of the I2C SDA and SCL Pins for Vdd < 3.0V (Fas t Mode Not Supported)
Symbol Description Standard Mode Fast Mode Units NotesMin Max Min Max
FSCLI2C SCL Clock Frequency 0 100 ––kHz
THDSTAI2C Hold T ime (repeated) ST AR T Condition. After this period, the
first clock pulse is generated. 4.0 – – – µs
TLOWI2C LOW Period of the SCL Clock 4.7 – – – µs
THIGHI2C HIGH Period of the SCL Clock 4.0 – – – µs
TSUSTAI2C Set-up Time for a Repeated START Condition 4.7 – – – µs
THDDATI2C Data Hold Time 0 – – – µs
TSUDATI2C Data Set-up Time 250 – – –ns
TSUSTOI2C Set-up Time for STOP Condition 4.0 – – – µs
TBUFI2C Bus Free Time Between a STOP and START Condition 4.7 – – – µs
TSPI2C Pulse Width of spikes are suppressed by the input filter. ––––ns
SDA
SCL
SSr SP
TBUFI2C
TSPI2C
THDSTAI2C
TSUSTOI2C
TSUSTAI2C
TLOWI2C
THIGHI2C
THDDATI2C
THDSTAI2C
TSUDATI2C
November 2, 2004 Document No. 38-12028 Rev. *C 42
4. Packaging Information
This chapt er ill us trates the p ack ag ing spe ci fic ati ons for the C Y8C 24 x2 3A PSoC dev ic e, alo ng wit h the the r ma l im ped anc es for eac h
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dime ns ion s at
http://www.cypress.com/support/link.cfm?mr=poddim.
4.1 Packaging Dimensions
Figure 4-1. 8-Lead (300-Mil) PDIP
51-85075 - *A
November 2, 2004 Document No. 38-12028 Rev. *C 43
CY8C24x23A Final Data Sheet 4. Packaging Information
Figure 4-2. 8-Lead (150-Mil) SOIC
Figure 4-3. 20-Lead (300-Mil) Molded DIP
51-85066 *B
51-85066 - *C
51-85011-A
20-Lead(300-Mil)MoldedDIPP5
51-85011 - *A
November 2, 2004 Document No. 38-12028 Rev. *C 44
CY8C24x23A Final Data Sheet 4. Packaging Information
Figure 4-4. 20-Lead (210-Mil) SSOP
Figure 4-5. 20-Lead (300-Mil) Molded SOIC
51-85077 - *C
51-85024 - *B
November 2, 2004 Document No. 38-12028 Rev. *C 45
CY8C24x23A Final Data Sheet 4. Packaging Information
Figure 4-6. 28-Lead (300-Mil) Molded DIP
Figure 4-7. 28-Lead (210-Mil) SSOP
51-85014 - *D
51-85079 - *C
November 2, 2004 Document No. 38-12028 Rev. *C 46
CY8C24x23A Final Data Sheet 4. Packaging Information
Figure 4-8. 28-Lead (300-Mil) Molded SOIC
Figure 4-9. 32-Lead (5x5 mm) MLF
51-85026 - *C
51-85188 - **
32
X = 138 MIL
Y = 138 MIL
November 2, 2004 Document No. 38-12028 Rev. *C 47
CY8C24x23A Final Data Sheet 4. Packaging Information
4.2 Ther m al Impe dances
4.3 Capacitance on Crystal Pins
Table 4-1. Thermal Impedances per Package
Package Typical θJA *
8 PDIP 123 oC/W
8 SOIC 185 oC/W
20 PDIP 109 oC/W
20 SSOP 117 oC/W
20 SOIC 81 oC/W
28 PDIP 69 oC/W
28 SSOP 101 oC/W
28 SOIC 74 oC/W
32 MLF 22 oC/W
* TJ = TA + POWER x θJA
Table 4-2: Typical Package Capacitance on Crystal Pins
Package Package Capacitance
8 PDIP 2.8 pF
8 SOIC 2.0 pF
20 PDIP 3.0 pF
20 SSOP 2.6 pF
20 SOIC 2.5 pF
28 PDIP 3.5 pF
28 SSOP 2.8 pF
28 SOIC 2.7 pF
32 MLF 2.0 pF
November 2, 2004 Document No. 38-12028 Rev. *C 48
CY8C24x23A Final Data Sheet 4. Packaging Information
4.4 S older Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 4-3. Solder Reflow Peak Te mperature
Package Minimum Peak Temperature* Maximum Peak Temperature
8 PDIP 220oC260oC
8 SOIC 220oC260oC
20 PDIP 220oC260oC
20 SSOP 240oC260oC
20 SOIC 220oC260oC
28 PDIP 220oC260oC
28 SSOP 240oC260oC
28 SOIC 220oC260oC
32 MLF 220oC260oC
*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5oC
with Sn-Pb or 245+/-5oC with Sn-Ag-Cu p aste. Refer to the solder manufacturer specifications.
November 2, 2004 Document No. 38-12028 Rev. *C 49
5. Ordering Information
The following table lists the CY8C24x23A PSoC device’s key package features and ordering codes.
5.1 Ordering Code Definitions
Table 5-1. CY8C24x23A PSoC Device Key Features and Ordering Information
Package
Ordering
Code
Flash
(Bytes)
SRAM
(Bytes)
Switch Mo de
Pump
Temperatu re
Range
Digital Blocks
Analog Blocks
Dig ital IO Pins
Ana l og Inputs
Analog Outputs
XRES Pin
8 Pin (300 Mil) DIP CY8C24123A-24PXI 4K 256 No -40C to +85C 4 6 6 4 2 No
8 Pin (150 Mil) SOIC CY8C24123A-24SXI 4K 256 Yes -40C to +85C 4 6 6 4 2 No
8 Pin (150 Mil) SOIC
(Tape and Reel) CY8C24123A-24SXIT 4K 256 Yes -40C to +85C 4 6 6 4 2 No
20 Pin (300 Mil) DIP CY8C24223A-24PXI 4K 256 Yes -40C to +85C 4 6 16 8 2 Yes
20 Pin (210 Mil) SSOP CY8C24223A-24PVXI 4K 256 Yes -40C to +85C 4 6 16 8 2 Yes
20 Pin (210 Mil) SSOP
(Tape and Reel) CY8C24223A-24PVXIT 4K 256 Yes -40C to +85C 4 6 16 8 2 Yes
20 Pin (300 Mil) SOIC CY8C24223A-24SXI 4K 256 Yes -40C to +85C 4 6 16 8 2 Yes
20 Pin (300 Mil) SOIC
(Tape and Reel) CY8C24223A-24SXIT 4K 256 Yes -40C to +85C 4 6 16 8 2 Yes
28 Pin (300 Mil) DIP CY8C24423A-24PXI 4K 256 Yes -40C to +85C 4 6 24 10 2Yes
28 Pin (210 Mil) SSOP CY8C24423A-24PVXI 4K 256 Yes -40C to +85C 4 6 24 10 2Yes
28 Pin (210 Mil) SSOP
(Tape and Reel) CY8C24423A-24PVXIT 4K 256 Yes -40C to +85C 4 6 24 10 2Yes
28 Pin (300 Mil) SOIC CY8C24423A-24SXI 4K 256 Yes -40C to +85C 4 6 24 10 2Yes
28 Pin (300 Mil) SOIC
(Tape and Reel) CY8C24423A-24SXIT 4K 256 Yes -40C to +85C 4 6 24 10 2Yes
32 Pin (5x5 mm) MLF CY8C24423A-24LFXI 4K 256 Yes -40C to +85C 4 6 24 10 2Yes
CY 8 C 24 xxx-SPxx
Package Type: Thermal Rating:
PX = PDI P Pb-Free C = Comm ercial
SX = SOIC Pb-Free I = Industrial
PVX = SSOP Pb-Free E = Extended
LFX = MLF Pb-Free
AX = TQFP Pb-Free
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress MicroSystems
Company ID: CY = Cypress
November 2, 2004 © Cypress MicroSystems, Inc. 2004 — Document No. 38-12028 Rev. *C 50
6. Sales and Company Information
To obt ain info rmatio n about Cypre ss Micro System s or PSoC sales an d techn ical s upport, referenc e the fol lowing i nfor mation or go to
the section titled “Getting Started” on page 4 in this document.
Cypress MicroSystems
6.1 Revision History
6.2 Copyrights and Code Protection
Copyrights
© Cypre ss MicroSystem s, Inc. 2004. A ll rights reserved . PSoC™, PS oC Designer™ , and Program mable System -on-Chip™ are trademarks o f Cypress MicroSys tems,
Inc. All other trademarks or registered trademarks referenced herein are property of the respective corporations.
The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry
embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSys tem s do es n o t a u t hori z e its pr od u c t s
for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of
Cypress MicroSystems products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress
MicroSystems against all charges. Cypress MicroSystems products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety
app lications, unless pursuant to an express writ ten agreement with Cypress MicroSystems.
Flash Code Protection
Note the following details of the Flash code protection features on Cypress MicroSystems devices.
Cypress MicroSystems products meet the specifications contained in their particular Cypress MicroSystems Data Sheets. Cypress MicroSystems believes that its family of
products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unkno wn to Cy p ress MicroSystems,
that can br each the code protection fe atures. An y of these methods , to our kno wledge, woul d be dishone st and possibly i llegal. Neith er Cypress MicroSyste ms nor any
other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
Cypress MicroSystems is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress Micro-
Systems are committed to continuously improving the code protection features of our products.
2700 162nd Street SW
Building D
Lynnwood, WA 98037
Phone: 800.669.0557
Facsimile: 425.787.4641
Web Sites: Company Information – http://www.cypress.com
Sales – http://www.cypress.com/aboutus/sales_locations.cfm
Technical Support – http://www.cypress.com/support/login.cfm
Table 6-1. CY8C24x23A Data Sheet Revision History
Document Title: CY8C24123A, CY8C24223A, and CY8C24423A PSoC Mixed-Signal Array Final Data Sheet
Document Number: 38-12028
Revision ECN # Issue Date Origin of Change Description of Change
** 236409 S ee E CN SFV New silicon and new document – Preliminary Data Sheet.
*A 247589 S ee E CN SFV Changed the title to read “Final” data sheet. Updated Electrical Specifications chapter.
*B 261711 See ECN HMT Input all SFV memo changes. Updated Electrical Specifications chapter.
*C 279731 S ee E CN HMT Update Electrical Specifications chapter, including 2.7 VIL DC GPIO spec. Add Solder Reflow Peak
Temperature table. Clean up pinouts and fine tune wordi ng and format throughout.
Distribution: External/Public Posting: None
