HY57V56420C(L)T
4 Banks x 16M x 4Bit Synchronous DRAM
This document is a gene ral product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.4 / July 2003 1
DESCRIPTION
The HY57V56420C is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large
memory density and high bandwidth. HY57V56420C is organized as 4banks of 16,777,216x4.
HY57V56420C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage
levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or
write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
• Single 3. 3±0.3V power supply
• All device pins are compat i b l e w it h LVTT L interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
• All inputs and outputs referenced to positive edge of system
clock
• Data mask function by DQM
• Internal four banks opera ti on
• Auto refresh and self refresh
• 8192 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No. Clock Frequency Power Organization Interface Package
HY57V56420CT-6 166MHz
Normal
4Banks x 16Mbits x 4 LVTTL 400mil 54pin TSOP II
HY57V56420CT-K 133MHz
HY57V56420CT-H 133MHz
HY57V56420CT-8 125MHz
HY57V56420CT-P 100MHz
HY57V56420CT-S 100MHz
HY57V56420CLT-6 166MHz
Low power
HY57V56420CLT-K 133MHz
HY57V56420CLT-H 133MHz
HY57V56420CLT-8 125MHz
HY57V56420CLT-P 100MHz
HY57V56420CLT-S 100MHz
HY57V56420C(L)T
Rev. 0.4 / July 2003 2
PIN CONFIGURATION
PIN DESCRIPTION
PIN PIN NAME DESCRIPTION
CLK Clock The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS Chip Select Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1 Bank Address Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A12 Address Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA9, CA11
Auto-precharge flag : A10
RAS, CAS, WE Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
DQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ3 Data Input/Output Multiplexed data input / output pin
VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers
NC No Connection No connection
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
54pin TSOP II
400 mil x 875mil
0.8 mm pin pitch
HY57V56420C(L)T
Rev. 0.4 / July 2003 3
FUNCTIONAL BLOCK DIAGRAM
16Mbit x 4banks x 4 I/O Synchronous DRAM
State Machine
A0
A1
A12
BA0
BA1
Address buffers
Address
Registers
Mode Registers
Row
Pre
Decoders
Column
Pre
Decoders
Column Add
Counter
Row active
Column
Active
Burst
Counter
Data Out Control
CAS Latency
X decoders
Internal Row
counter
DQ0
DQ1
DQ2
DQ3
refresh
Self refresh logic
& timer
Pipe Line Control
I/O Buffer & Logic
Bank Select
Sense AMP & I/O Gate
CLK
CKE
CS
RAS
CAS
WE
DQM
X decoders
X decoders
Memory
Cell
Array
Y decoders
X decoders
16Mx4 Bank 1
16Mx4 Bank 0
16Mx4 Bank 2
16Mx4 Bank 3
HY57V56420C(L)T
Rev. 0.4 / July 2003 4
ABSOLUTE MAXIMUM RATINGS
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70°C)
Note :
1.All voltages are referenced to VSS = 0V
2.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration
3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration
AC OPERATING CONDITION (TA=0 to 70°C, VDD=3.3 ± 0.3V, VSS=0V)
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
Parameter Symbol Rating Unit
Ambient Temperature TA0 ~ 70 °C
Storage Temperature TSTG -55 ~ 125 °C
Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V
Short Circuit Output Current IOS 50 mA
Power Dissipation PD1W
Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 °C ⋅ Sec
Parameter Symbol Min Typ. Max Unit Note
Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1
Input High Voltage VIH 2.0 3.0 VDDQ + 0.3 V 1,2
Input Low Voltage VIL - 0.3 0 0.8 V 1,3
Parameter Symbol Value Unit Note
AC Input High / Low Level Voltage VIH / VIL 2.4/0.4 V
Input Timing Measurement Reference Level Voltage Vtrip 1.4 V
Input Rise / Fall Time tR / tF 1 ns
Output T iming Measurement Reference Level Voutref 1.4 V
Output Load Capacitance for Access T ime Measurement CL 50 pF 1
HY57V56420C(L)T
Rev. 0.4 / July 2003 5
CAPACITANCE (TA=25°C, f=1MHz)
OUTPUT LOAD CIRCUIT
DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)
Note :
1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2.DOUT is disabled, VOUT=0 to 3.6V
Parameter Pin Symbol -6/K/H -8/P/S Unit
Min Max Min Max
Input capacitance CLK CI1 2.5 3.5 2.5 4.0 pF
A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS,
WE, DQM CI22.5 3.8 2.5 5.0 pF
Data input / output capacitance DQ0 ~ DQ3 CI/O 4.0 6.5 4.0 6.5 pF
Parameter Symbol Min. Max Unit Note
Input Leakage Current ILI -1 1 uA 1
Output Leakage Current ILO -1 1 uA 2
Output High Voltage VOH 2.4 - V IOH = -4mA
Output Low Voltage VOL -0.4VIOL = +4mA
Vtt=1.4V
RT=250 Ω
50pF
Output
50pF
Output
DC Output Load Circuit AC Output Load Circuit
HY57V56420C(L)T
Rev. 0.4 / July 2003 6
DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V56420CT-6/K/H/8/P/S
4.HY57V56420CLT-6/K/H/8/P/S
Parameter Symbol Test Condition Speed Unit Note
-6 -K -H -8 -P -S
Operating Current IDD1 Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA 130 120 120 120 110 100 mA 1
Precharge Standby Current
in Power Down Mode
IDD2P CKE ≤ VIL(max), tCK = 15ns 2.5 mA
IDD2PS CKE ≤ VIL(max), tCK = ∞2.0
Precharge Standby Current
in Non Power Down Mode
IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V 35
mA
IDD2NS CKE ≥ VIH(min), tCK = ∞
Input signals are stable. 20
Active Standby Current
in Power Down Mode
IDD3P CKE ≤ VIL(max), tCK = 15ns 5.0 mA
IDD3PS CKE ≤ VIL(max), tCK = ∞5.0
Active Standby Current
in Non Power Down Mode
IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V 45.0
mA
IDD3NS CKE ≥ VIH(min), tCK = ∞
Input signals are stable. 30.0
Burst Mode Operating
Current IDD4 tCK ≥ tCK(min), IOL=0mA
All banks active 150 130 130 130 120 110 mA 1
Auto Refresh Current IDD5 tRRC ≥ tRRC(min), All banks active 120 220 220 200 200 200 mA 2
Self Refresh Current IDD6 CKE ≤ 0.2V 3mA3
1.5 mA 4
HY57V56420C(L)T
Rev. 0.4 / July 2003 7
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Parameter Symbol -6 -K -H -8 -P -S Unit Note
Min Max Min Max Min Max Min Max Min Max Min Max
System Clock Cycle
Time
CAS Latency = 3 tCK3 6 1000 7.5 1000 7.5 1000 81000 10 1000 10 1000 ns
CAS Latency = 2 tCK2 7.5 7.5 10 10 10 12 ns
Clock High Pulse Width tCHW 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1
Clock Low Pulse Width tCLW 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1
Access Time From
Clock
CAS Latency = 3 tAC3 - 5.4 - 5.4 - 5.4 - 6 - 6 - 6 ns 2
CAS Latency = 2 tAC2 - 6 - 5.4 - 6 - 6 - 6 - 6 ns
Data-Out Hold Time tOH 2.7 - 2.7 - 2.7 - 3 - 3 - 3 - ns
Data-Input Setup T i me tDS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1
Data-Input Hold Time tDH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1
Address Setup Time tAS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1
Address Hold Time tAH 0.8 - 0.8 - 0 .8 - 1 - 1 - 1 - ns 1
CKE Setup Time tCKS 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1
CKE Hold Time tCKH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1
Command Setup Time tCS 1.5 - 1.5 - 1 .5 - 2 - 2 - 2 - ns 1
Command Hold Time tCH 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1
CLK to Data Output in Low-Z Time tOLZ 1-1-1-1-1-1-ns
CLK to Data Output
in High-Z Time
CAS Latency = 3tOHZ32.75.42.75.42.75.4363636ns
CAS Latency = 2tOHZ22.75.42.75.436363636ns
HY57V56420C(L)T
Rev. 0.4 / July 2003 8
AC CHARACTERISTICS II
Note :
1. A new command can be given tRRC after self refresh exit
Parameter Symbol -6 -K -H -8 -P -S Unit Note
Min Max Min Max Min Max Min Max Min Max Min Max
RAS Cycle Time Operation tRC 60 - 60 - 65 - 68 - 70 - 70 - ns
Auto Refresh tRRC 60 - 60 - 65 - 68 - 70 - 70 - ns
RAS to CAS Delay tRCD 18 - 15 - 20 - 20 - 20 - 20 - ns
RAS Active Time tRAS 42 100K 45 100K 45 100K 48 100K 50 100K 50 100K ns
RAS Precharge Time tRP 18 - 15 - 20 - 20 - 20 - 20 - ns
RAS to RAS Bank Active Delay tRRD 12 - 15 - 15 - 16 - 20 - 20 - ns
CAS to CAS Delay tCCD 1 - 1 - 1 - 1 - 1 - 1 - CLK
Write Command to Data-In Delay tWTL 0 - 0 - 0 - 0 - 0 - 0 - CLK
Write Recovery Time tWR 2-2-2-2-2-2-CLK
Data-In to Active Command tDAL 5-5-5-5-5-5-CLK
DQM to Data-Out Hi-Z tDQZ 2 - 2 - 2 - 2 - 2 - 2 - CLK
DQM to Data-In Mask tDQM0-0-0-0-0-0-CLK
MRS to New Command tMRD 2 - 2 - 2 - 2 - 2 - 2 - CLK
Precharge to Dat a
Output Hi-Z
CAS Latency = 3 tPROZ3 3 - 3 - 3 - 3 - 3 - 3 - CLK
CAS Latency = 2 tPROZ2 2 - 2 - 2 - 2 - 2 - 2 - CLK
Power Down Exit Time tPDE 1 - 1 - 1 - 1 - 1 - 1 - CLK
Self Refresh Exit Time tSRE 1-1-1-1-1-1-CLK1
Refresh Time tREF - 64 - 64 - 64 - 64 - 64 - 64 ms
HY57V56420C(L)T
Rev. 0.4 / July 2003 9
IBIS SPECIFICATION
IOH Characteristics (Pull-up)
IOL Characteristics (Pull-down)
Voltage 100MHz
(Min) 100MHz
(Max) 66MHz
(Min)
(V) I(mA) I(mA) I(mA)
3.45 -2.4
3.3 -27.3
3.0 0 -74.1 -0.7
2.6 -21.1 -129.2 -7.5
2.4 -34.1 -153.3 -13.3
2.0 -58.7 -197 -27.5
1.8 -67.3 -226.2 -35.5
1.65 -73 -248 -41.1
1.5 -77.9 -269.7 -47.9
1.4 -80.8 -284.3 -52.4
1.0 -88.6 -344.5 -72.5
0 -93 -502.4 -93
Voltage 100MHz
(Min) 100MHz
(Max) 66MHz
(Min)
(V) I(mA) I(mA) I(mA)
0000
0.4 27.5 70.2 17.7
0.65 41.8 107.5 26.9
0.85 51.6 133.8 33.3
1.0 58.0 151.2 37.6
1.4 70.7 187.7 46.6
1.5 72.9 194.4 48.0
1.65 75.4 202.5 49.5
1.8 77.0 208.6 50.7
1.95 77.6 212.0 51.5
3.0 80.3 219.6 54.2
3.45 81.4 222.6 54.9
-600
-500
-400
-300
-200
-100
000.511.522.533.5
Voltag e (V)
I (mA)
I
OH
Min (66MHz)
66MHz and 100MHz Pull-up
I
OH
Min (100MHz)
I
OH
Max (66 /100MH z)
0
50
100
150
200
250
00.511.522.533.5
Voltage (V)
I (mA)
66MHz and 100MHz Pull-down
I
OL
Min (100MHz)
I
OL
Min (66MHz)
I
OL
Max (100MHz)
HY57V56420C(L)T
Rev. 0.4 / July 2003 10
DEVICE OPERATING OPTION TABLE
HY57V56420C(L)T-6
HY57V56420C(L)T-K
HY57V56420C(L)T-H
HY57V56420C(L)T-8
HY57V56420C(L)T-P
HY57V56420C(L)T-S
CAS Latency tRCD tRAS tRC tRP tAC tOH
166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.7ns
143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
133MHz(7.5ns) 2CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
133MHz(7.5ns) 2CLKs 2CLKs 6CLKs 8CLKs 2CLKs 5.4ns 2.7ns
125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns
125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
83MHz(12ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns
66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns
HY57V56420C(L)T
Rev. 0.4 / July 2003 11
COMMAND TRUTH TABLE
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10/
AP BA Note
Mode Register Set H X L L L L X OP code
No Operation H X HXXXXX
LHHH
Bank Active H X L L H H X RA V
Read HXLHLHXCA
LV
Read with Autoprecharge H
Write HXLHLLXCA
LV
Write with Autoprecharge H
Precharge All Banks HXLLHLXX
HX
Precharge selected Bank LV
Burst Stop H X L H H L X X
DQM H X V X
Auto Refresh H H L L L H X X
Burst-Read-Single-
WRITE HXLLLHX A9 Pin High
(Other Pins OP code)
Self Refresh1
Entry H L L L L H X
X
Exit L H HXXXX
LHHH
Precharge
power down
Entry H L HXXXX
X
LHHH
Exit L H HXXXX
LHHH
Clock
Suspend
Entry H L HXXXXXLVVV
Exit L H X X
HY57V56420C(L)T
Rev. 0.4 / July 2003 12
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
11.938(0.4700)
11.735(0.4620)
10.262(0.4040)
10.058(0.3960)
22.327(0.8790)
22.149(0.8720)
5deg
0deg 0.597(0.0235)
0.406(0.0160) 0.210(0.0083)
0.120(0.0047)
1.194(0.0470)
0.991(0.0390)
0.80(0.0315)BSC 0.400(0.016)
0.300(0.012)
UN IT : mm (inch)
0.150(0.0059)
0.050(0.0020)
