TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 3A Processor Supply with I2C Compatible Interface and Remote Sense Check for Samples: TPS62360, TPS62361B, TPS62362, TPS62363 FEATURES DESCRIPTION * * The TPS6236x are a family of high-frequency synchronous step down dc-dc converter optimized for battery-powered portable applications for a small solution size. With an input voltage range of 2.5V to 5.5V, common battery technologies are supported. The device provides up to 3A peak load current, operating at 2.5MHz typical switching frequency. 1 2 * * * * * * 3A Peak Output Current Highest Efficiency: - Low RDS,on Switch and Active Rectifier - Power Save Mode for Light Loads I2C High Speed Compatible Interface Programmable Output Voltage for Digital Voltage Scaling - TPS62360/62: 0.77V to 1.4V, 10mV Steps - TPS62361B/63: 0.5V to 1.77V, 10mV Steps Excellent DC/AC Output Voltage Regulation - Differential Load Sensing - Precise DC Output Voltage Accuracy - DCS-ControlTM Architecture for Fast and Precise Transient Regulation Multiple Robust Operation/Protection Features: - Soft Start - Programmable Slew Rate at Voltage Transition - Over Temperature Protection - Input Under Voltage Detection and Lockout Available in 16-Bump, 2mm x 2mm NanoFreeTM Package Low External Device Count: 27.5 mm2 Solution Size * * * Dynamic Voltage Scale Compliant Processors and DSPs, Memory SmartReflexTM Compliant Power Supply Cell Phones, Smart Phones, Feature Phones Tablets, Netbooks, Clamshells TPS6236x 2.5V .. 5.5V 10F 0.1F VIN AVIN VSEL0 VSEL1 The devices focus on a high output voltage accuracy. The differential sensing and the DCS-ControlTM architecture achieve precise static and dynamic, transient output voltage regulation. The TPS6236x devices offer high efficiency step down conversion. The area of highest efficiency is extended towards low output currents to increase the efficiency while the processor is operating in retention mode, as well as towards highest output currents increasing the battery on-time. 1H The 2mm x 2mm package and the low number of required external components lead to a tiny solution size of approximately 27.5 mm2. 0.77V .. 1.4V (TPS62360/62) 0.5V .. 1.77V (TPS62361B) SW SW 10F EN VDD SCL SDA The TPS6236x supports low-voltage DSPs and processor cores in smart-phones and handheld computers including latest submicron processes. Dedicated hardware input pins allow simple transitions to performance operating points and retention modes of processors. The robust architecture and multiple safety features allow perfect system integration. APPLICATIONS * The devices convert to an output voltage range of 0.77V to 1.4V (TPS62360/62) and 0.5V to 1.77V (TPS62361B/63), programmable via I2C interface in 10mV steps. Dedicated inputs allow fast voltage transition to address processor performance operating points. SENSE+ CPU SENSEPGND PGND AGND PGND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DCS-Control, NanoFree, SmartReflex are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011-2012, Texas Instruments Incorporated TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (2) DEVICE SPECIFIC FEATURES (1) PART NUMBER PACKAGE MARKING PACKAGE Output Voltage Range Output Voltage Presets TPS62360 (2) See PACKAGE SUMMARY Section CSP-16 VOUT = 0.77V to 1.4V, 10mV Steps 1.40V, 1.00V, 1.40V, 1.10V TPS62361B (2) See PACKAGE SUMMARY Section CSP-16 VOUT = 0.5V to 1.77V, 10mV Steps 0.96V, 1.40V, 1.16V, 1.16V TPS62362 (2) See PACKAGE SUMMARY Section CSP-16 VOUT = 0.77V to 1.4V, 10mV Steps 1.23V, 1.10V, 1.20V, 1.10V TPS62363 (2) See PACKAGE SUMMARY Section CSP-16 VOUT = 0.5V to 1.77V, 10mV Steps 1.20V, 1.36V, 1.50V, 1.00V Contact the factory to check availability of other output voltage or feature versions. The YZH package is available in tape and reel. Add R suffix (e.g. TPS62360YZHR) to order quantities of 3000 parts per reel, T suffix for 250 parts per reel (e.g. TPS62360YZHT). For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder on ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE VIN, AVIN, SW pin (2) EN, VSEL0, VSEL1, SENSE+ Voltage range (2) MAX -0.3 7 V -0.3 (VAVIN+0.3V) V SENSE- (2) -0.3 0.3 V SCL, SDA (2) -0.3 (VDD+0.3V) V VDD (2) -0.3 3.6 V 1275 mA Continuous RMS VIN / SW current (3) Temperature ESD rating (5) Operating ambient temperature range, TA (4) -40 85 C Maximum operating junction temperature, TJ (MAX) -40 150 C Storage temperature range, Tstg -65 150 C Machine model 200 V Charge device model 500 V 2 kV Human body model (1) (2) (3) (4) (5) 2 UNIT MIN Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. In order to be consistent with the TI reliability requirement for the silicon chips (100K Power-On-Hours at 105C junction temperature), the current should not continuously exceed 1275mA in the VIN pin and 2550mA in the SW pins so as to prevent electromigration failure in the solder. See THERMAL AND DEVICE LIFE TIME INFORMATION. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part/package in the application (JA), as given by the following equation: TA(max) = TJ(max) - (JA x PD(max)) The human body model is a 100-pF capacitor discharged through a 1.5-k resistor into each pin. The machine model is a 200-pF capacitor discharged directly into each pin. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 THERMAL INFORMATION TPS6236x THERMAL METRIC (1) YZH UNITS 16 PINS Junction-to-ambient thermal resistance (2) JA 94.8 (3) JCtop Junction-to-case (top) thermal resistance JB Junction-to-board thermal resistance (4) 60 JT Junction-to-top characterization parameter (5) 3.2 JB Junction-to-board characterization parameter (6) 57 JCbot Junction-to-case (bottom) thermal resistance (7) n/a (1) (2) (3) (4) (5) (6) (7) 25 C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. RECOMMENDED OPERATING CONDITIONS MIN IOUT 2.5A TYP VIN Input voltage range, VIN IOUT Max. continuous output current (1) 2.5 TA Operating ambient temperature TJ Operating junction temperature IOUT > 2.5A (1) MAX UNIT 2.5 5.5 V 3 5.5 V -40 85 C -40 125 C A Drawing continuously more than 2.5A might impact the device life time. SeeTHERMAL AND DEVICE LIFE TIME INFORMATION for details. ELECTRICAL CHARACTERISTICS Unless otherwise noted the specification applies for VIN = 3.6V over an operating ambient temp. -40C TA 85C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are for TA = 25C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT VIN Input voltage range at VIN, AVIN VDD I2C and registers supply voltage range ISD(AVIN) Shutdown current into AVIN ISD(VIN) ISD(VDD) Shutdown current into VIN Shutdown current into VDD 5.5 V 3.6 V EN = LOW, VDD = 0V EN = LOW, VDD = 0V 0.65 5 A TA = 25C 0.5 1 A TA = 85C 1 3 A 2 EN = LOW, I C bus idle 0.01 A 56 A Forced PWM mode (Test Mode) 180 A Input voltage falling, EN = High 2.3 Input voltage rising, EN = Low 1.3 V 110 mV EN = HIGH, IOUT = 0mA, not switching PFM mode IQ Operating quiescent current into (AVIN + VIN) VUVLO Under voltage lock out at AVIN VUVLO,HYST(AVIN) Under voltage lock out hysteresis at AVIN Input voltage rising VDD,UVLO Under voltage lock out at VDD Input voltage falling Copyright (c) 2011-2012, Texas Instruments Incorporated 2.5 1.15 0.7 0.92 2.45 1.1 Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 V V 3 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted the specification applies for VIN = 3.6V over an operating ambient temp. -40C TA 85C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are for TA = 25C. PARAMETER VUVLO,HYST(VDD) Under voltage lock out hysteresis at VDD TEST CONDITIONS MIN Input voltage rising TYP MAX 50 UNIT mV LOGIC INTERFACE VIH High-level input voltage at EN, VSEL0, VSEL1 VIL Low-level input voltage at EN, VSEL0, VSEL1 trf Signal transition time at EN, VSEL0, VSEL1 VIH,I2C High-level input voltage at SCL, SDA VIL,I2C Low-level input voltage at SCL, SDA ILKG Logic input leakage current at EN, VSEL0, VSEL1, SDA, SCL Internal pulldown resistors disabled 0.05 A RPD Pull down resistance at EN, VSEL0, VSEL1 Internal pulldown resistors enabled 300 k I2C clock frequency 1.2 V 0.4 rising and falling edge 30 V mV/s 0.7x VDD V 0.3x VDD V Fast mode 400 kHz High speed mode 3.4 MHz 75 m POWER SWITCH RDS(on) High side MOSFET switch VIN = 3.6V Low side MOSFET switch 25 44 VIN = 3.6V 25 32 50 m High side MOSFET forward current limit VIN = 3.6V 3.0 3.6 4.3 A Low side MOSFET forward current limit VIN = 3.6V 2.6 3 3.8 A Low side MOSFET negative current limit VIN = 3.6V, PWM mode 2.2 2.5 2.9 A fSW Nominal switching frequency PWM mode 2.5 MHz TJEW Die temperature early warning 120 C TJSD Thermal shutdown 150 C TJSD,HYST Thermal shutdown hysteresis 20 C tON,min Minimum on time 120 ns ILIMF OUTPUT VOUT Output voltage range Output voltage accuracy 10mV increments TPS62360/62 0.77 1.4 0.5 1.77 TPS62360/62: VIN = 2.5V .. 5.5V VOUT = 0.77V .. 1.4V No load, Forced PWM, VOUT = [0.77V, 1.3V] TJ = 85C -0.5% +0.5% TPS62361B/63: VIN = 2.7V .. 5.5V VOUT = 0.5V .. 1.77V No load, Forced PWM, TJ = -40 .. 150C -1% TPS62361B/63 Line regulation IOUT = 1A, forced PWM Load regulation VOUT = 1.2V, forced PWM tStart Start-up time Time from active EN to VOUT = 1.4V, COUT < 100F, RMP[2:0] = 000, IOUT = 0mA RSense Input resistance between Sense+, Sense- 4 Submit Documentation Feedback 0.5% V +1% < 0.1 %/V < 0.05 %/A 1 2.2 ms M Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted the specification applies for VIN = 3.6V over an operating ambient temp. -40C TA 85C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are for TA = 25C. PARAMETER Ramp timer Copyright (c) 2011-2012, Texas Instruments Incorporated TEST CONDITIONS MIN TYP RMP[2:0] = 000 32 RMP[2:0] = 001 16 RMP[2:0] = 010 8 RMP[2:0] = 011 4 RMP[2:0] = 100 2 RMP[2:0] = 101 1 RMP[2:0] = 110 0.5 RMP[2:0] = 111 0.25 MAX UNIT mV/s Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 5 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com I2C INTERFACE TIMING REQUIREMENTS (1) (2) PARAMETER f(SCL) TEST CONDITIONS SCL clock frequency Bus free time between a STOP and START condition tBUF MAX UNIT Standard mode MIN 100 kHz Fast mode 400 kHz High-speed mode (write operation), CB - 100 pF max 3.4 MHz High-speed mode (read operation), CB - 100 pF max 3.4 MHz High-speed mode (write operation), CB - 400 pF max 1.7 MHz High-speed mode (read operation), CB - 400 pF max 1.7 MHz Standard mode 4.7 s Fast mode 1.3 s 4 s Fast mode 600 ns High-speed mode 160 ns Standard mode 4.7 s Fast mode 1.3 s High-speed mode, CB - 100 pF max 160 ns High-speed mode, CB - 400 pF max 320 ns 4 s Standard mode tHD, tSTA tLOW Hold time (repeated) START condition Low period of the SCL clock Standard mode tHIGH High period of the SCL clock tSU, tSTA tSU, tDAT Setup time for a repeated START condition Data setup time Fast mode 600 ns High-speed mode, CB - 100 pF max 60 ns High-speed mode, CB - 400 pF max 120 ns Standard mode 4.7 s Fast mode 600 ns High-speed mode 160 ns Standard mode 250 ns Fast mode 100 ns High-speed mode tHD, tDAT tRCL Data hold time Rise time of SCL signal tRCL1 Rise time of SCL signal after a repeated START condition and after an acknowledge bit 10 0 3.45 s Fast mode 0 0.9 s High-speed mode, CB - 100 pF max 0 70 ns High-speed mode, CB - 400 pF max 0 150 ns Standard mode 20 + 0.1 CB 1000 ns Fast mode 20 + 0.1 CB 300 ns High-speed mode, CB - 100 pF max 10 40 ns High-speed mode, CB - 400 pF max 20 80 ns Standard mode 20 + 0.1 CB 1000 ns Fast mode 20 + 0.1 CB 300 ns 10 80 ns High-speed mode, CB - 100 pF max High-speed mode, CB - 400 pF max tFCL (1) (2) 6 Fall time of SCL signal ns Standard mode 20 160 ns Standard mode 20 + 0.1 CB 300 ns Fast mode 20 + 0.1 CB 300 ns High-speed mode, CB - 100 pF max 10 40 ns High-speed mode, CB - 400 pF max 20 80 ns S/M = standard mode; F/M = fast mode Specified by design. Not tested in production. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 I2C INTERFACE TIMING REQUIREMENTS(1)(2) (continued) PARAMETER tRDA TEST CONDITIONS Rise time of SDA signal MIN MAX UNIT Standard mode 20 + 0.1 CB 1000 ns Fast mode 20 + 0.1 CB 300 ns 10 80 ns High-speed mode, CB - 100 pF max High-speed mode, CB - 400 pF max tFDA Fall time of SDA signal 20 160 ns Standard mode 20 + 0.1 CB 300 ns Fast mode 20 + 0.1 CB 300 ns ns High-speed mode, CB - 100 pF max 10 80 High-speed mode, CB - 400 pF max 20 160 tSU, tSTO Setup time for STOP condition CB ns 4 s Fast mode 600 ns High-speed mode 160 Standard mode Capacitive load for SDA and SCL ns 400 pF I2C TIMING DIAGRAMS SDA tsu;DAT tf tr tLOW tf thd;STA thd;STA tBUF tr SCL thd;STA tsu;STO thd;DAT HIGH Sr S P S Figure 1. Serial Interface Timing for F/S Mode tfDA Sr P trDA SDAH thd;DAT tsu;STA tsu;DAT thd;STA tsu;STO SCLH Sr tfCL tfCL1 See Note A tHIGH tLOW tfCL tLOW trCL1 tHIGH See Note A = MCS Current Source Pull-Up = R(P) Resistor Pull-Up Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit. Figure 2. Serial Interface Timing for H/S Mode Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 7 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com DEVICE INFORMATION PIN ASSIGNMENTS (TOP VIEW) (BOTTOM VIEW) AVIN AGND VSEL1 VIN A1 A2 A3 A4 SENSE+ EN SW SW B1 B2 B3 B4 PGND PGND SENSE- VSEL0 C1 C2 C3 C4 VDD SDA SCL PGND D1 D2 D3 D4 A4 A3 A2 A1 B4 B3 B2 B1 C4 C3 C2 C1 D4 D3 D2 D1 PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. AVIN A1 I Analog Supply Voltage Input. AGND A2 - Analog Ground Connection. EN B2 I Device Enable Logic Input. Logic HIGH enables the device, logic LOW disables the device and turns it into shutdown. The pin must be terminated to either HIGH or LOW if the internal pull down resistor is deactivated. VDD D1 I I2C Logic and Registers supply voltage. For resetting the internal registers, this connection must be pulled below its UVLO level. SCL D3 I/O I2C clock signal. SDA D2 I/O I2C data signal. VSEL0 C2 I VSEL1 A3 I B3 - SW B4 Output Settings Selection Logic Inputs. Predefined register settings can be chosen for setting output voltage and mode. The pins must be terminated to logic HIGH or LOW if the internal pull down resistors are deactivated. Inductor connection SENSE+ B1 I Positive Output Voltage Remote Sense. Must be connected closest to the load supply node. SENSE- C1 I Negative Output Voltage Remote Sense. Must be connected closest to the load ground node. A4 I Power Supply Voltage Input. C3 - VIN PGND C4 Power Ground Connection. D4 8 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 FUNCTIONAL BLOCK DIAGRAM ramp Softstart AVIN AGND direct control & compensation comparator error amplifier Analog Circuit Supply Differential Sense SENSE+ SENSE- Thermal Shutdown DCS-CONTROL TM REF EN VDD SCL RDISCHARGE I2C Interface High Side Current Limit VIN SDA Bandgap Control Logic High Side P-MOS Gate Driver 2 SW Under Voltage Shutdown Low Side N-MOS PGND 3 VSEL0 Low Side Current Limit VSEL1 Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 9 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs. Output Current (Power Save and Forced PWM Mode) Efficiency VOUT = 1.1V Figure 6 VOUT = 1.0V Figure 7 VOUT = 0.9V Figure 8 Figure 9 IOUT = 1000mA Figure 11 IOUT = 100mA Figure 12 IOUT = 10mA Figure 13 VOUT = 1.5V, TA = 25C Figure 14 VOUT = 1.2V, TA = 25C Figure 15 VOUT = 0.9V, TA = 25C Figure 16 VOUT = 0.6V, TA = 25C Figure 17 VOUT = 0.5V, IOUT = 0mA Figure 18 VOUT = 1.5V, IOUT = 0mA Figure 19 VOUT = 0.5V, IOUT = 1000mA Figure 20 VOUT = 1.5V, IOUT = 1000mA Figure 21 IOUT = 10mA Figure 22 IOUT = 200mA Figure 23 IOUT = 1000mA Figure 24 IOUT = 3000mA Figure 25 IOUT = 0mA Figure 26 IOUT = 1000mA Figure 27 IOUT = 5mA to 200mA Figure 28 IOUT = 5mA to 1000mA Figure 29 IOUT = 200mA to 1000mA Figure 30 IOUT = 1000mA to 3000mA Figure 31 Line Transient Response VIN = 3.2 to 4.2V Figure 32 Shutdown Current at AVIN and VIN TA = [-40C, 25C, 125C] Figure 33 TA = [-40C, 25C, 125C], auto PFM/PWM Figure 34 TA = [-40C, 25C, 125C] forced PWM Figure 35 VOUT = 1.2V Figure 36 vs. Output Current (Power Save and Forced PWM Mode) Startup Into Load Switching Wave forms Output Voltage Ramp Control Transition 0.6V .. 1.5V Load Transient Response Quiescent Current vs. Input Voltage vs. Input Voltage fSW Switching Frequency vs. Output Current ILIM Current Limit vs. Input Voltage 10 Figure 5 Figure 10 Into No Load IQ Figure 4 VOUT = 1.2V IOUT = 3000mA DC Output Voltage ISD(VIN), ISD(AVIN) Figure 3 VOUT = 1.4V VOUT = 0.6V vs. Input Voltage (Power Save and Forced PWM Mode) VO VOUT = 1.5V Submit Documentation Feedback Figure 37 Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs OUTPUT CURRENT VOUT = 1.4V 100 100 90 90 80 80 70 70 60 Efficiency (%) Efficiency (%) EFFICIENCY vs OUTPUT CURRENT VOUT = 1.5V TPS62361B VOUT = 1.5V TA = 25C 50 40 30 10 0 1m 10m 100m Output Current (A) 1 TPS6236x VOUT = 1.4V TA = 25C 50 40 30 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 20 60 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 20 10 0 1m 3 10m 100m Output Current (A) 1 G002 Figure 3. Figure 4. EFFICIENCY vs OUTPUT CURRENT VOUT = 1.2V EFFICIENCY vs OUTPUT CURRENT VOUT = 1.1V 100 100 90 90 80 80 70 70 60 Efficiency (%) Efficiency (%) G001 TPS6236x VOUT = 1.2V TA = 25C 50 40 30 20 10 0 1m 10m 100m Output Current (A) 1 60 TPS6236x VOUT = 1.1V TA = 25C 50 40 30 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 20 10 3 0 1m 10m 100m Output Current (A) 1 G003 Figure 5. Copyright (c) 2011-2012, Texas Instruments Incorporated 3 3 G004 Figure 6. Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 11 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs OUTPUT CURRENT VOUT = 0.9V 100 100 90 90 80 80 70 70 60 Efficiency (%) Efficiency (%) EFFICIENCY vs OUTPUT CURRENT VOUT = 1.0V TPS6236x VOUT = 1.0V TA = 25C 50 40 30 10 0 1m 10m 100m Output Current (A) 1 TPS6236x VOUT = 0.9V TA = 25C 50 40 30 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 20 60 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 20 10 0 1m 3 10m 100m Output Current (A) 1 3 G006 Figure 8. EFFICIENCY vs OUTPUT CURRENT VOUT = 0.6V EFFICIENCY vs INPUT VOLTAGE IOUT = 3A 100 100 90 90 80 80 70 70 60 Efficiency (%) Efficiency (%) G005 Figure 7. TPS62361B VOUT = 0.6V TA = 25C 50 40 30 10 0 1m 10m 100m Output Current (A) 1 50 40 30 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 20 60 20 10 3 0 2.5 Auto PFM/PWM, VOUT = 1.0V Auto PFM/PWM, VOUT = 1.1V Auto PFM/PWM, VOUT = 1.4V TPS6236x IOUT = 3A TA = 25C 3.0 3.5 4.0 4.5 Input Voltage (V) G007 Figure 9. 12 Submit Documentation Feedback 5.0 5.5 G008 Figure 10. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs INPUT VOLTAGE IOUT = 100mA 100 100 90 90 80 80 70 70 60 60 Efficiency (%) Efficiency (%) EFFICIENCY vs INPUT VOLTAGE IOUT = 1A 50 40 50 40 30 30 20 20 10 0 2.5 Auto PFM/PWM, VOUT = 1.0V Auto PFM/PWM, VOUT = 1.1V Auto PFM/PWM, VOUT = 1.4V TPS6236x IOUT = 1A TA = 25C 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 10 0 2.5 5.5 Forced PWM, VOUT = 1.0V Forced PWM, VOUT = 1.1V Forced PWM, VOUT = 1.4V Auto PFM/PWM, VOUT = 1.0V Auto PFM/PWM, VOUT = 1.1V Auto PFM/PWM, VOUT = 1.4V TPS6236x IOUT = 100mA TA = 25C 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 G009 Figure 12. EFFICIENCY vs INPUT VOLTAGE IOUT = 10mA DC OUTPUT VOLTAGE vs OUTPUT CURRENT VOUT = 1.5V 100 1.55 90 1.54 80 1.53 DC Output Voltage (V) 70 Efficiency (%) G010 Figure 11. Forced PWM, VOUT = 1.0V Forced PWM, VOUT = 1.1V Forced PWM, VOUT = 1.4V Auto PFM/PWM, VOUT = 1.0V Auto PFM/PWM, VOUT = 1.1V Auto PFM/PWM, VOUT = 1.4V 60 50 40 1.52 1.51 1.50 1.49 30 1.48 20 1.47 10 0 2.5 TPS6236x IOUT = 10mA TA = 25C 3.0 TPS62361B VOUT = 1.5V TA = 25C Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 1.46 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 1.45 1m 10m 100m Output Current (A) 1 G011 Figure 13. Copyright (c) 2011-2012, Texas Instruments Incorporated 3 G012 Figure 14. Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 13 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) DC OUTPUT VOLTAGE vs OUTPUT CURRENT VOUT = 1.2V DC OUTPUT VOLTAGE vs OUTPUT CURRENT VOUT = 0.9V 1.25 0.94 1.23 0.93 1.22 0.92 DC Output Voltage (V) DC Output Voltage (V) 1.24 0.95 TPS6236x VOUT = 1.2V TA = 25C 1.21 1.20 1.19 1.18 1.16 1.15 1m 10m 100m Output Current (A) 1 0.91 0.90 0.89 0.88 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 1.17 TPS6236x VOUT = 0.9V TA = 25C Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 0.87 0.86 3 0.85 1m 10m 100m Output Current (A) 1 3 G013 Figure 16. DC OUTPUT VOLTAGE vs OUTPUT CURRENT VOUT = 0.6V STARTUP INTO NO LOAD VOUT = 0.5V 0.65 0.64 TPS62361B RAMP[2:0] = 000 (32mV/s) IOUT = 0A VIN = 3.6V VOUT = 0.5V TPS62361B VOUT = 0.6V TA = 25C 0.63 DC Output Voltage (V) G014 Figure 15. 0.62 0.61 0.60 0.59 Inductor Current 200mA/Div 0.58 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 0.57 0.56 0.55 1m 10m 100m Output Current (A) 1 EN 2V/DIV 3 Time Base - 20s/Div G017 G015 Figure 17. 14 VOUT 200mV/Div Submit Documentation Feedback Figure 18. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) STARTUP INTO NO LOAD VOUT = 1.5V TPS62361B RAMP[2:0] = 000 (32mV/s) IOUT = 0A VIN = 3.6V VOUT = 1.5V STARTUP INTO LOAD VOUT = 0.5V TPS62361B RAMP[2:0] = 000 (32mV/s) IOUT = 1A VIN = 3.6V VOUT = 0.5V VOUT 1V/Div VOUT 200mV/Div Inductor Current 500mA/Div Inductor Current 500mA/Div EN 2V/DIV EN 2V/DIV Time Base - 20s/Div Time Base - 20s/Div G019 G018 Figure 19. Figure 20. STARTUP INTO LOAD VOUT = 1.5V SWITCHING WAVE FORMS IOUT = 10mA TPS62361B RAMP[2:0] = 000 (32mV/s) ILOAD = 1A VIN = 3.6V VOUT = 1.5V VOUT 1V/Div VOUT 10mV/Div w/ 1.2V Offset Inductor Current 200mA/Div Inductor Current 1A/Div EN 2V/DIV SW Pin 2V/Div TPS62361B IOUT = 10mA Time Base - 20s/Div VIN = 3.6V VOUT = 1.2V Time Base - 4s/Div G021 G020 Figure 21. Copyright (c) 2011-2012, Texas Instruments Incorporated Figure 22. Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 15 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) SWITCHING WAVE FORMS IOUT = 200mA TPS62361B IOUT = 200mA VIN = 3.6V VOUT = 1.2V SWITCHING WAVE FORMS IOUT = 1A TPS62361B IOUT = 1A VIN = 3.6V VOUT = 1.2V VOUT 10mV/Div w/ 1.2V Offset Inductor Current 200mA/Div w/ 200mA Offset VOUT 10mV/Div w/ 1.2V Offset Inductor Current 200mA/Div w/ 1A Offset SW Pin 2V/Div SW Pin 2V/Div Time Base - 250ns/Div Time Base - 250ns/Div G023 G022 TPS62361B IOUT = 3A VIN = 3.6V VOUT = 1.2V Figure 23. Figure 24. SWITCHING WAVE FORMS IOUT = 3A OUTPUT VOLTAGE RAMP CONTROL NO LOAD TPS62361B RAMP[2:0] = 000 (32mV/s) VOUT 1V/Div w/ 0.6V Offset VOUT 10mV/Div w/ 1.2V Offset IOUT = 0A VIN = 3.6V VOUT = 0.6V to 1.5V Inductor Current 200mA/Div w/ 3A Offset Inductor Current 500mA/Div VSEL0 2V/Div SW Pin 2V/Div Time Base - 20s/Div Time Base - 250ns/Div G025 G024 Figure 25. 16 Submit Documentation Feedback Figure 26. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE RAMP CONTROL IOUT = 1A TPS62361B RAMP[2:0] = 000 (32mV/s) LOAD TRANSIENT RESPONSE IOUT RANGE: 5mA to 200mA TPS62361B CLOAD = 22F VOUT 1V/Div w/ 0.6V Offset VIN = 3.6V VOUT = 1.2V VOUT 20mV/Div w/ 1.2V Offset Inductor Current 500mA/Div IOUT = 1A VIN = 3.6V VOUT = 0.6V to 1.5V Inductor Current 200mA/Div VSEL0 2V/Div IOUT 100mA/Div Time Base - 20s/Div Time Base - 100s/Div G026 G027 Figure 27. Figure 28. LOAD TRANSIENT RESPONSE IOUT RANGE: 5mA to 1A LOAD TRANSIENT RESPONSE IOUT RANGE: 200mA to 1A TPS62361B CLOAD = 22F VIN = 3.6V VOUT = 1.2V TPS62361B CLOAD = 22F VIN = 3.6V VOUT = 1.2V VOUT 50mV/Div w/ 1.2V Offset VOUT 50mV/Div w/ 1.2V Offset Inductor Current 500mA/Div Inductor Current 500mA/Div IOUT 1A/Div IOUT 1A/Div Time Base - 100s/Div Time Base - 100s/Div G029 G028 Figure 29. Copyright (c) 2011-2012, Texas Instruments Incorporated Figure 30. Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 17 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) LOAD TRANSIENT RESPONSE IOUT RANGE: 1A to 3A LINE TRANSIENT RESPONSE VIN RANGE: 4.2V to 3.2V TPS62361B CIN = 100nF TPS62361B CLOAD = 22F VIN = 3.6V VOUT = 1.2V VOUT = 1.2V CLOAD = 22F IOUT = 300mA VIN 1V/Div w/ 4.2V Offset VOUT 50mV/Div w/ 1.2V Offset VOUT 20mV/Div w/ 1.2V Offset Inductor Current 1A/Div Inductor Current 200mA/Div IOUT 2A/Div Time Base - 20s/Div Time Base - 100s/Div G031 G030 Figure 31. Figure 32. SHUTDOWN CURRENT vs INPUT VOLTAGE QUIESCENT CURRENT vs INPUT VOLTAGE 10 150 130 TPS6236x MODE0 = 0 (Auto PFM/PWM) EN = HIGH 1 Quiescent Current (A) Shutdown Current (A) 110 TPS6236x EN = LOW 0.1 90 70 50 0.01 AVIN, TA = -40C AVIN, TA = 25C AVIN, TA = 125C 0.001 2.5 3.0 3.5 4.0 4.5 Input Voltage (V) 30 VIN, TA = -40C VIN, TA = 25C VIN, TA = 125C 5.0 5.5 10 2.5 TA = -40C, Auto PFM/PWM TA = 25C, Auto PFM/PWM TA = 125C, Auto PFM/PWM 3.0 3.5 4.0 4.5 Input Voltage (V) G034 Figure 33. 18 Submit Documentation Feedback 5.0 5.5 G035 Figure 34. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) QUIESCENT CURRENT vs INPUT VOLTAGE SWITCHING FREQUENCY vs OUTPUT CURRENT 300 1000 Switching Frequency (kHz) Quiescent Current (A) 250 10000 TPS6236x MODE0 = 1 (Forced PWM) EN = HIGH 200 150 100 TPS6236x VOUT = 1.2V VIN = 3.6V 10 1 50 0 2.5 100 TA = -40C, Forced PWM TA = 25C, Forced PWM TA = 125C, Forced PWM 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 Auto PFM/PWM Forced PWM 0.1 0.1 5.5 1 10 100 Output Current (mA) 1000 3000 G036 G037 Figure 35. Figure 36. FET CURRENT LIMIT vs INPUT VOLTAGE 4.0 3.8 3.6 FET Current Limit (A) 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 2.5 High Side PMOS Current Limit Low Side NMOS Current Limit Negative NMOS Current Limit TPS6236x TA = 25C 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 G038 Figure 37. Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 19 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION TPS6236x VIN VIN AVIN L C4 EN C1 C2 VDD SCL SDA VDD VSEL0 VSEL1 C3 VOUT SW SW SENSE+ SENSEPGND PGND AGND PGND Table 1. List of Components REFERENCE DESCRIPTION MANUFACTURER TPS6236x 3A Processor Supply with I2C Compatible Interface and Remote Sense Texas Instruments L 1 H, 4 mm x 4 mm x 2.1 mm Coilcraft (XFL4020-102ME1.0) C2, C4 10 F, Ceramic, 6.3V, X5R Murata (GRM188R60J106ME84D) C1, C3 0.1 F, Ceramic, 10V, X5R Standard 20 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 DETAILED DESCRIPTION The TPS6236x are a family of high-frequency synchronous step down dc-dc converter optimized for batterypowered portable applications. With an input voltage range of 2.5V to 5.5V, common battery technologies are supported. The device provides up to 3A peak load current, operating at 2.5MHz typical switching frequency. The devices convert to an output voltage range of 0.77V to 1.4V (TPS62360 / TPS62362) and 0.5V to 1.77V (TPS62361B / TPS62363), programmable via I2C interface in 10mV steps. The TPS6236x supports low-voltage DSPs and processor cores in smart-phones and handheld computers, including latest submicron processes and their retention modes and addresses digital voltage scaling technologies such as SmartReflexTM. Output Voltages and Modes can be fully programmed via I2C. To address different performance operating points and/or startup conditions, the device offers four output voltage / mode presets which can be chosen via dedicated hardware input pins allowing simple and zero latency output voltage transition. The devices focus on a high output voltage accuracy. The fully differential sensing and the DCS-ControlTM architecture achieve precise static and dynamic, transient output voltage regulation. This accounts for stable processor operation. Output voltage security margins can be kept small, resulting in an increased overall system efficiency. The TPS6236x devices offer high efficiency step down conversion. The area of highest efficiency is extended towards low output currents to increase the efficiency while the processor is operating in retention mode, as well as towards highest output currents reducing the power loss. This addresses the power profile of processors. High efficiency conversion is required for low output currents to support the retention modes of processors, resulting in an increased battery on-time. To address the processor maximum performance operating points with highest output currents, high efficiency conversion is enabled as well to save the battery on-time and reduce input power. The robust architecture and multiple safety features allow perfect system integration. The 2mm x 2mm package and the low number of required external components lead to a tiny solution size of approximately 27.5 mm2. OPERATION The TPS6236x synchronous switched mode power converters are based on DCS-ControlTM, an advanced regulation topology, that combines the advantages of hysteretic, voltage mode and current mode control architectures. While a comparator stage provides excellent load transient response, an additional voltage loop ensures high DC accuracy as well. The TPS6236x compensates ground shifts at the load by the differentially sensing the output voltage at the point of load. The internal ramp generator adds information about the load current and fast output voltage changes. The internally compensated regulation network achieves fast and stable operation with low ESR capacitors. The DCS-ControlTM topology supports PWM (Pulse Width Modulation) mode for medium and heavy load conditions and a Power Save Mode at light loads. During PWM it operates at its nominal switching frequency in continuous conduction mode. This frequency is typically about 2.5MHz with a controlled frequency variation depending on the input voltage. As the load current decreases, the converter enters Power Save Mode to sustain high efficiency down to light loads. The transition from PWM to Power Save Mode is seamless and avoids output voltage transients. An internal current limit supports nominal output currents of up to 3A. The TPS6236x family offers both excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits. ENABLING AND DISABLING THE DEVICE The device is enabled by setting the EN input to a logic high. Accordingly, a logic low disables the device. If the device is enabled, the internal power stage will start switching and regulate the output voltage to the programmed threshold. The EN input must be terminated unless the internal pull down resistor is activated. Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 21 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com The I2C interface is operable when VDD and AVIN are present, regardless of the state of the EN pin. If the device is disabled by pulling the EN to a logic low, the output capacitor can actively be discharged. Per default, this feature is disabled. Programming the EN_DISC bit to a logic high will discharge the output capacitor via a typ. 300 path on the SENSE+ pin. SOFT START The device incorporates an internal soft start circuitry that controls the ramp up of the output voltage after enabling the device. This circuitry eliminates inrush current to avoid excessive voltage drops of primary cells and rechargeable batteries with high internal impedance. During soft start, the output voltage is monotonically ramped up to the minimum programmable output voltage. After reaching this threshold, the output voltage is further increased following the slope as programmed in the ramp rate settings (see RAMP RATE CONTROLLING) until reaching the programmed output voltage. Once the nominal voltage is reached, regular operation as described above will continue. The device is able to start into a pre biased output capacitor as well. PROGRAMMING THE OUTPUT The TPS6236x devices offer four similar registers to program the output. Two dedicated hardware input pins, VSEL0 and VSEL1, are implemented for choosing the active register. The logic state of VSEL0 and VSEL1 select the register whose settings are present at the output. The VSEL0 and VSEL1 pins must be terminated unless the internal pull-down resistors are activated. The registers have a certain initial default value (see Table 2) and can be readjusted via I2C during operation. This allows a simple transition between several output options by triggering the dedicated input pins. At the same time since the presets can be readjusted during operation, this offers highest flexibility. Table 2. Output Presets INPUT PINS PRESET 2 I C REGISTER DEFAULT OPERATION MODE DEFAULT OUTPUT VOLTAGE [V] TPS62360, TPS62361B, TPS62362, TPS62363 TPS62360 TPS62361B TPS62362 TPS62363 0x00h - see Table 13, Table 14 and Table 15 Power Save Mode 1.40 0.96 1.23 1.20 SET1 0x01h - see Table 17, Table 18 and Table 19 Power Save Mode 1.00 1.40 1.00 1.36 0 SET2 0x02h - see Table 21, Table 22 and Table 23 Power Save Mode 1.40 1.16 1.20 1.50 1 SET3 0x03h - see Table 25, Table 26 and Table 27 Power Save Mode 1.10 1.16 1.10 1.00 VSEL1 VSEL0 0 0 SET0 0 1 1 1 Via the I2C interface and/or the four preset options, the following output parameters can be changed: * Output voltage from 0.77V to 1.4V (TPS62360/62) and 0.5V to 1.77V (TPS62361B/63) with 10 mV granularity * Mode of operation: Power Save Mode or forced PWM mode The slope for transition between different output voltages (Ramp Rate) can be changed via I2C as well. The slope applies for all presets globally. See RAMP RATE CONTROLLING for further details. Since the output parameters can be changed by dedicated pins for selecting presets and by I2C, the following use scenarios are feasible: * Control the device via dedicated pins only, after programming the presets, to choose and change within the programmed settings * Program via I2C only. The dedicated input pins have fixed connections. Changes are conducted by changing the preset values of the active register. * Dedicated input pins and I2C mixed operation. The non active presets might be changed. The dedicated input pins are used for the transition to the new output condition. Changes within an active preset via I2C are feasible as well. 22 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 DYNAMIC VOLTAGE SCALING The output voltage can be adjusted dynamically. Each of the four output registers can be programmed individually by setting OV[5:0] (TPS62360/62) and OV[6:0] (TPS62361B/63) respectively in the SET0, SET1, SET2 and SET3 registers. Table 3. TPS62360, TPS62362 Output Voltage Settings for Registers SET0, SET1, SET2 and SET3 REGISTERS: SET0, SET1, SET2, SET3 OV[D5:D0] OUTPUT VOLTAGE 00 0000 770 mV 00 0001 780 mV 00 0010 790 mV 00 0011 800 mV ... ... 11 1101 1380 mV 11 1110 1390 mV 11 1111 1400 mV Table 4. TPS62361B, TPS62363 Output Voltage Settings for Registers SET0, SET1, SET2 and SET3 REGISTERS: SET0, SET1, SET2, SET3 OV[D6:D0] OUTPUT VOLTAGE 000 0000 500 mV 000 0001 510 mV 000 0010 520 mV 000 0011 530 mV ... ... 111 1101 1750 mV 111 1110 1760 mV 111 1111 1770 mV If the output voltage is changed at the active register (selected by VSEL0 and VSEL1), these changes will apply after the I2C command is sent. POWER SAVE MODE AND FORCED PWM MODE The TPS6236x devices feature a Power Save Mode to gain efficiency at light output current conditions. The device automatically transitions in both directions between pulse width modulation (PWM) operation at high load and pulse frequency modulation (PFM) operation at light load current. This maintains high efficiency at both light and heavy load currents. In PFM Mode, the device generates single switching pulses when required to maintain the programmed output voltage. The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in both directions. The output current, at which the device transitions from PWM to PFM operation can be estimated as follows: V - VOUT VOUT 1 IOUT,TRANS = IN 2 VIN (f L) (1) With: VIN = Input voltage VOUT = Output Voltage = Switching frequency, typ. 2.5 MHz L = Inductor value Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 23 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com The TPS6236x is optimized for low output voltage ripple. Therefore, the peak inductor current in PFM mode is kept small and can be calculated as follows: IL,PFM,peak = t ON (VIN - VOUT ) L (2) And: t ON = VOUT 350ns + 20ns VIN (3) With: VIN = Input Voltage VOUT = Output Voltage tON = On-time of the High Side FET, from Equation 3 L = Inductor value The TPS6236x offers a forced PWM mode as well. In this mode, the converter is forced in PWM mode even at light load currents. This comes with the benefit that the converter is operating with lower output voltage ripple. Compared to the PFM mode, the efficiency is lower during light load currents. According to the output voltage, the Power Save Mode / forced PWM Mode can be programmed individually for each preset via I2C by setting the MODE0 - MODE3 bit D7. Table 2 shows the factory presets after enabling the I2C. For additional flexibility, the Power Save Mode can be changed at a preset that is currently active. RAMP RATE CONTROLLING If the output voltage is changed, the TPS6236x can actively control the voltage ramp rate during the transition. An internal oscillator is embedded for high timing precision. Figure 38 and Figure 39 show the operation principle. If the output voltage changes, the device will change the output voltage through discrete steps with a programmable ramp rate resulting in a corresponding transition time. The ramp up/down slope can be programmed via I2C interface (see Table 5). Table 5. Ramp Rates RMP [2:0] RAMP RATE [mV/s] [s/10mV] 000 32 0.3125 001 16 0.625 010 8 1.25 011 4 2.5 100 2 5 101 1 10 110 0.5 20 111 0.25 40 For a transition of the output voltage from VOUT,A to VOUT,B and vice versa, the resulting ramp up/down slope can be calculated as VOUT mV 1 = 32 t s 2(RMP[2-0] )2 (4) If the device is operating in forced PWM Mode, the device actively controls both the ramp up and down slope. If Power Save Mode is activated, the ramp up phase follows the programmed slope. To force the output voltage to follow the ramp down slope in Power Save Mode, the RAMP_PFM bit needs to be set. This will force the converter to follow the ramp down slope during PFM operation as well. 24 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 If the RAMP_PFM bit is not set in Power Save Mode, the slope can be less at low output currents since the device does not actively source energy back from the output capacitor to the input or it might be sharper at high output currents since the output capacitor is discharged quickly. Output Voltage Output Voltage VOUT,B VOUT,B VOUT 10 mV VOUT,A VOUT 20 mV VOUT,A 10 mV/Ramp Rate 20 mV/Ramp Rate time t time t (TPS62360 / TPS62362) (TPS62361B / TPS62363) Figure 38. Ramp Up Output Voltage Output Voltage VOUT,A 10 mV/Ramp Rate 10 mV VOUT 20 mV/Ramp Rate VOUT,B VOUT VOUT,B 20 mV VOUT,A time t (TPS62360 / TPS62362) t time (TPS62361B / TPS62363) Figure 39. Ramp Down The TPS62360 and TPS62362 ramp the output voltage taking 10mV steps, while the TPS62361B and TPS62363 ramp taking 20mV steps with a final 10mV step if required. The resulting slope remains equal for both devices. While the output voltage setpoint is changed in a digital stair step fashion, the connected output capacitor flattens the steps to create a linear change in the output voltage. SAFE OPERATION AND PROTECTION FEATURES Inductor Current Limit The inductor current limiting prevents the device from drawing high inductor current and excessive current from the battery. Excessive current might occur with a shorted/saturated inductor or a heavy load/shorted output circuit condition. The incorporated inductor peak current limit measures the current while the high side power MOSFET is turned on. Once the current limit is tripped, the high side MOSFET is turned off and the low side MOSFET is turned on to ramp down the inductor current. This prevents high currents to be drawn from the battery. Once the low side MOSFET is on, the low side forward current limit keeps the low side MOSFET on until the current through it decreases below the low side forward current limit threshold. The negative current limit acts if current is flowing back to the battery from the output. It works differently in PWM and PFM operation. In PWM operation, the negative current limit prevents excessive current from flowing back through the inductor to the battery, preventing abnormal voltage conditions at the switching node. In PFM operation, a zero current limits any power flow back to the battery by preventing negative inductor current. Die Temperature Monitoring and Over Temperature Protection The TPS6236x offers two stages of die temperature monitoring and protection. Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 25 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com The Early Warning Monitoring Feature monitors the device temperature and provides the host an indication that the die temperature is in the higher range. If the device's junction temperature, TJ, exceeds 120C typical, the TJEW bit is set high. To avoid the thermal shutdown being triggered, the current drawn from the TPS6236x should be reduced at this early stage. The Over Temperature Protection feature disables the device if the temperature increases due to heavy load and/or high ambient temperature. It monitors the device die temperature and, if required, triggers the device into shutdown until the die temperature falls sufficiently. If the junction temperature, TJ, exceeds 150C typical, the device goes into thermal shutdown. In this mode, the power stage is turned off. During thermal shutdown, the I2C interface remains operable. All register values are kept. For the thermal shutdown, a hysteresis of 20C typical is implemented allowing the device to cool after the shutdown is triggered. Once the junction temperature TJ cools down to 130C typical, the device resumes operation. If a thermal shutdown has occurred, the TJTS bit is latched and remains a logic high as long as VDD and AVIN are present and until the bit is reset by the host. Input Under Voltage Protection The input under voltage protection is implemented in order to prevent operation of the device for low input voltage conditions. If the device is enabled, it prevents the device from switching if AVIN falls below the under voltage lockout threshold. If the AVIN under voltage protection threshold is tripped, the device will go into under voltage shutdown instantaneously, turning the power stage off and resetting all internal registers. The input under voltage protection is also implemented on the VDD input. If the VDD under voltage protection threshold is tripped, the device will reset all internal registers. A under voltage lockout hysteresis of VUVLO,HYST(AVIN) at AVIN and VUVLO,HYST(VDD) at VDD is implemented. The I2C compatible interface remains fully functional if AVIN and VDD are present. If the under voltage lockout of AVIN or VDD is triggered during operation, all internal registers are reset to their default values. Figure 40 shows the UVLO block diagram. AVIN external low ohmic connection AVIN Under Voltage? Device Shutdown VIN VDD VDD Under Voltage? Register Reset, 2 I C I/F Disabled Figure 40. UVLO State Chart By connecting VIN and AVIN to the same potential, VIN is included in the under voltage monitoring. If a low pass input filter is applied at AVIN (not mandatory for the TPS6236x), the delay and shift in the voltage level can be calculated by taking the typical quiescent current IQ at AVIN. As an example, for IQ and 10 series resistance, this results in a minimal static shift of approx. 560V. VIN and AVIN must be connected to the same source for proper device operation. 26 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 APPLICATION INFORMATION I2C INTERFACE Serial Interface Description I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a micro controller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The TPS6236x device works as a slave and supports the following data transfer modes, as defined in the I2CBus Specification: * Standard mode (100 kbps) * Fast mode (400 kbps) * Fast mode plus (1Mbps) * High-speed mode (3.4 Mbps) The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as VDD and AVIN are present in the specified range. Tripping the under voltage lockout of AVIN or VDD deletes the registers and establishes the default values once the supply is present again. The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as HS-mode. The TPS6236x device supports 7-bit addressing. 10-bit addressing and general call addressing are not supported. Table 6 shows the TPS6236x devices and their assigned I2C addresses. Table 6. I2C Address I2C ADDRESS DEVICE OPTION HEXADECIMAL CODED BINARY CODED TPS62360 (0x60)HEX (110 0000)2 TPS62361B (0x60)HEX (110 0000)2 TPS62362 (0x60)HEX (110 0000)2 TPS62363 (0x60)HEX (110 0000)2 F/S-Mode Protocol The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 41. All I2C-compatible devices should recognize a start condition. SDA SCL S P START condition STOP condition Figure 41. START and STOP Conditions Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 27 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 42). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 43) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established. SDA SCL Data line stable; data valid Change of data allowed Figure 42. Bit Transfer on the Serial Interface The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 41). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. Attempting to read data from register addresses not listed in this section will result in 00h being read out. Data Output by Transmitter Data Output by Receiver Not Acknowledge Acknowledge SCL 1 2 8 9 S Clock Pulse for Acknowledgment START condition Figure 43. Acknowledge on the I2C Bus 28 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 Recognize repeated START or STOP Condition Recognize START or repeated START Condition Generate ACKNOWLEDGE Signal P SDA Sr Acknowledgment Signal From Slave S SCL 1 or 2 Sr 7 8 1 9 ACK 2-8 Sr 9 ACK or P Address Clock Line Held Low While Interrupts are Serviced START or repeated START Condition repeated START or STOP Condition Figure 44. Bus Protocol HS-Mode Protocol When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices. The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation. The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS-mode. Attempting to read data from register addresses not listed in this section will result in 00h being read out. I2C UPDATE SEQUENCE The TPS6236x requires a start condition, a valid I2C address, a register address byte, and a data byte for a single update. After the receipt of each byte, the TPS6236x device acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the TPS6236x. The TPS6236x performs an update on the falling edge of the acknowledge signal that follows the LSB byte. 1 7 S Slave Address 1 1 R/W A 8 1 8 1 1 Register Address A Data A P "0" Write A S Sr P From Master to TPS6236x From TPS6236x to Master = = = = Acknowledge START condition REPEATED START condition STOP condition Figure 45. Write Data Transfer Format in F/S-Mode 1 7 S Slave Address 1 R/W A 8 1 1 7 Register Address A Sr Slave Address "0" Write From Master to TPS6236x From TPS6236x to Master 1 1 R/W A 8 1 1 Data A P "1" Read A S Sr P = = = = Acknowledge START condition REPEATED START condition STOP condition Figure 46. Read Data Transfer Format in F/S-Mode Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 29 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com F/S Mode 1 H/S Mode 8 S HS-Master Code 1 1 7 A Sr Slave Address 1 1 F/S Mode 8 R/W A Register Address 1 8 1 1 A Data A/A P Data Transferred (n x Bytes + Acknowledge) From Master to TPS6236x From TPS6236x to Master A A S Sr P = = = = = H/S Mode continues Acknowledge Acknowledge START condition REPEATED START condition STOP condition Sr Slave Address Figure 47. Data Transfer Format in H/S-Mode Slave Address Byte MSB X X X X X X A1 LSB A0 The slave address byte is the first byte received following the START condition from the master device. Register Address Byte MSB 0 0 0 0 0 D2 D1 LSB D0 Following the successful acknowledgment of the slave address, the bus master will send a byte to the TPS6236x, which will contain the address of the register to be accessed. I2C REGISTER RESET The I2C registers can be reset by pulling VDD to GND. Refer to the Input Under Voltage Protection section for details. PULL DOWN RESISTORS The EN, VSEL0 and VSEL1 inputs feature internal pull down resistors to discharge the potential if one of the pins is not connected or is triggered by a high impedance source. To achieve lowest possible quiescent current, the pull down resistors can be disabled individually at EN, VSEL0 and VSEL1 by I2C programming the registers PD_EN, PD_VSEL0 and PD_VSEL1. By default, the pull down resistors are enabled. INPUT CAPACITOR SELECTION The input capacitor is required to buffer the pulsing current drawn by the device at VIN and reducing the input voltage ripple. The pulsing current is originated by the operation principles of a step down converter. Low ESR input capacitors are required for best input voltage filtering and minimal interference with other system components. For best performance, ceramic capacitors with a low ESR at the switching frequency are recommended. X7R or X5R type capacitors should be used. A ceramic input capacitor in the nominal range of CIN = 4.7F to 22F should be a good choice for most application scenarios. In general, there is no upper limit for increasing the input capacitor. For typical operation, a 10F X5R type capacitor is recommended. Table 7 shows a list of recommended capacitors. 30 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 Table 7. List of Recommended Capacitors CAPACITANCE [F] TYPE DIMENSIONS L x W x H [mm3] MANUFACTURER 10 GRM188R60J106M 0603: 1.6 x 0.8 x 0.8 Murata 10 CL10A106MQ8NRNC 0603: 1.6 x 0.8 x 0.8 Samsung 22 GRM188R60G226M 0603: 1.6 x 0.8 x 0.8 Murata 22 CL10A106MQ8NRNC 0603: 1.6 x 0.8 x 0.8 Samsung DECOUPLING CAPACITORS AT AVIN, VDD Noise impacts can be reduced by buffering AVIN and VDD with a decoupling capacitor. It is recommended to buffer AVIN and VDD with a X5R or X7R ceramic capacitor of at least 0.1F connected between AVIN, AGND and VDD, AGND respectively. The capacitor closest to the pin should be kept small (< 0.22F) in order to keep a low impedance at high frequencies. In general, there is no upper limit for the total capacitance. Adding a low pass input filter at AVIN (e.g. by adding a resistor in series) is not mandatory for the TPS6236x to filter out noise. INDUCTOR SELECTION The choice of the inductor type and value has an impact on the inductor ripple current, the transition point of PFM to PWM operation, the output voltage ripple and accuracy. The subsections below support for choosing the proper inductor. Inductance Value The TPS6236x is designed for best operation with a nominal inductance value of 1H. Choosing a smaller value than 1H improves the load transient behavior, whereas choosing a higher value reduces the ripple current resulting in a smaller output voltage ripple and better DC output regulation. The inductor current ripple can be calculated as: V 1 - OUT VIN IL = VOUT L | (5) With: VIN = Input Voltage VOUT = Output Voltage = Switching frequency, typ. 2.5 MHz L = Inductor value Inductor Saturation Current The inductor needs to be selected for its current rating. To pick the proper saturation current rating, the maximum inductor current can be calculated as: IL IL,MAX = IOUT,MAX + 2 (6) With: IL = Inductor ripple current (see Equation 5) IOUT,MAX = Maximum output current Since the inductance can be decreased by saturation effects and temperature impact, the inductor needs to be chosen to have an effective inductance of at least 0.6H under temperature and saturation effects. Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 31 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com Table 8. List of Recommended Inductors (1) INDUCTANCE [H] SATURATION CURRENT RATING (30% inductance drop, typ) [A] DIMENSIONS L x W x H [mm3] DC RESISTANCE [m typ] TYPE MANUFACTURER 1.0 3.4 3.2 x 2.5 x 1.2 51 PST032251B-1R0MS-11 Cyntec 1.0 3.9 3.2 x 2.5 x 1.0 48 DFE322510C1276AS-H1R0N (1) Toko 1.0 4.6 3.2 x 2.5 x 1.2 37 DFE322512C1277AS-H1R0N (1) Toko 1.0 3.8 2.5 x 2.0 x 1.2 45 DFE252012C1239AS-H1R0N=P2 Toko 1.0 5.4 4 x 4 x 2.1 10 XFL4020-102ME1.0 Coilcraft 1.0 5.4 3.2 x 3 x 1.2 57 SPM3012T-1R0M TDK Release planned for Q4/2011. Contact manufacturer for details. OUTPUT CAPACITOR SELECTION The unique hysteretic control scheme allows the use of tiny ceramic capacitors. For best performance, ceramic capacitors with low ESR values are recommended to achieve high conversion efficiency and low output voltage ripple. For stable operation, X7R or X5R type capacitors are recommended. The TPS6236x is designed to operate with an output capacitor of 10F to 22F, placed at the device's output. In addition a 0.1F capacitor can be added to the output to reduce the high frequency content created by a very sudden load change. At light loads, if the device is operating in PFM Mode, choosing a higher value will minimize the voltage ripple resulting in a better DC output accuracy. Buffering the processor input by an additional ceramic capacitor in the range of 10F to 22F improves the voltage quality at the processor input and the dynamic load step behavior. This is especially true if the trace between the TPS6236x and the microprocessor is longer than the smallest possible. This additional capacitor needs to be taken into account for the recommended capacitance value. For stability, the sum of the VOUT capacitors should not exceed 75F effective capacitance. Table 7 shows a list of tested capacitors. The TPS6236x is not designed for use with polymer, tantalum, or electrolytic output capacitors. OUTPUT FILTER DESIGN The inductor and the output capacitor build the output filter. The load might be buffered with an input capacitor CLOAD, which needs to be factored in. Based on the output capacitor and inductance recommendation sections and factoring in CLOAD, these components should be in the range: * COUT + CLOAD= 10F to 75F * L = 1 H For further performance or specific demands, these values might be tweaked. In any case, the loop stability should be checked since the control loop stability might be affected. THERMAL AND DEVICE LIFE TIME INFORMATION Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component. Thermal performance can be enhanced by proper PCB layout. Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi layer PCB designs with vias to different layers. Proper PCB layout with focus on thermal performance results in a reduced junction-to-ambient thermal resistance JA and thereby reduces the device junction temperature, TJ. 32 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 The TI reliability requirement for the silicon chip's life time (100K Power-On-Hours at TJ = 105C) is affected by the junction temperature and the continuously drawn current at the VIN pin and the SW pins. In order to be consistent with the TI reliability requirement for the silicon chips (100000 Power-On-Hours at TJ = 105C), the VIN pin current should not continuously exceed 1275mA and the SW pins current should not continuously exceed 2550mA so as to prevent electromigration failure in the solder bump. Drawing 1150mA at VIN would, as an example, be the case for typically IOUT = 2350mA, VOUT = 1.5V and VIN = 3.6V. Exceeding the VIN pin / SW pins current rating might affect the device reliability. As an example, drawing current peaks IOUT = 3000mA with up to 10% of the application time over a base continuous output current IOUT = 2000mA might reduce the Power-on-Hours to 90000 hours for conditions such as VIN = 2.7V, VOUT = 1.5V, TJ = 105C. In this example, exceeding TJ = 105C in combination with a higher peak output current duty cycle clearly further affects the device life time. For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics Application Note (SZZA017), and IC Package Thermal Metrics Application Note (SPRA953). PCB LAYOUT CONSIDERATIONS The PCB layout is an important step to maintain the high performance of the TPS6236x. Both the high current and the fast switching nodes demands full attention to the PCB layout. The input / output capacitors and the inductor should be placed as close as possible to the IC. This keeps the traces short. Routing these traces direct and wide results in low trace resistance and low parasitic inductance. A common power GND should be used. The low side of the input and output capacitors must be connected to the power GND, as well as the PGND node. AGND and PGND should be connected close to the IC but at a single place. The sense traces connected to SENSE+ and SENSE- are signal traces. Special care should be taken to avoid noise being induced. By a direct routing, parasitic inductance can be kept small. GND layers might be used for shielding if the parasitic capacitance can be kept small. Routing the SENSE+ and SENSE- close to each other minimizes inductive noise injection. Keep these traces away from switching nodes and swiftly alternating signal lines such as the I2C bus. Improper layout might show the symptoms of poor line or load regulation, ground and output voltage shifts, stability issues or unsatisfying EMI behavior. See Figure 48 for the recommended layout. AGND VIN AVIN PGND VDD VOUT Figure 48. Layout Suggestion (top view). Overall Solution Size: 27.5mm2 Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 33 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com REGISTER SETTINGS Overview Table 9. TPS62360 Register Settings Overview ADDRESS REGISTER REGISTER (default / reset values) RESET / DEFAULT STATE READ / WRITE MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 DIS_TS TJEW TJTS EN_DISC RAMP_PFM 0x00h SET0 0x111111 R/W MODE0 OV0[5:0] 0x01h SET1 0x010111 R/W MODE1 OV1[5:0] 0x02h SET2 0x111111 R/W MODE2 OV2[5:0] 0x03h SET3 0x100001 R/W MODE3 0x04h Ctrl 111xxxxx R/W PD_EN 0x05h Temp xxxxx000 R/W 0x06h RmpCtrl 000xx00x R/W 0x07h (Reserved) xxxxxxxx 0x08h Chip_ID 0x09h Chip_ID 100000xx OV3[5:0] PD_VSEL0 PD_VSEL1 RMP[2:0] R Table 10. TPS62361B Register Settings Overview ADDRESS REGISTER REGISTER (default / reset values) RESET / DEFAULT STATE READ / WRITE MSB D7 LSB D6 D5 D4 D3 0x00h SET0 00101110 R/W MODE0 OV0[6:0] 0x01h SET1 01011010 R/W MODE1 OV1[6:0] 0x02h SET2 01000010 R/W MODE2 OV2[6:0] 0x03h SET3 01000010 R/W MODE3 OV3[6:0] 0x04h Ctrl 111xxxxx R/W PD_EN 0x05h Temp xxxxx000 R/W 0x06h RmpCtrl 000xx00x R/W 0x07h (Reserved) xxxxxxxx 0x08h Chip_ID 0x09h Chip_ID 100001xx PD_VSEL0 D2 D1 D0 DIS_TS TJEW TJTS EN_DISC RAMP_PFM PD_VSEL1 RMP[2:0] R Table 11. TPS62362 Register Settings Overview ADDRESS 34 REGISTER REGISTER (default / reset values) RESET / DEFAULT STATE READ / WRITE MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 DIS_TS TJEW TJTS EN_DISC RAMP_PFM 0x00h SET0 0x101110 R/W MODE0 OV0[5:0] 0x01h SET1 0x010111 R/W MODE1 OV1[5:0] 0x02h SET2 0x101011 R/W MODE2 OV2[5:0] 0x03h SET3 0x100001 R/W MODE3 0x04h Ctrl 111xxxxx R/W PD_EN 0x05h Temp xxxxx000 R/W 0x06h RmpCtrl 000xx00x R/W 0x07h (Reserved) xxxxxxxx 0x08h Chip_ID 0x09h Chip_ID 100010xx OV3[5:0] PD_VSEL0 PD_VSEL1 RMP[2:0] R Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 Table 12. TPS62363 Register Settings Overview ADDRESS REGISTER REGISTER (default / reset values) RESET / DEFAULT STATE READ / WRITE MSB D7 LSB D6 D5 D4 D3 0x00h SET0 01000110 R/W MODE0 OV0[6:0] 0x01h SET1 01010011 R/W MODE1 OV1[6:0] 0x02h SET2 01100100 R/W MODE2 OV2[6:0] 0x03h SET3 00110010 R/W MODE3 0x04h Ctrl 111xxxxx R/W PD_EN 0x05h Temp xxxxx000 R/W 0x06h RmpCtrl 000xx00x R/W 0x07h (Reserved) xxxxxxxx 0x08h Chip_ID 0x09h Chip_ID 100001xx D2 D1 D0 DIS_TS TJEW TJTS EN_DISC RAMP_PFM OV3[6:0] PD_VSEL0 PD_VSEL1 RMP[2:0] R Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 35 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com Register 0x00h Description: SET0 The register settings apply by choosing SET0 ( VSEL1 = LOW, VSEL0 = LOW). Table 13. TPS62360 Register 0x00h Description REGISTER ADDRESS: 0x00h Read/Write BIT NAME D7 MODE0 DEFAULT MSB DESCRIPTION 0 Operation mode for SET0 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 x Reserved for future use D5 1 Output voltage for SET0 Default: (111111)2 = 1.4V D4 1 D5-D0 Output voltage D3 1 00 0000 770 mV 00 0001 780 mV 00 0010 790 mV ... ... 11 1111 1400 mV D2 OV0[5:0] 1 D1 1 D0 LSB 1 VOUT = (xx xxxx)2 x 10mV + 770 mV Table 14. TPS62361B Register 0x00h Description REGISTER ADDRESS: 0x00h Read/Write BIT NAME DEFAULT MSB D7 MODE0 0 DESCRIPTION Operation mode for SET0 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 0 D5 1 Output voltage for SET0 Default: (0101110)2 = 0.96V D4 0 D6-D0 Output voltage 1 000 0000 500 mV 000 0001 510 mV 000 0010 520 mV ... ... 111 1111 1770 mV D3 D2 OV0[6:0] 1 D1 D0 36 1 LSB 0 VOUT = (xxx xxxx)2 x 10mV + 500 mV Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 Table 15. TPS62362 Register 0x00h Description REGISTER ADDRESS: 0x00h Read/Write BIT NAME D7 MODE0 DEFAULT MSB DESCRIPTION 0 Operation mode for SET0 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 x Reserved for future use D5 1 Output voltage for SET0 Default: (101110)2 = 1.23V D4 0 D5-D0 Output voltage D3 1 00 0000 770 mV 00 0001 780 mV 00 0010 790 mV ... ... 11 1111 1400 mV D2 OV0[5:0] 1 D1 1 D0 LSB 0 VOUT = (xx xxxx)2 x 10mV + 770 mV Table 16. TPS62363 Register 0x00h Description REGISTER ADDRESS: 0x00h Read/Write BIT NAME DEFAULT MSB D7 MODE0 0 DESCRIPTION Operation mode for SET0 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 1 D5 0 Output voltage for SET0 Default: (1000110)2 = 1.2V D4 0 D6-D0 Output voltage 0 000 0000 500 mV 000 0001 510 mV 000 0010 520 mV ... ... 111 1111 1770 mV D3 D2 OV0[6:0] 1 D1 D0 1 LSB 0 VOUT = (xxx xxxx)2 x 10mV + 500 mV Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 37 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com Register 0x01h Description: SET1 The register settings apply by choosing SET1 ( VSEL1 = LOW, VSEL0 = HIGH). Table 17. TPS62360 Register 0x01h Description REGISTER ADDRESS: 0x01h Read/Write BIT NAME D7 MODE1 DEFAULT MSB DESCRIPTION 0 Operation mode for SET1 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 x Reserved for future use D5 0 Output voltage for SET1 Default: (010111)2 = 1.0V D4 1 D5-D0 Output voltage D3 0 00 0000 770 mV 00 0001 780 mV 00 0010 790 mV ... ... 11 1111 1400 mV D2 OV1[5:0] 1 D1 1 D0 LSB 1 VOUT = (xx xxxx)2 x 10mV + 770 mV Table 18. TPS62361B Register 0x01h Description REGISTER ADDRESS: 0x01h Read/Write BIT NAME DEFAULT MSB D7 MODE1 0 DESCRIPTION Operation mode for SET1 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 1 D5 0 Output voltage for SET1 Default: (1011010)2 = 1.4V D4 1 D6-D0 Output voltage 1 000 0000 500 mV 000 0001 510 mV 000 0010 520 mV ... ... 111 1111 1770 mV D3 D2 OV1[6:0] 0 D1 D0 38 1 LSB 0 VOUT = (xxx xxxx)2 x 10mV + 500 mV Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 Table 19. TPS62362 Register 0x01h Description REGISTER ADDRESS: 0x01h Read/Write BIT NAME D7 MODE1 DEFAULT MSB DESCRIPTION 0 Operation mode for SET1 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 x Reserved for future use D5 0 Output voltage for SET1 Default: (010111)2 = 1.0V D4 1 D5-D0 Output voltage D3 0 00 0000 770 mV 00 0001 780 mV 00 0010 790 mV ... ... 11 1111 1400 mV D2 OV1[5:0] 1 D1 1 D0 LSB 1 VOUT = (xx xxxx)2 x 10mV + 770 mV Table 20. TPS62363 Register 0x01h Description REGISTER ADDRESS: 0x01h Read/Write BIT NAME DEFAULT MSB D7 MODE1 0 DESCRIPTION Operation mode for SET1 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 1 D5 0 Output voltage for SET1 Default: (1010011)2 = 1.36V D4 1 D6-D0 Output voltage 0 000 0000 500 mV 000 0001 510 mV 000 0010 520 mV ... ... 111 1111 1770 mV D3 D2 OV1[6:0] 0 D1 D0 1 LSB 1 VOUT = (xxx xxxx)2 x 10mV + 500 mV Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 39 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com Register 0x02h Description: SET2 The register settings apply by choosing SET2 ( VSEL1 = HIGH, VSEL0 = LOW). Table 21. TPS62360 Register 0x02h Description REGISTER ADDRESS: 0x02h Read/Write BIT NAME D7 MODE2 DEFAULT MSB DESCRIPTION 0 Operation mode for SET2 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 x Reserved for future use D5 1 Output voltage for SET2 Default: (111111)2 = 1.4V D4 1 D5-D0 Output voltage D3 1 00 0000 770 mV 00 0001 780 mV 00 0010 790 mV ... ... 11 1111 1400 mV D2 OV2[5:0] 1 D1 1 D0 LSB 1 VOUT = (xx xxxx)2 x 10mV + 770 mV Table 22. TPS62361B Register 0x02h Description REGISTER ADDRESS: 0x02h Read/Write BIT NAME DEFAULT MSB D7 MODE2 0 DESCRIPTION Operation mode for SET2 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 1 D5 0 Output voltage for SET2 Default: (1000010)2 = 1.16V D4 0 D6-D0 Output voltage 0 000 0000 500 mV 000 0001 510 mV 000 0010 520 mV ... ... 111 1111 1770 mV D3 D2 OV2[6:0] 0 D1 D0 40 1 LSB 0 VOUT = (xxx xxxx)2 x 10mV + 500 mV Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 Table 23. TPS62362 Register 0x02h Description REGISTER ADDRESS: 0x02h Read/Write BIT NAME D7 MODE2 DEFAULT MSB DESCRIPTION 0 Operation mode for SET2 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 x Reserved for future use D5 1 Output voltage for SET2 Default: (101011)2 = 1.2V D4 0 D5-D0 Output voltage D3 1 00 0000 770 mV 00 0001 780 mV 00 0010 790 mV ... ... 11 1111 1400 mV D2 OV2[5:0] 0 D1 1 D0 LSB 1 VOUT = (xx xxxx)2 x 10mV + 770 mV Table 24. TPS62363 Register 0x02h Description REGISTER ADDRESS: 0x02h Read/Write BIT NAME DEFAULT MSB D7 MODE2 0 DESCRIPTION Operation mode for SET2 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 1 D5 1 Output voltage for SET2 Default: (1100100)2 = 1.5V D4 0 D6-D0 Output voltage 0 000 0000 500 mV 000 0001 510 mV 000 0010 520 mV ... ... 111 1111 1770 mV D3 D2 OV2[6:0] 1 D1 D0 0 LSB 0 VOUT = (xxx xxxx)2 x 10mV + 500 mV Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 41 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com Register 0x03h Description: SET3 The register settings apply by choosing SET3 ( VSEL1 = HIGH, VSEL0 = HIGH). Table 25. TPS62360 Register 0x03h Description REGISTER ADDRESS: 0x03h Read/Write BIT NAME D7 MODE3 DEFAULT MSB DESCRIPTION 0 Operation mode for SET3 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 x Reserved for future use D5 1 Output voltage for SET3 Default: (100001)2 = 1.1V D4 0 D5-D0 Output voltage D3 0 00 0000 770 mV 00 0001 780 mV 00 0010 790 mV ... ... 11 1111 1400 mV D2 OV3[5:0] 0 D1 0 D0 LSB 1 VOUT = (xx xxxx)2 x 10mV + 770 mV Table 26. TPS62361B Register 0x03h Description REGISTER ADDRESS: 0x03h Read/Write BIT NAME DEFAULT MSB D7 MODE3 0 DESCRIPTION Operation mode for SET3 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 1 D5 0 Output voltage for SET3 Default: (1000010)2 = 1.16V D4 0 D6-D0 Output voltage 0 000 0000 500 mV 000 0001 510 mV 000 0010 520 mV ... ... 111 1111 1770 mV D3 D2 OV3[6:0] 0 D1 D0 42 1 LSB 0 VOUT = (xxx xxxx)2 x 10mV + 500 mV Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 Table 27. TPS62362 Register 0x03h Description REGISTER ADDRESS: 0x03h Read/Write BIT NAME D7 MODE3 DEFAULT MSB DESCRIPTION 0 Operation mode for SET3 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 x Reserved for future use D5 1 Output voltage for SET3 Default: (100001)2 = 1.1V D4 0 D5-D0 Output voltage D3 0 00 0000 770 mV 00 0001 780 mV 00 0010 790 mV ... ... 11 1111 1400 mV D2 OV3[5:0] 0 D1 0 D0 LSB 1 VOUT = (xx xxxx)2 x 10mV + 770 mV Table 28. TPS62363 Register 0x03h Description REGISTER ADDRESS: 0x03h Read/Write BIT NAME DEFAULT MSB D7 MODE3 0 DESCRIPTION Operation mode for SET3 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 0 D5 1 Output voltage for SET3 Default: (0110010)2 = 1.0V D4 1 D6-D0 Output voltage 0 000 0000 500 mV 000 0001 510 mV 000 0010 520 mV ... ... 111 1111 1770 mV D3 D2 OV3[6:0] 0 D1 D0 1 LSB 0 VOUT = (xxx xxxx)2 x 10mV + 500 mV Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 43 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com Register 0x04h Description: Ctrl Table 29. TPS6236x Register 0x04h Description REGISTER ADDRESS: 0x04h Read / Write BIT NAME DEFAULT MSB DESCRIPTION D7 PD_EN 1 EN internal pull down resistor 0 = disabled 1 = enabled D6 PD_VSEL0 1 VSEL0 internal pull down resistor 0 = disabled 1 = enabled D5 PD_VSEL1 1 VSEL1 internal pull down resistor 0 = disabled 1 = enabled D4 x Reserved for future use D3 x Reserved for future use D2 x Reserved for future use x Reserved for future use x Reserved for future use D1 D0 LSB Register 0x05h Description: Temp Table 30. TPS6236x Register 0x05h Description REGISTER ADDRESS: 0x05h Read/Write BIT NAME D7 DEFAULT MSB DESCRIPTION x Reserved for future use D6 x Reserved for future use D5 x Reserved for future use D4 x Reserved for future use D3 x Reserved for future use D2 DIS_TS 0 Disable temperature shutdown feature 0 = Temperature shutdown enabled 1 = Temperature shutdown disabled D1 TJEW 0 TJ early warning bit 0 = TJ < 120C (typ) 1 = TJ 120C (typ) D0 TJTS 0 TJ temperature shutdown bit 0 = die temperature within the valid range 1 = temperature shutdown was triggered LSB 44 Bit needs to be reset after it has been latched. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 Register 0x06h Description: RmpCtrl Table 31. TPS6236x Register 0x06h Description REGISTER ADDRESS: 0x06h Read/Write BIT NAME DEFAULT MSB D7 D6 DESCRIPTION Output voltage ramp timing 0 0 RMP[2:0] D7-D5 Slope 000 32 mV / s 001 16 mV / s 010 8 mV / s ... ... 110 0.5 mV / s 111 0.25 mV / s VOUT mV 1 = 32 t s 2(RMP[2-0] )2 D5 0 D4 x Reserved for future use D3 x Reserved for future use 0 Active output capacitor discharge at shutdown 0 = disabled 1 = enabled 0 Defines the ramp behavior if the device is in Power Save (PFM) mode 0 = output cap will be discharged by the load 1 = output voltage will be forced to follow the ramp down slope x Reserved for future use EN_DISC D2 D1 RAMP_PFM D0 LSB Register 0x07h Description: (Reserved) Table 32. TPS6236x Register 0x07h Description REGISTER ADDRESS: 0x07h BIT D7 NAME DEFAULT x Reserved for future use D6 x Reserved for future use D5 x Reserved for future use D4 x Reserved for future use D3 x Reserved for future use D2 x Reserved for future use D1 x Reserved for future use x Reserved for future use D0 MSB DESCRIPTION LSB Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 45 TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9B - MAY 2011 - REVISED MARCH 2012 www.ti.com Register 0x08h, 0x09h Description Chip_ID: Table 33. TPS6236x Register 0x08h and 0x09h Description REGISTER ADDRESS: 0x08h, 0x09 Read BIT D7 NAME DEFAULT MSB D6 0 D5 0 D4 0 D3 x D2 x D1 x D0 x LSB 46 DESCRIPTION 1 Vendor ID D3-D2 Part number ID 00 TPS62360 01 TPS62361B 10 TPS62362 11 TPS62363 D1-D0 Chip revision ID 00 Rev. 1 01 Rev. 2 10 Rev. 3 11 Rev. 4 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9B - MAY 2011 - REVISED MARCH 2012 PACKAGE SUMMARY CHIP SCALE PACKAGE (TOP VIEW) Code: TIYMLLLLS XXXXXXXXX E * TI -- Texas Instruments * YM -- Year Month date code * LLLL -- Lot trace code * S -- Assembly site code * XXXXXXXX -- Part number * TPS62360 = TPS62360 * TPB62361 = TPS62361B * TPS62362 = TPS62362 * TPS62363 = TPS62363 A1 D Figure 49. Package Marking and Dimensions CHIP SCALE PACKAGE DIMENSIONS The TPS6236x device is available in a 16-bump chip scale package (YZH, NanoFreeTM). The package dimensions are given as: * D = 2.076mm (+/- 0.03mm) * E = 2.076mm (+/- 0.03mm) Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363 47 PACKAGE OPTION ADDENDUM www.ti.com 28-Mar-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS62360YZHR ACTIVE DSBGA YZH 16 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TPS62360YZHT ACTIVE DSBGA YZH 16 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TPS62361BYZHR ACTIVE DSBGA YZH 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS62361BYZHT ACTIVE DSBGA YZH 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS62362YZHR ACTIVE DSBGA YZH 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS62362YZHT ACTIVE DSBGA YZH 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS62363YZHR ACTIVE DSBGA YZH 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS62363YZHT ACTIVE DSBGA YZH 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 28-Mar-2012 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS62360YZHR DSBGA YZH 16 3000 180.0 8.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.18 2.18 0.81 4.0 8.0 Q1 TPS62360YZHT DSBGA YZH 16 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 TPS62361BYZHR DSBGA YZH 16 3000 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 TPS62361BYZHT DSBGA YZH 16 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 TPS62362YZHR DSBGA YZH 16 3000 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 TPS62362YZHT DSBGA YZH 16 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 TPS62363YZHR DSBGA YZH 16 3000 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 TPS62363YZHT DSBGA YZH 16 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS62360YZHR DSBGA YZH 16 3000 210.0 185.0 35.0 TPS62360YZHT DSBGA YZH 16 250 210.0 185.0 35.0 TPS62361BYZHR DSBGA YZH 16 3000 210.0 185.0 35.0 TPS62361BYZHT DSBGA YZH 16 250 210.0 185.0 35.0 TPS62362YZHR DSBGA YZH 16 3000 210.0 185.0 35.0 TPS62362YZHT DSBGA YZH 16 250 210.0 185.0 35.0 TPS62363YZHR DSBGA YZH 16 3000 210.0 185.0 35.0 TPS62363YZHT DSBGA YZH 16 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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