TPS6236x
PGND
PGND
PGND
AGND
SW
SW
CPU
10µF
0.1µF
SENSE-
SENSE+
VIN
SCL
SDA
VSEL0
VSEL1
EN
AVIN
VDD
2.5V .. 5.5V
0.77V .. 1.4V (
0.5
TPS62360/62)
V .. 1.77V (TPS62361B)
1µH
10µF
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
3A Processor Supply with I
2
C Compatible Interface and Remote Sense
Check for Samples: TPS62360,TPS62361B,TPS62362,TPS62363
1FEATURES DESCRIPTION
The TPS6236x are a family of high-frequency
2• 3A Peak Output Current synchronous step down dc-dc converter optimized for
• Highest Efficiency: battery-powered portable applications for a small
– Low RDS,on Switch and Active Rectifier solution size. With an input voltage range of 2.5V to
5.5V, common battery technologies are supported.
– Power Save Mode for Light Loads The device provides up to 3A peak load current,
• I2C High Speed Compatible Interface operating at 2.5MHz typical switching frequency.
• Programmable Output Voltage for Digital The devices convert to an output voltage range of
Voltage Scaling 0.77V to 1.4V (TPS62360/62) and 0.5V to 1.77V
– TPS62360/62: 0.77V to 1.4V, 10mV Steps (TPS62361B/63), programmable via I2C interface in
– TPS62361B/63: 0.5V to 1.77V, 10mV Steps 10mV steps. Dedicated inputs allow fast voltage
transition to address processor performance
• Excellent DC/AC Output Voltage Regulation operating points.
– Differential Load Sensing The TPS6236x supports low-voltage DSPs and
– Precise DC Output Voltage Accuracy processor cores in smart-phones and handheld
– DCS-Control™ Architecture for Fast and computers including latest submicron processes.
Precise Transient Regulation Dedicated hardware input pins allow simple
transitions to performance operating points and
• Multiple Robust Operation/Protection retention modes of processors.
Features:
– Soft Start The devices focus on a high output voltage accuracy.
The differential sensing and the DCS-Control™
– Programmable Slew Rate at Voltage architecture achieve precise static and dynamic,
Transition transient output voltage regulation.
– Over Temperature Protection The TPS6236x devices offer high efficiency step
– Input Under Voltage Detection and Lockout down conversion. The area of highest efficiency is
• Available in 16-Bump, 2mm x 2mm NanoFree™ extended towards low output currents to increase the
Package efficiency while the processor is operating in retention
mode, as well as towards highest output currents
• Low External Device Count: 27.5 mm2Solution increasing the battery on-time.
Size The robust architecture and multiple safety features
APPLICATIONS allow perfect system integration.
• Dynamic Voltage Scale Compliant Processors The 2mm x 2mm package and the low number of
and DSPs, Memory required external components lead to a tiny solution
size of approximately 27.5 mm2.
• SmartReflex™ Compliant Power Supply
• Cell Phones, Smart Phones, Feature Phones
• Tablets, Netbooks, Clamshells
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2DCS-Control, NanoFree, SmartReflex are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER PACKAGE MARKING PACKAGE DEVICE SPECIFIC FEATURES(1)
Output Voltage Range Output Voltage Presets
TPS62360(2) See PACKAGE CSP-16 VOUT = 0.77V to 1.4V, 10mV Steps 1.40V, 1.00V, 1.40V, 1.10V
SUMMARY Section
TPS62361B(2) See PACKAGE CSP-16 VOUT = 0.5V to 1.77V, 10mV Steps 0.96V, 1.40V, 1.16V, 1.16V
SUMMARY Section
TPS62362(2) See PACKAGE CSP-16 VOUT = 0.77V to 1.4V, 10mV Steps 1.23V, 1.10V, 1.20V, 1.10V
SUMMARY Section
TPS62363(2) See PACKAGE CSP-16 VOUT = 0.5V to 1.77V, 10mV Steps 1.20V, 1.36V, 1.50V, 1.00V
SUMMARY Section
(1) Contact the factory to check availability of other output voltage or feature versions.
(2) The YZH package is available in tape and reel. Add R suffix (e.g. TPS62360YZHR) to order quantities of 3000 parts per reel, T suffix for
250 parts per reel (e.g. TPS62360YZHT). For the most current package and ordering information, see the Package Option Addendum at
the end of this document, or visit the device product folder on ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE UNIT
MIN MAX
VIN, AVIN, SW pin(2) –0.3 7 V
EN, VSEL0, VSEL1, SENSE+(2) –0.3 (VAVIN+0.3V) V
Voltage range SENSE–(2) –0.3 0.3 V
SCL, SDA(2) –0.3 (VDD+0.3V) V
VDD(2) –0.3 3.6 V
Continuous RMS VIN / SW 1275 mA
current(3)
Operating ambient temperature range, TA(4) –40 85 °C
Temperature Maximum operating junction temperature, TJ (MAX) –40 150 °C
Storage temperature range, Tstg –65 150 °C
Machine model 200 V
ESD rating(5) Charge device model 500 V
Human body model 2 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) In order to be consistent with the TI reliability requirement for the silicon chips (100K Power-On-Hours at 105°C junction temperature),
the current should not continuously exceed 1275mA in the VIN pin and 2550mA in the SW pins so as to prevent electromigration failure
in the solder. See THERMAL AND DEVICE LIFE TIME INFORMATION.
(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the
maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max) = TJ(max) – (θJA × PD(max))
(5) The human body model is a 100-pF capacitor discharged through a 1.5-kΩresistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
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Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
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SLVSAU9B –MAY 2011–REVISED MARCH 2012
THERMAL INFORMATION TPS6236x
THERMAL METRIC(1) YZH UNITS
16 PINS
θJA Junction-to-ambient thermal resistance(2) 94.8
θJCtop Junction-to-case (top) thermal resistance(3) 25
θJB Junction-to-board thermal resistance(4) 60 °C/W
ψJT Junction-to-top characterization parameter(5) 3.2
ψJB Junction-to-board characterization parameter(6) 57
θJCbot Junction-to-case (bottom) thermal resistance(7) n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range, VIN IOUT ≤2.5A 2.5 5.5 V
IOUT > 2.5A 3 5.5 V
IOUT Max. continuous output current(1) 2.5 A
TAOperating ambient temperature –40 85 °C
TJOperating junction temperature –40 125 °C
(1) Drawing continuously more than 2.5A might impact the device life time. SeeTHERMAL AND DEVICE LIFE TIME INFORMATION for
details.
ELECTRICAL CHARACTERISTICS
Unless otherwise noted the specification applies for VIN = 3.6V over an operating ambient temp. –40°C ≤TA≤85°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TA= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VIN Input voltage range at VIN, AVIN 2.5 5.5 V
VDD I2C and registers supply voltage range 1.15 3.6 V
ISD(AVIN) Shutdown current into AVIN EN = LOW, VDD = 0V 0.65 5 µA
TA= 25°C 0.5 1 µA
EN = LOW,
ISD(VIN) Shutdown current into VIN VDD = 0V TA= 85°C 1 3 µA
ISD(VDD) Shutdown current into VDD EN = LOW, I2C bus idle 0.01 µA
PFM mode 56 µA
EN = HIGH,
Operating quiescent current into (AVIN Forced PWM
IQIOUT = 0mA,
+ VIN) mode 180 µA
not switching (Test Mode)
Input voltage falling, EN = High 2.3 2.45 V
VUVLO Under voltage lock out at AVIN Input voltage rising, EN = Low 1.3 V
Under voltage lock out hysteresis at
VUVLO,HYST(AVIN) Input voltage rising 110 mV
AVIN
VDD,UVLO Under voltage lock out at VDD Input voltage falling 0.7 0.92 1.1 V
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
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TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted the specification applies for VIN = 3.6V over an operating ambient temp. –40°C ≤TA≤85°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TA= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Under voltage lock out hysteresis at
VUVLO,HYST(VDD) Input voltage rising 50 mV
VDD
LOGIC INTERFACE
High-level input voltage at EN, VSEL0,
VIH 1.2 V
VSEL1
Low-level input voltage at EN, VSEL0,
VIL 0.4 V
VSEL1
Signal transition time at EN, VSEL0,
trf rising and falling edge 30 mV/µs
VSEL1
VIH,I2C High-level input voltage at SCL, SDA 0.7x VDD V
VIL,I2C Low-level input voltage at SCL, SDA 0.3x VDD V
Logic input leakage current at EN, Internal pulldown resistors
ILKG 0.05 µA
VSEL0, VSEL1, SDA, SCL disabled
Pull down resistance at EN, VSEL0, Internal pulldown resistors
RPD 300 kΩ
VSEL1 enabled
Fast mode 400 kHz
I2C clock frequency High speed mode 3.4 MHz
POWER SWITCH
High side MOSFET switch VIN = 3.6V 25 44 75 mΩ
RDS(on) Low side MOSFET switch VIN = 3.6V 25 32 50 mΩ
High side MOSFET forward current limit VIN = 3.6V 3.0 3.6 4.3 A
Low side MOSFET forward current limit VIN = 3.6V 2.6 3 3.8 A
ILIMF Low side MOSFET negative current VIN = 3.6V, PWM mode 2.2 2.5 2.9 A
limit
fSW Nominal switching frequency PWM mode 2.5 MHz
TJEW Die temperature early warning 120 °C
TJSD Thermal shutdown 150 °C
TJSD,HYST Thermal shutdown hysteresis 20 °C
tON,min Minimum on time 120 ns
OUTPUT
TPS62360/62 0.77 1.4
10mV
VOUT Output voltage range V
increments TPS62361B/63 0.5 1.77
TPS62360/62: No load, Forced
VIN = 2.5V .. PWM,
5.5V VOUT = [0.77V, -0.5% +0.5%
VOUT = 0.77V .. 1.3V]
1.4V TJ= 85°C
Output voltage accuracy TPS62361B/63: No load, Forced
VIN = 2.7V .. PWM,
5.5V -1% ±0.5% +1%
TJ= -40 ..
VOUT = 0.5V .. 150°C
1.77V
Line regulation IOUT = 1A, forced PWM < 0.1 %/V
Load regulation VOUT = 1.2V, forced PWM < 0.05 %/A
Time from active EN to
VOUT = 1.4V,
tStart Start-up time 1 ms
COUT < 100µF, RMP[2:0] = 000,
IOUT = 0mA
Input resistance between Sense+,
RSense 2.2 MΩ
Sense–
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TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted the specification applies for VIN = 3.6V over an operating ambient temp. –40°C ≤TA≤85°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TA= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RMP[2:0] = 000 32
RMP[2:0] = 001 16
RMP[2:0] = 010 8
RMP[2:0] = 011 4
Ramp timer mV/µs
RMP[2:0] = 100 2
RMP[2:0] = 101 1
RMP[2:0] = 110 0.5
RMP[2:0] = 111 0.25
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
I2C INTERFACE TIMING REQUIREMENTS(1)(2)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Standard mode 100 kHz
Fast mode 400 kHz
High-speed mode (write operation), CB– 100 pF 3.4 MHz
max
High-speed mode (read operation), CB– 100 pF
f(SCL) SCL clock frequency 3.4 MHz
max
High-speed mode (write operation), CB– 400 pF 1.7 MHz
max
High-speed mode (read operation), CB– 400 pF 1.7 MHz
max
Standard mode 4.7 μs
Bus free time between a STOP and
tBUF START condition Fast mode 1.3 μs
Standard mode 4 μs
tHD, tSTA Hold time (repeated) START condition Fast mode 600 ns
High-speed mode 160 ns
Standard mode 4.7 μs
Fast mode 1.3 μs
tLOW Low period of the SCL clock High-speed mode, CB– 100 pF max 160 ns
High-speed mode, CB– 400 pF max 320 ns
Standard mode 4 μs
Fast mode 600 ns
tHIGH High period of the SCL clock High-speed mode, CB– 100 pF max 60 ns
High-speed mode, CB– 400 pF max 120 ns
Standard mode 4.7 μs
Setup time for a repeated START
tSU, tSTA Fast mode 600 ns
condition High-speed mode 160 ns
Standard mode 250 ns
tSU, tDAT Data setup time Fast mode 100 ns
High-speed mode 10 ns
Standard mode 0 3.45 μs
Fast mode 0 0.9 μs
tHD, tDAT Data hold time High-speed mode, CB– 100 pF max 0 70 ns
High-speed mode, CB– 400 pF max 0 150 ns
Standard mode 20 + 0.1 CB1000 ns
Fast mode 20 + 0.1 CB300 ns
tRCL Rise time of SCL signal High-speed mode, CB– 100 pF max 10 40 ns
High-speed mode, CB– 400 pF max 20 80 ns
Standard mode 20 + 0.1 CB1000 ns
Rise time of SCL signal after a repeated Fast mode 20 + 0.1 CB300 ns
tRCL1 START condition and after an High-speed mode, CB– 100 pF max 10 80 ns
acknowledge bit High-speed mode, CB– 400 pF max 20 160 ns
Standard mode 20 + 0.1 CB300 ns
Fast mode 20 + 0.1 CB300 ns
tFCL Fall time of SCL signal High-speed mode, CB– 100 pF max 10 40 ns
High-speed mode, CB– 400 pF max 20 80 ns
(1) S/M = standard mode; F/M = fast mode
(2) Specified by design. Not tested in production.
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Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
tf
HIGH
S
SDA
SCL
thd;STA thd;DAT
tr
tLOW
tsu;DAT
tf
thd;STA
thd;STA
tsu;STO
tr
Sr P S
tBUF
tfDA
tsu;STA
Sr P
Sr
= MCS Current Source Pull-Up
= R(P) Resistor Pull-Up
SDAH
SCLH
Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit.
See Note ASee Note A
thd;STA
trDA
thd;DAT
tfCL
tfCL1 tfCL
tsu;DAT
tLOW
tHIGH tLOW tHIGH
trCL1
tsu;STO
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
I2C INTERFACE TIMING REQUIREMENTS(1)(2) (continued)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Standard mode 20 + 0.1 CB1000 ns
Fast mode 20 + 0.1 CB300 ns
tRDA Rise time of SDA signal High-speed mode, CB– 100 pF max 10 80 ns
High-speed mode, CB– 400 pF max 20 160 ns
Standard mode 20 + 0.1 CB300 ns
Fast mode 20 + 0.1 CB300 ns
tFDA Fall time of SDA signal High-speed mode, CB– 100 pF max 10 80 ns
High-speed mode, CB– 400 pF max 20 160 ns
Standard mode 4 μs
tSU, tSTO Setup time for STOP condition Fast mode 600 ns
High-speed mode 160 ns
CBCapacitive load for SDA and SCL 400 pF
I2C TIMING DIAGRAMS
Figure 1. Serial Interface Timing for F/S Mode
Figure 2. Serial Interface Timing for H/S Mode
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
A1
B1
C1
D1
A2
B2
C2
D2
A3
B3
C3
D3
A4
B4
C4
D4
(TOP VIEW) (BOTTOM VIEW)
AVIN
EN
AGND
VDD
SCLSDA
VSEL0
VSEL1
SW SWSENSE+
SENSE-
VIN
PGND
PGND
PGND
A4
B4
C4
D4
A3
B3
C3
D3
A2
B2
C2
D2
A1
B1
C1
D1
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
DEVICE INFORMATION
PIN ASSIGNMENTS
PIN FUNCTIONS
PIN I/O DESCRIPTION
NAME NO.
AVIN A1 I Analog Supply Voltage Input.
AGND A2 – Analog Ground Connection.
EN B2 I Device Enable Logic Input. Logic HIGH enables the device, logic LOW disables the device and turns it into
shutdown. The pin must be terminated to either HIGH or LOW if the internal pull down resistor is deactivated.
VDD D1 I I2C Logic and Registers supply voltage. For resetting the internal registers, this connection must be pulled below
its UVLO level.
SCL D3 I/O I2C clock signal.
SDA D2 I/O I2C data signal.
VSEL0 C2 I Output Settings Selection Logic Inputs. Predefined register settings can be chosen for setting output voltage and
mode. The pins must be terminated to logic HIGH or LOW if the internal pull down resistors are deactivated.
VSEL1 A3 I
B3 –
SW Inductor connection
B4
SENSE+ B1 I Positive Output Voltage Remote Sense. Must be connected closest to the load supply node.
SENSE– C1 I Negative Output Voltage Remote Sense. Must be connected closest to the load ground node.
VIN A4 I Power Supply Voltage Input.
C3 –
PGND C4 Power Ground Connection.
D4
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Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
Gate
Driver
Control
Logic
High Side
Current Limit
Low Side
Current Limit
Low Side
N-MOS
High Side
P-MOS
Differential
Sense
I2C
Interface
Analog
Circuit
Supply
Thermal
Shutdown
Softstart
Under
Voltage
Shutdown
Bandgap
SENSE+
SENSE-
VIN
SW2
PGND3
AGND
AVIN
EN
SCL
SDA
VSEL0
VSEL1
VDD
direct control
&
compensation
REF
ramp
DCS-CONTROLTM
error
amplifier
comparator
RDIS-
CHARGE
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
FUNCTIONAL BLOCK DIAGRAM
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VOUT = 1.5V Figure 3
VOUT = 1.4V Figure 4
VOUT = 1.2V Figure 5
vs. Output Current (Power Save and Forced VOUT = 1.1V Figure 6
PWM Mode) VOUT = 1.0V Figure 7
ηEfficiency VOUT = 0.9V Figure 8
VOUT = 0.6V Figure 9
IOUT = 3000mA Figure 10
IOUT = 1000mA Figure 11
vs. Input Voltage (Power Save and Forced PWM
Mode) IOUT = 100mA Figure 12
IOUT = 10mA Figure 13
VOUT = 1.5V, TA=Figure 14
25°C
VOUT = 1.2V, TA=Figure 15
25°C
vs. Output Current (Power Save and Forced
VODC Output Voltage PWM Mode) VOUT = 0.9V, TA=Figure 16
25°C
VOUT = 0.6V, TA=Figure 17
25°C
VOUT = 0.5V, IOUT =Figure 18
0mA
Into No Load VOUT = 1.5V, IOUT =Figure 19
0mA
Startup VOUT = 0.5V, IOUT =Figure 20
1000mA
Into Load VOUT = 1.5V, IOUT =Figure 21
1000mA
IOUT = 10mA Figure 22
IOUT = 200mA Figure 23
Switching Wave forms IOUT = 1000mA Figure 24
IOUT = 3000mA Figure 25
IOUT = 0mA Figure 26
Output Voltage Ramp Control Transition 0.6V .. 1.5V IOUT = 1000mA Figure 27
IOUT = 5mA to 200mA Figure 28
IOUT = 5mA to 1000mA Figure 29
IOUT = 200mA to
Load Transient Response Figure 30
1000mA
IOUT = 1000mA to Figure 31
3000mA
Line Transient Response VIN = 3.2 to 4.2V Figure 32
ISD(VIN), Shutdown Current at AVIN and TA= [-40°C, 25°C,
vs. Input Voltage Figure 33
ISD(AVIN) VIN 125°C]
TA= [-40°C, 25°C,
125°C], Figure 34
auto PFM/PWM
IQQuiescent Current vs. Input Voltage TA= [-40°C, 25°C,
125°C] Figure 35
forced PWM
fSW Switching Frequency vs. Output Current VOUT = 1.2V Figure 36
ILIM Current Limit vs. Input Voltage Figure 37
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0
10
20
30
40
50
60
70
80
90
100
1m 10m 100m 1 3
Output Current (A)
Efficiency (%)
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
TPS62361B
VOUT = 1.5V
TA = 25°C
G001
0
10
20
30
40
50
60
70
80
90
100
1m 10m 100m 1 3
Output Current (A)
Efficiency (%)
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
TPS6236x
VOUT = 1.4V
TA = 25°C
G002
0
10
20
30
40
50
60
70
80
90
100
1m 10m 100m 1 3
Output Current (A)
Efficiency (%)
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
TPS6236x
VOUT = 1.2V
TA = 25°C
G003
0
10
20
30
40
50
60
70
80
90
100
1m 10m 100m 1 3
Output Current (A)
Efficiency (%)
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
TPS6236x
VOUT = 1.1V
TA = 25°C
G004
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
TYPICAL CHARACTERISTICS (continued)
EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT OUTPUT CURRENT
VOUT = 1.5V VOUT = 1.4V
Figure 3. Figure 4.
EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT OUTPUT CURRENT
VOUT = 1.2V VOUT = 1.1V
Figure 5. Figure 6.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
0
10
20
30
40
50
60
70
80
90
100
1m 10m 100m 1 3
Output Current (A)
Efficiency (%)
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
TPS6236x
VOUT = 1.0V
TA = 25°C
G005
0
10
20
30
40
50
60
70
80
90
100
1m 10m 100m 1 3
Output Current (A)
Efficiency (%)
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
TPS6236x
VOUT = 0.9V
TA = 25°C
G006
0
10
20
30
40
50
60
70
80
90
100
1m 10m 100m 1 3
Output Current (A)
Efficiency (%)
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
TPS62361B
VOUT = 0.6V
TA = 25°C
G007
0
10
20
30
40
50
60
70
80
90
100
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
Efficiency (%)
Auto PFM/PWM, VOUT = 1.0V
Auto PFM/PWM, VOUT = 1.1V
Auto PFM/PWM, VOUT = 1.4V
TPS6236x
IOUT = 3A
TA = 25°C
G008
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT OUTPUT CURRENT
VOUT = 1.0V VOUT = 0.9V
Figure 7. Figure 8.
EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
VOUT = 0.6V IOUT = 3A
Figure 9. Figure 10.
12 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
0
10
20
30
40
50
60
70
80
90
100
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
Efficiency (%)
Auto PFM/PWM, VOUT = 1.0V
Auto PFM/PWM, VOUT = 1.1V
Auto PFM/PWM, VOUT = 1.4V
TPS6236x
IOUT = 1A
TA = 25°C
G009
0
10
20
30
40
50
60
70
80
90
100
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
Efficiency (%)
Forced PWM, VOUT = 1.0V
Forced PWM, VOUT = 1.1V
Forced PWM, VOUT = 1.4V
Auto PFM/PWM, VOUT = 1.0V
Auto PFM/PWM, VOUT = 1.1V
Auto PFM/PWM, VOUT = 1.4V
TPS6236x
IOUT = 100mA
TA = 25°C
G010
0
10
20
30
40
50
60
70
80
90
100
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
Efficiency (%)
Forced PWM, VOUT = 1.0V
Forced PWM, VOUT = 1.1V
Forced PWM, VOUT = 1.4V
Auto PFM/PWM, VOUT = 1.0V
Auto PFM/PWM, VOUT = 1.1V
Auto PFM/PWM, VOUT = 1.4V
TPS6236x
IOUT = 10mA
TA = 25°C
G011
1.45
1.46
1.47
1.48
1.49
1.50
1.51
1.52
1.53
1.54
1.55
1m 10m 100m 1 3
Output Current (A)
DC Output Voltage (V)
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
TPS62361B
VOUT = 1.5V
TA = 25°C
G012
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
TYPICAL CHARACTERISTICS (continued)
EFFICIENCY EFFICIENCY
vs vs
INPUT VOLTAGE INPUT VOLTAGE
IOUT = 1A IOUT = 100mA
Figure 11. Figure 12.
EFFICIENCY DC OUTPUT VOLTAGE
vs vs
INPUT VOLTAGE OUTPUT CURRENT
IOUT = 10mA VOUT = 1.5V
Figure 13. Figure 14.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
1m 10m 100m 1 3
Output Current (A)
DC Output Voltage (V)
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
TPS6236x
VOUT = 1.2V
TA = 25°C
G013
0.85
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
1m 10m 100m 1 3
Output Current (A)
DC Output Voltage (V)
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
TPS6236x
VOUT = 0.9V
TA = 25°C
G014
Time Base - 20 s/Divμ
G017
TPS62361B
RAMP[2:0] = 000 (32mV/ s)μ
I = 0A
V = 3.6V
OUT
IN
V = 0.5V
OUT
V 200mV/Div
OUT
Inductor Current 200mA/Div
EN 2V/DIV
0.55
0.56
0.57
0.58
0.59
0.60
0.61
0.62
0.63
0.64
0.65
1m 10m 100m 1 3
Output Current (A)
DC Output Voltage (V)
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
TPS62361B
VOUT = 0.6V
TA = 25°C
G015
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
DC OUTPUT VOLTAGE DC OUTPUT VOLTAGE
vs vs
OUTPUT CURRENT OUTPUT CURRENT
VOUT = 1.2V VOUT = 0.9V
Figure 15. Figure 16.
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT STARTUP INTO NO LOAD
VOUT = 0.6V VOUT = 0.5V
Figure 17. Figure 18.
14 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
Time Base - 20 s/Divμ
G018
TPS62361B
RAMP[2:0] = 000 (32mV/ s)μ
I = 0A
V = 3.6V
OUT
IN
V = 1.5V
OUT
V 1V/Div
OUT
Inductor Current 500mA/Div
EN 2V/DIV
Time Base - 20 s/Divμ
G019
TPS62361B
RAMP[2:0] = 000 (32mV/ s)μ
I = 1A
V = 3.6V
OUT
IN
V = 0.5V
OUT
V 200mV/Div
OUT
Inductor Current 500mA/Div
EN 2V/DIV
Time Base - 20 s/Divμ
G020
V 1V/Div
OUT
Inductor Current 1A/Div
TPS62361B
RAMP[2:0] = 000 (32mV/ s)μ
I = 1A
V = 3.6V
LOAD
IN
V = 1.5V
OUT
EN 2V/DIV
Time Base - 4 s/Divμ
SW Pin 2V/Div
Inductor Current 200mA/Div
TPS62361B
I = 10mA
OUT
V = 3.6V
V = 1.2V
IN
OUT
G021
V 10mV/Div w/ 1.2V Offset
OUT
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
TYPICAL CHARACTERISTICS (continued)
STARTUP INTO NO LOAD STARTUP INTO LOAD
VOUT = 1.5V VOUT = 0.5V
Figure 19. Figure 20.
STARTUP INTO LOAD SWITCHING WAVE FORMS
VOUT = 1.5V IOUT = 10mA
Figure 21. Figure 22.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
Time Base - 250ns/Div
SW Pin 2V/Div
Inductor Current 200mA/Div w/ 200mA Offset
TPS62361B
I = 200mA
OUT
V = 3.6V
V = 1.2V
IN
OUT
G022
V 10mV/Div w/ 1.2V Offset
OUT
Time Base - 250ns/Div
SW Pin 2V/Div
Inductor Current 200mA/Div w/ 1A Offset
TPS62361B
I = 1A
OUT
V = 3.6V
V = 1.2V
IN
OUT
G023
V 10mV/Div w/ 1.2V Offset
OUT
Time Base - 250ns/Div
SW Pin 2V/Div
Inductor Current 200mA/Div w/ 3A Offset
TPS62361B
I = 3A
V = 3.6V
V = 1.2V
OUT
IN
OUT
G024
V 10mV/Div w/ 1.2V Offset
OUT
Time Base - 20 s/Divμ
G025
V 1V/Div w/ 0.6V Offset
OUT
Inductor Current
500mA/Div
TPS62361B
RAMP[2:0] = 000 (32mV/ s)μ
I
V
OUT
IN
OUT
= 0A
= 3.6V
V = 0.6V to 1.5V
V 2V/Div
SEL0
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
SWITCHING WAVE FORMS SWITCHING WAVE FORMS
IOUT = 200mA IOUT = 1A
Figure 23. Figure 24.
SWITCHING WAVE FORMS OUTPUT VOLTAGE RAMP CONTROL
IOUT = 3A NO LOAD
Figure 25. Figure 26.
16 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
Time Base - 20 s/Divμ
G026
V 1V/Div w/ 0.6V Offset
OUT
Inductor Current 500mA/Div
TPS62361B
RAMP[2:0] = 000 (32mV/ s)μ
I
V
OUT
IN
OUT
= 1A
= 3.6V
V = 0.6V to 1.5V V 2V/Div
SEL0
Time Base - 100 s/Divμ
G027
Inductor Current 200mA/Div
TPS62361B
C = 22 F
LOAD μV
V = 3.6V
= 1.2V
IN
OUT
V 20mV/Div w/ 1.2V Offset
OUT
I 100mA/Div
OUT
Time Base - 100 s/Divμ
G028
Inductor Current 500mA/Div
TPS62361B
C = 22 F
V
LOAD μ
V = 3.6V
= 1.2V
IN
OUT
V 50mV/Div w/ 1.2V Offset
OUT
I 1A/Div
OUT
Time Base - 100 s/Divμ
G029
Inductor Current 500mA/Div
TPS62361B
C = 22 F
V
LOAD μ
V = 3.6V
= 1.2V
IN
OUT
I 1A/Div
OUT
V 50mV/Div w/ 1.2V Offset
OUT
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE RAMP CONTROL LOAD TRANSIENT RESPONSE
IOUT = 1A IOUT RANGE: 5mA to 200mA
Figure 27. Figure 28.
LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
IOUT RANGE: 5mA to 1A IOUT RANGE: 200mA to 1A
Figure 29. Figure 30.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
Time Base - 100 s/Divμ
G030
Inductor Current 1A/Div
TPS62361B
C = 22 F
V
LOAD μ
V = 3.6V
= 1.2V
IN
OUT
I 2A/Div
OUT
V 50mV/Div w/ 1.2V Offset
OUT
Time Base - 20 s/Divμ
G031
V 20mV/Div w/ 1.2V Offset
OUT
V 1V/Div w/ 4.2V Offset
IN
VOUT = 1.2VTPS62361B
C = 100nF
IN
C = 22 F
I
LOAD μ
OUT = 300mA
Inductor Current 200mA/Div
0.001
0.01
0.1
1
10
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
Shutdown Current (µA)
AVIN, TA = −40°C
AVIN, TA = 25°C
AVIN, TA = 125°C
VIN, TA = −40°C
VIN, TA = 25°C
VIN, TA = 125°C
TPS6236x
EN = LOW
G034
10
30
50
70
90
110
130
150
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
Quiescent Current (µA)
TA = −40°C, Auto PFM/PWM
TA = 25°C, Auto PFM/PWM
TA = 125°C, Auto PFM/PWM
TPS6236x
MODE0 = 0 (Auto PFM/PWM)
EN = HIGH
G035
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
IOUT RANGE: 1A to 3A VIN RANGE: 4.2V to 3.2V
Figure 31. Figure 32.
SHUTDOWN CURRENT QUIESCENT CURRENT
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 33. Figure 34.
18 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
0
50
100
150
200
250
300
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
Quiescent Current (µA)
TA = −40°C, Forced PWM
TA = 25°C, Forced PWM
TA = 125°C, Forced PWM
TPS6236x
MODE0 = 1 (Forced PWM)
EN = HIGH
G036
0.1
1
10
100
1000
10000
0.1 1 10 100 1000 3000
Output Current (mA)
Switching Frequency (kHz)
Auto PFM/PWM
Forced PWM
TPS6236x
VOUT = 1.2V
VIN = 3.6V
G037
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
FET Current Limit (A)
High Side PMOS Current Limit
Low Side NMOS Current Limit
Negative NMOS Current Limit
TPS6236x
TA = 25°C
G038
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
TYPICAL CHARACTERISTICS (continued)
QUIESCENT CURRENT SWITCHING FREQUENCY
vs vs
INPUT VOLTAGE OUTPUT CURRENT
Figure 35. Figure 36.
FET CURRENT LIMIT
vs
INPUT VOLTAGE
Figure 37.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
TPS6236x
PGND
PGND
PGND
AGND
SW
SW
C4
C2
SENSE-
SENSE+
VIN
SCL
SDA
VSEL0
VSEL1
EN
AVIN
VDD
L
C1
VDD
VIN
C3
VOUT
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION
Table 1. List of Components
REFERENCE DESCRIPTION MANUFACTURER
TPS6236x 3A Processor Supply with I2C Texas Instruments
Compatible Interface and Remote
Sense
L 1 μH, 4 mm x 4 mm x 2.1 mm Coilcraft (XFL4020-102ME1.0)
C2, C410 μF, Ceramic, 6.3V, X5R Murata (GRM188R60J106ME84D)
C1, C30.1 μF, Ceramic, 10V, X5R Standard
20 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
DETAILED DESCRIPTION
The TPS6236x are a family of high-frequency synchronous step down dc-dc converter optimized for battery-
powered portable applications. With an input voltage range of 2.5V to 5.5V, common battery technologies are
supported.
The device provides up to 3A peak load current, operating at 2.5MHz typical switching frequency.
The devices convert to an output voltage range of 0.77V to 1.4V (TPS62360 / TPS62362) and 0.5V to 1.77V
(TPS62361B / TPS62363), programmable via I2C interface in 10mV steps.
The TPS6236x supports low-voltage DSPs and processor cores in smart-phones and handheld computers,
including latest submicron processes and their retention modes and addresses digital voltage scaling
technologies such as SmartReflex™.
Output Voltages and Modes can be fully programmed via I2C. To address different performance operating points
and/or startup conditions, the device offers four output voltage / mode presets which can be chosen via
dedicated hardware input pins allowing simple and zero latency output voltage transition.
The devices focus on a high output voltage accuracy. The fully differential sensing and the DCS-Control™
architecture achieve precise static and dynamic, transient output voltage regulation. This accounts for stable
processor operation. Output voltage security margins can be kept small, resulting in an increased overall system
efficiency.
The TPS6236x devices offer high efficiency step down conversion. The area of highest efficiency is extended
towards low output currents to increase the efficiency while the processor is operating in retention mode, as well
as towards highest output currents reducing the power loss. This addresses the power profile of processors. High
efficiency conversion is required for low output currents to support the retention modes of processors, resulting in
an increased battery on-time. To address the processor maximum performance operating points with highest
output currents, high efficiency conversion is enabled as well to save the battery on-time and reduce input power.
The robust architecture and multiple safety features allow perfect system integration.
The 2mm x 2mm package and the low number of required external components lead to a tiny solution size of
approximately 27.5 mm2.
OPERATION
The TPS6236x synchronous switched mode power converters are based on DCS-Control™, an advanced
regulation topology, that combines the advantages of hysteretic, voltage mode and current mode control
architectures.
While a comparator stage provides excellent load transient response, an additional voltage loop ensures high DC
accuracy as well. The TPS6236x compensates ground shifts at the load by the differentially sensing the output
voltage at the point of load.
The internal ramp generator adds information about the load current and fast output voltage changes. The
internally compensated regulation network achieves fast and stable operation with low ESR capacitors.
The DCS-Control™ topology supports PWM (Pulse Width Modulation) mode for medium and heavy load
conditions and a Power Save Mode at light loads. During PWM it operates at its nominal switching frequency in
continuous conduction mode. This frequency is typically about 2.5MHz with a controlled frequency variation
depending on the input voltage. As the load current decreases, the converter enters Power Save Mode to sustain
high efficiency down to light loads. The transition from PWM to Power Save Mode is seamless and avoids output
voltage transients.
An internal current limit supports nominal output currents of up to 3A. The TPS6236x family offers both excellent
DC voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing
interference with RF circuits.
ENABLING AND DISABLING THE DEVICE
The device is enabled by setting the EN input to a logic high. Accordingly, a logic low disables the device. If the
device is enabled, the internal power stage will start switching and regulate the output voltage to the programmed
threshold. The EN input must be terminated unless the internal pull down resistor is activated.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
The I2C interface is operable when VDD and AVIN are present, regardless of the state of the EN pin.
If the device is disabled by pulling the EN to a logic low, the output capacitor can actively be discharged. Per
default, this feature is disabled. Programming the EN_DISC bit to a logic high will discharge the output capacitor
via a typ. 300Ωpath on the SENSE+ pin.
SOFT START
The device incorporates an internal soft start circuitry that controls the ramp up of the output voltage after
enabling the device. This circuitry eliminates inrush current to avoid excessive voltage drops of primary cells and
rechargeable batteries with high internal impedance.
During soft start, the output voltage is monotonically ramped up to the minimum programmable output voltage.
After reaching this threshold, the output voltage is further increased following the slope as programmed in the
ramp rate settings (see RAMP RATE CONTROLLING) until reaching the programmed output voltage. Once the
nominal voltage is reached, regular operation as described above will continue.
The device is able to start into a pre biased output capacitor as well.
PROGRAMMING THE OUTPUT
The TPS6236x devices offer four similar registers to program the output. Two dedicated hardware input pins,
VSEL0 and VSEL1, are implemented for choosing the active register. The logic state of VSEL0 and VSEL1
select the register whose settings are present at the output. The VSEL0 and VSEL1 pins must be terminated
unless the internal pull-down resistors are activated.
The registers have a certain initial default value (see Table 2) and can be readjusted via I2C during operation.
This allows a simple transition between several output options by triggering the dedicated input pins. At the same
time since the presets can be readjusted during operation, this offers highest flexibility.
Table 2. Output Presets
DEFAULT OPERATION
INPUT PINS DEFAULT OUTPUT VOLTAGE [V]
MODE
PRESET I2C REGISTER TPS62360, TPS62361B,
VSEL1 VSEL0 TPS62360 TPS62361B TPS62362 TPS62363
TPS62362, TPS62363
0 0 SET0 0x00h – see Table 13, Power Save Mode 1.40 0.96 1.23 1.20
Table 14 and Table 15
0 1 SET1 0x01h – see Table 17, Power Save Mode 1.00 1.40 1.00 1.36
Table 18 and Table 19
1 0 SET2 0x02h – see Table 21, Power Save Mode 1.40 1.16 1.20 1.50
Table 22 and Table 23
1 1 SET3 0x03h – see Table 25, Power Save Mode 1.10 1.16 1.10 1.00
Table 26 and Table 27
Via the I2C interface and/or the four preset options, the following output parameters can be changed:
• Output voltage from 0.77V to 1.4V (TPS62360/62) and 0.5V to 1.77V (TPS62361B/63) with 10 mV granularity
• Mode of operation: Power Save Mode or forced PWM mode
The slope for transition between different output voltages (Ramp Rate) can be changed via I2C as well. The
slope applies for all presets globally. See RAMP RATE CONTROLLING for further details.
Since the output parameters can be changed by dedicated pins for selecting presets and by I2C, the following
use scenarios are feasible:
• Control the device via dedicated pins only, after programming the presets, to choose and change within the
programmed settings
• Program via I2C only. The dedicated input pins have fixed connections. Changes are conducted by changing
the preset values of the active register.
• Dedicated input pins and I2C mixed operation. The non active presets might be changed. The dedicated input
pins are used for the transition to the new output condition. Changes within an active preset via I2C are
feasible as well.
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Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
V -
IN VOUT
2
VOUT
VIN
1
( f L )
I =
OUT,TRANS
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
DYNAMIC VOLTAGE SCALING
The output voltage can be adjusted dynamically. Each of the four output registers can be programmed
individually by setting OV[5:0] (TPS62360/62) and OV[6:0] (TPS62361B/63) respectively in the SET0, SET1,
SET2 and SET3 registers.
Table 3. TPS62360, TPS62362 Output Voltage Settings
for Registers SET0, SET1, SET2 and SET3
REGISTERS: SET0, SET1, SET2, SET3
OV[D5:D0] OUTPUT VOLTAGE
00 0000 770 mV
00 0001 780 mV
00 0010 790 mV
00 0011 800 mV
… …
11 1101 1380 mV
11 1110 1390 mV
11 1111 1400 mV
Table 4. TPS62361B, TPS62363 Output Voltage
Settings for Registers SET0, SET1, SET2 and SET3
REGISTERS: SET0, SET1, SET2, SET3
OV[D6:D0] OUTPUT VOLTAGE
000 0000 500 mV
000 0001 510 mV
000 0010 520 mV
000 0011 530 mV
… …
111 1101 1750 mV
111 1110 1760 mV
111 1111 1770 mV
If the output voltage is changed at the active register (selected by VSEL0 and VSEL1), these changes will apply
after the I2C command is sent.
POWER SAVE MODE AND FORCED PWM MODE
The TPS6236x devices feature a Power Save Mode to gain efficiency at light output current conditions. The
device automatically transitions in both directions between pulse width modulation (PWM) operation at high load
and pulse frequency modulation (PFM) operation at light load current. This maintains high efficiency at both light
and heavy load currents. In PFM Mode, the device generates single switching pulses when required to maintain
the programmed output voltage.
The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in
both directions.
The output current, at which the device transitions from PWM to PFM operation can be estimated as follows:
(1)
With:
VIN = Input voltage
VOUT = Output Voltage
ƒ = Switching frequency, typ. 2.5 MHz
L = Inductor value
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
( )
´ -
ON
L,PFM,peak IN OUT
t
I = V V
L
350 20ns ns´ +
OUT
ON
IN
V
t = V
( )2
OUT
RMP[2-0]
ΔV mV 1
= 32
Δt μs 2
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
The TPS6236x is optimized for low output voltage ripple. Therefore, the peak inductor current in PFM mode is
kept small and can be calculated as follows:
(2)
And:
(3)
With:
VIN = Input Voltage
VOUT = Output Voltage
tON = On-time of the High Side FET, from Equation 3
L = Inductor value
The TPS6236x offers a forced PWM mode as well. In this mode, the converter is forced in PWM mode even at
light load currents. This comes with the benefit that the converter is operating with lower output voltage ripple.
Compared to the PFM mode, the efficiency is lower during light load currents.
According to the output voltage, the Power Save Mode / forced PWM Mode can be programmed individually for
each preset via I2C by setting the MODE0 – MODE3 bit D7. Table 2 shows the factory presets after enabling the
I2C. For additional flexibility, the Power Save Mode can be changed at a preset that is currently active.
RAMP RATE CONTROLLING
If the output voltage is changed, the TPS6236x can actively control the voltage ramp rate during the transition.
An internal oscillator is embedded for high timing precision.
Figure 38 and Figure 39 show the operation principle. If the output voltage changes, the device will change the
output voltage through discrete steps with a programmable ramp rate resulting in a corresponding transition time.
The ramp up/down slope can be programmed via I2C interface (see Table 5).
Table 5. Ramp Rates
RAMP RATE
RMP [2:0] [mV/µs] [µs/10mV]
000 32 0.3125
001 16 0.625
010 8 1.25
011 4 2.5
100 2 5
101 1 10
110 0.5 20
111 0.25 40
For a transition of the output voltage from VOUT,A to VOUT,B and vice versa, the resulting ramp up/down slope can
be calculated as
(4)
If the device is operating in forced PWM Mode, the device actively controls both the ramp up and down slope.
If Power Save Mode is activated, the ramp up phase follows the programmed slope.
To force the output voltage to follow the ramp down slope in Power Save Mode, the RAMP_PFM bit needs to be
set. This will force the converter to follow the ramp down slope during PFM operation as well.
24 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
Output
Voltage
time
VOUT,A
VOUT,B
Δt
ΔVOUT 10 mV
10 mV/Ramp Rate
(TPS62360 / TPS62362)
Output
Voltage
time
VOUT,A
VOUT,B
Δt
ΔVOUT 20 mV
20 mV/Ramp Rate
(TPS62361B / TPS62363)
Output
Voltage
time
VOUT,A
VOUT,B
Δt
ΔVOUT 10 mV
10 mV/Ramp Rate
Output
Voltage
time
VOUT,A
VOUT,B
Δt
ΔVOUT 20 mV
20 mV/Ramp Rate
(TPS62360 / TPS62362) (TPS62361B / TPS62363)
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
If the RAMP_PFM bit is not set in Power Save Mode, the slope can be less at low output currents since the
device does not actively source energy back from the output capacitor to the input or it might be sharper at high
output currents since the output capacitor is discharged quickly.
Figure 38. Ramp Up
Figure 39. Ramp Down
The TPS62360 and TPS62362 ramp the output voltage taking 10mV steps, while the TPS62361B and
TPS62363 ramp taking 20mV steps with a final 10mV step if required. The resulting slope remains equal for both
devices.
While the output voltage setpoint is changed in a digital stair step fashion, the connected output capacitor flattens
the steps to create a linear change in the output voltage.
SAFE OPERATION AND PROTECTION FEATURES
Inductor Current Limit
The inductor current limiting prevents the device from drawing high inductor current and excessive current from
the battery. Excessive current might occur with a shorted/saturated inductor or a heavy load/shorted output
circuit condition.
The incorporated inductor peak current limit measures the current while the high side power MOSFET is turned
on. Once the current limit is tripped, the high side MOSFET is turned off and the low side MOSFET is turned on
to ramp down the inductor current. This prevents high currents to be drawn from the battery.
Once the low side MOSFET is on, the low side forward current limit keeps the low side MOSFET on until the
current through it decreases below the low side forward current limit threshold.
The negative current limit acts if current is flowing back to the battery from the output. It works differently in PWM
and PFM operation. In PWM operation, the negative current limit prevents excessive current from flowing back
through the inductor to the battery, preventing abnormal voltage conditions at the switching node. In PFM
operation, a zero current limits any power flow back to the battery by preventing negative inductor current.
Die Temperature Monitoring and Over Temperature Protection
The TPS6236x offers two stages of die temperature monitoring and protection.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
Device Shutdown
Register Reset,
I C I/F Disabled
2
AVIN
VIN
VDD VDD
Under Voltage?
AVIN
Under Voltage?
external low
ohmic connection
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
The Early Warning Monitoring Feature monitors the device temperature and provides the host an indication that
the die temperature is in the higher range. If the device's junction temperature, TJ, exceeds 120°C typical, the
TJEW bit is set high. To avoid the thermal shutdown being triggered, the current drawn from the TPS6236x
should be reduced at this early stage.
The Over Temperature Protection feature disables the device if the temperature increases due to heavy load
and/or high ambient temperature. It monitors the device die temperature and, if required, triggers the device into
shutdown until the die temperature falls sufficiently.
If the junction temperature, TJ, exceeds 150°C typical, the device goes into thermal shutdown. In this mode, the
power stage is turned off. During thermal shutdown, the I2C interface remains operable. All register values are
kept.
For the thermal shutdown, a hysteresis of 20°C typical is implemented allowing the device to cool after the
shutdown is triggered. Once the junction temperature TJcools down to 130°C typical, the device resumes
operation.
If a thermal shutdown has occurred, the TJTS bit is latched and remains a logic high as long as VDD and AVIN
are present and until the bit is reset by the host.
Input Under Voltage Protection
The input under voltage protection is implemented in order to prevent operation of the device for low input
voltage conditions. If the device is enabled, it prevents the device from switching if AVIN falls below the under
voltage lockout threshold. If the AVIN under voltage protection threshold is tripped, the device will go into under
voltage shutdown instantaneously, turning the power stage off and resetting all internal registers. The input under
voltage protection is also implemented on the VDD input. If the VDD under voltage protection threshold is
tripped, the device will reset all internal registers.
A under voltage lockout hysteresis of VUVLO,HYST(AVIN) at AVIN and VUVLO,HYST(VDD) at VDD is implemented.
The I2C compatible interface remains fully functional if AVIN and VDD are present. If the under voltage lockout of
AVIN or VDD is triggered during operation, all internal registers are reset to their default values. Figure 40 shows
the UVLO block diagram.
Figure 40. UVLO State Chart
By connecting VIN and AVIN to the same potential, VIN is included in the under voltage monitoring. If a low pass
input filter is applied at AVIN (not mandatory for the TPS6236x), the delay and shift in the voltage level can be
calculated by taking the typical quiescent current IQat AVIN. As an example, for IQand 10Ωseries resistance,
this results in a minimal static shift of approx. 560µV.
VIN and AVIN must be connected to the same source for proper device operation.
26 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
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START condition STOP condition
SDA
SCL SP
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
APPLICATION INFORMATION
I2C INTERFACE
Serial Interface Description
I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus
through open drain I/O pins, SDA and SCL. A master device, usually a micro controller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The TPS6236x device works as a slave and supports the following data transfer modes, as defined in the I2C-
Bus Specification:
• Standard mode (100 kbps)
• Fast mode (400 kbps)
• Fast mode plus (1Mbps)
• High-speed mode (3.4 Mbps)
The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new
values depending on the instantaneous application requirements. Register contents remain intact as long as
VDD and AVIN are present in the specified range. Tripping the under voltage lockout of AVIN or VDD deletes the
registers and establishes the default values once the supply is present again.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as
F/S-mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as
HS-mode. The TPS6236x device supports 7-bit addressing. 10-bit addressing and general call addressing are
not supported.
Table 6 shows the TPS6236x devices and their assigned I2C addresses.
Table 6. I2C Address
I2C ADDRESS
DEVICE OPTION HEXADECIMAL BINARY CODED
CODED
TPS62360 (0x60)HEX (110 0000)2
TPS62361B (0x60)HEX (110 0000)2
TPS62362 (0x60)HEX (110 0000)2
TPS62363 (0x60)HEX (110 0000)2
F/S-Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 41. All I2C-compatible devices should
recognize a start condition.
Figure 41. START and STOP Conditions
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
Data line stable;
data valid
Change of
data allowed
SDA
SCL
START condition Clock Pulse for
Acknowledgment
Data Output
by Transmitter
S
SCL 1 2 8 9
Not Acknowledge
Acknowledge
Data Output
by Receiver
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 42). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 43) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
Figure 42. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high (see Figure 41). This releases the bus and stops the communication link with the
addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
Figure 43. Acknowledge on the I2C Bus
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Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
START or
repeated START
Condition
Clock Line Held Low While
Interrupts are Serviced
S
Sr
or
SCL 12
ACK
79
812-8 9
ACK
Recognize START or
repeated START
Condition
Acknowledgment
Signal From Slave
SDA
Generate ACKNOWLEDGE
Signal
repeated START
or STOP
Condition
Sr
P
or
P
Sr
Recognize
repeated START
or STOP
Condition
Address
S Register Address A Data A P
8
8111
From TPS6236x to Master
From Master to TPS6236x
A
S
Sr
P
=
=
=
=
Acknowledge
START condition
REPEATED START condition
STOP condition
Slave Address R/W A
711
1
Slave Address
“0” Write
“0” Write “1” Read
S Slave Address R/W A Register Address A Sr Slave Address R/W A Data A P
8
7
87 11111111
From TPS6236x to Master
From Master to TPS6236x
A
S
Sr
P
=
=
=
=
Acknowledge
START condition
REPEATED START condition
STOP condition
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
Figure 44. Bus Protocol
HS-Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of
the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be
used to secure the bus in HS-mode.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
I2C UPDATE SEQUENCE
The TPS6236x requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, the TPS6236x device acknowledges by pulling the SDA line low
during the high period of a single clock pulse. A valid I2C address selects the TPS6236x. The TPS6236x
performs an update on the falling edge of the acknowledge signal that follows the LSB byte.
Figure 45. Write Data Transfer Format in F/S-Mode
Figure 46. Read Data Transfer Format in F/S-Mode
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
S HS-Master Code A Sr Register Address A Data A/A P
8
88 11111
From TPS6236x to Master
From Master to TPS6236x
A
A
S
Sr
P
=
=
=
=
=
Acknowledge
Acknowledge
START condition
REPEATED START condition
STOP condition
Slave Address R/W A
711
1
F/S Mode H/S Mode F/S Mode
Sr Slave Address
Sr Slave Address
H/S Mode continues
Data Transferred
(n x Bytes + Acknowledge)
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
Figure 47. Data Transfer Format in H/S-Mode
Slave Address Byte
MSB LSB
X X X X X X A1 A0
The slave address byte is the first byte received following the START condition from the master device.
Register Address Byte
MSB LSB
0 0 0 0 0 D2 D1 D0
Following the successful acknowledgment of the slave address, the bus master will send a byte to the
TPS6236x, which will contain the address of the register to be accessed.
I2C REGISTER RESET
The I2C registers can be reset by pulling VDD to GND. Refer to the Input Under Voltage Protection section for
details.
PULL DOWN RESISTORS
The EN, VSEL0 and VSEL1 inputs feature internal pull down resistors to discharge the potential if one of the pins
is not connected or is triggered by a high impedance source.
To achieve lowest possible quiescent current, the pull down resistors can be disabled individually at EN, VSEL0
and VSEL1 by I2C programming the registers PD_EN, PD_VSEL0 and PD_VSEL1.
By default, the pull down resistors are enabled.
INPUT CAPACITOR SELECTION
The input capacitor is required to buffer the pulsing current drawn by the device at VIN and reducing the input
voltage ripple. The pulsing current is originated by the operation principles of a step down converter.
Low ESR input capacitors are required for best input voltage filtering and minimal interference with other system
components. For best performance, ceramic capacitors with a low ESR at the switching frequency are
recommended. X7R or X5R type capacitors should be used.
A ceramic input capacitor in the nominal range of CIN = 4.7µF to 22µF should be a good choice for most
application scenarios. In general, there is no upper limit for increasing the input capacitor.
For typical operation, a 10µF X5R type capacitor is recommended. Table 7 shows a list of recommended
capacitors.
30 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
OUT
IN
L OUT
V
1V
ΔI = V L
-
´´ ¦
L
L,MAX OUT,MAX
ΔI
I = I + 2
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
Table 7. List of Recommended Capacitors
CAPACITANCE DIMENSIONS
TYPE MANUFACTURER
[µF] L x W x H [mm3]
10 GRM188R60J106M 0603: 1.6 x 0.8 x 0.8 Murata
10 CL10A106MQ8NRNC 0603: 1.6 x 0.8 x 0.8 Samsung
22 GRM188R60G226M 0603: 1.6 x 0.8 x 0.8 Murata
22 CL10A106MQ8NRNC 0603: 1.6 x 0.8 x 0.8 Samsung
DECOUPLING CAPACITORS AT AVIN, VDD
Noise impacts can be reduced by buffering AVIN and VDD with a decoupling capacitor. It is recommended to
buffer AVIN and VDD with a X5R or X7R ceramic capacitor of at least 0.1µF connected between AVIN, AGND
and VDD, AGND respectively. The capacitor closest to the pin should be kept small (< 0.22µF) in order to keep a
low impedance at high frequencies. In general, there is no upper limit for the total capacitance.
Adding a low pass input filter at AVIN (e.g. by adding a resistor in series) is not mandatory for the TPS6236x to
filter out noise.
INDUCTOR SELECTION
The choice of the inductor type and value has an impact on the inductor ripple current, the transition point of
PFM to PWM operation, the output voltage ripple and accuracy. The subsections below support for choosing the
proper inductor.
Inductance Value
The TPS6236x is designed for best operation with a nominal inductance value of 1µH.
Choosing a smaller value than 1µH improves the load transient behavior, whereas choosing a higher value
reduces the ripple current resulting in a smaller output voltage ripple and better DC output regulation. The
inductor current ripple can be calculated as:
(5)
With:
VIN = Input Voltage
VOUT = Output Voltage
ƒ = Switching frequency, typ. 2.5 MHz
L = Inductor value
Inductor Saturation Current
The inductor needs to be selected for its current rating. To pick the proper saturation current rating, the maximum
inductor current can be calculated as:
(6)
With:
ΔIL= Inductor ripple current (see Equation 5)
IOUT,MAX = Maximum output current
Since the inductance can be decreased by saturation effects and temperature impact, the inductor needs to be
chosen to have an effective inductance of at least 0.6µH under temperature and saturation effects.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 31
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TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
Table 8. List of Recommended Inductors
SATURATION
CURRENT RATING
INDUCTANCE DIMENSIONS DC RESISTANCE
(30% inductance TYPE MANUFACTURER
[µH] L x W x H [mm3] [mΩtyp]
drop, typ)
[A]
1.0 3.4 3.2 x 2.5 x 1.2 51 PST032251B-1R0MS-11 Cyntec
1.0 3.9 3.2 x 2.5 x 1.0 48 DFE322510C1276AS-H- Toko
1R0N(1)
1.0 4.6 3.2 x 2.5 x 1.2 37 DFE322512C1277AS-H- Toko
1R0N(1)
1.0 3.8 2.5 x 2.0 x 1.2 45 DFE252012C1239AS-H- Toko
1R0N=P2
1.0 5.4 4 x 4 x 2.1 10 XFL4020-102ME1.0 Coilcraft
1.0 5.4 3.2 x 3 x 1.2 57 SPM3012T-1R0M TDK
(1) Release planned for Q4/2011. Contact manufacturer for details.
OUTPUT CAPACITOR SELECTION
The unique hysteretic control scheme allows the use of tiny ceramic capacitors. For best performance, ceramic
capacitors with low ESR values are recommended to achieve high conversion efficiency and low output voltage
ripple. For stable operation, X7R or X5R type capacitors are recommended.
The TPS6236x is designed to operate with an output capacitor of 10µF to 22µF, placed at the device's output. In
addition a 0.1µF capacitor can be added to the output to reduce the high frequency content created by a very
sudden load change.
At light loads, if the device is operating in PFM Mode, choosing a higher value will minimize the voltage ripple
resulting in a better DC output accuracy.
Buffering the processor input by an additional ceramic capacitor in the range of 10µF to 22µF improves the
voltage quality at the processor input and the dynamic load step behavior. This is especially true if the trace
between the TPS6236x and the microprocessor is longer than the smallest possible. This additional capacitor
needs to be taken into account for the recommended capacitance value. For stability, the sum of the VOUT
capacitors should not exceed 75µF effective capacitance.
Table 7 shows a list of tested capacitors. The TPS6236x is not designed for use with polymer, tantalum, or
electrolytic output capacitors.
OUTPUT FILTER DESIGN
The inductor and the output capacitor build the output filter. The load might be buffered with an input capacitor
CLOAD, which needs to be factored in. Based on the output capacitor and inductance recommendation sections
and factoring in CLOAD, these components should be in the range:
• COUT + CLOAD= 10µF to 75µF
• L = 1 µH
For further performance or specific demands, these values might be tweaked. In any case, the loop stability
should be checked since the control loop stability might be affected.
THERMAL AND DEVICE LIFE TIME INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Thermal performance can be enhanced by proper PCB layout. Wide power traces come with the ability to sink
dissipated heat. This can be improved further on multi layer PCB designs with vias to different layers.
Proper PCB layout with focus on thermal performance results in a reduced junction-to-ambient thermal
resistance θJA and thereby reduces the device junction temperature, TJ.
32 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
AVIN
VOUT
VDD
VIN
AGND
PGND
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
The TI reliability requirement for the silicon chip's life time (100K Power-On-Hours at TJ= 105°C) is affected by
the junction temperature and the continuously drawn current at the VIN pin and the SW pins. In order to be
consistent with the TI reliability requirement for the silicon chips (100000 Power-On-Hours at TJ= 105°C), the
VIN pin current should not continuously exceed 1275mA and the SW pins current should not continuously
exceed 2550mA so as to prevent electromigration failure in the solder bump. Drawing 1150mA at VIN would, as
an example, be the case for typically IOUT = 2350mA, VOUT = 1.5V and VIN = 3.6V.
Exceeding the VIN pin / SW pins current rating might affect the device reliability. As an example, drawing current
peaks IOUT = 3000mA with up to 10% of the application time over a base continuous output current IOUT =
2000mA might reduce the Power-on-Hours to 90000 hours for conditions such as VIN = 2.7V, VOUT = 1.5V, TJ=
105°C. In this example, exceeding TJ= 105°C in combination with a higher peak output current duty cycle clearly
further affects the device life time.
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Note (SZZA017), and IC Package Thermal Metrics Application Note (SPRA953).
PCB LAYOUT CONSIDERATIONS
The PCB layout is an important step to maintain the high performance of the TPS6236x. Both the high current
and the fast switching nodes demands full attention to the PCB layout.
The input / output capacitors and the inductor should be placed as close as possible to the IC. This keeps the
traces short. Routing these traces direct and wide results in low trace resistance and low parasitic inductance. A
common power GND should be used. The low side of the input and output capacitors must be connected to the
power GND, as well as the PGND node. AGND and PGND should be connected close to the IC but at a single
place.
The sense traces connected to SENSE+ and SENSE- are signal traces. Special care should be taken to avoid
noise being induced. By a direct routing, parasitic inductance can be kept small. GND layers might be used for
shielding if the parasitic capacitance can be kept small. Routing the SENSE+ and SENSE- close to each other
minimizes inductive noise injection. Keep these traces away from switching nodes and swiftly alternating signal
lines such as the I2C bus.
Improper layout might show the symptoms of poor line or load regulation, ground and output voltage shifts,
stability issues or unsatisfying EMI behavior.
See Figure 48 for the recommended layout.
Figure 48. Layout Suggestion (top view). Overall Solution Size: 27.5mm2
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
REGISTER SETTINGS
Overview
Table 9. TPS62360 Register Settings Overview
REGISTER (default / reset values)
RESET / READ /
ADDRESS REGISTER DEFAULT MSB LSB
WRITE
STATE D7 D6 D5 D4 D3 D2 D1 D0
0x00h SET0 0x111111 R/W MODE0 OV0[5:0]
0x01h SET1 0x010111 R/W MODE1 OV1[5:0]
0x02h SET2 0x111111 R/W MODE2 OV2[5:0]
0x03h SET3 0x100001 R/W MODE3 OV3[5:0]
0x04h Ctrl 111xxxxx R/W PD_EN PD_VSEL0 PD_VSEL1
0x05h Temp xxxxx000 R/W DIS_TS TJEW TJTS
0x06h RmpCtrl 000xx00x R/W RMP[2:0] EN_DISC RAMP_PFM
0x07h (Reserved) xxxxxxxx
0x08h Chip_ID 100000xx R
0x09h Chip_ID
Table 10. TPS62361B Register Settings Overview
REGISTER (default / reset values)
RESET / READ /
ADDRESS REGISTER DEFAULT MSB LSB
WRITE
STATE D7 D6 D5 D4 D3 D2 D1 D0
0x00h SET0 00101110 R/W MODE0 OV0[6:0]
0x01h SET1 01011010 R/W MODE1 OV1[6:0]
0x02h SET2 01000010 R/W MODE2 OV2[6:0]
0x03h SET3 01000010 R/W MODE3 OV3[6:0]
0x04h Ctrl 111xxxxx R/W PD_EN PD_VSEL0 PD_VSEL1
0x05h Temp xxxxx000 R/W DIS_TS TJEW TJTS
0x06h RmpCtrl 000xx00x R/W RMP[2:0] EN_DISC RAMP_PFM
0x07h (Reserved) xxxxxxxx
0x08h Chip_ID 100001xx R
0x09h Chip_ID
Table 11. TPS62362 Register Settings Overview
REGISTER (default / reset values)
RESET / READ /
ADDRESS REGISTER DEFAULT MSB LSB
WRITE
STATE D7 D6 D5 D4 D3 D2 D1 D0
0x00h SET0 0x101110 R/W MODE0 OV0[5:0]
0x01h SET1 0x010111 R/W MODE1 OV1[5:0]
0x02h SET2 0x101011 R/W MODE2 OV2[5:0]
0x03h SET3 0x100001 R/W MODE3 OV3[5:0]
0x04h Ctrl 111xxxxx R/W PD_EN PD_VSEL0 PD_VSEL1
0x05h Temp xxxxx000 R/W DIS_TS TJEW TJTS
0x06h RmpCtrl 000xx00x R/W RMP[2:0] EN_DISC RAMP_PFM
0x07h (Reserved) xxxxxxxx
0x08h Chip_ID 100010xx R
0x09h Chip_ID
34 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
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TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
Table 12. TPS62363 Register Settings Overview
REGISTER (default / reset values)
RESET / READ /
ADDRESS REGISTER DEFAULT MSB LSB
WRITE
STATE D7 D6 D5 D4 D3 D2 D1 D0
0x00h SET0 01000110 R/W MODE0 OV0[6:0]
0x01h SET1 01010011 R/W MODE1 OV1[6:0]
0x02h SET2 01100100 R/W MODE2 OV2[6:0]
0x03h SET3 00110010 R/W MODE3 OV3[6:0]
0x04h Ctrl 111xxxxx R/W PD_EN PD_VSEL0 PD_VSEL1
0x05h Temp xxxxx000 R/W DIS_TS TJEW TJTS
0x06h RmpCtrl 000xx00x R/W RMP[2:0] EN_DISC RAMP_PFM
0x07h (Reserved) xxxxxxxx
0x08h Chip_ID 100001xx R
0x09h Chip_ID
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 35
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TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
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Register 0x00h Description: SET0
The register settings apply by choosing SET0 ( VSEL1 = LOW, VSEL0 = LOW).
Table 13. TPS62360 Register 0x00h Description
REGISTER ADDRESS: 0x00h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET0
D7 MODE0 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 x Reserved for future use
Output voltage for SET0
D5 1 Default: (111111)2= 1.4V
D4 1 D5-D0 Output voltage
D3 1 00 0000 770 mV
00 0001 780 mV
OV0[5:0]
D2 1 00 0010 790 mV
... ...
D1 1 11 1111 1400 mV
D0 LSB 1 VOUT = (xx xxxx)2× 10mV + 770 mV
Table 14. TPS62361B Register 0x00h Description
REGISTER ADDRESS: 0x00h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET0
D7 MODE0 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 0 Output voltage for SET0
Default: (0101110)2= 0.96V
D5 1
D4 0 D6-D0 Output voltage
D3 1 000 0000 500 mV
000 0001 510 mV
OV0[6:0]
D2 1 000 0010 520 mV
... ...
D1 1 111 1111 1770 mV
D0 LSB 0 VOUT = (xxx xxxx)2× 10mV + 500 mV
36 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
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TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
Table 15. TPS62362 Register 0x00h Description
REGISTER ADDRESS: 0x00h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET0
D7 MODE0 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 x Reserved for future use
Output voltage for SET0
D5 1 Default: (101110)2= 1.23V
D4 0 D5-D0 Output voltage
D3 1 00 0000 770 mV
00 0001 780 mV
OV0[5:0]
D2 1 00 0010 790 mV
... ...
D1 1 11 1111 1400 mV
D0 LSB 0 VOUT = (xx xxxx)2× 10mV + 770 mV
Table 16. TPS62363 Register 0x00h Description
REGISTER ADDRESS: 0x00h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET0
D7 MODE0 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 1 Output voltage for SET0
Default: (1000110)2= 1.2V
D5 0
D4 0 D6-D0 Output voltage
D3 0 000 0000 500 mV
000 0001 510 mV
OV0[6:0]
D2 1 000 0010 520 mV
... ...
D1 1 111 1111 1770 mV
D0 LSB 0 VOUT = (xxx xxxx)2× 10mV + 500 mV
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 37
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TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
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Register 0x01h Description: SET1
The register settings apply by choosing SET1 ( VSEL1 = LOW, VSEL0 = HIGH).
Table 17. TPS62360 Register 0x01h Description
REGISTER ADDRESS: 0x01h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET1
D7 MODE1 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 x Reserved for future use
Output voltage for SET1
D5 0 Default: (010111)2= 1.0V
D4 1 D5-D0 Output voltage
D3 0 00 0000 770 mV
00 0001 780 mV
OV1[5:0]
D2 1 00 0010 790 mV
... ...
D1 1 11 1111 1400 mV
D0 LSB 1 VOUT = (xx xxxx)2× 10mV + 770 mV
Table 18. TPS62361B Register 0x01h Description
REGISTER ADDRESS: 0x01h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET1
D7 MODE1 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 1 Output voltage for SET1
Default: (1011010)2= 1.4V
D5 0
D4 1 D6-D0 Output voltage
D3 1 000 0000 500 mV
000 0001 510 mV
OV1[6:0]
D2 0 000 0010 520 mV
... ...
D1 1 111 1111 1770 mV
D0 LSB 0 VOUT = (xxx xxxx)2× 10mV + 500 mV
38 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
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TPS62360, TPS62361B
TPS62362, TPS62363
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SLVSAU9B –MAY 2011–REVISED MARCH 2012
Table 19. TPS62362 Register 0x01h Description
REGISTER ADDRESS: 0x01h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET1
D7 MODE1 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 x Reserved for future use
Output voltage for SET1
D5 0 Default: (010111)2= 1.0V
D4 1 D5-D0 Output voltage
D3 0 00 0000 770 mV
00 0001 780 mV
OV1[5:0]
D2 1 00 0010 790 mV
... ...
D1 1 11 1111 1400 mV
D0 LSB 1 VOUT = (xx xxxx)2× 10mV + 770 mV
Table 20. TPS62363 Register 0x01h Description
REGISTER ADDRESS: 0x01h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET1
D7 MODE1 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 1 Output voltage for SET1
Default: (1010011)2= 1.36V
D5 0
D4 1 D6-D0 Output voltage
D3 0 000 0000 500 mV
000 0001 510 mV
OV1[6:0]
D2 0 000 0010 520 mV
... ...
D1 1 111 1111 1770 mV
D0 LSB 1 VOUT = (xxx xxxx)2× 10mV + 500 mV
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 39
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
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Register 0x02h Description: SET2
The register settings apply by choosing SET2 ( VSEL1 = HIGH, VSEL0 = LOW).
Table 21. TPS62360 Register 0x02h Description
REGISTER ADDRESS: 0x02h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET2
D7 MODE2 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 x Reserved for future use
Output voltage for SET2
D5 1 Default: (111111)2= 1.4V
D4 1 D5-D0 Output voltage
D3 1 00 0000 770 mV
00 0001 780 mV
OV2[5:0]
D2 1 00 0010 790 mV
... ...
D1 1 11 1111 1400 mV
D0 LSB 1 VOUT = (xx xxxx)2× 10mV + 770 mV
Table 22. TPS62361B Register 0x02h Description
REGISTER ADDRESS: 0x02h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET2
D7 MODE2 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 1 Output voltage for SET2
Default: (1000010)2= 1.16V
D5 0
D4 0 D6-D0 Output voltage
D3 0 000 0000 500 mV
000 0001 510 mV
OV2[6:0]
D2 0 000 0010 520 mV
... ...
D1 1 111 1111 1770 mV
D0 LSB 0 VOUT = (xxx xxxx)2× 10mV + 500 mV
40 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
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TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
Table 23. TPS62362 Register 0x02h Description
REGISTER ADDRESS: 0x02h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET2
D7 MODE2 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 x Reserved for future use
Output voltage for SET2
D5 1 Default: (101011)2= 1.2V
D4 0 D5-D0 Output voltage
D3 1 00 0000 770 mV
00 0001 780 mV
OV2[5:0]
D2 0 00 0010 790 mV
... ...
D1 1 11 1111 1400 mV
D0 LSB 1 VOUT = (xx xxxx)2× 10mV + 770 mV
Table 24. TPS62363 Register 0x02h Description
REGISTER ADDRESS: 0x02h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET2
D7 MODE2 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 1 Output voltage for SET2
Default: (1100100)2= 1.5V
D5 1
D4 0 D6-D0 Output voltage
D3 0 000 0000 500 mV
000 0001 510 mV
OV2[6:0]
D2 1 000 0010 520 mV
... ...
D1 0 111 1111 1770 mV
D0 LSB 0 VOUT = (xxx xxxx)2× 10mV + 500 mV
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TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
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Register 0x03h Description: SET3
The register settings apply by choosing SET3 ( VSEL1 = HIGH, VSEL0 = HIGH).
Table 25. TPS62360 Register 0x03h Description
REGISTER ADDRESS: 0x03h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET3
D7 MODE3 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 x Reserved for future use
Output voltage for SET3
D5 1 Default: (100001)2= 1.1V
D4 0 D5-D0 Output voltage
D3 0 00 0000 770 mV
00 0001 780 mV
OV3[5:0]
D2 0 00 0010 790 mV
... ...
D1 0 11 1111 1400 mV
D0 LSB 1 VOUT = (xx xxxx)2× 10mV + 770 mV
Table 26. TPS62361B Register 0x03h Description
REGISTER ADDRESS: 0x03h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET3
D7 MODE3 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 1 Output voltage for SET3
Default: (1000010)2= 1.16V
D5 0
D4 0 D6-D0 Output voltage
D3 0 000 0000 500 mV
000 0001 510 mV
OV3[6:0]
D2 0 000 0010 520 mV
... ...
D1 1 111 1111 1770 mV
D0 LSB 0 VOUT = (xxx xxxx)2× 10mV + 500 mV
42 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
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TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9B –MAY 2011–REVISED MARCH 2012
Table 27. TPS62362 Register 0x03h Description
REGISTER ADDRESS: 0x03h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET3
D7 MODE3 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 x Reserved for future use
Output voltage for SET3
D5 1 Default: (100001)2= 1.1V
D4 0 D5-D0 Output voltage
D3 0 00 0000 770 mV
00 0001 780 mV
OV3[5:0]
D2 0 00 0010 790 mV
... ...
D1 0 11 1111 1400 mV
D0 LSB 1 VOUT = (xx xxxx)2× 10mV + 770 mV
Table 28. TPS62363 Register 0x03h Description
REGISTER ADDRESS: 0x03h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET3
D7 MODE3 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 0 Output voltage for SET3
Default: (0110010)2= 1.0V
D5 1
D4 1 D6-D0 Output voltage
D3 0 000 0000 500 mV
000 0001 510 mV
OV3[6:0]
D2 0 000 0010 520 mV
... ...
D1 1 111 1111 1770 mV
D0 LSB 0 VOUT = (xxx xxxx)2× 10mV + 500 mV
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 43
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
Register 0x04h Description: Ctrl
Table 29. TPS6236x Register 0x04h Description
REGISTER ADDRESS: 0x04h Read / Write
BIT NAME DEFAULT DESCRIPTION
MSB EN internal pull down resistor
D7 PD_EN 1 0 = disabled
1 = enabled
VSEL0 internal pull down resistor
D6 PD_VSEL0 1 0 = disabled
1 = enabled
VSEL1 internal pull down resistor
D5 PD_VSEL1 1 0 = disabled
1 = enabled
D4 x Reserved for future use
D3 x Reserved for future use
D2 x Reserved for future use
D1 x Reserved for future use
D0 LSB x Reserved for future use
Register 0x05h Description: Temp
Table 30. TPS6236x Register 0x05h Description
REGISTER ADDRESS: 0x05h Read/Write
BIT NAME DEFAULT DESCRIPTION
D7 MSB x Reserved for future use
D6 x Reserved for future use
D5 x Reserved for future use
D4 x Reserved for future use
D3 x Reserved for future use
Disable temperature shutdown feature
D2 DIS_TS 0 0 = Temperature shutdown enabled
1 = Temperature shutdown disabled
TJearly warning bit
D1 TJEW 0 0 = TJ< 120°C (typ)
1 = TJ≥120°C (typ)
TJtemperature shutdown bit
D0 TJTS 0 0 = die temperature within the valid range
1 = temperature shutdown was triggered
LSB Bit needs to be reset after it has been latched.
44 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
( )2
OUT
RMP[2-0]
ΔV mV 1
= 32
Δt μs 2
TPS62360, TPS62361B
TPS62362, TPS62363
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SLVSAU9B –MAY 2011–REVISED MARCH 2012
Register 0x06h Description: RmpCtrl
Table 31. TPS6236x Register 0x06h Description
REGISTER ADDRESS: 0x06h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Output voltage ramp timing
D7 0 D7-D5 Slope
000 32 mV / µs
001 16 mV / µs
010 8 mV / µs
D6 0 . . . . . .
RMP[2:0] 110 0.5 mV / µs
111 0.25 mV / µs
D5 0
D4 x Reserved for future use
D3 x Reserved for future use
EN_DISC Active output capacitor discharge at shutdown
D2 0 0 = disabled
1 = enabled
Defines the ramp behavior if the device is in Power Save (PFM) mode
D1 RAMP_PFM 0 0 = output cap will be discharged by the load
1 = output voltage will be forced to follow the ramp down slope
D0 LSB x Reserved for future use
Register 0x07h Description: (Reserved)
Table 32. TPS6236x Register 0x07h Description
REGISTER ADDRESS: 0x07h
BIT NAME DEFAULT DESCRIPTION
D7 MSB x Reserved for future use
D6 x Reserved for future use
D5 x Reserved for future use
D4 x Reserved for future use
D3 x Reserved for future use
D2 x Reserved for future use
D1 x Reserved for future use
D0 LSB x Reserved for future use
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 45
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9B –MAY 2011–REVISED MARCH 2012
www.ti.com
Register 0x08h, 0x09h Description Chip_ID:
Table 33. TPS6236x Register 0x08h and 0x09h Description
REGISTER ADDRESS: 0x08h, 0x09 Read
BIT NAME DEFAULT DESCRIPTION
D7 MSB 1
D6 0 Vendor ID
D5 0
D4 0
D3-D2 Part number ID
D3 x 00 TPS62360
01 TPS62361B
10 TPS62362
D2 x 11 TPS62363
D1 x D1-D0 Chip revision ID
00 Rev. 1
01 Rev. 2
D0 x 10 Rev. 3
11 Rev. 4
LSB
46 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
A1
TIYMLLLLS
XXXXXXXXX
E
D
Code:
• YM — Year Month date code
• LLLL — Lot trace code
• S — Assembly site code
• TI — Texas Instruments
• XXXXXXXX — Part number
• TPS62360 = TPS62360
• TPB62361 = TPS62361B
• TPS62362 = TPS62362
• TPS62363 = TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
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SLVSAU9B –MAY 2011–REVISED MARCH 2012
PACKAGE SUMMARY
CHIP SCALE PACKAGE
(TOP VIEW)
Figure 49. Package Marking and Dimensions
CHIP SCALE PACKAGE DIMENSIONS
The TPS6236x device is available in a 16-bump chip scale package (YZH, NanoFree™). The package
dimensions are given as:
• D = 2.076mm (+/- 0.03mm)
• E = 2.076mm (+/- 0.03mm)
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 47
Product Folder Link(s): TPS62360 TPS62361B TPS62362 TPS62363
PACKAGE OPTION ADDENDUM
www.ti.com 28-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS62360YZHR ACTIVE DSBGA YZH 16 3000 Green (RoHS
& no Sb/Br) Call TI Level-1-260C-UNLIM
TPS62360YZHT ACTIVE DSBGA YZH 16 250 Green (RoHS
& no Sb/Br) Call TI Level-1-260C-UNLIM
TPS62361BYZHR ACTIVE DSBGA YZH 16 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TPS62361BYZHT ACTIVE DSBGA YZH 16 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TPS62362YZHR ACTIVE DSBGA YZH 16 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TPS62362YZHT ACTIVE DSBGA YZH 16 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TPS62363YZHR ACTIVE DSBGA YZH 16 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TPS62363YZHT ACTIVE DSBGA YZH 16 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Mar-2012
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS62360YZHR DSBGA YZH 16 3000 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1
TPS62360YZHT DSBGA YZH 16 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1
TPS62361BYZHR DSBGA YZH 16 3000 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1
TPS62361BYZHT DSBGA YZH 16 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1
TPS62362YZHR DSBGA YZH 16 3000 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1
TPS62362YZHT DSBGA YZH 16 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1
TPS62363YZHR DSBGA YZH 16 3000 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1
TPS62363YZHT DSBGA YZH 16 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-May-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS62360YZHR DSBGA YZH 16 3000 210.0 185.0 35.0
TPS62360YZHT DSBGA YZH 16 250 210.0 185.0 35.0
TPS62361BYZHR DSBGA YZH 16 3000 210.0 185.0 35.0
TPS62361BYZHT DSBGA YZH 16 250 210.0 185.0 35.0
TPS62362YZHR DSBGA YZH 16 3000 210.0 185.0 35.0
TPS62362YZHT DSBGA YZH 16 250 210.0 185.0 35.0
TPS62363YZHR DSBGA YZH 16 3000 210.0 185.0 35.0
TPS62363YZHT DSBGA YZH 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-May-2012
Pack Materials-Page 2
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