MOTOROLA SEMICONDUCTOR EEE TECHNICAL DATA Differential Video Amplifier The MC1733CB is a wideband amplifier with differential input and differential output. Gain is fixed at 10 V, 100 V, or 400 V without external components. With the addition of one external resistor, gain becomes adjustable from 10 V to 400 V. Bandwidth: 120 MHz Typical @ Ayg = 10 Rise Time: 2.5 ns Typical @ Ayg = 10 MC1733CB DIFFERENTIAL VIDEO WIDEBAND AMPLIFIER SILICON MONOLITHIC INTEGRATED CIRCUIT D SUFFIX PLASTIC PACKAGE Propagation Delay Time: 3.6 ns Typical @ Ayg = 10 Figure 1. Basic Circuit Gain Select ~ Veg Sia GiB Output 1 Input 2 Output 2 Figure 2. Voltage Gain Adjust Circuit Ragj Input 1 51 : MC1733B Input 2 ne 51 Vee Goa Gog Vee Gog Gop Gain Setect Gain Select Figure 3. Equivalent Circuit Schematic Voc oO s kk = 1k S 24k S 24k = 10k = tC Input 20 7 a 7k Output 1 Input 1 oO Gy & Gain ) 1A 250 = 50 Select ) z 5 24 Oo} r__] 7 Output 2 Gop o Gain = 590 = 500 Select Gig t fn 1.4k Ke be nT tnd fl CASE 751A (SO-14) 1 L SUFFIX CERAMIC PACKAGE CASE 632 P SUFFIX PLASTIC PACKAGE CASE 646 PIN CONNECTIONS wi Input 2 [7} f14] Input 1 Ne [| [13] NC Gain Gap (3 tI Gan Gain Select Gig ] y [11] Gia Select Vee EI fo] V NC [6] [9] NC Output 2 [7] 18] Output 1 (Top View) ORDERING INFORMATION Temperature Device Range Package MC1733CBD $0-14 MC1733CBL 0 to +70C Plastic DIP MC1733CBP Ceramic DIP MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-114MC1733CB MAXIMUM RATINGS (Ta = +25C, unless otherwise noted.) Rating Symbol Value Unit Power Supply Voltage Voc +8.0 Vv VEE -8.0 Differential input Voltage Vin +5.0 Common Mode Input Voitage VICM +6.0 Output Current lo 10 mA Internal Power Dissipation Pp 500 mw Operating Temperature Range Ta 0 to +70 C Storage Temperature Range Tstg 65 to +150 C ELECTRICAL CHARACTERISTICS (Vcc = +6.0 Vdc, VEE = -6.0 Vdc, @ +25C, unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Differential Voltage Gain Avd VN Gain 1 (Note 2) 250 400 600 Gain 2 (Note 3) 80 100 120 Gain 3 (Note 4) 8.0 10 12 Bandwidth (Rg = 50 Q) BW MHz Gain 1 _ 40 _- Gain 2 _ 90 _ Gain 3 _ 120 _ Rise Time (Rg = 50 9, Vo = 1.0 Vp-p) tTLH ns Gain 1 tTHL _ 10.5 _ Gain 2 _ 4.5 - Gain 3 _ 2.5 _ Propagation Delay (Rg = 50 Q, Vo = 1.0 Vp-p) tPLH ns Gain 1 tPHL _ 7.5 _ Gain 2 _ 6.0 _ Gain 3 _ 3.6 _ Input Resistance Rin kQ Gain 1 _ 4.0 _ Gain 2 10 30 _ Gain 3 - 250 _ Input Capacitance (Gain 2) Cin _ 2.0 _ pF Input Offset Current (Gain 3) tho} _ 0.4 5.0 pA Input Bias Current (Gain 3) iB _ 9.0 30 pA Input Noise Voltage (Rg = 50 Q, BW = 1.0 kHz to 10 MHz) Vn _ t2 _ pVirms) Input Voltage Range (Gain 2) Vin +1.0 _ _ Vv Common Mode Rejection CMR dB Gain 2 (Vow = 1.0 V, f = 100 kHz) 60 86 _ Gain 2 (Vow = +1.0 V, f = 5.0 MHz) - 60 _ Supply Voltage Rejection PSR 50 70 dB Gain 2 (A Vg = +0.5 V) Output Offset Voltage Voo Vv Gain 1 _ 0.6 2.0 Gain 2 and Gain 3 _ 0.35 1.5 Output Common Mode Voltage (Gain 3) VoMO 2.4 29 3.4 v Output Voltage Swing (Gain 2) Vo 3.0 4.0 _ Vp-p Output Sink Current (Gain 2) \Sink 2.5 3.6 = mA Output Resistance Rout - 20 _ Q Power Supply Current (Gain 2) Ip _ 18 24 mA MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-115MC1733CB ELECTRICAL CHARACTERISTICS (Vcc = +6.0 Vdc, Veg = -6.0 Vdc, @ Ta = Thigh to Tiow, unless otherwise noted.)* Characteristics Symbol Min Typ Max Unit Differential Voltage Gain AvD VN Gain 1 (Note 2) 250 _ 600 Gain 2 (Note 3) 80 _ 120 Gain 3 (Note 4) 8.0 _ 12 input Resistance Rin 8.0 _ _ kQ Gain 2 Input Offset Current (Gain 3) lol _ _ 6.0 HA Input Bias Current (Gain 3) lip _ 40 pA Input Voltage Range (Gain 2) Vin +1.0 _ - Vv Common Mode Rejection CMR 50 _ _ dB Gain 2 (Voy = 1.0 V, f < 100 kHz) Supply Voltage Rejection PSR 50 _ _ dB Gain 2 (A Vs = +0.5 V) Output Offset Voltage Voo v Gain 1 _ _ 1.5 Gain 2 and Gain 3 _ _ Output Voltage Swing (Gain 2) Vo 2.5 _ _ Vp-p Output Sink Current (Gain 2) lo 25 _ mA Power Supply Current (Gain 2) Ip =_ _ 27 mA Tlow = 0C for MC1733. Thigh = +70C for MC1733C. NOTES: 1. Derate dual-in-line package at 9.0 mW/C for operation at ambient temperatures above 100C (see Figure 4). If operation at high ambient temperatures is required a heatsink may be necessary to limit maximum junction temperature at 150C. 2. Gain Select pins Gy a and G1B connected together. 3. Gain Select pins Goa and Gog connected together. 4. All Gain Select pins open. Figure 4. Maximum Allowable Power Dissipation Figure 5. Supply Current versus Temperature 800 = Ceramic Dual = 600 In-Line Package Fe 9.0 mv/C 5 =e Ww E wn n Oo 2 400 > c a = z o = 2 200 2 a a 0 0 50 100 150 200 -60 -20 20 60 100 140 Ta, AMBIENT TEMPERATURE (C) Ta, AMBIENT TEMPERATURE (C) Figure 6. Supply Current versus Supply Voltage 28 24 20 Ip , SUPPLY CURRENT (mA) 8.0 3.0 4.0 5.0 6.0 7.0 8.0 Vcc. [VEEI, SUPPLY VOLTAGES (Vj MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-116Ay. RELATIVE VOLTAGE GAIN Ay. RELATIVE VOLTAGE GAIN Ayg, SINGLE-ENDED VOLTAGE GAIN (dB) MC1733CB Figure 7. Gain versus Temperature Figure 8. Gain versus Frequency 1.15 110 gS RL=1.0kQ d > . = Gain 4 1.05 Ww - oO Gain 2 = 4.0 3 > 0.95 a a a 0.90 uy S 0.85 5 a 0.80 < -60 -20 20 60 100 140 1.0 10 100 T, TEMPERATURE (C) t, FREQUENCY (MHz) Figure 9. Gain versus Supply Voltage Figure 10. Gain versus Radjust 1000 Gain 2 Gain 1 Ayp, DIFFERENTIAL VOLTAGE GAIN 8 3.0 40 5.0 6.0 7.0 BO 10 Voc. Veg), SUPPLY VOLTAGES (Vv) Figure 11. Gain versus Frequency and Figure 12. Gain versus Frequency Supply Voltage and Temperature Gain 2 Re = 1.0kQ Avg, SINGLE-ENDED VOLTAGE GAIN (dB) 1.0 10 100 f, FREQUENCY (MHz) f, FREQUENCY (MHz) o = o 10 100 1.0k MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-117MC1733CB Figure 13. Pulse Response versus Gain 1.6 Rr = 10 kQ = 12 a = 08 > E = a 5 04 S 7 9 -0.4 -15 -10 -50 0 50 10 15 2 2 30 3 t, TIME (ns) Figure 15. Pulse Response versus Temperature 1.6 Gain 2 Ry = 10kQ = 12 L Ww g = 08 > ke = a 5 04 = 0 -0.4 -15 -10 -50 0 50 10 15 2 2 30 3 t, TIME (ns) Figure 17. Phase Shift versus Frequency PHASE SHIFT (DEGREES) 0 20 40 60 8.0 10 f, FREQUENCY (MHz) Figure 14. Pulse Response versus Supply Voltage 1.6 =+8.0V 1.2 16.0V 08 13.0V 0.4 Vo , OUTPUT VOLTAGE (V) -15 -10 -50 0 50 10 1 2 2 30 3 {, TIME (ns) Figure 16. Differential Overdrive Recovery Time V in, DIFFERENTIAL VOLTAGE (mV) 0 10 20 30 40 50 60 70 80 OVERDRIVE RECOVERY TIME (ns) Figure 18. Phase Shift versus Frequency PHASE SHIFT (DEGREES) 1.0 10 100 1.0k f, FREQUENCY (MHz) MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-118Vg, OUTPUT VOLTAGE SWING (Vp-p) MC1733CB Figure 19. Input Resistance versus Temperature Figure 20. Input Noise Voltage 70 D> So an o 2 So Gain 2 BW = 10 MHz Rin, INPUT RESISTANCE (k 2) 8 & 3 INPUT NOISE VOLTAGE ( \.Virms} 2 -60 -20 20 60 100 140 1.0 10 100 1.0k 10k Ta, AMBIENT TEMPERATURE (C) Rg, SOURCE RESISTANCE (22) Figure 21. Output Voltage Swing and Figure 22. Output Voltage Swing versus Sink Current versus Supply Voitage Load Resistance 8.0 > Voltage Current Ig, OUTPUT SINK CURRENT (mA) nm > oa o Vo_, OUTPUT VOLTAGE SWING (Vp-p) 3.0 4.0 5.0 6.0 7.0 8.0 10 100 1.0k 10k Voc, SUPPLY VOLTAGE (V) Ri, LOAD RESISTANCE (Q) Figure 23. Output Voltage Swing versus Frequency Figure 24. Common Mode Rejection Ratio Vo, OUTPUT VOLTAGE SWING (Vp-p) 7.0 gS 2 6.0 ie a =z 5.0 6 e a 4.0 4 AL = 1.0kQ 3.0 a oO = 2.0 2 So = 1.0 5 oc 0 S 1.0 10 100 10k 2 10k 100k 1.0M 10M 100M f, FREQUENCY (MHz) f, FREQUENCY (Hz) MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-119MC1733CB Figure 25. Voltage Controlled Oscillator Vec Ri 620 O 2N4360 or Controt Equivalent Voltage Vo VEE By changing the voltage Vc the gain will vary over a range of 10 V to 400 V. This will give a frequency variation about the value set by the capacitor and shown in Figure 26. Tape, Drum or Disc Memory Read Amplifiers The first of several methods to be discussed is shown in Figure 27. This block diagram describes a simple Read circuit with no threshold circuitry. Each block represents a basic function that must be performed by the Read circuit. The first block, referred to as amplification, increases the level of the signal available from the Read head to a level adequate to drive the Peak Detector. Obviously, these signal levels will vary depending on factors such as tape speed, whether the system used is disc or tape, and the type of head and the circuitry used. For a representative tape system, levels of 7.0 mV to 25 mV for the signal from the Read head and 2.0 V for the signal to the Peak Detector are typical. These signal levels are peak-to-peak unless otherwise specified. On the basis of the signal levels mentioned above, the overall amplification required is 38 dB to 49 dB. How the overall gain requirement is implemented will depend somewhat on the system used. For instance, a tape cassette system with variable tape speed may utilize a first stage for gain and a second stage primarily for gain control. Thus, a typical circuit would utilize 35 dB in the first stage and 10 dB to 15 dB in the second stage. Devices suitable for use as amplifiers fall into one of two categories, operational amplifiers or wideband video amplifiers. Lower speed equipment with low transfer rates commonly uses low cost operational amplifiers. Examples of these are the MC1741, MC1458, and MLM301. Equipment requiring higher transfer rates, such as disk systems normally use wideband amplifiers such as the MC1733CB. The actual crossover point where wideband amplifiers are used exclusively varies with equipment design. For purposes of comparison, the MLM301 has slightly less than a 40 dB open-loop gain at 100 kHz; the MC1741, a compensated op amp, has approximatley 20 dB open-loop gain at 100 kHz; the MC1733CB has approximately 33 dB of gain out to 100 MHz (depending on a gain option and loading). There are a number of ways to implement the Peak Detector function. However, the simplest and most widely used method is a passive differentiator that generates zero crossing for each of the data peaks in the Read signal. Figure 26. Oscillator Frequency for Various Capacitor Values CAPACITANCE (pF} 100 10k 100 k 1.0M 10M f, FREQUENCY (Hz) Figure 27. Typical Read Circuit (Method 1) (ee HBHe}~ Detector The actual circuitry used to differentiate the Read signal varies from a differential LC type in disc systems to a simple RC type in reel and cassette systems. Either type, of course, attenuates the signal by an amount depending on the circuit used and system specifications. A good approximation of attenuation using the RC type is 30 dB. Thus, the 2.0 V signal going into the differentiator is reduced to 200 mV. The next block in Figure 27 to be discussed is the Zero Crossing Detector. in most cases detection of the zero crossings is combined with the limiter. These functions serve to generate a TTL compatible pulse waveform with edges corresponding to zero crossings. For low transfer rates, the circuit often used consists of an operational amplifier with series or shunt limiting. For higher transfer rates (greater than 100k B/S) comparators are used. The method described above is often modified to include threshold sensing. In Figure 28, the function called Double Ended Limit Detector enables the output NAND gate when either the negative or positive data peaks of the Read signal exceed a predetermined threshold. This function can be implemented in either of two ways. One method first rectifies the signal before it is applied to a comparator with a set threshold. The other method utilizes two comparators, one comparator for positive-going peaks and the other for negative-going peaks. These comparator outputs are then combined in the output logic gates. Figure 28. Read Circuit (Method 2) MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-120MC1733CB Another common technique is shown in Figure 29. The branch labeled rectifiers, Peak Detector, etc., provides a clock transition of the D flip-flop that corresponds to the peak of both the positive and negative-going data peaks. This branch may include threshold circuitry prior to the Peak Detector. The detector in the lower path detects whether the signal peaks are positive or negative and feeds this data to the flip-flop. This detector can be implemented using a comparator with preset threshold. Figure 29. Read Circuit (Method 3) Amplifiers Rectie Peak Zero n rs Crossing F ae 7338 Detector Det or Detector Output The technique shown in Figure 30 uses separate circuits with threshold provisions for both negative and positive peaks. The peak detectors and threshold detectors may be implemented with two comparators and two passive differentiators. Each of the methods shown offer certain intrinsic advantages or disadvantages. The overall decision as to which method to use however often invoives other important considerations. These could include cost and system requirements or circuitry other than simply the Read circuitry. For instance, if cost is the predominate overall factor, then Method 1 may be the only feasible alternative. Method 4 was included as a design example because it illustrates several unique advantages. First, it uses threshold sensing to reduce noise peak errors. Second, it may be implemented using only integrated circuits. Third, it offers Separate, direct threshold sensing for both positive and negative peaks. Figure 30. Read Circuit (Method 4) Positive Peak rac Detector Positive Threshoki D Head Amplifiers Detector ut MC1733CB Negative Peak Detector Negative Threshold 0 Detector MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-121