Low Power Pseudo SRAM 2 M Word x 16 bit CS26LV32163 Revision History Rev. No. History Issue Date 2.0 Initial issue with new naming rule Mar. 01, 2005 2.1 Revise 1. page 2 & 4: page address inputs Nov. 23, 2005 Remark 2. Add Vcc absolute max. in page 5 2.2 Modify Deep Power Down Mode & Page Mode Jun. 15, 2006 2.3 Revise DC/AC Char. Oct. 29, 2007 2.4 Change wafer process from 0.13um to 90nm Aug. 26, 2008 2.5 Add 48BGA-6*8mm package Jan. 06, 2010 2.6 Delete Die form information Apr.12,2010 1 Rev 2.6 Chiplus reserves the right to change product or specification without notice. Low Power Pseudo SRAM CS26LV32163 2 M Word x 16 bit Product Description The CS26LV32163 is a 32M-bit PSRAM organized as 2M words by 16 bits. It provides high density, high speed and low power. The device operates single power supply. The device also features SRAM-like W/R timing whereby the device is controlled by /CE, /OE and /WE on asynchronous. The device has the page access operation. Page size is 16 words. The device also supports deep power-down mode, realizing low-power standby. The CS26LV32163 is available die form and 48-Ball BGA package. Features 3/4 Single power supply voltage of 2.6 to 3.3V 3/4 Direct TTL compativility for all inputs and outputs. 3/4 Deep power-down mode : Memory cell data invalid. 3/4 Page operation mode Page read operation by 16 words. 3/4 Logic compatible with SRAM R/W pin. 3/4 Standby Current Standby 120 uA(Max) Deep power-down standby 10 uA(Max) 3/4 Access Time /CE1 Access Time: 70ns /OE Access Time: 25ns Page Access Time: 20ns Product Family Product Family Operating Temp Vcc. Range Speed(ns) Standby(Max.) 0~70oC CS26LV32163 Package Type Dice 2.6~3.3 -40~85oC 70 120 uA 48BGA-6*7mm 48BGA-6*8mm 2 Rev 2.6 Chiplus reserves the right to change product or specification without notice. Low Power Pseudo SRAM 2 M Word x 16 bit CS26LV32163 Pin Configuration <48BGA> 3 Rev 2.6 Chiplus reserves the right to change product or specification without notice. Low Power Pseudo SRAM 2 M Word x 16 bit CS26LV32163 Functional Block Diagram 4 Rev 2.6 Chiplus reserves the right to change product or specification without notice. Low Power Pseudo SRAM CS26LV32163 2 M Word x 16 bit Pin Descriptions Name Type Function A0~A20 input Address input A0~A3 input Page Address input /CE1 input Chip Enable Input1, Low : Enable CE2 input Chip Enable Input2, High:Enable, Low:Enter Power Down mode /WE input Write Enable input, Low :Enable /OE input Output Enable input, Low :Enable /LB input Lower byte write control /UB input Upper byte write control DQ0~DQ15 I/O Data inputs/outputs VDD Power Device Power supply VSS Power VSS must be connected ground VDDQ Power I/O Power supply VSSQ Power VSSQ must be connected ground Not Connection NC Truth Table MODE /CE1 CE2 /OE /WE /LB /UB DQ0~7 DQ8~15 Deep power down X L X X X X High Z High Z Standby H H X X X X High Z High Z ICCSB, ICCSB1 Output Disabled L H H H X X High Z High Z ICC L L DOUT DOUT ICC L H DOUT High Z ICC Lower Byte Read H L High Z DOUT ICC Write L L DIN DIN ICC L H DIN Invalid ICC H L Invalid DIN ICC Read Upper Byte Read Upper Byte Write L L H H L H X L Lower Byte Write VDD Current Note: X means don't care. (Must be low or high state) 5 Rev 2.6 Chiplus reserves the right to change product or specification without notice. Low Power Pseudo SRAM CS26LV32163 2 M Word x 16 bit Absolute Maximum Ratings(1) Symbol Parameter Rating Unit V VIN Input Voltage -1.0 to 3.6 VOUT Output Voltage -1.0 to 3.6 VDD Device Power Supply Voltage -1.0 to 3.6 TSTG Storage Temperature -55 to +150 O -40 to +85 O TA Operating Temperature PD Power Dissipation V C C 0.6 W 1. Stresses greater than those listed above "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. o DC Electrical Characteristics ( TA = 0 to + 70 C , VDD= 3.0V ) Parameter Parameter Name Test Conduction Input Low Voltage (2) VIL (2) VIH Input High Voltage IIL Input Leakage Current IOL Output Leakage Current Output disable, VOUT= 0V to VDD VOL Output Low Voltage IOL = 0.5mA, VDD=VDDmin VOH Output High Voltage IOH = -0.5mA ICC1 Operating Current ICC2 ICCSB1 ICCSB2 VIN=0 to VDD MIN TYP(1) MAX Unit -0.3 0.6 V 2.4 VDD + 0.3 V -1 1 uA -1 1 uA 0.6 V 2.4 tRC= Min, /CE1=VIL , CE2=VIH , V 25 mA Page Access Operating tPC = Min, /CE1=VIL, CE2=VIH , current IOUT=0mA, Page add. cycling. 15 mA Standby Current -CMOS /CE1VDD-0.2V, CE2=VDD -0.2V 120 uA Deep Power-down 10 uA IOUT=0mA CE2 = 0.2V Standby Current o 1. Typical characteristics are at TA = 25 C. 2. VIH(Max) VDD+1.0V with 10ns pulse width, VIL(Min)-1.0V with 10ns pulse width Capacitance (1) (TA = 25oC, f =1.0 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions MAX. Unit VIN=0V 10 pF VOUT=0V 10 pF 1. This parameter is sampled periodically and is not 100% tested 6 Rev 2.6 Chiplus reserves the right to change product or specification without notice. Low Power Pseudo SRAM CS26LV32163 2 M Word x 16 bit AC Test Conditions Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.2V to VDDQ-0.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : VDDQ /2 Output Load (See right) : CL1) = 30pF 1. Including scope and Jig capacitance Key To Switching Waveforms Waveform Inputs Outputs Must be standby Must be standby May change for H to L Will be change from H to L May change for L to H May change for L to H Don't care any change permitted Change state unknown Does not apply Center line is high impedance "OFF" state 7 Rev 2.6 Chiplus reserves the right to change product or specification without notice. Low Power Pseudo SRAM CS26LV32163 2 M Word x 16 bit AC Characteristics <Read cycle & Write Cycle> Parameter Name Name 70 Min Max Unit Read cycle time tRC 70 10,000 ns Page mode cycle time tMRC 20 10,000 ns Address access time tACC - 70 ns Page Address Access Time tAA 20 ns Chip enable access time (/CE1) tCO - 70 ns Output enable to output valid (/OE) tOE - 25 ns Byte enable access time tBA - 25 ns Output data hold time tOH 5 - ns Page mode output data hold time tAOH 5 - ns Chip enable to output in low Z (/CE1) tCOE 10 - ns Output enable to output in low Z (/OE) tOEE 0 - ns Byte enable to output in low Z tBE 0 - ns Chip disable to output in High Z (/CE1) tOD - 20 ns Output disable to output in High Z (OE) tODO - 20 ns Byte disable to output in High Z tBD - 20 ns Write cycle time tWC 70 10,000 ns Byte enable to end of write tBW 60 - ns Address valid to end of write tAW 60 - ns Chip select to end of write tCW 65 - ns Data set up time tDS 30 - ns Data hold time tDH 0 - ns Write pulse width tWP 50 - ns Address set up time tAS 0 - ns Write recovery time(/WE) tWR 0 - ns /WE high to output low Z tOEW 0 - ns /WE low to output high Z tODW - 20 ns Chip enable high pulse width tCEH 10 Write enable high pulse width tWEH 6 - ns CE2 set -up time tCS 0 - ns CE2 hold time tCH 300 - ns CE2 pulse width tDPD 10 - ns CE2 hold from /CE1 tCHC 0 - ns CE2 hold from power on tCHP 30 - ns 8 ns Rev 2.6 Chiplus reserves the right to change product or specification without notice. Low Power Pseudo SRAM 2 M Word x 16 bit CS26LV32163 TIMING DIAGRAMS <READ CYCLE> PAGE READ CYCLE (16 words access) 9 Rev 2.6 Chiplus reserves the right to change product or specification without notice. Low Power Pseudo SRAM 2 M Word x 16 bit CS26LV32163 WRITE CYCLE (1) (/WE controlled) WRITE CYCLE (2) (/CE1 controlled) 10 Rev 2.6 Chiplus reserves the right to change product or specification without notice. Low Power Pseudo SRAM 2 M Word x 16 bit CS26LV32163 NOTES 1. AC measurement are assumed tR, tF = 5ns. 1. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not output voltage reference levels. 2. Data cannot be retained at deep power-down stand-by mode. 3. If /OE is high during the write cycle, the outputs will remain at high impedence. 4. During the output state of DQ signals, input signals of reverse polarity must not be applied. 5. If /CE1 or /LB&/UB goes LOW coincident with or after /WE goes LOW, the outputs will remain at high impedence. 6. If /CE1 or /LB&/UB goes HIGH coincident with or before /WE goes HIGH, the outputs will remain at high impedence. DEEP POWER-DOWN TIMING POWER_ON TIMING 11 Rev 2.6 Chiplus reserves the right to change product or specification without notice. Low Power Pseudo SRAM 2 M Word x 16 bit CS26LV32163 PROVISIONS OF ADDRESS SKEW Read In case, multiple invalid address cycles shorter than tRC_min sustain over 10us in a active status, as least one valid address cycle over tRC_min must be needed during 10us. Write In case, multiple invalid address cycles shorter than tWC_min sustain over 10us in a active status, as least one valid address cycle over tRC_min with tWP_min must be needed during 10us. 12 Rev 2.6 Chiplus reserves the right to change product or specification without notice. Low Power Pseudo SRAM 2 M Word x 16 bit CS26LV32163 Order information Note: Package material code "P" meets RoHS 13 Rev 2.6 Chiplus reserves the right to change product or specification without notice.