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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90LV047A
SNLS044D –MAY 2000–REVISED JULY 2016
DS90LV047A 3-V LVDS Quad CMOS Differential Line Driver
1
1 Features
1• >400-Mbps (200 MHz) Switching Rates
• Flow-Through Pinout Simplifies PCB Layout
• 300-ps Typical Differential Skew
• 400-ps Maximum Differential Skew
• 1.7-ns Maximum Propagation Delay
• 3.3-V Power Supply Design
• ±350-mV Differential Signaling
• Low Power Dissipation (13 mW at 3.3-V Static)
• Interoperable With Existing 5-V LVDS Receivers
• High impedance on LVDS Outputs on Power
Down
• Conforms to TIA/EIA-644 LVDS Standard
• Industrial Operating Temperature Range
(−40°C to +85°C)
• Available in Surface Mount SOIC and Low Profile
TSSOP Package
2 Applications
• Multifunction Printers
• LVDS – LVCMOS Translation
3 Description
The DS90LV047A device is a quad CMOS flow-
through differential line driver designed for
applications requiring ultra-low power dissipation and
high data rates. The device is designed to support
data rates in excess of 400 Mbps (200 MHz) using
Low Voltage Differential Signaling (LVDS)
technology.
The DS90LV047A accepts low voltage TTL/CMOS
input levels and translates them to low voltage
(350 mV) differential output signals. In addition, the
driver supports a TRI-STATE function that may be
used to disable the output stage, disabling the load
current, and thus dropping the device to an ultra low
idle power state of 13 mW typical. The DS90LV047A
has a flow-through pinout for easy PCB layout.
The EN and EN* inputs are ANDed together and
control the TRI-STATE outputs. The enables are
common to all four drivers. The DS90LV047A and
companion line receiver (DS90LV048A) provide a
new alternative to high power psuedo-ECL devices
for high speed point-to-point interface applications.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
DS90LV048A SOIC (16) 9.90 mm × 3.91 mm
TSSOP (16) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Diagram
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics .......................................... 4
6.6 Switching Characteristics ......................................... 5
6.7 Typical Characteristics.............................................. 6
7 Parameter Measurement Information .................. 8
8 Detailed Description............................................ 11
8.1 Overview................................................................. 11
8.2 Functional Block Diagram....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 13
9 Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 17
12 Device and Documentation Support................. 18
12.1 Documentation Support ........................................ 18
12.2 Receiving Notification of Documentation Updates 18
12.3 Community Resources.......................................... 18
12.4 Trademarks........................................................... 18
12.5 Electrostatic Discharge Caution............................ 18
12.6 Glossary................................................................ 18
13 Mechanical, Packaging, and Orderable
Information........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2013) to Revision D Page
• Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
Changes from Revision B (April 2013) to Revision C Page
• Changed layout of National Semiconductor Data Sheet to TI format .................................................................................. 15
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5 Pin Configuration and Functions
D or PW Package
16-Pin SOIC or TSSOP
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
DIN 2, 3, 6, 7 I Driver input pin, TTL/CMOS compatible
DOUT+ 10, 11, 14, 15 O Non-inverting driver output pin, LVDS levels
DOUT−9, 12, 13, 16 O Inverting driver output pin, LVDS levels
EN 1 I Driver enable pin: When EN is low, the driver is disabled. When EN is high and EN* is low
or open, the driver is enabled. If both EN and EN* are open circuit, then the driver is
disabled.
EN* 8 I Driver enable pin: When EN* is high, the driver is disabled. When EN* is low or open and
EN is high, the driver is enabled. If both EN and EN* are open circuit, then the driver is
disabled.
GND 5 — Ground pin
VCC 4 — Power supply pin, +3.3 V ± 0.3 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
See (1)
MIN MAX UNIT
Supply voltage (VCC)−0.3 4 V
Input voltage (DIN)−0.3 VCC + 0.3 V
Enable input voltage (EN, EN*) −0.3 VCC + 0.3 V
Output voltage (DOUT+, DOUT–)−0.3 3.9 V
Short-circuit duration (DOUT+, DOUT–) Continuous
Maximum package power
dissipation at +25°C
D0016A package 1088 mW
PW0016A package 866
Derate D0016A package above +25°C 8.5 mW/°C
Derate PW0016A package above +25°C 6.9
Lead temperature Soldering (4 s) 260 °C
Maximum junction temperature 150 °C
Storage temperature, Tstg −65 150 °C
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(1) ESD Ratings:
HBM (1.5 kΩ, 100 pF)
EIAJ (0 Ω, 200 pF)
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge(1) Human-body model (HBM) ±10000 V
Machine Model ±1200
6.3 Recommended Operating Conditions MIN NOM MAX UNIT
Supply voltage, VCC 3 3.3 3.6 V
Operating free air temperature, TA−40 25 85 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1) DS90LV047A
UNITPW (TSSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance 114 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 51 °C/W
RθJB Junction-to-board thermal resistance 59 °C/W
ψJT Junction-to-top characterization parameter 8 °C/W
ψJB Junction-to-board characterization parameter 58 °C/W
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except: VOD1 and ΔVOD1.
(2) All typicals are given for: VCC = 3.3 V, TA= +25°C.
(3) The DS90LV047A is a current mode device and only functions within datasheet specifications when a resistive load is applied to the
driver outputs typical range is (90 Ωto 110 Ω).
6.5 Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified(1)(2)(3)
PARAMETER TEST CONDITIONS PIN MIN TYP MAX UNIT
VOD1 Differential output voltage
RL= 100 Ω(Figure 17)DOUT−
DOUT+
250 310 450 mV
ΔVOD1 Change in magnitude of VOD1 for
complementary output states 1 35 |mV|
VOS Offset voltage 1.125 1.17 1.375 V
ΔVOS Change in magnitude of VOS for
complementary output states 1 25 |mV|
VOH Output high voltage 1.33 1.6 V
VOL Output low voltage 0.9 1.02 V
VIH Input high voltage
DIN,
EN,
EN*
2 VCC V
VIL Input low voltage GND 0.8 V
IIH Input high current VIN = VCC or 2.5 V −10 2 +10 µA
IIL Input low current VIN = GND or 0.4 V −10 −2 +10 µA
VCL Input clamp voltage ICL =−18 mA −1.5 −0.8 V
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Electrical Characteristics (continued)
Over supply voltage and operating temperature ranges, unless otherwise specified(1)(2)(3)
PARAMETER TEST CONDITIONS PIN MIN TYP MAX UNIT
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
IOS Output short-circuit current(4) ENABLED,
DIN = VCC, DOUT+ = 0 V or
DIN = GND, DOUT−= 0 V
DOUT−
DOUT+
−4.2 −9 mA
IOSD Differential output short-circuit
current(4) ENABLED, VOD = 0 V −4.2 −9 mA
IOFF Power-off leakage VOUT = 0 V or 3.6 V, VCC = 0 V or
Open −20 ±1 20 µA
IOZ Output TRI-STATE current EN = 0.8 V and EN* = 2.0 V
VOUT = 0 V or VCC −10 ±1 10 µA
ICC No load supply current drivers enabled DIN = VCC or GND
VCC
4 8 mA
ICCL Loaded supply current drivers enabled RL= 100 Ωall channels, DIN = VCC
or GND (all inputs) 20 30 mA
ICCZ No load supply current drivers
disabled DIN = VCC or GND, EN = GND,
EN* = VCC 2.2 6 mA
(1) All typicals are given for: VCC = 3.3 V, TA= +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO= 50 Ω, tr≤1 ns, and tf≤1 ns.
(3) CLincludes probe and jig capacitance.
(4) tSKD1 |tPHLD – tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(5) tSKD2 is the differential channel-to-channel skew of any event on the same device.
(6) tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation
delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(7) tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max −Min|
differential propagation delay.
(8) fMAX generator input conditions: tr= tf< 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% / 55%,
VOD > 250 mV, all channels switching.
6.6 Switching Characteristics
VCC = +3.3V ± 10%, TA=−40°C to +85°C(1)(2)(3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPHLD Differential propagation delay high to
low
RL= 100 Ω, CL= 15 pF
(Figure 18 and Figure 19)
0.5 0.9 1.7 ns
tPLHD Differential propagation delay low to
high 0.5 1.2 1.7 ns
tSKD1 Differential pulse skew |tPHLD −tPLHD|(4) 0 0.3 0.4 ns
tSKD2 Channel-to-channel skew(5) 0 0.4 0.5 ns
tSKD3 Differential part-to-part skew(6) 0 1 ns
tSKD4 Differential part-to-part skew(7) 0 1.2 ns
tTLH Rise time 0.5 1.5 ns
tTHL Fall time 0.5 1.5 ns
tPHZ Disable time high to Z
RL= 100 Ω, CL= 15 pF
(Figure 20 and Figure 21)
2 5 ns
tPLZ Disable time low to Z 2 5 ns
tPZH Enable time Z to high 3 7 ns
tPZL Enable time Z to low 3 7 ns
fMAX Maximum operating frequency(8) 200 250 MHz
6
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6.7 Typical Characteristics
Figure 1. Output High Voltage vs Power Supply Voltage Figure 2. Output Low Voltage vs Power Supply Voltage
Figure 3. Output Short Circuit Current vs
Power Supply Voltage Figure 4. Output TRI-STATE Current vs
Power Supply Voltage
Figure 5. Differential Output Voltage vs
Power Supply Voltage Figure 6. Differential Output Voltage vs Load Resistor
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Typical Characteristics (continued)
Figure 7. Offset Voltage vs Power Supply Voltage Figure 8. Power Supply Current vs Power Supply Voltage
Figure 9. Power Supply Current vs Ambient Temperature Figure 10. Differential Propagation Delay vs
Power Supply Voltage
Figure 11. Differential Propagation Delay vs
Ambient Temperature Figure 12. Differential Skew vs Power Supply Voltage
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Typical Characteristics (continued)
Figure 13. Differential Skew vs Ambient Temperature Figure 14. Transition Time vs Power Supply Voltage
Figure 15. Transition Time vs Ambient Temperature Figure 16. Data Rate vs Cable Length
7 Parameter Measurement Information
Figure 17. Driver VOD and VOS Test Circuit
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Parameter Measurement Information (continued)
Figure 18. Driver Propagation Delay and Transition Time Test Circuit
Figure 19. Driver Propagation Delay and Transition Time Waveforms
Figure 20. Driver TRI-STATE Delay Test Circuit
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8 Detailed Description
8.1 Overview
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 23. This configuration provides a clean signaling environment for the fast edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media
is in the range of 100 Ω. A termination resistor of 100 Ω(selected to match the media), and is located as close to
the receiver input pins as possible. The termination resistor converts the driver output current (current mode) into
a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver
configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as
well as ground shifting, noise margin limits, and total termination loading must be taken into account.
The DS90LV047A differential line driver is a balanced current source design. A current mode driver, generally
speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode
driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in
one direction to produce a logic state and in the other direction to produce the other logic state. The output
current is typically 3.1 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode driver requires
(as discussed above) that a resistive termination be employed to terminate the signal and to complete the loop
as shown in Figure 23. AC or unterminated configurations are not allowed. The 3.1-mA loop current develops a
differential voltage of 310 mV across the 100-Ωtermination resistor which the receiver detects with a 250-mV
minimum differential noise margin, (driven signal minus receiver threshold (250 mV – 100 mV = 150 mV). The
signal is centered around +1.2 V (Driver Offset, VOS) with respect to ground as shown in Figure 22.
NOTE
The steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD)
and is typically 620 mV.
The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its
quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver
increases exponentially in most case from 20 MHz to 50 MHz. This is due to the overlap current that flows
between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed
current between its output without any substantial overlap current. This is similar to some ECL and PECL
devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires > 80% less
current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing
RS-422 drivers.
The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when
the transmission of data is not required.
12
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8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 LVDS Fail-Safe
This section addresses the common concern of fail-safe biasing of LVDS interconnects, specifically looking at the
DS90LV047A driver outputs and the DS90LV048A receiver inputs.
The LVDS receiver is a high-gain, high-speed device that amplifies a small differential signal (20 mV) to CMOS
logic levels. Due to the high gain and tight threshold of the receiver, take care to prevent noise from appearing as
a valid signal.
The internal fail-safe circuitry of the receiver is designed to source or sink a small amount of current, providing
fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated, or shorted receiver
inputs.
1. Open Input Pins. The DS90LV048A is a quad receiver device, and if an application requires only 1, 2, or 3
receivers, the unused channel(s) inputs must be left OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high value pullup and pulldown resistors to set the output
to a HIGH state. This internal circuitry ensures a HIGH, stable output state for open inputs.
2. Terminated Input. If the DS90LV047A driver is disconnected (cable unplugged), or if the DS90LV047A
driver is in a TRI-STATE or power-off condition, the receiver output is again in a HIGH state, even with the
end of cable 100-Ωtermination resistor across the input pins. The unplugged cable can become a floating
antenna which can pick up noise. If the cable picks up more than 10 mV of differential noise, the receiver
may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not
differential, a balanced interconnect must be used. Twisted pair cable offers better balance than flat ribbon
cable.
3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0-V
differential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (GND to 2.4 V). It is only supported with inputs shorted and no
external common-mode voltage applied.
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Feature Description (continued)
External lower value pullup and pulldown resistors (for a stronger bias) may be used to boost fail-safe in the
presence of higher noise levels. The pullup and pulldown resistors should be in the 5-kΩto 15-kΩrange to
minimize loading and waveform distortion to the driver. The common-mode bias point should be set to
approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry.
Figure 22. Driver Output Levels
8.4 Device Functional Modes
Table 1 lists the functional modes DS90LV047A.
Table 1. Truth Table
ENABLES INPUT OUTPUTS
EN EN* DIN DOUT+ DOUT−
H L or Open L L H
H H L
All other combinations of ENABLE inputs X Z Z
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS90LV047A has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of
the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and
the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise
isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.
9.2 Typical Application
Figure 23. Point-to-Point Application
9.2.1 Design Requirements
When using LVDS devices, it is important to remember to specify controlled impedance PCB traces, cable
assemblies, and connectors. All components of the transmission media should have a matched differential
impedance of about 100 Ω. They should not introduce major impedance discontinuities.
Balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable) for noise
reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also
tend to pick up electromagnetic radiation as common-mode (not differential mode) noise which is rejected by the
LVDS receiver.
For cable distances < 0.5 M, most cables can be made to work effectively. For distances 0.5 M ≤d≤10 M,
CAT5 (Category 5) twisted pair cable works well, is readily available and relatively inexpensive.
9.2.2 Detailed Design Procedure
9.2.2.1 Probing LVDS Transmission Lines
Always use high impedance (> 100 kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing gives deceiving results.
9.2.2.2 Data Rate vs Cable Length Graph Test Procedure
A pseudo-random bit sequence (PRBS) of 29−1 bits was programmed into a function generator (Tektronix
HFS9009) and connected to the driver inputs through 50-Ωcables and SMB connectors. An oscilloscope
(Tektronix 11801B) was used to probe the resulting eye pattern, measured differentially at the input to the
receiver. A 100-Ωresistor was used to terminate the pair at the far end of the cable. The measurements were
taken at the far end of the cable, at the input of the receiver, and used for the jitter analysis for this graph
(Figure 16). The frequency of the input signal was increased until the measured jitter (ttcs) equaled 20% with
respect to the unit interval (ttui) for the particular cable length under test. Twenty percent jitter is a reasonable
place to start with many system designs. The data used was NRZ. Jitter was measured at the 0-V differential
voltage of the differential eye pattern. The DS90LV047A and DS90LV048A can be evaluated using the new
DS90LV047-048AEVM.
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Typical Application (continued)
Figure 24 shows very good typical performance that can be used as a design guideline for data rate vs cable
length. Increasing the jitter percentage increases the curve respectively, allowing the device to transmit faster
over longer cable lengths. This relaxes the jitter tolerance of the system allowing more jitter into the system,
which could reduce the reliability and efficiency of the system. Alternatively, decreasing the jitter percentage has
the opposite effect on the system. The area under the curve is considered the safe operating area based on the
above signal quality criteria. For more information on eye pattern testing, please see AN-808 Long Transmission
Lines and Data Signal Quality (SNLA028).
9.2.3 Application Curve
Figure 24. Power Supply Current vs Frequency
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10 Power Supply Recommendations
Although the DS90LV047A draws very little power while at rest. At higher switching frequencies there is a
dynamic current component which increases the overall power consumption. The DS90LV047A power supply
connection must take this additional current consumption into consideration for maximum power requirements.
11 Layout
11.1 Layout Guidelines
• Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals.
• Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put
TTL and LVDS signals on different layers which are isolated by a power/ground plane(s).
• Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
11.1.1 Power Decoupling Recommendations
Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)
0.1-µF and 0.001-µF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the
device supply pin. Additional scattered capacitors over the printed-circuit board improves decoupling. Multiple
vias must be used to connect the decoupling capacitors to the power planes. A 10-µF (35-V) or greater solid
tantalum capacitor must be connected at the power entry point on the printed-circuit board between the supply
and ground.
11.1.2 Differential Traces
Use controlled impedance traces which match the differential impedance of your transmission medium (that is,
cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they
leave the IC (stubs must be < 10 mm long). This helps eliminate reflections and ensure noise is coupled as
common-mode. In fact, we have seen that differential signals which are 1 mm apart radiate far less noise than
traces 3 mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise
induced on the differential lines is much more likely to appear as common-mode which is rejected by the
receiver.
Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase
difference between signals, which destroys the magnetic field cancellation benefits of differential signals and
EMI, results.
NOTE
The velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or
0.0118 in/ps
Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match
differential impedance and provide isolation for the differential lines. Minimize the number or vias and other
discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces must be minimized to maintain common-mode
rejection of the receivers. On the printed-circuit board, this distance must remain constant to avoid discontinuities
in differential impedance. Minor violations at connection points are allowable.
11.1.3 Termination
Use a termination resistor which best matches the differential impedance or your transmission line. The resistor
must be between 90 Ωand 130 Ω. Remember that the current mode outputs need the termination resistor to
generate the differential voltage. LVDS does not work without resistor termination. Typically, connecting a single
resistor across the pair at the receiver end will suffice.
8
7
Decoupling Cap
6
5
4
3
2
1
9
10
11
12
13
14
15
16
VCC
DIN2
DIN1
EN
DIN3
DIN4
EN*
GND
DOUT4-
DOUT4+
DOUT3+
DOUT3-
DOUT2-
DOUT2+
DOUT1+
DOUT1-
DS90LV047A
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
ROUT2
ROUT1
EN
ROUT3
ROUT4
EN*
GND
DS90LV048A
RIN4-
RIN4+
RIN3+
RIN3-
RIN2-
RIN2+
RIN1+
RIN1-
LVCMOS
Inputs
VCC Decoupling Cap
Series Termination (optional)
Series Termination (optional)
LVCMOS
Outputs
Input Termination
(Required)
17
DS90LV047A
www.ti.com
SNLS044D –MAY 2000–REVISED JULY 2016
Product Folder Links: DS90LV047A
Submit Documentation FeedbackCopyright © 2000–2016, Texas Instruments Incorporated
Layout Guidelines (continued)
Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination
to the receiver inputs must be minimized. The distance between the termination resistor and the receiver should
be < 10 mm (12 mm maximum).
11.2 Layout Example
Figure 25. Layout Recommendation
18
DS90LV047A
SNLS044D –MAY 2000–REVISED JULY 2016
www.ti.com
Product Folder Links: DS90LV047A
Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
•LVDS Owner's Manual (SNLA187)
•AN-808 Long Transmission Lines and Data Signal Quality (SNLA028)
•AN-977 LVDS Signal Quality: Jitter Measurements Using Eye Patterns Test Report #1 (SNLA166)
•AN-971 An Overview of LVDS Technology (SNLA165)
•AN-916 A Practical Guide to Cable Selection (SNLA219)
•AN-805 Calculating Power Dissipation for Differential Line Drivers (SNOA233)
•AN-903 A Comparison of Differential Termination Techniques (SNLA034)
•AN-1194 Failsafe Biasing of LVDS Interfaces (SNLA051)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS90LV047ATM NRND SOIC D 16 48 Non-RoHS &
Non-Green Call TI Call TI -40 to 85 DS90LV047A
TM
DS90LV047ATM/NOPB ACTIVE SOIC D 16 48 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS90LV047A
TM
DS90LV047ATMTC NRND TSSOP PW 16 92 Non-RoHS &
Non-Green Call TI Call TI -40 to 85 DS90LV
047AT
DS90LV047ATMTC/NOPB ACTIVE TSSOP PW 16 92 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS90LV
047AT
DS90LV047ATMTCX/NOPB ACTIVE TSSOP PW 16 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS90LV
047AT
DS90LV047ATMX/NOPB ACTIVE SOIC D 16 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS90LV047A
TM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS90LV047ATMTCX/NO
PB TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
DS90LV047ATMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS90LV047ATMTCX/NOP
BTSSOP PW 16 2500 367.0 367.0 35.0
DS90LV047ATMX/NOPB SOIC D 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
BNOTE 4
4.5
4.3
A
NOTE 3
5.1
4.9
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
89
16
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
89
16
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