19-1156; Rev 1; 7/97 MAX LAA +2./V, Low-Power, 10-Bit Serial ADCs in SO-8 General Description The MAX1242/MAX1243 are low-power, 10-bit analog- to-digital converters (ADCs) available in 8-pin pack- ages. The MAX1242 operates with a single +2.7V to +3.6V supply, and the MAX1243 operates with a single +2.7V to +5.25V supply. Both devices feature a 7.5us successive-approximation ADC, a fast track/hold (1.5us), an on-chip clock, and a high-speed, 3-wire ser- ial interface. Power consumption is only 3mW (Vpp = 3V) at the 73ksps maximum sampling speed. A 2vA shutdown mode reduces power at slower throughput rates. The MAX1242 has an internal 2.5V reference, while the MAX1243 requires an external reference. The MAX1243 accepts signals from OV to Vref, and the reference input range includes the positive supply rail. An exter- nai clock accesses data from the 3-wire interface, which connects directly to standard microcontroller 1/0 ports. The interface is compatible with SPI, QSPi, and Microwire. Excellent AC characteristics and very low power com- bined with ease of use and small package size make these converters ideal tor remote-sensor and data- acquisition applications, or for other circuits with demanding power consumption and space require- ments. The MAX1242/MAX1243 are available in 8-pin DIP and SO packages. Applications Portable Data Logging Process Contro! Monitoring Test Equipment Temperature Measurement lsolated Data Acquisition Pin Configuration TOP VIEW a Vo [11] rs | SCLK At [2] AAAXLAA [77 6 anpN MAX1242 SHON [3] Igavjoqg |S.) DouT REF 4 il GND DIP/SO Features # Single-Supply Operation: +2.7V to +3.6V (MAX1242) +2,7V to +5.25V (MAX1243) # 10-Bit Resolution * Internal 2.5V Reference (MAX1242)} # Smali Footprint: 8-Pin DIP and SO Packages @ Low Power: 3.7mW (73ksps, MAX1242) 3mW (73ksps, MAX1243) 66pW (1ksps, MAX1243) 5yW (power-down mode) Internal Track/Hold @ SPI'"/QSPI/Microwire 3-Wire Serial Interface @ Pin-Compatible 12-Bit Upgrades: MAX1240/MAX1241 Ordering Information PIN- INL. PART TEMP.RANGE package (LSB) MAX1242CCPA O to +70C 8 Plastic DIP te MAX1242DCPA O0C to +70C = 8 Plastic DIP, +1 MAX1242CCSA = OC: to +70C = B SO +e MAX1242DCSA = OC to +70C = 8 SO +f MAX{242CEPA -40C10+85C 8Plastic DIP* = + Ye MAX1242DEPA -40C to +85C = @ Plastic DIP* 1 *Contact factory tor availability. Ordering information continued at end of data sheet. Functional Diagram [aw |: MAX 1 | REFERENCE J MAX1242 + MAX1242 ONLY MAXT243 REF > 4} tle 4 15 GND SPI and QSPi are trademarks of Motorola, inc. Microwire is a trademark of National Semiconductor Corp. MAMAXLAA Maxim Integrated Products 7-217 For free samples & the latest literature: http:/;www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. : : .MAX1242/MAX1 243 +2.7V, Low-Power, 10-Bit Serial ADCs in SO-8 ABSOLUTE MAXIMUM RATINGS Vop to GND... cde daeveneseeverevaeventvansvttereenssetes -0.3V to +6V AIN to GND... -0.3V to (Vpp + 0.3V} REF to GND wo... -0.3V to (Vpp + 0.3V) Digital Inputs to GND. eee ereerenerreee -0.3V to +6V DOUT to GND...... -0.3V to (Vpp + 0.3V) DOUT Current... ceccccseenetenseereteesseaveeesectensterssecnuers 25mMA Continuous Power Dissipation (Ta = +70C) Plastic DIP (derate 9.09mW/C above +70C)........... 727mW SO (derate 5.88mW/C above +70C).......... 471m CERDIP (derate 8. 0OmW/C above +70C) 00... 640mWw Operating Temperature Ranges MAX1242/MAX1243_ CA ccc ceececter eres OPC to +70C MAX1242/MAX1243 E_A.. -40C to +85C MAX1242/MAX1243_MJA .. . 55C to +125C Storage Temperature Range............. .- 60C to +150C Lead Temperature (soldering, 10S6C)...0.00 eee +300C Stresses beyond those fisied under Absolute Maximum Ralings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods ray affect device reliability. ELECTRICAL CHARACTERISTICS (Vop = +2.7V to +3.6V (MAX1242), Vop = +2,7V to +5.25V (MAX1243); 73ksps; fscLk = 2. 1MHz (50% duty cycle); MAX12424 7UF capacitor at REF pin, MAX1243external reference; VREF = 2.5V applied to REF pin: Ta = TMIN to Tmax: unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS DC ACCURACY (Nore 1) Resolution 10 Bits : MAX1242C/MAX1243A +05 Relative Accuracy (Note 2) MAXI 242) MAX1243B <0 LSB Differential Nonlinearity DNL No missing codes over temperature +1 LSB MAX1242C/MAX1243A +1 Offset Error MAX1242D/MAX1243B re) LSB ; MAX1242C/MAX1243A +1 Gain Error (Note 3) MAX12420/MAX1243B 22 LSB Gain Temperature Coefficient 0.25 pom/c DYNAMIC SPECIFICATIONS (10kHz sine-wave input, OV to 2.5Vp-p, 73ksps, fsck = 2.1MHz) ignal-to-Noise Plus Detarion Ratio SINAD 66 a6 Tatal Harmonic Distortion THD Up to the Sth harmonic -70 db Spurious-Free Dynamic Range SFDR 70 dB Smail-Signal Bandwidth - 30B rolloff 2.25 MHz Fuil-Power Bandwidth 1.0 MHz CONVERSION RATE Conversion Time tCONV 85 7.5 us Track/Hald Acquisition Time taca 1.5 us Throughput Rate fsck = 2. MHz 73 ksps Aperture Delay tap Figure 9 30 as Aperture Jitter <50 ps ANALOG INPUT Input Voltage Range 0 VREF Vv input Capacitance 16 pF 7-218 MAAXLAA+2.4V, Low-Power, 10-Bit Serial ADCs in SO-8 ELECTRICAL CHARACTERISTICS (continued) (Vpp = +2.7V to +3.6V (MAX1242), Vop = +2.7V to +5.25V (MAX1243); 73ksps; fscLk = 2. 1MHz (50% duty cycle); MAX12424,7pF capacitor at REF pin, MAX1243-external reference; VreF = 2.5V applied to REF pin; Ta = TMIN to Tmax; unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS INTERNAL REFERENCE (MAX1242 only) REF Output Voltage Ta = +25C (Note 4) 2470 2500 2.530 Vv REF Short-Circuit Current 30 mA REF Temperature Coefficient MAX1242 +30 pom/eC Load Regulation (Note 5) OmA to 0.2mA output load 0.35 mv Capacitive Bypass at REF 4.7 LF EXTERNAL REFERENCE (Vacr = 2.5V) input Voltage Range 1.00 40. y Vv input Current 100 150 pA Input Resistance 18 25 kQ REF Input Current in Shutdown SHDN = OV 20.01 10 HA Capacitive Bypass at REF 0.1 HF DIGITAL INPUTS: SCLK, CS, SHDN SCLK, CS Input High Voltage VIH = oe (MA 243) - Vv SCLK, CS Input Low Voltage Vit 0B V SCLK, CS input Hysteresis VHYST 0.2 V SCLK, C5 Input Leakage tin Vin = OV or Vop 20.01 +1 pA SCLK, CS Input Capacitance Cin (Note 6) 15 pF SHON Input High Voltage VsH Vop - 0.4 V SHON Input Low Voltage VSL 0.4 Vv SHDN Input Current SHDN = OV or Vop #4.0 pA SHDN Input Mid Voltage Vso 11 Vop- 1.1 Vv SHDN Voltage, Floating Vett | SHDN = float Vop / 2 V SHON Max Allowed Leakage, SHON = float +100 nA Mid Input DIGITAL OUTPUT: DOUT Output Voltage Low VoL os _~ a3 Output Voltage High VOH ISOURCE = 0.5mA Vpn - 0.5 Vv Three-State Leakage Current IL CS = Vop #0.01 +10 LA Three-State Output Capacitance] Cour | CS = Vpp (Note 6) 15 pF POWER REQUIREMENTS MAX 1242 27 3.6 Supply Voltage VoD Maxi243 27 5.25 v Operating mode (MAX1242) | Vpp = 3.6V 1.4 2.0 . Vpp = 3.6V 0.9 15 mA Supply Current Inn | Operating mode (MAX1243) Te oey 16 25 Vopo = 3.6V 1.9 10 Power-down was TE DEV a5 15 LA Supply Rejection (Note 7) PSR Vpo = Vb0, min to Vpp, max, full-scale input +0.3 mV MAXUM rz =MAX1242/MAX1 243 +2.7V, Low-Power, 10-Bit Serial ADCs in SO-8 TIMING CHARACTERISTICS (VoD = +2.7V to +3.6V (MAX1242), Vop = +2.7V to +5.25V (MAX1243); Ta = TMIN to Tax; unless otherwise noted.) (Figure 9) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Acquisition Time taco | CS = Vpp (Note 8) 15 us . Figure 1, MAX124__C/E 20 200 SCLK Fall to Output Data Valid too Cron b = 50pF MAX124__M 20 340 ns CS Fall to Output Enable tov Figure 1, CLoap = 50pF 240 ns Rise to Output Disable tt Figure 2, CLoap = SOpF 240 ns SCLK Clock Frequency fscL_k 0 2.1 MHz SCLK Pulse Width High {CH 200 ns SCLK Pulse Width Low tCL 206 ns SCLK Low to CS Fall Setup Time | _ tcso 50 ns DOUT Rise to SCLK Risa (Note 6) {STR 0 ns CS Pulse Width tcs 240 ns Note 1: Tested at Vop = +2.7V. Note 2: Relative accuracy is the deviation of the analog value at any Code from its theoretical value after the full-scale range and offset have been calibrated. Note 3: Offset nuiled. Note 4: Sample tested to 0.1% AQL. Note 5: External load should not change during conversion for specified accuracy. Note 6: Guaranteed by design. Not subject to production testing. Note 7: Measured as [Ves (Vop, min} - VFS (VDD, max). Note 8: To guarantee acquisition time, taca is the maximum time the device takes ta acquire the signal, and is also the minimum time needed fcr the signal to be acquired. +2.V 6k DOUT + T DOoUT ek Cian = S00F Cr gap = S0RF L => pena = =~ OGND a) High-Z to Voy anid Vg, t0 Voy, b) High-2 fo Vey and Voy to Va, Figure 1. Load Circuits for DOUT Enable Tine 427V 6k BOUT + + BOUT 6k L Chon = 500F Loap = S0pF = =DGND Lt L DGND a} Voy; to High-2 b) Vo, to High-2 Figure 2. Load Circuits for DOUT Disable Time 7-220 MAAK+2,/V, Low-Power, 10-Bit Serial ADCs in SO-8 Typical Operating Characteristics (Vop = +3.0V, VREF = 2.5V, fscLk = 2.1MHz, CLoap = 20pF, Ta = +25C, unless otherwise noted.) SUPPLY CURRENT SHUTDOWN SUPPLY CURRENT INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE 2.00 j 40 Z 25015 a og 3 5 = MAXi242 _ Casa Tet 3 = aot z 2 5 we 150 7 maxizee 5 25 S 2.5005 2 = 3 S125 z 20 % 25000 PJ 5 Chong = S0pF 2 15 o S100 , MAX1242/MAX1243 g 245 a Z x = 075 hen Bos 2.4990 CODE = 1010101000 0.50 0 2.4985 225 278 3.25 375 425 475 5.25 22 275 325 375 425 475 525 225 275 4.25 ays SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SHUTDOWN CURRENT INTERNAL REFERENCE VOLTAGE SUPPLY CURRENT vs. TEMPERATURE vs. TEMPERATURE vs. TEMPERATURE 3.00 3 2501 : z MAX1242 g 7 3 _ 275 a = 2500 Vor i = 3 250 = 2.499 Q = = 23 2.498 s S 200 a > z & 2497 = 8 175 a 3 MAX1243 & 150 Be RLoag = 1.25 = 2495 CODE = 1910101000 1.00 2.494 o 20 2m 6 10 140 0-20 tO -60 ~40 20 -@ 20 40 60 80 100 120 140 TEMPERATURE (C) TEMPERATURE (C) TEMPERATURE (C) INTEGRAL NOMLINEARITY INTEGRAL NONLINEARITY INTEGRAL WOMLINEARITY vs. SUPPLY VOLTAGE vs. TEMPERATURE vs. CODE 0.15 2 g =2V 0.10 = 0.05 a a 4 z z MAX1242 0.05 t tt aH MAX1242 010 MAX1243 MAX1243 oo 0 0.15 225 275 325 375 425 475 5.25 -60 40-20 0 20 40 60 80 100 120 140 0 256 512 768 1024 SUPPLY VOLTAGE (V) TEMPERATURE (C) CODE MAAXLAA 7-221 : :MAX 1242/MAX1 243 +2.7V, Low-Power, 10-Bit Serial ADCs in SO-8 Pin Description PIN NAME FUNCTION Vop Positive Supply Voltage: +2.7V to +3.6V (MAX1242); +2.7V to +5.25V (MAX1243) 2 AIN Sampling Analog Input, OV to VRer range Three-Leve! Shutdown Input. Pulling SHDN tow shuts the MAX1242/MAX1243 down to 15uA (max) 3 SHDN supply current. Both MAX1242 and MAX1243 are fully operational with either SHDN high or floating. For the MAX1242, pulling SHDN high enables the internal reference, and letting SHDN float disables the internat reference and allows for the use of an external reference. Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output for MAX1242; 4 REF bypass with a 4.7LF capacitor. External reference voltage input for MAX1243, or for MAX1242 with the internal reference disabled. Bypass REF with a minimurn of 0.1uF when using an external reference, 5 GND Analog and Digital Ground 6 DOUT Serial-Data Output. Data changes state at SCLKs falling edge. High impedance when CS is high. 7 te Active-Low Chip Select. initiates conversions on the falling edge. When CS is high, DOUT is high ~ impedance. 8 SCLK Serial-Clock input. SCLK ciocks data out at rates up to 2.1MHz. _Detailed Description Converter Operation The MAX1242/MAX1243 use an input track/hoid (T/H) and successive-approximation register (SAR) circuitry {o convert an analog input signal to a digital 10-bit out- put. Figure 3 shows the MAX1242/MAX12493 in their simplest configuration. The MAX1242/MAX1243 convert input signals in the OV to Veer range in Sys, including T/H acquisition time. The MAX1242s internal reference is trimmed to 2.5V, while the MAX1243 requires an external reference. Both devices accept external refer- ence voltages from 1.0V to Vpp. The serial interface requires only three digital lines (SCLK, CS, and DOUT) and provides an easy interface to microprocessors (yPs}. The MAX1242/MAX1243 have two modes: normal and shutdown. Pulling SHDN low shuts the device down and reduces supply current below 10pA (Vpp < 3.6V), while pulling SHDN high or leaving it open puts the devices into operational mode. A conversion is initiated by pulling CS low. Tne conversion result is available at DOUT in unipolar serial format. The serial-data stream consists of a high bit, signaling the end of conversion (EOC), followed by the data bits (MSB first). Analog Input Figure 4 illustrates the sampling architecture of the ana- log-to-digital converter's (ADC's) comparator. The fuil- scale input voltage is set by the voltage at REF. 7-222 Track/Hold in track mode, the analog signal is acquired and stored in the internal hold capacitor. in hold mode, the T/H switch opens and maintains a constant input to the ADCs SAR section. During acquisition, the analog input AIN charges capacitor Cuo_p. Bringing Cs low ends the acquisition interval. At this instant, the T/H switches the input side of Cuaip to GND. The retained charge on Cyo.p repre- senis a sample of the input, unbalancing node ZERO at the comparators input. In hold mode, the capacitive digital-to-analog converter (DAC) adjusts during the remainder of the conversion cycle to restore node ZERO to OV within the limits of 10- bit resolution. This action is equivalent to transferring a charge from Cyo.p to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. At the conversions end, the input side of Cyuoip switches back to AIN, and Cuoip charges to the input signal again. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signals source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time. taca, is the maximum time the device takes to acquire the signal and the minimum time needed for the signal to be acquired. Acquisition time is calculated by: taca = 7(Rg + Rin) x 16pF MAAXISA+2./V, Low-Power, 10-Bit Serial ADCs in SO-8 +2.7V to +3.6V" fe be ate 1 ANALOG INPUT 2 OV TO Veer AIN Gs MAXIMA MAXI242 MAN1243 5 | SHON BOUT pi \__>- : 5 REFERENCE p+ REF GND | + INPUT ma + Vop, MAx = +5.25V (MAX1243) 4. 7UF, MAX1242 O.1uF, MAX1243 SERIAL INTERFACE SHUTDOWN a CAPACITIVE DAG REF -~~~--{} 7 COMPARATOR AIN TRACK iypyy 109 ZERO lt *6pF HOLD ? AT THE SAMPLING INSTANT, THE INPUT SWITCHES FROM AIN TO GND. Gno Figure 3. Operational Diagram where Riy = 9kQ, Rg = the input signals source imped- ance, and tacg is never less than 1.5ys. Source imped- ances below 4kQ do not significantly affect the ADCs AC performance. Higher source impedances can be used if a 0.01yF capacitor is connected to the analog input. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC's input signal bandwidth. Input Bandwidth The ADC's input tracking circuitry has a 2.25MHz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic sig- nais with bandwidths exceeding the ADCs sampling rate by using undersampling techniques. To avoid aliasing of unwanted high-frequency signals into the frequency band of interest, anti-alias filtering is recom- mended. Analog Input Protection internal protection diodes, which clamp the analog input to Vop and GND, allow the input to swing from GND - 0.3V to Vopp + 0.3V without damage. However, for accurate conversions near full scale, the input must not exceed Vpp by more than 5OmvV, or be lower than GND by 50mV. if the analog input exceeds 50mV beyond the supplies, limit the input current to 2mA. Figure 4. Equivaient fnput Circuit internal Reference (MAX1242) The MAX1242 has an on-chip voltage reference trimmed to 2.5V. The internal reference output is con- nected to REF and also drives the internal capacitive DAC. The output can be used as a reference voltage source for other components and can source up to 400uA. Bypass REF with a 4.7pF capacitor. Larger capacitors increase wake-up time when exiting shut- down (see Using SHDN to Reduce Supply Current). The internal reference is enabled by pulling the SHDN pin high. Letting SHDN float disables the internal refer- ence, which allows the use of an external reference, as described in the External Reference section. External Reference The MAX1242/MAX1243 operate with an external refer- ence at the REF pin. To use the MAX1242 with an external reference, disable the internal reference by let- ting SHDN float. Stay within the voltage range 1.0V to Vop to achieve specified accuracy. The minimum input impedance is 18kQ for DC currents. During conver- sion, the external reference must be able to deliver up to 250uA of DC load current and have an output impedance of 10 or less. The recommended mini- mum value for the bypass capacitor is 0.1uF. If the ref- erence has higher output impedance or is noisy, bypass it close to the REF pin with a 4 7HF capacitor. 7-223 MAAXLIA = :MAX1 242/MAX1 243 +2.7V, Low-Power, 10-Bit Serial ADCs in $O-8 Serial Interface initialization after Power-Up and Starting a Conversion When power is first applied, and if SHDN is not pulled low, it takes the fully discharged 4.7uF reference bypass capacitor up to 20ms to provide adequate charge for specified accuracy. With an external refer- ence, the internal reset time is 10y5 after the power supplies have stabilized. No conversions should be performed during these times. To start a conversion, pull CS low. At CS's falling edge, the T/H enters its hold mode and a conversion is initiat- ed. After an internally timed conversion period, the end of conversion is signaled by DOUT pulling high. Data can then be shifted out serially with the external clock. Using SHDN to Reduce Supply Current Power consumption can be reduced significantly by shutting down the MAX1242/MAX1243 between con- versions. Figure 6 shows a plot of average supply cur- rent vs. conversion rate, Bacause the MAX1243 uses an external reference voltage (assumed to be present continuously), it wakes up from shutdown more quick- ly, providing lower average supply currents. The wake- up time, twaKE, is the time from SHDN deasserted to the time when a conversion may be initiated (Figure 5). For the MAX1242, this time depends on the time in shutdown (Figure 7) because the external 4.7yF refer- ence bypass capacitor loses charge slowly during shutdown. The MAX1243's wake-up time is largely dependent on the external reference's power-up time. {f the external reference is not shut down, the wake-up time is approximately 4ys. }+ COMPLETE CONVERSION SEQUENCE ZL BF SHON \_ ff ad twaKE >| pour _ [hy CONVERSION 0 POWERED UP >|- POWERED DOWN CONVERSION 1 |~~_ POWERED UP are Figure 5, Shutdown Sequence bg 40,000 Vog = Vpgr = 3.0 | Rupap ==, CLoap = SOpF wey = 1000 F- cone = o1ato10100 / / = z oa S100 f S 2 10 f<. i 77 r 4 == : or) 10G~COtKSSCdOk 100 CONVERSIONS/SEC Wa SE a8 06 04 POWER-UP DELAY {ms} 02 ao 0.001 0.01 O41 i 10 TIME IN SHUTDOWN (sec) Figure 6. Average Supply Current vs. Conversion Rate 7-224 Figure 7. Typical Referance-Buffer Power-Up Delay vs. Time in Shutdown PRAAXIMA+2.7V, Low-Power, 10-Bit Serial ADCs in SO-8 cs _{ ae su STU i _ Lo aR EO OOOO OOa____-__ INTERFACE 10LED> |e fORTERSION pe | xe E06 be |< CLOCK QUT SERIAL DATA 8 TRANS | tne TRACK/HOLD STATE TRACK -~#>|<- HOLD t> |< TRACK p> |<4 HOLD O.24us |#-7.5u5 (tony) | Ops ee_ 125 x 0.4768 = 5.958 _ >a Os sit! CYCLE TIME |~ TOTAL = 13 Pus Figure 8a. Interface Timing Sequence 55 ! woe se UA pour 55 { oy (89 X BB X87 B6 \ Bs X B4 XB3 KX B2 KX Bt YX BO) _ 3 ia _ INTERFACE (OLE o> | CONVERSION |e 0 foe CLOCK OUT SERIAL DATA 4 ID TRACK/HOLD STATE TRACK ~B>| ~~ HOLD te (-< TRACK_ ____|- 010 0.24us | <-7.51s (tog) |t Qus 2 et 10.5 x 0.47618 = 5,5 >| <-> i | CYCLE TIME fog@ 0 212 2635 Figure 8b. Interface Timing SequenceMinimum Cycle Time e| tH [<A | | i > | iat: tc. [<+ e| ota tov + tenny + | o0 - Pe a RS ' | ap Of? Thera | >| + > sin INTERNAL __ (TRACK/ACQUIRE} (HOLD) oe (TRACK/ACQUIRE} [ TH ! Figure 9. Detailed Serial-interface Timing MAXUM 7-225 = x : : x : a)MAX1242/MAX1243 +2Z2,.1/V, Low-Power, 10-Bit Serial ADCs in SO-8 External Clock The actual conversion does not require the external clock. This allows the conversion result to be read back at the pPs convenience at any clock rate up to 2.1MHz. The clock duty cycle is unrestricted if each clock phase is at least 200ns. Do not run the clock while a conversion is in progress. Timing and Control Conversion-start and data-read operations are con- trolied by the CS and SCLK digital inputs. The timing diagrams of Figures 8 and 9 outline serial-interface operation. A GS falling edge initiates a conversion sequence: the T/H stage holds the input voltage, the ADC begins to canvert, and DOUT changes from high impedance to logic iow. SCLK must be kept low during the conver- sion. An internal register stores the data when the con- version is in progress. EOC is signaled by DOUT going high. DOUT's rising edge can be used as a framing signal. SCLK shifts the data out of this register any time alter the conversion is complete. DOUT transitions on SCLKs falling edge. The next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits. Since there are 10 data bits, two sub-bits, and ane teading high bit, at least 13 falling clock edges are needed to shift out these bits. Extra clock pulses occur- ring after the conversion result has been clocked out, and prior to a rising edge of CS, produce trailing zeros at DOUT and have no effect on converter operation. For minimum cycle time, use DOUTs rising edge as the EOC signal and then clock out the data with 10.5 clock cycles at full speed (Figure 8b). Pull CS high after reading the conversion's LSB. After the specified mini- mum time, tcs, pull CS fow again to initiate the next conversion. Output Coding and Transfer Function The data output from the MAX1242/MAX1 243 is binary. Figure 10 depicts the nominal transfer function. Code transitions occur halfway between successive-integer LSB values. If VaeF = 2.5V, then 1LSB = 2.44mV or 2.5V / 1024. _Applications Information Connection to Standard Interfaces The MAX1242/MAX1243 serial interface is fully compat- ible with SP}, QSPI, and Microwire standard serial inter- faces (Figure 11). 7-226 OUTPUT CODE FULLSCALE WA TRANSITION 11.410 11...101 . { | 4 ! / / ; FS = Vper - 1LS8 ye | 1098 Yake 4024 ! / i / ! 90...011 / ' 00...010 00,..008 ; oo... Ltypiyp yp ply oot 2 3 A ogg INPUT VOLTAGE (LSB) FS - 3/2188 Figure 10. Unipolar Transfer Function, Full Scale (FS) = Vaer - 1LSB, Zero Scale (ZS) = GND yo e-] oS SCK -e-| SCLK Miso |~q_J pour a MAXIM MAX1242 _ MAX1243 5 a) SP! cS o | 6S stk }___| scix go |<<} pour if 8 JAAXLAN MAX1242 & MAX1243 b) OSPI oOo --__-e] 65 Sk wv] SCLK st bw DOUT MAXIM MAX1242 MAXI1243 ) MIGROWIRE Figure 71, Common Serial-interface Connections to the MAX 1242/MAX 1243 PRAMASA+2.7V, Low-Power, 10-Bit Serial ADCs in SO-8 |< 1ST BYTE READ 1>- | |~<-2ND BYTE READ fi | uF 4 HH] (HHH HR ERE BT LPL it ETT EL | Litt ye eh tcow yivivietielvie riyivlielelel HIGH-Z pout = } Cag K GENK 07 XE XS YGF D3 k bX 0X St) lL + 4 MSB LSB EOC Figure 12. SPl/Microwire Serial-Interface Timing (CPOL = CPHA = 0) SCLK Le. on HEHEHE = Tel bow [eT iy Viv iy iy iy Vivi HiGH-2 BOUT A, h <b9 K D3 XK D7 X 06 X D5 KDA X 03K D2 X Di X DO KS) KO MSB LSB EOC Figure 13. QSPI Serial-interface Timing (CPOL = CPHA = 0) If a serial interface is available, set the CPU's serial SPi and Microwire interface in master mode so the CPU generates the ser- ial clock. Choose a clock frequency up to 2.1MHz. +) Use a general-purpose I/O line on the CPU to pull CS low. Keep SCLK low. 2) Wait the maximum conversion time specified before activating SCLK. Alternatively, look for a DOUT rising edge to determine the end of conversion. 3) Activate SCLK for a minimum of 11 clock cycles. The first falling clock edge produces the MSB of the DOUT conversion. DOUT output data transitions on SCLKs falling edge and is available in MSB-first for- mat. Observe the SCLK-to-DOUT valid timing char- acteristic. Data can be clocked into the pP on SCLKs rising edge. 4) Pull 6S high at or after the 11th falling clock edge. If CS remains low, the two sud-bits and trailing zeros are clocked out after the LSB. 5) With CS = high, wait ihe minimum specified time, tcs, before initiating a new conversion by pulling CS low. if a conversion is aborted by pulling CS high before the conversions end, wait the minimum acquisition time, taca, before starting a new conversion. Data can be output in two bytes or continuously, as shown in Figures 8a and 8b. The bytes contain the resuit of the conversion padded with one leading 1, two sub-bits, and trailing Os if SCLK is still active with CS keot low. MAAXIMA When using SPI or QSPI, set CPOL = 0 and CPHA = 0. Conversion begins with a CS falling edge. DOUT goes low, indicating a conversion is in progress. Wait until DOUT goes high or until the maximum specified 7.5us conversion time elapses. Two consecutive 1-byte reads are required to get the full 10+2 bits from the ADC. DOUT output data transitions on SCLK's falling edge and is clocked into the EP on SCLKs rising edge. The first byte contains a leading 1, and seven bits of conversion result. The second byte contains the remain- ing three bits, two sub-bits, and three trailing zeras. See Figure 11 for connections and Figure 12 for timing. QsPI Set CPOL = CPHA = 0. Unlike SPI, wnich requires two {-byte reads to acquire the 10 bits of data from the ADC, QSPI allows the minimum number of clock cycles neces- sary to clock in the data. The MAX1242/MAX1243 require 11 clock cycles from the uP to clock out the 10 bits of data. Additional clock cycles clock out the two sub-bits followed by trailing zeros (Figure 13). The maximum clock frequency to ensure Compatibility with QSPI is 2.097MHz. Layout and Grounding For best performance, use printed circuit boards. Wire- wrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digi- tal (especially clock) lines parallel to one another, or digital lines underneath the ADC package. 7-227 : >< wl, 5MAX1242/MAX1 243 +2.7V, Low-Power, 10-Bit Serial ADCs in SO-8 _Ordering Information (continued) PART TEMP.RANGE ACKAGE ase) MAX1242CESA = -40C to +85C =. 8 SO* +'/2 MAX1242DESA 40C to +85C 8 SO HI MAX1242CMJA _-55C to +125C BCERDIP 12 MAX1242DMJA__-55C to +125C @CERDIP +1 MAX1243ACPA OCto+70C aPlasicDIP aia MAX1243BCPA OCto+70C @PlastioDIP a1 MAX1243ACSA OCto+70C 8SO zip MAX1243BCSA OCto+70C 8 SO Ht MAX1243AEPA -40C to +85C 6 Plastic DIP =o MAX1243BEPA 40C to 485C 8 Plastic DIP 1 MAX1243AESA 40C to 485C. 8 SO 22 MAX1243BESA -40C to +85C 8 SO HH MAX1243AMJA 85C to +125C BCERDIP MAX1243BMJA 85C to 125C BCERDIP af *Contact factory for availability. Contact factory for availability and processing to MIL-STD-883. 7-228 TRANSISTOR COUNT: 2559 SUBSTRATE CONNECTED TO GND Chip Information MAAXIIA