8304I Low Skew, 1-to-4 LVCMOS/LVTTL Fanout Buffer Data Sheet GENERAL DESCRIPTION FEATURES The 8304I is a low skew, 1-to-4 Fanout Buffer. The 8304I is characterized at full 3.3V for input VDD, and mixed 3.3V and 2.5V for output operating supply modes (VDDO). Guaranteed output and part-to-part skew characteristics make the 8304I ideal for those clock distribution applications demanding well defined performance and repeatability. * Four LVCMOS / LVTTL outputs * LVCMOS clock input * CLK can accept the following input levels: LVCMOS, LVTTL * Maximum output frequency: 166MHz * Output skew: 60ps (maximum) * Part-to-part skew: 650ps (maximum) * Small 8 lead SOIC package saves board space * 3.3V input, outputs may be either 3.3V or 2.5V supply modes * -40C to 85C ambient operating temperature * Available in lead-free (RoHS 6) compliant package BLOCK DIAGRAM PIN ASSIGNMENT Q0 VDDO VDD CLK GND Q1 CLK Pulldown Q2 8 7 6 5 Q3 Q2 Q1 Q0 8304I 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View Q3 (c)2015 Integrated Device Technology, Inc 1 2 3 4 1 December 10, 2015 8304I Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 VDDO Power 2 VDD Power 3 CLK Input 4 GND Power Power supply ground. Connect to ground. 5 Q0 Output Single clock output. LVCMOS / LVTTL interface levels. 6 Q1 Output Single clock output. LVCMOS / LVTTL interface levels. 7 Q2 Output Single clock output. LVCMOS / LVTTL interface levels. 8 Q3 Output Single clock output. LVCMOS / LVTTL interface levels. Output supply pin. Connect to 3.3V or 2.5V. Positive supply pin. Connect to 3.3V. Pulldown LVCMOS / LVTTL clock input. NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance (per output) RPULLDOWN Input Pulldown Resistor 51 k ROUT Output Impedance 7 (c)2015 Integrated Device Technology, Inc Test Conditions V ,V DD DDO Minimum Typical = 3.465V 2 Maximum Units 4 pF 15 pF December 10, 2015 8304I Data Sheet ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 112.7C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Power Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 18 mA IDDO Output Supply Current 11 mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C Symbol Parameter VDD VDDO IDD IDDO Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V Output Supply Voltage 2.375 2.5 2.625 V Power Supply Current 18 mA Output Supply Current 11 mA TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40C TO 85C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current VDD = VIN = 3.465V IIL Input Low Current VDD = 3.465V, VIN = 0V -5 A Refer to NOTE 1 2.6 V IOH = -16mA 2.9 V IOH = -100uA 3 V VOH VOL Test Conditions Output High Voltage Output Low Voltage Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 1.3 V 150 A Refer to NOTE 1 0.5 V IOL = 16mA 0.25 V IOL = 100uA 0.15 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Section, "3.3V Output Load Test Circuit". (c)2015 Integrated Device Technology, Inc 3 December 10, 2015 8304I Data Sheet TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current VDD = VIN = 3.465V IIL Input Low Current VDD = 3.465V, VIN = 0V VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 1.3 V 150 A -5 A 2.1 V 0.5 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Section, "3.3V/2.5V Output Load Test Circuit". TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum fMAX Output Frequency tpLH Propagation Delay, Low-to-High; NOTE 1 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section tsk(o) Output Skew; NOTE 2, 4 tsk(pp) Part-to-Part Skew; NOTE 3, 4 tR Output Rise Time 30% to 70% 250 tF Output Fall Time 30% to 70% odc Output Duty Cycle 166MHz Typical 2 125MHz, Integration Range 12kHz - 20MHz Maximum Units 166 MHz 3.3 ns 0.17 = 133MHz ps 50 ps 600 ps 500 ps 250 500 ps 40 60 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at 166MHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. (c)2015 Integrated Device Technology, Inc 4 December 10, 2015 8304I Data Sheet TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum 2.3 Typical Maximum Units 166 MHz 3.7 ns 60 ps fMAX Output Frequency tpLH Propagation Delay, Low-to-High; NOTE 1 166MHz tsk(o) Output Skew; NOTE 2, 4 = 133MHz tsk(pp) Part-to-Part Skew; NOTE 3, 4 650 ps tR Output Rise Time 30% to 70% 250 500 ps tF Output Fall Time 30% to 70% 250 500 ps odc Output Duty Cycle 40 60 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at 166MHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. (c)2015 Integrated Device Technology, Inc 5 December 10, 2015 8304I Data Sheet ADDITIVE PHASE JITTER (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels Additive Phase Jitter @ 125MHz (12kHz to 20MHz) = 0.17ps typical This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. (c)2015 Integrated Device Technology, Inc 6 December 10, 2015 8304I Data Sheet PARAMETER MEASUREMENT INFORMATION 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW PART-TO-PART SKEW OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD PROPAGATION DELAY (c)2015 Integrated Device Technology, Inc 7 December 10, 2015 8304I Data Sheet RELIABILITY INFORMATION TABLE 5. JAVS. AIR FLOW TABLE JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W 200 500 128.5C/W 103.3C/W 115.5C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for 8304I is: 416 PACKAGE OUTLINE AND DIMENSIONS PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC TABLE 6. PACKAGE DIMENSIONS - SUFFIX M SYMBOL Millimeters MINIMUN N MAXIMUM 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 Reference Document: JEDEC Publication 95, MS-012 (c)2015 Integrated Device Technology, Inc 8 December 10, 2015 8304I Data Sheet TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 8304AMILF 8304AMIL 8 lead "Lead Free" SOIC Tube -40C to +85C 8304AMILFT 8304AMIL 8 lead "Lead Free" SOIC Tape and Reel -40C to +85C (c)2015 Integrated Device Technology, Inc 9 December 10, 2015 8304I Data Sheet REVISION HISTORY SHEET Rev B B Table Page 3B 3 LVCMOS/LVTTL DC Characteristics Table, added IOH and IOL Test Conditions to VOH and VOL rows. T7 1 8 Features Section - added lead-free bullet. Ordering Information Table - added lead-free part number, marking and note. Updated datasheet format. 3.3V AC Characteristics Table - added Buffer Additive Phase Jitter spec. Added Buffer Additive Phase Jitter Plot. Ordering Information - Deleted "ICS" from the Part/Order number column. Pin Assignment - corrected "pullup" label to "pulldown" label. Pin Description Table - deleted pullup from note. Pin Characteristics Table - deleted Rpullup row. T4A T1 T2 4 6 9 1 2 2 T7 9 C T7 D D Description of Change Removed ICS in the part numbers. Removed LF note at the bottom of the Ordering Information table. Removed the quantity of 2500 from the Tape & Reel in the Ordering information table. Updated datasheet header and footer. (c)2015 Integrated Device Technology, Inc 10 Date 4/4/02 11/09/06 2/11/09 10/29/10 12/10/15 December 10, 2015 8304I Data Sheet Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. 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