8304AMILFT - INTEGRATED DEVICE TECHNOLOGY

Low Skew, 1-to-4 LVCMOS/LVTTL

Fanout Buffer 8304I

Data Sheet

GENERAL DESCRIPTION

The 8304I is a low skew, 1-to-4 Fanout Buffer. The 8304I is charac-

terized at full 3.3V for input VDD, and mixed 3.3V and 2.5V for output

operating supply modes (VDDO). Guaranteed output and part-to-part

skew characteristics make the 8304I ideal for those clock distribution

applications demanding well deﬁ ned performance and repeatability.

FEATURES

• Four LVCMOS / LVTTL outputs

• LVCMOS clock input

• CLK can accept the following input levels: LVCMOS, LVTTL

• Maximum output frequency: 166MHz

• Output skew: 60ps (maximum)

• Part-to-part skew: 650ps (maximum)

• Small 8 lead SOIC package saves board space

• 3.3V input, outputs may be either 3.3V or 2.5V supply modes

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) compliant package

BLOCK DIAGRAM PIN ASSIGNMENT

8304I

8-Lead SOIC

3.8mm x 4.8mm, x 1.47mm package body

M Package

Top View

VDDO

VDD

CLK

GND

CLK

Pulldown

8304I Data Sheet

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4pF

CPD

Power Dissipation Capacitance

(per output) VDD, VDDO = 3.465V 15 pF

RPULLDOWN Input Pulldown Resistor 51 kΩ

ROUT Output Impedance 7 Ω

Number Name Type Description

DDO Power Output supply pin. Connect to 3.3V or 2.5V.

DD Power Positive supply pin. Connect to 3.3V.

3 CLK Input Pulldown LVCMOS / LVTTL clock input.

4 GND Power Power supply ground. Connect to ground.

5 Q0 Output Single clock output. LVCMOS / LVTTL interface levels.

6 Q1 Output Single clock output. LVCMOS / LVTTL interface levels.

7 Q2 Output Single clock output. LVCMOS / LVTTL interface levels.

8 Q3 Output Single clock output. LVCMOS / LVTTL interface levels.

NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

8304I Data Sheet

TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Power Supply Voltage 3.135 3.3 3.465 V

VDDO Output Power Supply Voltage 3.135 3.3 3.465 V

IDD Power Supply Current 18 mA

IDDO Output Supply Current 11 mA

TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage 2 VDD + 0.3 V

VIL Input Low Voltage -0.3 1.3 V

IIH Input High Current VDD = VIN = 3.465V 150 µA

IIL Input Low Current VDD = 3.465V, VIN = 0V -5 µA

VOH Output High Voltage

Refer to NOTE 1 2.6 V

IOH = -16mA 2.9 V

IOH = -100uA 3 V

VOL Output Low Voltage

Refer to NOTE 1 0.5 V

IOL = 16mA 0.25 V

IOL = 100uA 0.15 V

NOTE 1: Outputs terminated with 50ΩΩ to VDDO/2. See Parameter Measurement Section, “3.3V Output Load Test Circuit”.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

DD 4.6V

Inputs, VI -0.5V to VDD + 0.5 V

Outputs, VO -0.5V to VDDO + 0.5V

Package Thermal Impedance, θ

JA 112.7°C/W (0 lfpm)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress speciﬁ cations only. Functional

operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not

implied. Exposure to absolute maximum rating conditions for ex-

tended periods may affect product reliability.

TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Positive Supply Voltage 3.135 3.3 3.465 V

VDDO Output Supply Voltage 2.375 2.5 2.625 V

IDD Power Supply Current 18 mA

IDDO Output Supply Current 11 mA

8304I Data Sheet

TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C

TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency 166 MHz

tpLH

Propagation Delay,

Low-to-High; NOTE 1 ƒ ≤ 166MHz 2 3.3 ns

tjit Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

125MHz,

Integration Range

12kHz – 20MHz

0.17 ps

tsk(o) Output Skew; NOTE 2, 4 ƒ = 133MHz 50 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 600 ps

tROutput Rise Time 30% to 70% 250 500 ps

tFOutput Fall Time 30% to 70% 250 500 ps

odc Output Duty Cycle 40 60 %

NOTE: Electrical parameters are guaranteed over the speciﬁ ed ambient operating temperature range, which is established

when the device is mounted in a test socket with maintained transverse airﬂ ow greater than 500 lfpm. The device will meet

speciﬁ cations after thermal equilibrium has been reached under these conditions.

NOTE: All parameters measured at 166MHz unless noted otherwise.

NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.

NOTE 2: Deﬁ ned as skew between outputs at the same supply voltage and with equal load conditions.

Measured at VDDO/2.

NOTE 3: Deﬁ ned as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at VDDO/2.

NOTE 4: This parameter is deﬁ ned in accordance with JEDEC Standard 65.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage 2 VDD + 0.3 V

VIL Input Low Voltage -0.3 1.3 V

IIH Input High Current VDD = VIN = 3.465V 150 µA

IIL Input Low Current VDD = 3.465V, VIN = 0V -5 µA

VOH Output High Voltage; NOTE 1 2.1 V

VOL Output Low Voltage; NOTE 1 0.5 V

NOTE 1: Outputs terminated with 50ΩΩΩΩ to VDDO/2. See Parameter Measurement Section, “3.3V/2.5V Output Load Test Circuit”.

8304I Data Sheet

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency 166 MHz

tpLH Propagation Delay, Low-to-High; NOTE 1 ƒ ≤ 166MHz 2.3 3.7 ns

tsk(o) Output Skew; NOTE 2, 4 ƒ = 133MHz 60 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 650 ps

tROutput Rise Time 30% to 70% 250 500 ps

tFOutput Fall Time 30% to 70% 250 500 ps

odc Output Duty Cycle 40 60 %

NOTE: Electrical parameters are guaranteed over the speciﬁ ed ambient operating temperature range, which is established

when the device is mounted in a test socket with maintained transverse airﬂ ow greater than 500 lfpm. The device will meet

speciﬁ cations after thermal equilibrium has been reached under these conditions.

All parameters measured at 166MHz unless noted otherwise.

NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.

NOTE 2: Deﬁ ned as skew between outputs at the same supply voltage and with equal load conditions.

Measured at VDDO/2.

NOTE 3: Deﬁ ned as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at VDDO/2.

NOTE 4: This parameter is deﬁ ned in accordance with JEDEC Standard 65.

TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C

8304I Data Sheet

ADDITIVE PHASE JITTER

The spectral purity in a band at a speciﬁ c offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the speciﬁ ed plot in many applications. Phase

noise is deﬁ ned as the ratio of the noise power present in a 1Hz

band at a speciﬁ ed offset from the fundamental frequency to the

power value of the fundamental. This ratio is expressed in decibels

As with most timing speciﬁ cations, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

ﬂ oor of the equipment is higher than the noise ﬂ oor of the device.

(dBm) or a ratio of the power in the 1Hz band to the power in the

fundamental. When the required offset is speciﬁ ed, the phase noise

is called a dBc value, which simply means dBm at a speciﬁ ed offset

from the fundamental. By investigating jitter in the frequency domain,

we get a better understanding of its effects on the desired application

over the entire time record of the signal. It is mathematically possible

to calculate an expected bit error rate given a phase noise plot.

This is illustrated above. The device meets the noise ﬂ oor of what

is shown, but can actually be lower. The phase noise is dependent

on the input source and measurement equipment.

Additive Phase Jitter @

125MHz (12kHz to 20MHz) = 0.17ps typical

8304I Data Sheet

PARAMETER MEASUREMENT INFORMATION

2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V OUTPUT LOAD AC TEST CIRCUIT

OUTPUT SKEW

OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

PROPAGATION DELAY

PART-TO-PART SKEW

8304I Data Sheet

TRANSISTOR COUNT

The transistor count for 8304I is: 416

TABLE 5. θJAVS. AIR FLOW TABLE

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

RELIABILITY INFORMATION

TABLE 6. PACKAGE DIMENSIONS - SUFFIX M

Reference Document: JEDEC Publication 95, MS-012

PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC

SYMBOL Millimeters

MINIMUN MAXIMUM

A 1.35 1.75

A1 0.10 0.25

B 0.33 0.51

C 0.19 0.25

D 4.80 5.00

E 3.80 4.00

e 1.27 BASIC

H 5.80 6.20

h 0.25 0.50

L 0.40 1.27

α0° 8°

PACKAGE OUTLINE AND DIMENSIONS

8304I Data Sheet

TABLE 7. ORDERING INFORMATION

Part/Order Number Marking Package Shipping Packaging Temperature

8304AMILF 8304AMIL 8 lead “Lead Free” SOIC Tube -40°C to +85°C

8304AMILFT 8304AMIL 8 lead “Lead Free” SOIC Tape and Reel -40°C to +85°C

8304I Data Sheet

REVISION HISTORY SHEET

Rev Table Page Description of Change Date

B3B 3 LVCMOS/LVTTL DC Characteristics Table, added IOH and IOL Test Conditions

to VOH and VOL rows. 4/4/02

BT7

Features Section - added lead-free bullet.

Ordering Information Table - added lead-free part number, marking and note.

Updated datasheet format.

11/09/06

T4A

3.3V AC Characteristics Table - added Buffer Additive Phase Jitter spec.

Added Buffer Additive Phase Jitter Plot.

Ordering Information - Deleted “ICS” from the Part/Order number column.

2/11/09

DT1

Pin Assignment - corrected “pullup” label to “pulldown” label.

Pin Description Table - deleted pullup from note.

Pin Characteristics Table - deleted Rpullup row.

10/29/10

T7 9

Removed ICS in the part numbers.

Removed LF note at the bottom of the Ordering Information table.

Removed the quantity of 2500 from the Tape & Reel in the Ordering information

table.

Updated datasheet header and footer.

12/10/15

8304I Data Sheet

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operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided

without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe-

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