NT1GT64UH8B0MN 1GB : 128M x 64 PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM 200 pin Unbuffered DDR2 SO-DIMM Based on 64Mx16 DDR2 SDRAM 1Gb B-Die Features * 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) * 128Mx64 Unbuffered DDR2 SO-DIMM based on 64Mx16 DDR2 SDRAM B die devices. * Performance: * DRAM DLL aligns DQ and DQS transitions with clock transitions. * Address and control signals are fully synchronous to positive clock edge * Programmable Operation: - DIMM Latency: 3, 4, 5 - Burst Type: Sequential or Interleave - Burst Length: 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * 13/10/2 Addressing * Serial Presence Detect * Gold contacts * SDRAMs in 92-ball BGA Package * RoHS Compliance PC2-4200 PC2-5300 Speed Sort DIMM Latency -37B -3C 3 4 Unit fCK Clock Frequency 266 333 tCK Clock Cycle 3.75 3 MHz ns fDQ DQ Burst Frequency 533 667 MHz * Intended for 266MHz and 333MHz applications * Inputs and outputs are SSTL-18 compatible * VDD = VDDQ = 1.8V 0.1V * SDRAMs have 4 internal banks for concurrent operation * Module has one physical bank * Differential clock inputs * Data is read or written on both clock edges Description NT1GT64UH8B0MN is unbuffered 200-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as two ranks of 128Mx64 high-speed memory array. Modules use eight 64Mx16 92-ball BGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 2.66" long space-saving footprint. The DIMM is intended for use in applications operating up to 266MHz (333MHz) clock speeds and achieves high-speed data transfer rates of up to 533MHz (667MHz). Prior to any access operation, the device latency and burst/length/operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. Ordering Information Part Number Speed NT1GT64UH8B0MN -37B DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4) NT1GT64UH8B0MN -3C DDR2-667 PC2-5300 333MHz (3ns @ CL = 5) REV 1.0 Dec 2006 Organization Power Leads Note 128Mx64 1.8V Gold Green 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8B0MN 1GB : 128M x 64 PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Pin Description CK0-CK1 - Differential Clock Inputs CKE0, CKE1 DQ0-DQ63 Clock Enable DQS0-DQS7 Row Address Strobe Chip Selects Address Inputs A10/AP Differential data strobes DM0-DM7 Write Enable , Bidirectional data strobes - Column Address Strobe A0-A9, A11-A13 Data input/output Input Data Masks VDD Power (1.8V) VREF Ref. Voltage for SSTL_18 inputs VDDSPD Serial EEPROM positive power supply Column Address Input/Auto-precharge VSS Ground BA0, BA1 SDRAM Bank Address Inputs SCL Serial Presence Detect Clock Input ODT0, ODT1 Active termination control lines NC SDA No Connect Serial Presence Detect Data input/output SA0, SA1 Serial Presence Detect Address Inputs Pinout Pin Front 1 VREF 2 VSS 51 3 VSS 4 DQ4 53 5 DQ0 6 DQ5 7 DQ1 8 VSS 9 VSS 10 DM0 11 Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46 VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 VSS 156 VSS 57 DQ19 58 DQ23 107 BA0 108 157 DQ48 158 DQ52 59 VSS 60 VSS 109 110 159 DQ49 160 DQ53 12 VSS 61 DQ24 62 DQ28 111 112 VDD 161 VSS 162 VSS 13 DQS0 14 DQ6 63 DQ25 64 DQ29 113 114 ODT0 163 NC 164 CK1 15 VSS 16 DQ7 65 VSS 66 VSS 115 116 A13 165 VSS 166 17 DQ2 18 VSS 67 DM3 68 117 VDD 118 VDD 167 168 VSS 19 DQ3 20 DQ12 69 NC 70 DQS3 119 ODT1 120 NC 169 DQS6 170 DM6 21 VSS 22 DQ13 71 VSS 72 VSS 121 VSS 122 VSS 171 VSS 172 VSS 23 DQ8 24 VSS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54 25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55 27 VSS 28 VSS 77 VSS 78 VSS 127 VSS 128 VSS 177 VSS 178 VSS 30 CK0 79 CKE0 80 CKE1 129 130 DM4 179 DQ56 180 DQ60 29 VDD 31 DQS1 32 81 VDD 82 VDD 131 DQS4 132 VSS 181 DQ57 182 DQ61 33 VSS 34 VSS 83 NC 84 NC 133 VSS 134 DQ38 183 VSS 184 VSS 35 DQ10 36 DQ14 85 BA2 86 NC 135 DQ34 136 DQ39 185 DM7 186 37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 VSS 187 VSS 188 DQS7 39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS 41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62 43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63 45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 195 SDA 196 VSS 47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1 49 REV 1.0 Dec 2006 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8B0MN 1GB : 128M x 64 PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Input/Output Functional Description Symbol CK0-CK1, - CKE0, CKE1 , , VREF Type Polarity Function (SSTL) Cross Point The system clock inputs. All the DDR2 SDRAM address and control inputs are sampled on the cross point of the rising edge of CK and falling edge of (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. (SSTL) Active Low When sampled at the positive rising edge of the clock, to be executed by the SDRAM. Supply , , define the operation Reference voltage for SSTL-18 inputs ODT0, ODT1 Input Active High BA0 - BA2 (SSTL) - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A13 defines the row address when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 - A13 defines the column address when sampled at the rising clock edge. In addition to the column address, A10/AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. A0 - A9 A10/AP A11 - A13 (SSTL) - DQ0 - DQ63 (SSTL) Active High VDD, VSS Supply DQS0 - DQS7 - (SSTL) DM0 - DM7 Input On-Die Termination control signals Data and Check Bit Input/Output pins. Power and ground for the DDR2 SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDD to act as a pull-up. VDDSPD REV 1.0 Dec 2006 Supply Serial EEPROM positive power supply. 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8B0MN 1GB : 128M x 64 PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Functional Block Diagram (1GB, 2Ranks, 64Mx16 DDR2 SDRAMs) , ! )% *+ , 6 , 6 &' &' & ' . $ * 1 2 . 6 . 0%, 0%, 0%, $ 0%, 0%, 0%, * 0%, 1 0%, 2 & ' , , $ 6 . 0%, 0%, 0%, $ 0%, 0%, 0%, * 0%, 1 0%, 2 * 1 2 3 4 . . 0%, 0%, 0%, $ 0%, 0%, 0%, * 0%, 1 0%, 2 * * -$ --* -1 -2 5 5 0%, 3 0%, 4 0%, 0%, 0%, $ 0%, 0%, 0%, * 1 1 -3 -4 * * *$ * *** . . 0%, 0%, 0%, $ 0%, 0%, 0%, * 0%, 1 0%, 2 2 2 *1 *2 *3 *4 1 1 1$ 1 5 5 0%, 3 0%, 4 0%, 0%, 0%, $ 0%, 0%, 0%, * - * 5 5 0%, 3 0%, 4 0%, 0%, 0%, $ 0%, 0%, 0%, * $ $ 1 2 3 4 $ $ $$ $ . . 0%, 0%, 0%, $ 0%, 0%, 0%, * 0%, 1 0%, 2 $$* $1 $2 $3 $4 5 5 0%, 3 0%, 4 0%, 0%, 0%, $ 0%, 0%, 0%, * 3 4 $ & ' , . 6 , 6 . 0%, 0%, 0%, $ 0%, 0%, 0%, * 0%, 1 0%, 2 , 6 & ' . 1 5 5 0%, 3 0%, 4 0%, 0%, 0%, $ 0%, 0%, 0%, * & ' , 6 & ' . , , 6 . 0%, 0%, 0%, $ 0%, 0%, 0%, * 0%, 1 0%, 2 * 7 , 6 . 0%, 0%, 0%, $ 0%, 0%, 0%, * 0%, 1 0%, 2 $ 5 5 0%, 3 0%, 4 0%, 0%, 0%, $ 0%, 0%, 0%, * & ' & ' 2 5 5 0%, 3 0%, 4 0%, 0%, 0%, $ 0%, 0%, 0%, * 5 5 0%, 3 0%, 4 0%, 0%, 0%, $ 0%, 0%, 0%, * ! )% *+ 2 7 2 &' 2 - ! - ! 2 &' 2 &. $ REV 1.0 Dec 2006 % % % % %&' % % !! ! !" # ! ! (! $$)% *+ , ! &. $ !! / 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8B0MN 1GB : 128M x 64 PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Serial Presence Detect (Part 1 of 2) SPD Entry Value Byte Description PC2-4200 Serial PD Data Entry (Hexadecimal) PC2-5300 PC2-4200 -3C -37B -37B PC2-5300 -3C 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 Number of Column Addresses on Assembly 5 Number of DIMM Ranks 6 Data Width of Assembly 64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 9 DDR2 SDRAM Device Cycle Time at CL=5 3.75ns 3ns 3D 30 10 DDR2 SDRAM Device Access Time from Clock at CL=5 0.5ns 0.45ns 50 45 11 DIMM Configuration Type 12 Refresh Rate/Type 13 DDR2 08 13 0D 10 0A 2 rank, Height=30mm 61 05 Non parity/ECC 00 7.8s/self 82 Primary DDR2 SDRAM Width x16 10 14 Error Checking DDR2 SDRAM Device Width N/A 00 15 Reserved 16 DDR2 SDRAM Device Attributes: Burst Length Supported 17 18 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: Undefined 00 4,8 0C DDR2 SDRAM Device Attributes: Number of Device Banks 8 08 DDR2 SDRAM Device Attributes: CAS Latencies Supported 5,4,3 38 <3.80mm 01 Regular SODIMM (67.6mm) 04 Normal DIMM 00 Support weak driver /50ohm ODT/ PASR 07 3D 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 3.75ns 24 Maximum Data Access Time from Clock at CL=4 0.5ns 50 25 Minimum Clock Cycle Time at CL=3 5.0ns 50 26 Maximum Data Access Time from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 10ns 28 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum RAS Pulse Width (tRAS) 45.0 2D 31 Module Bank Density 32 Address and Command Setup Time Before Clock (tIS) 0.25ns 0.2ns 25 20 33 Address and Command Hold Time After Clock (tIH) 0.375ns 0.275ns 37 27 34 Data Input Setup Time Before Clock (tDS) 0.10ns 0.10ns 10 10 35 Data Input Hold Time After Clock (tDH) 0.225ns 0.175ns 22 17 36 Write Recovery Time (tWR) 15.0ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 39 Reserved Undefined 00 40 Extension of Byte 41 tRC and Byte 42 tRFC The number below a decimal point of tRC=0 and tRFC=5, tRFC is less than 256ns 06 41 Minimum Core Cycle Time (tRC) 60.0ns 3C REV 1.0 Dec 2006 Note 512MB 80 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8B0MN 1GB : 128M x 64 PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Serial Presence Detect (Part 2 of 2) SPD Entry Value Byte Description Serial PD Data Entry (Hexadecimal) PC2-4200 PC2-5300 PC2-4200 -37B -3C -37B 127.5ns PC2-5300 -3C 42 Min. Auto Refresh Command Cycle Time (tRFC) 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tDQS) 0.30ns 0.24ns 1E 45 Read Data Hold Skew Factor (tQHS) 0.40ns 0.34ns 28 46 PLL Relock Time 47 Tcasemax 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) TBD TBD 00 00 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) TBD TBD 00 00 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) TBD TBD 00 00 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) TBD TBD 00 00 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) TBD TBD 00 00 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) TBD TBD 00 00 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) TBD TBD 00 00 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) TBD TBD 00 00 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) TBD 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) TBD 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) TBD 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) TBD 00 62 SPD Revision 63 Checksum for Byte 0-62 72 TBD Dec 2006 TBD 22 00 TBD 00 00 TBD 00 1.2 92-255 Reserved 18 00 Checksum data 73-91 Module Part Number REV 1.0 80 N/A Module Manufacturing Location Note1: NT1GT64UH8B0MN-37B NT1GT64UH8B0MN-3C 7F 8.0ns 64-71 Manufacturer's JEDEC ID Code Note 12 ED A9 NANYA 7F7F7F0B00000000 Manufacturing code -- Module Part Number in ASCII -- Undefined -- 1 4E54314754363455483842304D4E2D33374220 4E54314754363455483842304D4E2D33432020 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8B0MN 1GB : 128M x 64 PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Absolute Maximum DC Ratings Symbol VIN, VOUT VDD VDDQ VDDL Rating Units Voltage on I/O pins relative to Vss Parameter -0.5 to +2.3 V Voltage on VDD pins relative to Vss -1.0 to +2.3 V Voltage on VDDQ pins relative to Vss -0.5 to +2.3 V Voltage on VDDL pins relative to Vss -0.5 to +2.3 V Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating temperature Conditions Symbol Rating Units TOPR Operating Temperature (Ambient) Parameter 0 to 65 C HOPR Operating Humidity (relative) 10 to 90 % TSTG Storage Temperature -50 to 100 C HSTG Storage Humidity (without condensation) 5 to 95 % 105 to 69 kPa Barometric Pressure (operating & storage) Note: Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating condition for extended periods may affect reliability Barometric pressure up to 9850 ft. DC Electrical Characteristics and Operating Conditions Symbol Min Typ. Max Units Notes VDD Supply Voltage 1.7 1.8 1.9 V 1 VDDL DLL Supply Voltage 1.7 1.8 1.9 V 1 VDDQ Output Supply Voltage 1.7 1.8 1.9 V 1 VREF Input Reference Voltage 0.49VDDQ 0.50VDDQ 0.51VDDQ V 1, 2 VREF - 0.04 VREF VREF + 0.04 V 3 VTT Parameter Termination Voltage Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT of transmitting device must track VREF of receiving device. Input AC/DC logic level Symbol Parameter PC2-4200 -37B Min PC2-5300 -3C Max Min Units Notes Max VIH (AC) Input High (Logic1) Voltage VREF + 0.250 - VREF + 0.200 - V 1 VIL (AC) Input Low (Logic0) Voltage - VREF - 0.250 - VREF - 0.200 V 1 VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 VREF + 0.125 VDDQ + 0.3 V VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 -0.3 VREF - 0.125 V REV 1.0 Dec 2006 1 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8B0MN 1GB : 128M x 64 PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (1GB, 2 Ranks, 64Mx16 DDR2 SDRAMs) Symbol Parameter/Condition PC2-4200 PC2-5300 (37B) (3C) Unit IDD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 760 840 mA IDD1 Operating Current: one bank; active/read/precharge; Burst = 4; tRC = tRC (MIN); CL= 4; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 820 1060 mA IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 104 104 mA IDD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 480 640 mA IDD2Q Precharge Quiet Stand by Current 440 520 mA Active Power-Down Standby Current: one bank active; power-down mode; IDD3PF CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 360 360 mA IDD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 200 200 mA IDD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 520 640 mA Operating Current: one bank; Burst = 4; reads; continuous burst; address IDD4R and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 4; tCK = tCK (MIN); IOUT = 0mA 940 1060 mA Operating Current: one bank; Burst = 4; writes; continuous burst; address IDD4W and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL= 4; tCK = tCK (MIN) 1020 1140 mA IDD5 Auto-Refresh Current: tRC = tRFC (MIN) 1120 1340 mA IDD6 Self-Refresh Current: CKE 0.2V 104 104 mA IDD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1600 2040 mA Note: Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.0 Dec 2006 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8B0MN 1GB : 128M x 64 PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol tCK Parameter Clock Cycle Time PC2-4200 PC2-5300 Min. Max. 3750 8000 Clock Cycle Time (Average) Unit Min. Max. 3000 8000 ps ps tCH CK high-level width 0.45 0.55 0.48 0.52 tCK tCL CK low-level width 0.45 0.55 0.48 0.52 tCK WL Write command to DQS associated clock edge tDQSS Write command to 1st DQS latching transition -0.25 0.25 -0.25 +0.25 tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - 0.2 - tCK DQS input low (high) pulse width (write cycle) 0.35 - 0.35 - tCK Write preamble 0.35 - 0.35 - tCK Write postamble 0.4 0.6 0.40 0.60 tCK Address and control input setup time 250 - 200 - ps 375 - 275 - ps tDQSL,(H) tWPRE tWPST tIS tIH Address and control input hold time RL-1 RL-1 tCK tIPW Input pulse width 0.6 - 0.6 - tCK tDS DQ and DM input setup time(differential data strobe) 100 - 100 - ps tDH DQ and DM input hold time(differential data strobe) 225 - 175 - ps DQ and DM input pulse width (each input) 0.35 - 0.35 - tCK DQ output access time from CK/ -500 500 -450 450 ps DQS output access time from CK/ -450 450 -400 +400 ps - tAC max - tACmax ps tAC max tACmin tACmax ps tDIPW tAC tDQSCK tHZ Data-out high-impedance time from CK/ tLZ(DQS) DQS low-impedance time from CK/ tAC min tLZ(DQ) DQ low-impedance time from CK/ 2tAC min tAC max 2tAC min tAC max tDQSQ DQS-DQ skew (DQS & associated DQ signals) tHP 300 - 024 ps tCH or tCL - tCH or tCL - tCK - 400 - 340 ps tHP tQHS - tHP tQHS - ps Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tQHS Data hold Skew Factor tQH Data output hold time from DQS ps - tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 0.40 0.60 tCK tRRD Active bank A to Active bank B command 7.5 - 7.5 - ns tFAW Four Activate Window for 1KB page size products 37.5 - 37.5 - tCCD to tWR Write recovery time without Auto-Precharge tDAL Auto precharge write recovery + precharge time tWTR tRTP - 15 - ns - WR+tRP - tCK Internal write to read command delay 7.5 - 7.5 - ns Internal read to precharge command delay 7.5 CKE minimum pulse width Exit self refresh to a Non-read command tXSRD Exit self refresh to a Read command Dec 2006 ns tCK 15 tCKE REV 1.0 2 WR+tRP tXSNR tXP 2 3 7.5 ns 3 tCK tRFC+10 - tRFC+10 ns 200 - 200 tCK 2 - 2 Exit precharge power down to any Non- read command - tCK 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8B0MN 1GB : 128M x 64 PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol PC2-4200 Parameter Min. Max. - tXARD Exit active power down to read command 2 tXARDS Exit active power down to read command 6-AL tAOND ODT turn-on delay tAON PC2-5300 Max. 2 - tCK 2 tCK 7-AL 2 2 tCK 2 ODT turn-on tAC (min) tAC (max) tAC (min) tAC (max) ODT turn-on (Power down mode) tAC (min) +2 +1 +0.7 2tCK + tAC(max) +1 tAC (min) +2 2.5 2.5 ODT turn-off tAC(min) tAC(max) +0.6 tAOFPD ODT turn-off (Power down mode) tAC (min)+2 2.5tCK + tAC(max) +1 tANPD ODT to power down entry latency tAXPD ODT power down exit latency tAONPD tAOFD tAOF Unit Min. ODT turn-off delay ns 2tCK + tAC(max) +1 ns 2.5 2.5 tCK tAC(min) tAC(max) +0.6 ns tAC (min)+2 2.5tCK + tAC(max) +1 ns 3 3 - 8 8 tCK tCK tMRD Mode register set command cycle time 2 - 2 - tCK tMOD MRS command to ODT update delay 0 12 0 12 ns tOIT OCD drive mode output delay 0 12 0 12 ns tIS + tCK + tIH - ns tDelay tREFI Minimum time clocks remains ON after CKE asynchronously drops Low tIS+tCK+ tIH Average Periodic Refresh Interval (85C < TCASE 8 95C) 3.9 3.9 9s Average Periodic Refresh Interval (0C 8 TCASE 8 85C) 7.8 7.8 9s Speed Grade Definition Symbol Parameter -37B -3C Min Max Min Max Unit tRAS Row Active Time 45 70,000 45 70,000 ns tRC Row Cycle Time 60 - 60 - ns tRCD RAS to CAS delay 15 - 15 - ns Row Precharge Time 15 - 15 - ns tRP REV 1.0 Dec 2006 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8B0MN 1GB : 128M x 64 PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Package Dimensions (1GB, 1Rank, 128Mx8 DDR2 SDRAMs) ,:6 12 1 1 1 <$;= 3 4 $ * - 44 7 -$ -2 $2 $ -* 7 &' 0 3 ; )% 2 7 -* - )% 1 )% REV 1.0 Dec 2006 : > 5 !> ! ! (" "! )% *? !! ! ! ! 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8B0MN 1GB : 128M x 64 PC2-4200 / PC2-5300 Unbuffered DDR2 SO-DIMM Revision Log Rev Date 0.1 12/2005 Preliminary release. Modification 1.0 12/2006 Official release. Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.nanya.com Printed in Taiwan (c)2006 REV 1.0 Dec 2006 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.