PL135-67
Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:6 Oscillator Fanout Buffer
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408 ) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 02/14/11 Page 1
CLK3
GND
CLK1
CLK2CLK5
CLK4
VDD
CLK0
VDD
GND
OE1
GND
XIN
XOUT
VDD
1 2 3 4
8
7
6
5
12 11 10 9
13
14
15
16
OE0
QFN
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
CLK3
GND
CLK1
CLK2CLK5
CLK4
VDD
CLK0
VDD GND
OE1
GND
XIN XOUT
VDD
OE0
TSSOP
FEATURES
Advanced Oscillator Design for Wide
Frequency Coverage
6 LVCMOS Outputs with 2 Output Enable Pins
8mA Output Drive Strength
Input/Output Frequency:
o Fundamental Crystal: 10MHz to 40MHz
Very Low Jitter and Phase Noise
Low Current Consumption
Single 1.62V to 3.63V Power Supply
Available in QFN-16L and TSSOP-16L
GREEN/RoHS Compliant Packages
DESCRIPTION
The PL135-67 is an advanced oscillator fanout buffer
design for high performance, low-power, small form-
factor applications. The PL135-67 accepts a
fundamental input crystal of 10MHz to 40MHz and
produces six outputs of the same frequency, two with
their own Output Enable functions.
Offered in a small 3 x 3mm QFN or TSSOP package,
the PL135-67 offers the best phase noise and jitter
performance and lowest power consumption of any
comparable IC.
PACKAGE PIN CONFIGURATION
BLOCK DIAGRAM
CLK0
CLK1
CLK2
CLK3
XIN
XOUT
XTAL
OSC
OE0
CLK4
CLK5
OE1
PL135-67
Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:6 Oscillator Fanout Buffer
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408 ) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 02/14/11 Page 2
PACKAGE PIN ASSIGNMENT
Name
Package Pin #
Type
Description
QFN-16L
(T)SSOP-16L
CLK0
1
7
O
Output clock
VDD
2, 9, 15
5, 8, 15
P
VDD connection
GND
3, 6, 12
2, 9, 12
P
GND connection
OE1
4
6
I*
Output enable (OE) input for CLK1. Internal pull-up. Pull
low to tri-state CLK1.
CLK1
5
11
O
Output clock
CLK2
7
13
O
Output clock
CLK3
8
14
O
Output clock
XOUT
10
16
O
Crystal output. Do not connect when using reference clock.
XIN
11
1
I
Crystal input
CLK4
13
3
O
Output clock
CLK5
14
4
O
Output clock
OE0
14
4
I*
Output enable (OE) input for CLK0. Internal pull-up. Pull
low to tri-state CLK0.
* Note: These pins include an internal 60k pull up.
PL135-67
Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:6 Oscillator Fanout Buffer
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408 ) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 02/14/11 Page 3
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like ringing).
- Design long traces as “striplinesor microstripswith
defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Decoupling and Power Supply Considerations
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Multiple VDD pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency
dependant. Typical value to use is 0.1F.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
SYMBOL
MIN.
MAX.
UNITS
VDD
-0.5
4.6
V
VI
-0.5
VDD+0.5
V
VO
-0.5
VDD+0.5
V
TS
-65
150
C
-40
85
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
(Typical buffer impedance 20Ω)To CMOS Input
Series Resistor
Use value to match output buffer impedance to
50Ω trace. Typical value 30Ω
50Ω line
Crystal Tuning Circuit
Series and parallel capacitors used to fine tune the crystal load to the circuit load.
CST Series Capacitor, used to lower circuit load to match crystal load. Raises frequency offset.
This can be eliminated by using a crystal with a Cload of equal or greater value than the oscillator.
CPT Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers
frequency offset.
Crystal
XIN
1 8
XOUT
Cpt Cpt
Cst
PL135-67
Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:6 Oscillator Fanout Buffer
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408 ) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 02/14/11 Page 4
AC SPECIFICATIONS
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Crystal Input Frequency
Fundamental Crystal
10
40
MHz
Settling Time
At power-up (VDD > 1.62V)
2
ms
Output Enable Time
OE Function; Ta=25º C, 10pF Load
10
ns
VDD Sensitivity
Frequency vs. VDD, ±10%
-2
2
ppm
Output Rise Time
15pF Load, 10/90% VDD, 3.3V
2
4
ns
Output Fall Time
15pF Load, 90/10% VDD, 3.3V
2
4
ns
Output to Output Skew
Under all conditions
1
ns
Duty Cycle
Under all conditions
45
50
55
%
DC SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current, Dynamic
IDD
VDD = 3.3V, 25MHz, No Load
7.1
mA
VDD = 2.5V, 25MHz, No Load
4.8
mA
VDD = 1.8V, 25MHz, No Load
3.4
mA
Operating Voltage
VDD
1.62
3.63
V
Output Low Voltage
VOL
IOL = +4mA, 3.3V
0.4
V
Output High Voltage
VOH
IOH = -4mA, 3.3V
2.4
V
Output Current
IOSD
VOL = 0.4V, VOH = 2.4V
8
mA
CRYSTAL SPECIFICATIONS
PARAMETERS
SYMBOL
MIN.
TYP.
MAX.
UNITS
Fundamental Crystal Resonator Frequency
FXIN
10
40
MHz
Crystal Loading Rating
CL ( xta l)
15
pF
Operating Drive Level
0.1
2
mW
Metal Can Crystal
Shunt Capacitance
C0
5.5
pF
ESR Max
ESR
40
Small SMD Crystal
Shunt Capacitance
C0
2.5
pF
ESR Max
ESR
60
PL135-67
Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:6 Oscillator Fanout Buffer
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408 ) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 02/14/11 Page 5
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
QFN 16L
TSSOP 16L
Symbol
Dimension in MM
Min.
Max.
A
0.07
0.8
A1
0.05
0.05
A3
0.20
b
0.18
0.30
D
3.00 BSC
E
3.00 BSC
D1
--
1.70
E1
--
1.70
L
0.30
0.50
e
0.50 BSC
Symbol
Dimension in MM
Min.
Max.
A
-
1.20
A1
0.05
0.15
b
0.19
0.30
C
0.09
0.20
D
4.90
5.10
E
4.30
4.50
H
6.20
6.60
L
0.45
0.75
e
0.635 BSC
C
L
A
EH
D
A1
eB
SEATING PLANE
A1
A3
b
E1
D1
A
e
L
D
E
Pin1 Dot
PL135-67
Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:6 Oscillator Fanout Buffer
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408 ) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 02/14/11 Page 6
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
For part ordering, please contact our Sales Department:
2180 Fortune Drive, San Jose, CA 95131, USA
Tel: (408) 944-0800 Fax: (408) 474-1000
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
PL135-67 X X - X
Part Number
Package Type
O = TSSOP-16L
Q = QFN-16L
Temperature Range
C=Commercial (0°C to
70°C)
Shipping Option
None=Tubes
R=Tape and Reel
Part Number/Order Number
Marking
Package Option
PL135-67OC
P135-67
OC
LLLLL
16-Pin TSSOP (Tube)
PL135-67OC-R
16-Pin TSSOP (Tape and Reel)
PL135-67QC-R
P135
67
LLL
16-Pin QFN (Tape and Reel)
*Note: LLL designates lot number
Micrel Inc., reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Micrel is believed to be accurate
and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever
nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: Micrel’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the
President of Micrel Inc.