1. General description
The ISP1507 is a Universa l Serial Bus (USB) On-The-Go (OTG) transceiver that is fully
compliant with Universal Serial Bus Specification Rev. 2.0, On-The-Go Supplement to the
USB 2.0 Specification Rev. 1.3 and UTMI+ Low Pin Interface (ULPI) Specification
Rev. 1.1.
The ISP1507 can transmit and receive USB data at high-spe ed (480 Mbit/s), full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer
front-end attachment to USB host, peripheral and OTG devices.
It is ideal for use in portable electronic devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable
Logic Devices (PLDs) and any system chip set to interface with the physical layer of the
USB through a 12-pin interface.
The ISP1507 can interface to the link with digital I/O voltages in the range of 1.65 V to
3.6 V.
The ISP1507 is available in HVQFN32 package.
2. Features
Fully complies with:
Universal Serial Bus Specification Rev. 2.0
On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3
UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1
Interfaces to host, periph eral and OTG device core s; optimized for port a ble devices o r
system ASICs with built- in USB OT G device cor e
Complete Hi-Speed USB physical front-end solution that supports high-speed
(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
Integrated 45 Ω±10 % high-speed termination resistors, 1.5 kΩ±5 % full-speed
device pull-up resistor, and 15 kΩ±5 % host termination resistors
Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive
USB clock and data recovery to r eceive USB data up to ±500 ppm
Insertion of stuff bits during transmit and discardin g of stuff bits during receive
Non-Return-to-Zero Inverted (NRZI) encoding and decoding
Supports bus reset, suspend, resume and high-speed detection handshake (chirp)
Complete USB OTG physical front-end that supports Host Negotiation Protocol (HNP)
and Session Request Protocol (SRP)
ISP1507A; ISP1507B
ULPI Hi-Speed USB On-The-Go transceiver
Rev. 04 — 20 May 2010 Product data sheet
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 2 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
Integrated 5 V charge pump; also supports external charge pump or 5 V VBUS
switch
Complete control over bus resistors
Data line and VBUS pulsing session reque st me th od s
Integrated VBUS voltage comparators
Integrated cab l e (I D) de te cto r
Highly optimized ULPI-compliant
60 MHz, 12-bit interface between the core and the transceiver
Supports 60 MHz output clock configuration
Integrated Phase-Locked Loop (PLL) supporting one crystal or clock frequency:
19.2 MHz (ISP1507A) and 26 MHz (ISP1507B)
Fully programmable ULPI-compliant register set
Internal Power-On Reset (POR) circuit
Flexible system integration and very low current consumption, optimized for p ortable
devices
Power-supply input range is 3.0 V to 3.6 V
Internal voltage regula to r sup p lies 3. 3 V and 1.8 V
Charge pump regulator outputs 4.65 V to 5.25 V at a current of up to 50 mA,
tunable using an external capacitor
Supports external VBUS charge pump or 5 V VBUS switch:
External VBUS source is controlled using the PSW_N pin; open-drain PSW_N
allows per-port or ganged power control
Digital FAULT input to monitor the external VBUS supply status
Pin CHIP_SELECT_N 3-states the ULPI interface, allowing bu s reuse for other
applications
Supports wide range interfacing I/O voltage of 1.65 V to 3.6 V ; separate I/O voltage
pins minimize crosstalk
Typical operating current of 11 mA to 48 mA, depending on the USB speed and
bus utilization; not including the charge pump
Typical suspend current of 35 μA
Full industrial grade operating temperature range from 40 °C to +85 °C
4 kV ElectroStatic Discharge (ESD) protection at pins DP, DM, ID, VBUS and GND
Available in a small HVQFN32 (5 mm ×5 m m ) Res tr ictio n of Haza rd ou s Subs tances
(RoHS) compliant, halogen-free and lead-free package
3. Applications
Digital still camera
Digital TV
Digital Video Disc (DVD) recorder
External storage device, for example:
Magneto-Optical (MO) drive
Optical drive: CD-ROM, CD-RW, DVD
Zip drive
Mobile phone
MP3 player
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 3 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
PDA
Printer
Scanner
Set-Top Box (STB)
Video camera
4. Ordering information
[1] The package marking is the first line of text on the IC package and can be used for IC identification.
Table 1. Ordering information
Commercial
product code Marking Crystal or clock
frequency Pac kage description Packing Minimum sellable
quantity
ISP1507ABSTM 507A[1] 19.2 MHz HVQFN32; 32 terminals;
body 5 ×5×0.85 mm 13 inch tape and reel
non-dry pack 6000 pieces
ISP1507BBSTM 507B[1] 26 MHz HVQFN32; 32 terminals;
body 5 ×5×0.85 mm 13 inch tape and reel
non-dry pack 6000 pieces
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 4 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
5. Block diagram
Fig 1. Block diagram
REGISTER
MAP
ULPI
INTERFACE
CONTROLLER
USB DATA
SERIALIZER
USB DATA
DESERIALIZER
HI-SPEED USB ATX
DM
DP
STP
DIR
NXT
DATA
[7:0]
8
4
5
21
20
19
1, 23 to 26,
28, 31, 32
004aab035
CLOCK 27
TERMINATION
RESISTORS
ID
DETECTOR
VBUS
COMPARATORS
ON-THE-GO MODULE
SRP CHARGE
AND DISCHARGE
RESISTORS
5 V CHARGE
PUMP SUPPLY
POWER-ON
RESET
PLL
CRYSTAL
OSCILLATOR
VOLTAGE
REGULATOR
BAND GAP
REFERENCE
VOLTAGE RREF
3
internal power
VCC 11
REG3V3
REG1V8
14
18
RESET_N
GLOBAL
RESET
GLOBAL
CLOCKS
XTAL2
XTAL1 15
16
VCC(I/O) 2, 22, 30 interface voltage
PSW_N
DRV VBUS
EXTERNAL
DRV VBUS
ID
7
VBUS
13
FAULT
6
12
CPGND
8
10 C_A
C_B
9
ISP1507
17
ULPI
INTERFACE
USB
CABLE
VREF
CHIP_SELECT_N 29
VBUS VALID
EXTERNAL
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 5 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration HVQF N3 2 ; top vi e w
004aab036
ISP1507
Transparent top view
RESET_N
ID
CPGND
REG1V8
FAULT DIR
DP STP
DM NXT
RREF VCC(I/O)
VCC(I/O) DATA7
DATA0 DATA6
C_B
C_A
VCC
PSW_N
VBUS
REG3V3
XTAL1
XTAL2
DATA1
DATA2
VCC(I/O)
CHIP_SELECT_N
DATA3
CLOCK
DATA4
DATA5
8 17
7 18
6 19
5 20
4 21
3 22
2 23
1 24
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
terminal 1
index area
Table 2. Pin description
Symbol[1][2] Pin Type[3] Description[4]
DATA0 1 I/O pin 0 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); pla in input;
programmable pull down
VCC(I/O) 2 P I/O supply rail
RREF 3 AI/O resistor reference
DM 4 AI/O dat a minus (D) pin of the USB cable
DP 5 AI/O data plus (D+) pin of the USB cable
FAULT 6 I input pin for the external VBUS digital overcurrent or fault
detector signal
If this pin is not in use, connect it to GND.
plain input; 5 V tolerant
ID 7 I identification (ID) pin of the micro-USB cable
If this pin is not used, it is recommended to connect to
REG3V3.
plain inp u t; TT L level
CPGND 8 P charge pump ground
C_B 9 AI/O flying capacitor pin connection for the charge pump
If this pin is not in use, it must be left floating.
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 6 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
C_A 10 AI/O flying capacitor pin connection for the charge pump
If this pin is not in use, it must be left floating.
VCC 11 P input supply voltage or battery source
PSW_N 12 OD active LOW external VBUS power switch or external charge
pump enable
open-drain; 5 V tolerant
VBUS 13 AI/O VBUS pin of the USB cable
5V tolerant
REG3V3 14 P 3.3 V regulator out put; requires p arallel 0.1 μF and 4.7 μF
capacitors; internally powers AT X and other analog
circuits; must not be used to power external circuits
XTAL1 15 AI crystal oscillator or clock input
XTAL2 16 AO crystal oscillator output
RESET_N 17 I active LOW, asynchronous reset input
plain input
REG1V8 18 P 1.8 V regulator out put; requires p arallel 0.1 μF and 4.7 μF
capacitors; internally powers the digital core; must not be
used to power external circuits
DIR 19 O ULPI direction signal
slew-rate controlled output (1 ns)
STP 20 I ULPI stop signal
plain input; programmable pull up
NXT 21 O ULPI next signal
slew-rate controlled output (1 ns)
VCC(I/O) 22 P I/O supply rail
DATA7 23 I/O pin 7 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); pla in input;
programmable pull down
DATA6 24 I/O pin 6 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); pla in input;
programmable pull down
DATA5 25 I/O pin 5 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); pla in input;
programmable pull down
DATA4 26 I/O pin 4 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); pla in input;
programmable pull down
CLOCK 27 O 60 MHz clock output
slew-rate controlled output (1 ns); pla in input
DATA3 28 I/O pin 3 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); pla in input;
programmable pull down
Table 2. Pin description …continued
Symbol[1][2] Pin Type[3] Description[4]
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 7 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
[1] Symbol names ending with underscore N, for example, NAME_N, indicate active LOW signals.
[2] For details on external components required on each pin, see list of materials and application diagrams in
Section 16.
[3] I = input; O = output; I/O = digital input/output; OD = open-drain o utput; AI = analog input; AO = analog
output; AI/O = analog input/output; P = power or ground pin.
[4] A detailed description of these pins can be found in Section 7.9.
CHIP_SELECT_N 29 I active LOW chip select
If this pin is not in use, connect it to GND.
plain input
VCC(I/O) 30 P I/O supply rail
DATA2 31 I/O pin 2 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); pla in input;
programmable pull down
DATA1 32 I/O pin 1 of the bidirectional ULPI data bus
slew-rate controlled output (1 ns); pla in input;
programmable pull down
GND die pad P ground supply; down bonded to the exposed die pad (heat
sink); to be connected to the PCB ground
Table 2. Pin description …continued
Symbol[1][2] Pin Type[3] Description[4]
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 8 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
7. Functional description
7.1 ULPI interface controller
The ISP1507 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface
(ULPI) Specification Rev. 1.1. This int erface must be connected to the USB link.
The ULPI interface controller provides the following functions:
ULPI-compliant and register set
Allows full control over the USB peripheral, host and OTG functionality
Parses USB transmit and receive data
Prioritizes USB receive data, USB transmit data, interrupts and register o perations
Low-power mod e
Control of the VBUS charge pump or external source
VBUS monitoring, charging and discharging
6-pin serial mode and 3-pin serial mode
Generates RXCMDs; status updates
Maskable interrupts
Control over the ULPI bus state, allowing pins to 3-state or atta ch active weak
pull-down resistors
For more information on the ULPI protocol, see Section 9.
7.2 USB data serializer and deserializer
The USB data serializer prepares data to transmit on the USB bus. To transmit data, the
USB link sends a transmit command and data on the ULPI bus. The serializer performs
parallel-to-serial conversion, bit stuffing and NRZI encoding. For packets with a PID, the
serializer adds a SYNC pattern to the star t of the p acket, and an EOP p attern to the end of
the packet. When the serializer is busy and cannot accept any more data, the ULPI
interface controller deasse rts NXT.
The USB data deserializer decodes data received from the USB bus. When data is
received, the deserializer strips the SYNC and EOP patterns, and then performs
serial-to-parallel conversion, NRZI decoding and discarding of stuff bits on the data
payload. The ULPI interface controller sends data to the USB link by asserting DIR, and
then asserting NXT whenever a byte is ready. The deserializer also detects various
receive errors, including bit stuff errors, elasticity buffer underrun or overr un, and
byte-alignm en t er ro rs.
7.3 Hi-Speed USB (USB 2.0) ATX
The Hi-Speed USB ATX block is an analog front-end containing the circuitry needed to
transmit, receive and terminate the USB bus in high-speed, full-speed and low-speed, for
USB peripheral, host and OTG implementations. The following circuitry is included:
Differential drivers to transmit data at high-speed, full-speed and low-speed
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 9 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
Differential and single-ended receivers to receive data at high-speed, full-speed and
low-speed
Squelch circuit to detect high-speed bus activity
High-speed disconnect detector
45 Ω high-speed bus termina tions on DP and DM for peripheral and host modes
1.5 kΩ pull-up resistor on DP for full-speed peripheral mod e
15 kΩ bus terminations on DP and DM for host and OTG modes
For details on controlling resistor settings, see Table 8.
7.4 Voltage regulator
The ISP1507 contains a built-in voltage regulator that conditions the VCC supply for use
inside the ISP1507. The voltage regulator:
Supports input supply range of 3.0 V < VCC <3.6V
Supplies internal circuitry with 1.8 V and 3.3 V
Remark: The REG1V8 and REG3V3 pins require exter nal decoupling capacitors. For
details, see Section 16.
7.5 Crystal oscillator and PLL
The ISP1507 has a built-in crystal oscillator and a Phase-Locked Loop (PLL) for clock
generation.
The crystal oscillator takes a sine-wave input from an external crystal on the XTAL1 pin,
and convert s it to a squar e wave clo ck for internal u se. Alte rn ative ly, a square wave clock
of the same frequency can also be directly driven into the XTAL1 pin. Using an existing
square wave clock can save the cost of a crystal and also reduce the board size.
The PLL takes the square wave clock from the crystal oscillator and multiplies or divides it
into various frequencies for internal use.
The PLL produces the following fr equencies, irrespective of the clock source:
60 MHz clock for the ULPI interface controller
1.5 MHz for the low-speed USB data
12 MHz for the full-speed USB data
480 MHz for the high-speed USB data
Other internal freq uencies for data conversio n and data recovery
7.6 OTG module
This module contains several sub-blocks that provide all the functionality required by the
USB OTG specification. Specifically, it provides the following circuits:
The ID detector to sense the ID pi n of the micro-USB cab le. The ID pin dict ate s which
device is initially configured as the host and which as the peripheral.
VBUS comparators to determine the VBUS voltage level. This is required for the VBUS
detection, SRP and HNP.
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 10 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
Resistors to temporarily charge and discharge VBUS. This is required for SRP.
Charge pump to provide 5 V power on VBUS. The downstream periphera l can draw it s
power from the ISP1507 VBUS.
7.6.1 ID detector
The ID detector detects which end of the micro-USB cable is plugged in. The detector
must first be enabled by setting the ID_PULLUP register bit to logic 1. If the ISP1507
senses a value on ID that is different from the previously reported value, an RXCMD
status update will be sent to the USB link, or an interrupt will be asserted.
If the micro-B end of the cable is plugged in, the ISP1507 will report that ID_GND is
logic 1. The USB link must change to peripheral mode.
If the micro-A end of the cable is plugged in, the ISP1507 will report that ID_GND is
logic 0. The USB link must change to host mode.
7.6.2 VBUS comparators
The ISP1507 provides three comparators, VBUS valid comparator, session valid
comparator and session end comparator, to detect the VBUS voltage level.
7.6.2.1 VBUS valid comparator
This comparator is used by hosts and A-devices to determine whether the voltage on
VBUS is at a valid level for operation. The ISP1507 minimum threshold for the VBUS valid
comparator is 4.4 V. Any voltage on VBUS below this threshold is considered invalid.
During power-up, it is expected that the comparator output will be ignored.
7.6.2.2 Session valid comparator
The session valid comparator is a TTL-level input that determines when VBUS is high
enough for a session to start. Peripherals, A-devices and B-devices use this comparator
to detect when a session is started. The A-device also uses this comparator to determine
when a session is completed. Th e session va lid thr eshol d of th e ISP1507 is VB_SESS_VLD,
with a hysteresis of Vhys(B_SESS_VLD).
7.6.2.3 Session end compara tor
The ISP1507 session end comparator determines when VBUS is below the B-device
session end threshold. The B-device uses this th reshold to determine when a session has
ended. The session end threshold of the ISP1507 is VB_SESS_END.
7.6.3 SRP charge and discharge resistors
The ISP1507 provides on-chip resistors for short-term charging and discharging of VBUS.
These are used by the B-device to request a session, prompting the A-device to restore
the VBUS power. First, the B-device makes sure that VBUS is fully discharged from the
previous session by setting the DISCHRG_VBUS register bit to logic 1 and waiting for
SESS_END to be logic 1. Then the B-device charges VBUS by setting the CHRG_VBUS
register bit to logic 1. The A-device sees that VBUS is charged above the session valid
threshold and starts a session by turning on the VBUS power.
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 11 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
7.6.4 Charge pump
The ISP1507 uses a built-in charge pump to supply current to VBUS at a nominal voltage
of 5 V. The charge pump works as a capacitive DC-DC converter. An external holding
capacitor, Ccp(C_A)-(C_B), is required between the C_A and C_B pins as sho wn in Figure 3,
which also shows a typical OTG VBUS load. The value of Ccp(C_A)-(C_B) depends on the
amount of current drive required. If the internal charge pum p is not used, the Ccp(C_A)-(C_B)
capacitor is not required.
For details on the C_A and C_B pins, see Section 7.9.8.
7.7 Band gap reference voltage
The band gap circuit provides a stable internal voltage reference to bias the analog
circuitry. The band gap requires an accurate external reference, RRREF, resistor
connected between the RREF pin and GND. For details, see Section 16.
7.8 Power-On Reset (POR)
The ISP1507 has an internal power-on reset circuit that resets all internal logic on
power-up. The ULPI interface is also reset on power-up.
Remark: When CLOCK starts toggling after power-up, the USB link must issue a reset
command over the ULPI bus to ensure correct operation of the ISP1507.
7.9 Detailed description of pins
7.9.1 DATA[7:0]
The ISP1507 is a Physical layer (PHY) containing a USB transceiver. DATA[7:0] is the
bidirectional data bus. The USB link must drive DATA[7:0] to LOW when the ULPI bus is
idle. When the link has data to transmit to the PHY, it drives a nonzero value.
The data bus can be reconfigured to carry various data types, as given in Section 8 and
Section 9.
The DATA[7:0] pins can be 3-stated by driving pin CHIP_SELECT_N to HIGH. Weak
pull-down resistors are inco rporated into the DAT A[7:0] p ins as part of the interface protect
feature. For details, see Section 9.3.1.
Fig 3. External capacitors connection
004aab037
ISP1507
VBUS
C_B
C_A
Ccp(C_A)-(C_B)
OTG VBUS
4.7 μF0.1 μF
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 12 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
7.9.2 VCC(I/O)
The input power pin that set s the I/O volt age level. Fo r det ails, see Section 12, Section 13
and Section 16. VCC(I/O) provides power to on-chip pads of the following pins:
CHIP_SELECT_N
CLOCK
DATA[7:0]
DIR
NXT
RESET_N
STP
7.9.3 RREF
Resistor reference analog I/O pin. A resistor, RRREF, must be connected between RREF
and GND, as shown in Section 16. This provides an accurate voltage reference that
biases internal analog circuitry. Less accurate resistors cannot be used and will render the
ISP1507 unusable.
7.9.4 DP and DM
The DP (data plus) and DM (data minus) are USB differential data pins. These must be
connected to the D+ and D pins of the USB receptacle.
7.9.5 FAULT
If an external VBUS overcurrent or fault circuit is used, the output fault indicator of that
circuit can be connected to the ISP1507 FAULT input pin. The ISP1507 will inform the link
of VBUS fault events by sending RXCMDs on the ULPI bu s. To use the FAULT pin, the link
must:
Set the USE_EXT_VBUS_IND register bit to logic 1.
Set the polarity of the external fault signal using the IND_COMPL register bit.
Set the IND_PASSTHRU register bit to logic 1.
If the FAULT pin is not used, it is recommended to connect to GND.
7.9.6 ID
For OTG implementations, the ID (identification) pin is connected to the ID pin of the
micro-USB recept acle. As defined in On-The-Go Supplement to the USB 2.0 Specification
Rev. 1.3, the ID pin dictates the initial role of the link. If ID is detected as HIGH, the link
must assume the ro le of a pe rip h er al. If ID is detec te d as LOW, the link must assum e a
host role. Roles can be swapped at a later time by using HNP.
If the ISP1507 is not used a s an OTG PHY, but as a standard USB host or peripheral PHY,
the ID pin must be connected to REG3V3.
7.9.7 CPGND
CPGND indicates the analog ground for the o n-board charge pum p. CPGND must always
be connected to ground, even when the charge pump is not used.
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 13 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
7.9.8 C_A and C_B
The C_A and C_B pins are to connect the flying cap acitor of the charge pu mp. The output
current capability of the charge pump depends on the value of the capacitor used, as
shown in Table 3. For maximum efficiency, place capacitors as close as possible to pins.
For details, see Section 16.
If the charge pump is not used, C_A and C_B must be left floating (not connected).
7.9.9 VCC
VCC is the main input supply voltage for the ISP1507. Decoupling capacitors are
recommended. For details, see Section 16.
7.9.10 PSW_N
PSW_N is an active LOW, open-drain output pin. This pin can be connected to an active
LOW, external VBUS switch or charg e pu mp en a ble circu it to co ntro l the ex te rn al VBUS
power source. An external pull-up resistor, Rpullup, is required when PSW_N is used. This
pin is open-drain, allowing ganged-mode power control for multiple USB ports. For
application details, see Section 16.
If the link is in host mode, it can enable the external VBUS power source by setting the
DRV_VBUS_EXT bit in the OTG_CTR L re gist er (se e Section 10.1.4) to logic 1. The
ISP1507 will drive PSW_N to LOW to enable the external VBUS power source. If the link
detects an ov ercurrent conditio n (the VBUS state in RXCMD is not 11b), it must disable the
external VBUS power source by setting DRV_VBUS_EXT to logic 0.
7.9.11 VBUS
This pin acts as an input to VBUS comparators, and also as a powe r pin for th e charge
pump, and SRP charge and discharge resistors.
When the DRV_VBUS bit in the OTG_CTRL register (see Section 10.1.4) is set to logic 1,
the ISP1507 drives VBUS to a voltage of 4.4 V to 5.25 V, with a minimum output current
capability of 8 mA.
Fig 4. Charge pump capacitor
Table 3. Recommended charge pump capacitor value
Ccp(C_A)-(C_B) IL (max)
22 nF 8 mA
270nF 50mA
004aab038
IL
ISP1507
VBUS
C_A
C_B Ccp(C_A)-(C_B)
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 14 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
The VBUS pin requires a capacitive load as shown in Section 16.
To prevent electrical overstress, it is strongly recommended that you atta ch a series
resistor on the VBUS pin (RVBUS). RVBUS must not be attached when using the ISP1507
internal char ge pump. For deta ils, see Section 16.
7.9.12 REG3V3 and REG1V8
Regulator output voltage. Th ese supplies are used to power the ISP1507 internal digital
and analog circuits, and must not be used to power external circuits.
For correct operation of the regulator, it is recommended that you co nnect REG3V3 and
REG1V8 to decoupling capacitors. For examples, see Section 16.
7.9.13 XTAL1 and XTAL2
XTAL1 is the crystal input, and XTAL2 is the crysta l output. The allowed frequency on the
XTAL1 pin depends on the ISP1507 product version.
If the link requires a 60 MHz clock fr om the ISP1507, then either a crystal must be
attach ed, or a clock of the same frequency must be driven into XTAL1, with XTAL2 left
floating.
If a crystal is attached, it requires external load capacitors to GND on each terminal of the
crystal. For details, see Section 16.
If at any time the system wants to stop the clock on XTAL 1, th e link must first put the
ISP1507 into low-power mode. The clock on XTAL1 must be restarted before low-power
mode is exited.
7.9.14 RESET_N
An active LOW asynchronous reset pin that resets all circuits in the ISP1507. The
ISP1507 contains an internal power-on reset circuit, and therefore using the RESET_N
pin is optional. If RESET_N is not used, it must be connected to VCC(I/O).
For details on using RESET_N, see Section 9.3.2.
7.9.15 DIR
ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1507
holds DIR at LOW, causing the data bus to be an input. When DIR is LOW, the ISP1507
listens for data from the link. The ISP1507 pulls DIR to HIGH only when it has data to
send to the link, which is for one of two reasons:
To send USB receive data, RXCMD status updates and register read data to the link.
To block the link from driving the data bus during power-up, reset and low-power
(suspend ) m od e.
The DIR pin can also be 3-stated by driving CHIP_SELECT_N to HIGH.
For details on DIR usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 15 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
7.9.16 STP
ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet
or a register write operation. When DIR is asserted, the link can optionally assert STP to
abort the ISP1507, causing it to deassert DIR in the next clock cycle. A weak pull-up
resistor is incorporated into the STP pin as p art of the interface protect feature. For det ails,
see Section 9.3.1.
The STP input will be ignored when CHIP_SELECT_N is driven to HIGH.
For details o n STP usage, re fe r to UTMI+ Low Pin Interface (ULPI) Sp ecification Rev. 1.1.
7.9.17 NXT
ULPI next data output pin. The ISP1507 holds NXT at LOW, by default. When DIR is LOW
and the link is sending data to the ISP1507, NXT will be asserted to notify the link to
provide the next data byte. When DIR is at HIGH and the ISP1507 is sending data to the
link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is not
used for register read data or the RXCMD status update.
The NXT pin can also be 3-stated by driving CHIP_SELECT_N to HIGH.
For det ails on NXT usage, refer to UTMI+ Low Pin In terface (ULP I) Specification Rev. 1.1.
7.9.18 CLOCK
A 60 MHz interface clock to synchronize the ULPI bus. The ISP1507 provides two
clocking options:
A crystal attached between the XTAL1 and XTAL2 pins.
A clock driven into the XTAL1 pin, with the XTAL2 pin left floating.
For det ails on CLOCK usage, refer to UTMI+ Low Pin Interface (ULPI) Specification
Rev. 1.1.
7.9.19 CHIP_SELECT_N
Active LOW chip select pin. If CHIP_SELECT_N is not used, it must be connected to
GND. For more information on using CHIP_SELECT_N, see Section 9.3.3.
7.9.20 GND (die pad)
Global ground signal, except for the charge pump that uses CPGND. The die pad is
exposed on the under side of the package as a ground plate. This acts as a ground to all
circuits in the ISP1507, except the charge pump. To ensure correct operation of the
ISP1507, GND must be soldered to the cleanest ground available.
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 16 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
8. Modes of operation
8.1 ULPI modes
The ISP1507 ULPI bu s can be programmed to operate in four modes. Each mode
reconfigures the sign als on the data bus a s described in the following su bsections. Setting
more than one mode will lead to undefined behavior.
8.1.1 Synchronous mode
This is default mode. At power-up, and when CLOCK is stable, the ISP1507 will enter
synchronous mode. The link must synchronize all ULPI signa ls to CLOCK, meeting the
set-up time and the hold time as defined in Section 15. A description of the ULPI pin
behavior in synchronous mode i s given in Table 4.
This mode is used by the link to perform the following tasks:
High-speed detection handshake (chirp)
Transmit and receive USB packets
Read and write to registers
Receive USB status updates (RXCMDs)
For more information on various synchronous mode protocols, see Section 9.
Table 4. ULPI signal description
Signal
name Direction
on ISP1507 Signal description
CLOCK O 60 MHz interface clock. If a crystal is attached or a clock is driven into
the XTAL1 pin, the ISP1507 will drive a 60 MHz output clock.
DATA[7:0] I/O 8-bit dat a b us. In synchronous mode, the link drives DATA[7:0] to LOW
by default. The link initiates transfers by sending a nonzero data pattern
called TXCMD (transmit command). In synchronous mode, the direction
of DATA [7:0] is controlled by DIR. Conte nts of DATA[7:0] lines mu st be
ignored for exactly one clock cycle whenever DIR changes value. This
is called the turnaround cycle.
Data lines have fixed direction and different meaning in low-power and
serial modes.
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 17 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
8.1.2 Low-power mode
When the USB is idle, the link can pla ce the ISP1507 into low-power mode (also called
suspend mode). In low-power mode, the data bus definition changes to that shown in
Table 5. To enter low-power mode, the link sets the SUSPENDM bit in the FUNC_CTRL
register (see Section 10.1.2) to logic 0. To exit low-power mode, the link asserts the STP
signal. The ISP1507 will draw only suspend current from the VCC supply (see Table 46).
During low-power mode, the clock on XTAL1 may be stopped. The clock must be started
again before asserting STP to exit low-power mode. After exiting low-power mode, the
ISP1507 will send an RXCMD to the link if a change was detected in any interrupt source,
and the change still exists. An RXCMD may not be sent if the interrupt condition is
removed before exiting.
For more information o n low-power mode enter and exit proto cols, refer to UTMI+ Low Pin
Interface (ULPI) Specification Rev. 1.1.
DIR O Direction: Controls the direction of data bus DATA[7:0]. In synchronous
mode, the ISP1507 drives DIR to LOW by default, making the data bus
an input so that the ISP1507 can listen for TXCMDs from the link. T he
ISP1507 drives DIR to HIGH only when it has data for the link. When
DIR and NXT are HIGH, the byte on the data bus contains decoded
USB data. When DIR is HIGH and NXT is LOW , the byte contains status
information called RXCMD (receive command). The only exception to
this rule is when the PHY returns register read data, where NXT is also
LOW, replacing the usual RXCMD byte. Every change in DIR causes a
turnaround cycle on the data bus, during which DATA[7:0] is not valid
and must be ignored by the link.
DIR is always asserted during low-power and serial mode s.
STP I Stop: In synchronous mode, the link drives STP to HIGH for one cycle
after the last byte of data is sent to the ISP1507. The link can optionally
assert STP to force DIR to be deasserted.
In low-power and serial modes, the link holds STP at HIGH to wake up
the ISP1507, causing the ULPI bus to return to synchronous mode .
NXT O Next: In synchronous mode, the ISP1507 drives NXT to HIGH to throttle
data. If DIR is LOW, the ISP1507 asserts NXT to notify the link to place
the next data byte on DATA[7:0] in the following clock cycle. If DIR is
HIGH, the ISP1507 asserts NXT to notify the link that a valid USB data
byte is on DATA[7:0] in the current cycle. The ISP1507 always drives an
RXCMD when DIR is HIGH and NXT is LOW, unless register read data
is to be returned to the link in the current cycle.
NXT is not used in low-power or serial mode.
Table 4. ULPI signal description …continued
Signal
name Direction
on ISP1507 Signal description
Table 5. Signal mappi ng during low-po we r mode
Signal Map s to Direction Description
LINESTATE0 DATA0 O combinatorial LINESTATE0 directly driven by analog receiver
LINESTATE1 DATA1 O combinatorial LINESTATE1 directly driven by analog receiver
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 18 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
8.1.3 6-pin full-speed or low-speed serial mode
If the link requires a 6-pin s eri al int er fa ce to transm it an d rece ive full-s pe e d or low-s pe ed
USB data, it ca n set the ISP1507 to 6-pin seri al mode. In 6-pin seria l mode, the DATA[7:0]
bus definition ch an ges to that sho wn in Table 6. To enter 6-pin ser i al mode , th e link se ts
the 6PIN_FSLS_SERIAL bit in the INTF_CTRL register (see Section 10.1.3) to logic 1. To
exit 6-pin serial mode, the link assert s STP. This is provided prima rily for links that cont ain
legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path
to high-speed. An interrupt pin is also provid ed to inform the link of USB event s. If th e link
requires CLOCK to be running during 6-pin serial mode, the CLOCK_SUSPENDM
register bit must be set to logic 1.
For more informa tion on 6-pin serial mode enter and exit protocols, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1.
8.1.4 3-pin full-speed or low-speed serial mode
If the link requires a 3-pin s eri al int er fa ce to transm it an d rece ive full-s pe e d or low-s pe ed
USB data, it can set the ISP1507 to 3-pin serial mode. In 3-pin serial mode, the data bus
definition changes to that shown in Table 7. To enter 3-pin ser ial mo d e, the link sets the
3PIN_FSLS_SERIAL bit in the INTF_CTRL register (see Section 10.1.3) to logic 1. To exit
3-pin serial mode, the link asserts STP. This is primarily provided for links that contain
legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path
to high-speed. An interrupt pin is also provid ed to inform the link of USB event s. If th e link
requires CLOCK to be running during 3-pin serial mode, the CLOCK_SUSPENDM
register bit must be set to logic 1.
For more informa tion on 3-pin serial mode enter and exit protocols, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1.
Reserved DATA 2 O reserved; the ISP1507 will driv e this pin to LOW
INT DATA3 O active HIGH interrupt indication; will be asserted whenever any unmasked
interrupt occurs
Reserved DATA[7:4] O reserved; the ISP1507 will drive these pins to LOW
Table 5. Signal mappi ng during low-po we r mode …continued
Signal Map s to Direction Description
Table 6. Signal mapping for 6-pin serial mode
Signal Map s to Direction Description
TX_ENABLE DATA0 I active HIGH transmit enable
TX_DAT DATA1 I transmit differential data on DP and DM
TX_SE0 DATA2 I transmit single-ended zero on DP and DM
INT DATA3 O active HIGH interrupt indication; will be asserted whenever any
unmasked interrupt occurs
RX_DP DATA4 O single-en ded receive data from DP
RX_DM DATA5 O single-en ded receive data from DM
RX_RCV DATA6 O dif ferential receive data from DP and DM
Reserved DATA7 O reserved; the ISP1507 will drive this pin to LOW
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 19 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
8.2 USB and OTG state transitions
A Hi-S peed USB p eripheral, host or OTG device handles more than one electrical st ate as
defined in Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the
USB 2.0 Specification Rev. 1.3. The ISP1507 accommodates various states through
register bit settings of XCVRSELECT[1:0], TERMSELECT, OPMODE[1:0],
DP_PULLDOWN and DM_PULLDOWN.
Table 8 summarizes operating states. The values of register settings in Table 8 will force
resistor setting s as als o giv en in Table 8. Resistor setting signals are defined as follows:
RPU_DP_EN enables the 1.5 kΩ pull-up resistor on DP
RPD_DP_EN enables the 15 kΩ pull-down resistor on DP
RPD_DM_EN enables the 15 kΩ pull-down resistor on DM
HSTERM_EN enables the 45 Ω termination resistors on DP and DM
It is up to the link to set the desired register settings.
Table 7. Signal mapping for 3-pin serial mode
Signal Map s to Direction Description
TX_ENABLE DATA0 I active HIGH transmit enable
DAT DATA1 I/O transmit differential data on DP and DM when TX_ENABLE is HIGH
receive differential data from DP and DM when TX_ENABLE is LOW
SE0 DATA2 I/O transmit single-ended zero on DP and DM when TX_ENABLE is HIGH
receive single-ended zero from DP and DM when TX_ENABLE is LOW
INT DATA3 O active HIGH interrupt indication; will be asserted whenever any
unmasked interrupt occurs
Reserved DATA[7:4] O reserved; the ISP1507 wil l drive these pins to LOW
Table 8. Operating states and their corresponding resistor settings
Signaling mode Register se tti ngs Internal resistor settings
XCVR
SELECT
[1:0]
TERM
SELECT OPMODE
[1:0] DP_PULL
DOWN DM_PULL
DOWN RPU_
DP_EN RPD_
DP_EN RPD_
DM_EN HSTERM
_EN
General settings
3-state drivers XXb Xb 01b Xb Xb 0b 0b 0b 0b
Power-up or
VBUS <V
B_SESS_END
01b 0b 00b 1b 1b 0b 1b 1b 0b
Host settings
Host chirp 00b 0b 10b 1b 1b 0b 1b 1b 1b
Host high-speed 00b 0b 00b 1b 1b 0b 1b 1b 1b
Host full-speed X1 b 1b 00b 1b 1b 0b 1b 1b 0b
Host high-speed or
full-speed suspend 01b 1b 00b 1b 1b 0b 1b 1b 0b
Host high-speed or
full-speed resume 01b 1b 10b 1b 1b 0b 1b 1b 0b
Host low-speed 10b 1b 00b 1b 1 b 0b 1b 1b 0b
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 20 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
Host low-speed
suspend 10b 1b 00b 1b 1b 0b 1b 1b 0b
Host low-speed
resume 10b 1b 10b 1b 1b 0b 1b 1b 0b
Host Test J or Test K 00b 0b 10b 1b 1b 0b 1b 1b 1b
Peripheral settings
Peripheral chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b
Peripheral
high-speed 00b 0b 00b 0b 0b 0b 0b 0b 1b
Peripheral full-speed 01b 1b 00b 0b 0b 1b 0b 0b 0b
Peripheral
high-speed or
full-speed suspend
01b 1b 00b 0b 0b 1b 0b 0b 0b
Peripheral
high-speed or
full-speed resume
01b 1b 10b 0b 0b 1b 0b 0b 0b
Peripheral Test J or
Test K 00b 0b 10b 0b 0b 0b 0b 0b 1b
OTG settings
OTG device
peripheral chirp 00b 1b 10b 0b 1b 1b 0b 1b 0b
OTG device
peripheral
high-speed
00b 0b 00b 0b 1b 0b 0b 1b 1b
OTG device
peripheral full-speed 01b 1b 00b 0b 1b 1b 0b 1b 0b
OTG device
peripheral
high-speed and
full-speed suspend
01b 1b 00b 0b 1b 1b 0b 1b 0b
OTG device
peripheral
high-speed and
full-speed resume
01b 1b 10b 0b 1b 1b 0b 1b 0b
OTG device
peripheral Test J or
Test K
00b 0b 10b 0b 1b 0b 0b 1b 1b
Table 8. Operating states and their corresponding resistor settings …continued
Signaling mode Register se tti ngs Internal resistor settings
XCVR
SELECT
[1:0]
TERM
SELECT OPMODE
[1:0] DP_PULL
DOWN DM_PULL
DOWN RPU_
DP_EN RPD_
DP_EN RPD_
DM_EN HSTERM
_EN
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 21 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
9. Protocol description
The following subsections describe the protocol for using the ISP1507.
9.1 ULPI references
The ISP1507 provides a 12-pin ULPI interface to communicate with the link. It is highly
recommended that you read UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 and
UTMI+ Specification Rev. 1.0.
9.2 Power-On Reset (POR)
An internal POR is generated when REG1V8 rises above VPOR(trip), for at least
tw(REG1V8_H). The internal POR pulse will also be generated whenever REG1V8 drops
below VPOR(trip) for more than tw(REG1V8_L), and then rises above VPOR(trip) again. The
voltage on REG1V8 is generated from VCC.
To give a better view of the functionality, Figure 5 shows a possible curve of REG1V8. The
internal POR starts with logic 0 at t0. At t1, the detector will see the passing of the trip
level so that POR turns to logic 1 and a delay element will add another tPORP before it
drops to logic 0. If REG1V8 dips from t2 to t3 for > tw(REG1V8_L), another POR pulse is
generated. If the dip at t4 to t5 is too short, that is, < tw(REG1V8_L), the internal POR pulse
will not react and will remain LOW.
9.3 Power-up, reset and bus idle sequence
Figure 6 shows a typical start-up sequence.
On power-up, the ISP1507 performs an internal power-on reset and asserts DIR to
indicate to the link that the ULPI bus cannot be used. When the intern al PLL is st able, the
ISP1507 deasserts DIR. The power-up time depends on the VCC supply rise time, the
crystal st art-up time, and PLL st art-up time tstartup(o)(CLOCK). Whenever DIR is asserted, the
ISP1507 drives the NXT pin to LOW and drives DATA[7:0] with RXCMD values. When
DIR is deasserted, the link must drive the data bus to a valid level. By default, the link
must drive data to LOW. When the ISP1507 initially deasserts DIR on power-up, the link
must ignore all RXCMDs until it resets the ISP1507. Before beginning USB p ackets, the
link must set the RESET bit in the FUNC_CTRL register (see Section 10.1.2) to reset the
ISP1507. After the RESET bit is set, the ISP1507 will assert DIR until the internal reset
completes. The ISP1507 will automatically deassert DIR and clear the RESET bit when
reset has completed. After ever y reset, an RXCMD is sent to the link to update USB st atus
information. After this sequence, the ULPI bus is re ady fo r use and the link can start USB
operations.
Fig 5. Internal power-on reset timing
004aaa751
REG1V8
t0 t1 t2 t3 t4 t5
VPOR(trip)
tPORP POR
tPORP
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 22 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1507 will drive a
60 MHz clock out from the CLOCK pin when DIR deasserts. This is shown as CLOCK in
Figure 6.
The recommended power-up sequence for the link is as follows:
1. The link waits for tREGUP, ignoring all the ULPI pin status.
2. The link may st art to dete ct DIR status level. If DIR is detected as LOW for three clock
cycles, the link may send a RESET command.
The ULPI interface is ready for use.
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 23 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
9.3.1 Interface protection
By default, the ISP1507 enables a weak pull-up resistor on STP. If the STP pin is
unexpectedly HIGH at any time, the ISP1507 will protect the ULPI interface by enabling
weak pull-down resistors on DATA[7:0].
t1 = VCC and VCC(I/O) are applied to the ISP1507. The ISP1507 regulator starts to turn on.
t2 = ULPI pads detect REG1V8 rising above the REG1V8 regulator threshold and are not in 3-state. These pads may drive
either LOW or HIGH. It is recommended that the link ignores the ULPI pins status during tREGUP.
t3 = The POR threshold is reached and a POR pulse is generated. After the POR pulse, ULPI pins are driven to a defined level.
DIR is driven to HIGH and the other pins are drive n to LOW.
t4 = The ISP1507 regulator is powered up and is stable.
t5 = The internal PLL is stabilized after tstartup(PLL). If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL will
be stabilized after tstartup(PLL) from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH to LOW .
The DIR pin will remain LOW before the link issues a RESET command to the ISP1507.
t6 = The power-up sequence is completed and the ULPI bus interface is ready for use.
Fig 6. Power-up and reset sequence required before the ULPI bus is ready for use
CLOCK
TXCMD
DIR
DATA[7:0]
STP
NXT
004aaa885
RESET command
internal clocks stable
internal reset RXCMD
update
bus idle
D
VCC
VCC(I/O)
REG1V8
internal
REG1V8
detector
internal
POR
XTAL1
tstartup(PLL)
t1 t2 t3 t4 t5
tREGUP
t6
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 24 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
The interface protect feature prevents unwanted activity of the ISP1507 whenever the
ULPI interface is not correctly driven by the link. For example, when the link powers up
more slowly than the ISP1507.
The interface protect feature can be disabl ed by setting the INTF_PROT_DIS bit to
logic 1.
9.3.2 Interface behavior with respect to RESET_N
The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the
ISP1507 will assert DIR. All logic in the ISP1507 will be reset, including the analog
circuitry and UL PI reg isters. Du ring reset, the lin k must drive DATA[7:0] and STP to LOW;
otherwise undefined behavior may result. When RESET_N is deasserted (HIGH), the DIR
output will deassert (LOW) four or five clock cycles later. Figure 7 shows the ULPI
interface behavior when RESET_N is asserted (LOW), and subsequently deasserted
(HIGH). The behavior of Figure 7 applies only when CHIP_SELECT_N is asserted
(LOW). If RESET_N is not used, it must be connected to VCC(I/O).
9.3.3 Interface behavior with respect to CHIP_SELECT_N
At any time that CHIP_SELECT_N is HIGH, the ISP1507 will 3-state DATA[7:0], NXT and
DIR. STP input will be ignored. The link can reuse these pins for other purposes.
When CHIP_SELECT_N is LOW, ULPI output pins operate normally. During normal
operation, the PLL is always powered, regardless of the level of CHIP_SELECT_N.
During power-up, if CHIP_SELECT_N is HIGH, the PLL is not powered up to reduce
power consum p tion . Du rin g po wer-up, if CHIP_SELECT_N is LOW, the PLL is powered
and the ISP1507 operates normally.
If CHIP_SELECT_N is HIGH:
The DATA[7:0], NXT and DIR pins are 3-stated and ignored.
If the ISP1507 was previously in synchronous mode, the STP pin is ignored. If the
ISP1507 was previously in serial or suspend mode, STP is used to exit.
The pull-down resistors on DATA[7:0] are disabled.
Fig 7. Interface behavior with respect to RESET_N
CLOCK
004aaa720
STP
RESET_N
DATA[7:0]
DIR
NXT
Hi-Z (input)
Hi-Z (input)
Hi-Z (input)
Hi-Z (input)
Hi-Z (link must drive)
Hi-Z (link must drive)
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 25 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
The ULPI controller is forced into an idle state and any ULPI command is ignored.
Fig 8. Ente ring and exiting 3-state in normal mode
Remark: Clock timing is not to scale.
Fig 9. Entering and exiting 3-state in suspend mode
CLOCK
004aaa691
CHIP_
SELECT_N
entering
3-state mode exiting
3-state mode
3-stated pins
DATA[7:0]
DIR
NXT
STP
TXCMD DATA
entering
suspend mode exiting
suspend mode
SUSPENDM
input ignored
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 26 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
9.4 VBUS power and fault detection
9.4.1 Driving 5 V on VBUS
The ISP1507 provi des a built-in charge pump. To enable the charge pump, the link must
set the DRV_VBUS bit in the OTG_CTRL register (see Section 10.1.4).
The ISP1507 also supports external 5 V supplies. The ISP1507 can control the external
supply using the active-LOW PSW_N open-dr ain output pin. To enable the external supply
by driving PSW_N to LOW, the link must set the DRV_VBUS_EXT bit in the OTG_CTRL
register to logic 1. The link can optionally set both the DRV_VBUS and DRV_VBUS_EXT
bits to logic 1 to enable the external supply.
Table 9 summarizes settings to drive 5 V on VBUS.
9.4.2 Fault detection
The ISP1507 supports external VBUS fault detector circuits that output a digital fault
indicator signal. The indicator signal must be connected to the FAULT pin. To enable the
ISP1507 to monitor the digital fault input, the link must set the USE_EXT_VBUS_IND bit
in the OTG_CTR L regist er (se e Section 10.1.4) and the IND_PASSTHRU bit in the
INTF_CTRL register (see Section 10.1.3) to logic 1. For details, see Figure 11.
The FAULT input pin is mapped to the A_VBUS_VLD bit in RXCMD. Any changes for the
FA ULT input will trigger RXCMD carrying the FAULT condition with A_VBUS_VLD.
9.5 TXCMD and RXCMD
Commands between the ISP1507 and the link are described in the following subsections.
9.5.1 TXCMD
By default, the link must drive the ULPI b us to its idle st ate of 00h. To send commands and
USB packets, the link drives a nonzero value on DATA[7:0] to the ISP1507 by sending a
byte called TXCMD. Commands includ e USB packet transmissions, and register reads
and writes. Once the TXCMD is interpreted and acce pted by the ISP150 7, the NXT signal
is asserted and the link can follow up with the required number of data bytes. The TXCMD
byte format is given in Table 10. Any values other than those in Table 10 are illegal and
may result in undefined behavior.
Various TXCMD packet and register sequences are shown in later sec tio ns .
Table 9. OTG_CTRL register po wer control bits
DRV_VBUS DRV_VBUS_EXT Power source used
0 0 internal and external VBUS power sources are disabled
10 internal V
BUS charge pump is enabled
X 1 external 5 V VBUS supply is enabled
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 27 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
9.5.2 RXCMD
The ISP1507 communicates status information to the link by asserting DIR and sending
an RXCMD byte on the data bus. The RXCMD data byte format is given in Table 11.
The ISP1507 will automatically send an RXCMD whenever there is a change in any of the
RXCMD data fields. The link must be able to accept an RXCMD at any time; including
single RXCMDs, back-to-back RXCMDs, and RXCMDs at any time during USB receive
packets when NXT is LOW. An example is shown in Figure 10. For details and diagrams,
refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
An RXCMD may not be sent when exiting low-power mode or serial mode, if the interrupt
condition is removed before exiting.
Table 10. TXCMD byte format
Command
type name Command code
DATA[7:6] Command payload
DATA[5:0] Command
name Command description
Idle 00b 00 0000b NOOP No operation. 00h is the idle value of the data bus.
The link must drive NOOP by default.
Packet
transmit 01b 00 0000b NOPID Transmit USB data that does not have a PID, such
as chirp and resume signaling. The ISP1507 starts
transmitting only after accepting the next data byte.
00 XXXXb PID Transmit USB packet. DATA[3:0] indicates USB
packet identifier PID[3:0].
Register
write 10b 10 1111b EXTW Extended register write command (optional). The
8-bit address must be provided after the command is
accepted.
XX XXXXb REGW Register write command with 6-bit immediate
address.
Register read 11b 10 1111b EXTR Extended register read command (optional). The
8-bit address must be provided after the command is
accepted.
XX XXXXb REGR Register read command with 6-bit immediate
address.
Table 11. RXCMD byte format
DATA Name Description and valu e
1to0 LINESTATE LINESTATE signals: For a definition of LINESTATE, see Section 9.5.2.1.
DATA0 — LINESTATE[0]
DATA1 — LINESTATE[1]
3to2 V
BUS state Encoded VBUS voltage state: For an explanation of the VBUS state, see Section 9.5.2.2.
5to4 RxEvent Encoded USB event signals: For an explanation of RxEvent, see Section 9.5.2.4.
6 ID Set to the value of the ID pin.
7 ALT_INT By default, this signal is not used and is not needed in typical designs. Optionally , the link can enable
the BVALID_RISE and/or BVALID_FALL bits in the PWR_CTRL register (see Section 10.1.14).
Corresponding changes in BVALID will cause an RXCMD to be sent to the link with the ALT_INT bit
asserted.
CD00222689 © ST-ERICSSON 2010. All rights reserved.
Product data sheet Rev. 04 — 20 May 2010 28 of 81
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
9.5.2.1 Linestate encoding
LINESTATE[1:0] reflects the current state of DP and DM. Whenever the ISP1507 detects
a change in DP or DM, an RXCMD will be sent to the link with the new LINESTATE[1:0]
value. The value given on LINESTATE[1:0] depends on the setting of various registers.
Table 12 shows the LINESTATE[1:0] encoding for upstr eam facin g port s, wh ich applies to
peripherals. Table 13 shows the LINESTATE[1:0] encoding for downstream facing ports,
which applies to host controllers. Dual-role devices must choose the correct table,
depending on whether it is in peripheral or host mode.
[1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output.
Fig 10. Single and back-to-back RXCMDs from the ISP1 507 to the link
CLOCK
RXCMD
DATA[7:0]