NC7S08 TinyLogic(R) HS 2-Input AND Gate Features General Description Space saving SOT23 or SC70 5-lead package The NC7S08 is a single 2-Input high performance CMOS AND Gate. Advanced Silicon Gate CMOS fabrication assures high speed and low power circuit operation over a broad VCC range. ESD protection diodes inherently guard both inputs and output with respect to the VCC and GND rails. Three stages of gain between inputs and outputs assures high noise immunity and reduced sensitivity to input edge rate. Ultra small MicroPakTM Pb-Free leadless package High Speed; tPD 3.5ns typ Low Quiescent Power; ICC < 1A Balanced Output Drive; 2mA IOL, -2mA IOH Broad VCC Operating Range; 2V-6V Balanced Propagation Delays Specified for 3V operation Ordering Information Order Number Package Number Product Code Top Mark NC7S08M5X MA05B 7S08 5-Lead SOT23, JEDEC MO-178, 1.6mm 3k Units on Tape and Reel NC7S08P5X MAA05A S08 5-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3k Units on Tape and Reel NC7S08L6X MAC06A PP 6-Lead MicroPak, 1.0mm Wide 5k Units on Tape and Reel Package Description Supplied As Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. (c)1995 Fairchild Semiconductor Corporation NC7S08 Rev. 1.9.0 www.fairchildsemi.com NC7S08 -- TinyLogic(R) HS 2-Input AND Gate March 2008 Logic Symbol Pin Assignments for SC70 and SOT23 IEEE/IEC Function Table Y = AB (Top View) Inputs A Pad Assignments for MicroPak Output B Y L L L L H L H L L H H H H = HIGH Logic Level L = LOW Logic Level (Top Thru View) Pin Description Pin Names Description A, B Inputs Y Output NC No Connect (c)1995 Fairchild Semiconductor Corporation NC7S08 Rev. 1.9.0 www.fairchildsemi.com 2 NC7S08 -- TinyLogic(R) HS 2-Input AND Gate Connection Diagram Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC IIK Parameter Supply Voltage -0.5V to +7.0V DC Input Diode Current @ VIN -0.5V @ VIN VCC +0.5V VIN DC Input Voltage IOK DC Output Diode Current @ VOUT < -0.5V @ VOUT > VCC +0.5V -20mA +20mA -0.5V to VCC+0.5V -20mA +20mA VOUT DC Output Voltage IOUT DC Output Sourceor Sink Current ICC or IGND Rating -0.5V to VCC + 0.5V 12.5mA DC VCC or Ground Current per Output Pin 25mA TSTG Storage Temperature -65C to +150C TJ Junction Temperature 150C TL Lead Temperature (Soldering, 10 seconds) 260C PD Power Dissipation @ +85C SOT23-5 SC70-5 200mW 150mW Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Rating VCC Supply Voltage VIN Input Voltage 0V to VCC Output Voltage 0V to VCC VOUT TA Operating Temperature tr , tf Input Rise and Fall Time VCC @ 2.0V VCC @ 3.0V VCC @ 4.5V VCC @ 6.0V JA 2.0V to 6.0V -40C to +85C 0ns to 1000ns 0ns to 750ns 0ns to 500ns 0ns to 400ns Thermal Resistance SOT23-5 SC70-5 300C/W 425C/W Notes: 1. Unused inputs must be held HIGH or LOW. They may not float. (c)1995 Fairchild Semiconductor Corporation NC7S08 Rev. 1.9.0 www.fairchildsemi.com 3 NC7S08 -- TinyLogic(R) HS 2-Input AND Gate Absolute Maximum Ratings TA = -40C to +85C TA = +25C Symbol VIH VIL VOH VOL Parameter VCC (V) Min. Conditions Typ. Max. Min. Max. HIGH Level Input Voltage 2.0 1.50 1.50 3.0-6.0 0.7 x VCC 0.7 x VCC LOW Level Input Voltage 2.0 0.50 0.50 3.0-6.0 0.3 x VCC 0.3 x VCC HIGH Level Output Voltage LOW Level Output Voltage 2.0 3.0 IOH = -20A, VIN = VIH 1.90 2.0 1.90 2.90 3.0 2.90 4.5 4.40 4.5 4.40 6.0 5.90 6.0 5.90 3.0 VIN = VIH, IOH = -1.3mA 2.68 2.85 2.63 4.5 VIN = VIH, IOH = -2mA 4.18 4.35 4.13 6.0 VIN = VIH, IOH = -2.6mA 5.68 5.85 5.63 2.0 IOL = 20A VIN = VIL V V V 0.0 0.10 0.10 0.0 0.10 0.10 4.5 0.0 0.10 0.10 6.0 0.0 0.10 0.10 3.0 Units 3.0 VIN = VIH or VIL, IOH = 1.3mA 0.1 0.26 0.33 4.5 VIN = VIH or VIL, IOL = 2mA 0.1 0.26 0.33 6.0 VIN = VIH or VIL, IOL = 2.6mA 0.1 0.26 0.33 V IIN Input Leakage Current 6.0 VIN = VCC, GND 0.1 1.0 A ICC Quiescent Supply Current 6.0 VIN = VCC, GND 1.0 10.0 A (c)1995 Fairchild Semiconductor Corporation NC7S08 Rev. 1.9.0 www.fairchildsemi.com 4 NC7S08 -- TinyLogic(R) HS 2-Input AND Gate DC Electrical Characteristics TA = -40C to +85C TA = +25C Symbol Parameter tPLH, tPHL Propagation Delay tTLH, tTHL Output Transition Time Min. VCC (V) Conditions Typ. Max. Min. Max. 5.0 CL = 15pF 3.5 15 2.0 CL = 50pF 20 100 125 3.0 11 27 35 4.5 8 20 25 6.0 7 17 21 5.0 CL = 15pF 3.0 10 2.0 CL = 50pF 25 125 155 3.0 16 35 45 4.5 11 25 31 6.0 9 21 26 2 10 10 CIN Input Capacitance Open CPD Power Dissipation Capacitance 5.0 (2) 6 Figure Units Number ns Figure 1 Figure 3 ns Figure 1 Figure 3 pF pF Figure 2 Note: 2. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output loading and operating at 50% duty cycle. (See Figure 2.) CPD is related to ICCD dynamic operating current by the expression: ICCD = (CPD)(VCC)(fIN) + (ICCstatic). AC Loading and Waveforms CL includes load and stray capacitance Input PRR = 1.0 MHz; tW = 500 ns Figure 1. AC Test Circuit Figure 3. AC Waveforms Input = AC Waveform; PRR = variable; Duty Cycle = 50% Figure 2. ICCD Test Circuit (c)1995 Fairchild Semiconductor Corporation NC7S08 Rev. 1.9.0 www.fairchildsemi.com 5 NC7S08 -- TinyLogic(R) HS 2-Input AND Gate AC Electrical Characteristics Tape Format for SC70 and SOT23 Package Designator Tape Section Number Cavities Cavity Status Cover Tape Status M5X, P5X Leader (Start End) 125 (typ.) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (typ.) Empty Sealed Tape Dimensions inches (millimeters) Package Tape Size Dim A Dim B Dim F Dim Ko Dim P1 Dim W SC70-5 8mm 0.093 (2.35) 0.096 (2.45) 0.138 0.004 (3.5 0.10) 0.053 0.004 (1.35 0.10) 0.157 (4) 0.315 0.004 (8 0.1) SOT23-5 8mm 0.130 (3.3) 0.130 (3.3) 0.138 0.002 (3.5 0.05) 0.055 0.004 (1.4 0.11) 0.157 (4) 0.315 0.012 (8 0.3) (c)1995 Fairchild Semiconductor Corporation NC7S08 Rev. 1.9.0 www.fairchildsemi.com 6 NC7S08 -- TinyLogic(R) HS 2-Input AND Gate Tape and Reel Specifications Tape Format for MicroPak Package Designator Tape Section Number Cavities Cavity Status Cover Tape Status L6X Leader (Start End) 125 (typ.) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (typ.) Empty Sealed Reel Dimensions inches (millimeters) Tape Size A B 8mm 7.0 (177.8) 0.059 (1.50) (c)1995 Fairchild Semiconductor Corporation NC7S08 Rev. 1.9.0 C D N 0.512 0.795 2.165 (13.00) (20.20) (55.00) W1 W2 W3 0.331 + 0.059/-0.000 (8.40 + 1.50/-0.00) 0.567 (14.40) W1 + 0.078/-0.039 (W1 + 2.00/-1.00) www.fairchildsemi.com 7 NC7S08 -- TinyLogic(R) HS 2-Input AND Gate Tape and Reel Specifications (Continued) CL 3.00 2.80 5 0.95 A 0.95 4 B 3.00 2.60 1.70 1.50 1 2 2.60 3 (0.30) 1.00 0.50 0.30 0.95 1.90 0.20 C A B 0.70 TOP VIEW LAND PATTERN RECOMMENDATION SEE DETAIL A 1.30 0.90 1.45 MAX 0.15 0.05 0.22 0.08 C 0.10 C NOTES: UNLESS OTHEWISE SPECIFIED GAGE PLANE A) THIS PACKAGE CONFORMS TO JEDEC MO-178, ISSUE B, VARIATION AA, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) MA05Brev5 0.25 8 0 0.55 0.35 0.60 REF SEATING PLANE Figure 4. 5-Lead SOT23, JEDEC MO-178, 1.6mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1995 Fairchild Semiconductor Corporation NC7S08 Rev. 1.9.0 www.fairchildsemi.com 8 NC7S08 -- TinyLogic(R) HS 2-Input AND Gate Physical Dimensions NC7S08 -- TinyLogic(R) HS 2-Input AND Gate Physical Dimensions (Continued) Figure 5. 5-Lead SC70, EIAJ SC-88a, 1.25mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1995 Fairchild Semiconductor Corporation NC7S08 Rev. 1.9.0 www.fairchildsemi.com 9 2X 0.05 C 1.45 B 2X (1) 0.05 C (0.49) 5X 1.00 (0.75) (0.52) 1X A TOP VIEW 0.55MAX (0.30) 6X PIN 1 0.05 C 0.05 0.00 RECOMMENED LAND PATTERN 0.05 C C DETAIL A 0.25 0.15 6X 1.0 0.10 0.05 0.45 0.35 0.10 0.00 6X C B A C 0.40 0.30 0.35 5X 0.25 0.40 5X 0.30 (0.05) 6X 0.5 BOTTOM VIEW 0.075 X 45 CHAMFER DETAIL A PIN 1 TERMINAL (0.13) 4X Notes: 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.5M-1994 MAC06AREVC Figure 6. 6-Lead MicroPak, 1.0mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1995 Fairchild Semiconductor Corporation NC7S08 Rev. 1.9.0 www.fairchildsemi.com 10 NC7S08 -- TinyLogic(R) HS 2-Input AND Gate Physical Dimensions (Continued) ACEx(R) Build it NowTM CorePLUSTM CROSSVOLTTM CTLTM Current Transfer LogicTM EcoSPARK(R) EZSWITCHTM * TM PDP-SPMTM Power220(R) POWEREDGE(R) Power-SPMTM PowerTrench(R) Programmable Active DroopTM QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM SMART STARTTM SPM(R) STEALTHTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 FPSTM FRFET(R) Global Power ResourceSM Green FPSTM Green FPSTMe-SeriesTM GTOTM i-LoTM IntelliMAXTM ISOPLANARTM MegaBuckTM MICROCOUPLERTM MicroFETTM MicroPakTM MillerDriveTM Motion-SPMTM OPTOLOGIC(R) OPTOPLANAR(R) (R) Fairchild(R) Fairchild Semiconductor(R) FACT Quiet SeriesTM FACT(R) FAST(R) FastvCoreTM FlashWriter(R) * (R) SupreMOSTM SyncFETTM (R) The Power Franchise(R) TinyBoostTM TinyBuckTM TinyLogic(R) TINYOPTOTM TinyPowerTM TinyPWMTM TinyWireTM SerDesTM UHC(R) Ultra FRFETTM UniFETTM VCXTM * EZSWITCHTM and FlashWriter(R) are trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I33 (c)1995 Fairchild Semiconductor Corporation NC7S08 Rev. 1.9.0 www.fairchildsemi.com 11 NC7S08 -- TinyLogic(R) HS 2-Input AND Gate TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.