1.5SMCJ48A - DIOTEC SEMICONDUCTOR AG

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Features

MT9V137 DS- Rev. E Pub. 4/15 EN 1©Semiconductor Components Industries, LLC,2015

1/4-Inch Color CMOS NTSC/PAL Digital Image SOC

with Overlay Processor

MT9V137 Datasheet, Rev. E

For the latest datasheet, please visit www.onsemi.com

Features

• Low-power CMOS image sensor with integrated

image flow processor (IFP) and video encoder

• 1/4-inch optical format, VGA resolution (640H x

480V)

• ±2.5% additional columns and rows to compensate

for lens alignment tolerances

• Overlay generator for dynamic bitmap overlay

• Integrated video encoder for NTSC/PAL with overlay

capability and 10-bit I-DAC

• Integrated microcontroller for flexibility

• On-chip image flow processor performs

sophisticated processing, such as color recovery and

correction, sharpening, gamma, lens shading

correction, on-the-fly defect correction, auto white

balancing, and auto exposure

• Auto black level calibration

• 10-bit, on-chip analog-to-digital converter (ADC)

• Internal master clock generated by on-chip phase-

locked loop (PLL)

• Two-wire serial programming interface

• Interface to low-cost Flash through SPI bus

• High-level host command interface

• Stand alone operation support

• Comprehensive tool support for overlay generation

and lens correction setup

• Development system with DevWare

• Overlay generation and compilation tools

Applications

• Analog surveillance CCTV

• Surveillance network IP camera

Key parameters are continued on next page.

See details of new features on page 3.

See “Ordering Information” on page 4.

Table 1: Key Parameters

Parameter Typical Value

Pixel size

and type

5.6 m x 5.6 m active pinned-

photodiode with high-sensitivity mode

for low-light conditions

Sensor format 680H x 512V (includes ±2.5% of rows

and columns for lens alignment)

NTSC output 720H x 480V

PAL output 720H x 576V

Imaging area Total array size: 3.584 mm x 2.688 mm

Optical format ¼-inch

Frame rate 50/60 fields/sec

Sensor scan mode Progressive scan

Color filter array RGB standard Bayer

Shutter type Electronic rolling shutter (ERS)

Automatic

Functions

Exposure, white balance, black level

offset correction, flicker avoidance,

color saturation control, on-the-fly

defect correction, aperture correction

Programmable

Controls

Exposure, white balance, horizontal

and vertical blanking, color, sharpness,

gamma correction, lens shading

correction, horizontal and vertical

image flip, zoom, windowing, sampling

rates, GPIO control

MT9V137 DS- Rev. E Pub. 4/15 EN 2©Semiconductor Components Industries, LLC,2015.

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Applications

Notes: 1. Graphical overlay is available only in CCIR656 output format.

2. Analog output enabled; parallel output disabled.

Table 2: Key Parameters (continued)

Parameter Typical Value

Overlay Support1

Utilizes SPI interface to load overlay data from external flash/EEPROM memory with the

following features:

•Overlay Size 360 x 480 pixel rendered into 720 x 480 pixel display format

•Up to four (4) overlays may be blended simultaneously

•Selectable readout: Rotating order user selected

•Dynamic scenes by loading pre-rendered frames from external memory

•Palette of 32 colors out of 64,000

•8 colors per bitmap

•Blend factor dynamically programmable for smooth transitions

•Fast Update rate of up to 30 fps

•Every bitmap object has independent x/y position

•Statistic Engine to calibrate optical alignment

•Number Generator

Windowing Programmable to any size

Max analog gain 0.5–16x

ADC 10-bit, on-chip

Output interface Analog composite video out, single-ended or differential; 8-, 10-bit parallel digital

output

Output data formats1Digital: Raw Bayer 8-,10-bit, CCIR656, 565RGB, 555RGB, 444RGB

Data rate

Parallel: 27 MB/s

NTSC: 60 fields/sec

PAL: 50 fields/sec

Control interface

Two-wire I/F for register interface plus high-level command exchange. SPI port to

interface to external memory to load overlay data, register settings, or firmware

extensions.

Input clock for PLL 27 MHz

SPI Clock Frequencies 4.5 - 9.0 - 18 MHz, programmable

Supply voltage

Analog: 2.8 V ±5%

Core: 1.8 V ±5%

IO: 2.8V ±5%

Power consumption Full resolution at 60 fps: <350mW2

Package 48-pin Ceramic LCC, 11.43mm x 11.43mm, 0.8mm pitch

Ambient temperature

Operating: –30°C to 70°C

Storage: –50°C to +150°C

Dark Current < 200e/s at 60°C with a gain of 1

Fixed pattern noise Column < 2%

Row < 2%

Responsivity 11.9 V/lux-s at 550nm

Signal to noise ratio (S/N) 45 dB

Pixel dynamic range 74.6 dB

MT9V137 DS- Rev. E Pub. 4/15 EN 3©Semiconductor Components Industries, LLC,2015.

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

New Features

Integrated Video Encoder for PAL/NTSC with Overlay Capability

• Composite analog output (NTSC/PAL)

• 8-bit parallel digital output ITU-R BT.656 format

• Raw Bayer format

On-Chip Overlay Generator

• Static and dynamic overlay graphics with four overlay planes plus number plane

• Support for serial SPI memory up to 16 megabytes

•Number generator

• Overlay blending and x/y positioning

• Overlay position adjustment and statistics engine to calibrate overlay

• Overlay support utilizes SPI interface to load overlay data from external

Serial Flash/EEPROM to support the following features:

– Overlay size 360 x 480 pixel rendered into 720 x 480 pixel display format

– Up to four overlays may be blended simultaneously

– Selectable readout: rotating order user selected

– Dynamic scenes by loading pre-rendered frames from external memory

– Palette of 32 colors out of 64,000

– Eight colors per bitmap

– Blend factor dynamically programmable for smooth transitions

– Fast update rate of up to 30 fps

– Every bitmap object has independent x/y position

– Statistics engine to calibrate optical alignment

–

MT9V137 DS- Rev. E Pub. 4/15 EN 4©Semiconductor Components Industries, LLC,2015.

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Ordering Information

Table 3: Available Part Numbers

Part Number Product Description Orderable Product Attribute Description

MT9V137C12STC-DP VGA 1/4" SOC Dry Pack with Protective Film

MT9V137C12STC-DR VGA 1/4" CIS SOC Dry Pack without Protective Film

MT9V137 DS- Rev. E Pub. 4/15 EN 5©Semiconductor Components Industries, LLC,2015.

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

New Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Pin Descriptions and Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

SOC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Sensor Pixel Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Usage Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

External Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Multicamera Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

External Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Slave Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Integrated Lens Distortion Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Overlay Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Serial Memory Partition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Overlay Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Overlay Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

MT9V137 DS- Rev. E Pub. 4/15 EN 6©Semiconductor Components Industries, LLC,2015.

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

List of Figures

Figure 1: Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 2: System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 3: Using a Crystal Instead of an External Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 4: Sensor Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 5: Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 6: Image Capture Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 7: Sensor Pixel Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 8: Pixel Color Pattern Detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 9: Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 10: Color Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 11: Color Bar Test Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 12: Color Bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 13: Gamma Correction Curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 14: Auto-Config Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 15: Flash Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 16: Usage Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 17: Host Mode with Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 18: Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 19: External Overlay System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 20: Multicamera System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 21: External Signal Processing Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 22: Power-Up Sequence – Configuration Options Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 23: Interface Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 24: Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 25: Single Read from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 26: Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 27: Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 28: Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 29: Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 30: Barrel Distortion Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 31: Vertical Perspective Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 32: Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 33: Overlay Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 34: Memory Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 35: Overlay Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 36: Internal Block Diagram Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 37: Example of Character Descriptor 0 Stored in ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 38: Full Character Set for Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 39: Single-Ended Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 40: Differential Connection—Grounded Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 41: CCIR656 8-Bit Parallel Interface Format for 525/60 (625/50) Video Systems . . . . . . . . . . . . . . . . . . . .61

Figure 42: Typical CCIR656 Vertical Blanking Intervals for 525/60 Video System. . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 43: Typical CCIR656 Vertical Blanking Intervals for 625/50 Video System. . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 44: Parallel Input Data Timing Waveform Using DIN_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 45: Primary Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 46: Typical I/O Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 47: NTSC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 48: Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 49: Digital Output I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Figure 50: Slew Rate Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Figure 51: Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 52: Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Figure 53: Power Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 54: FRAME_SYNC to FRAME_VALID/LINE_VALID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 55: Reset to SPI Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 56: Reset to Serial Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

MT9V137 DS- Rev. E Pub. 4/15 EN 7©Semiconductor Components Industries, LLC,2015.

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

List of Figures

Figure 57: Reset to AE/AWB Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 58: SPI Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Figure 59: Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Figure 60: Equivalent Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Figure 61: V Pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Figure 62: Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Figure 63: Quantum Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Figure 64: 63-Ball iBGA Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

MT9V137 DS- Rev. E Pub. 4/15 EN 8©Semiconductor Components Industries, LLC,2015.

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

List of Tables

Table 1: Key Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 2: Key Parameters (continued). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3: Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Table 4: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 5: Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 6: Reset/Default State of Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 7: EIA Color Bars (NTSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 8: EBU Color Bars (PAL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 9: NTSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 10: PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 11: YCbCr Output Data Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 12: RGB Ordering in Default Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 13: 2-Byte Bayer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 14: SPI Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 15: SPI Commands Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 16: GPIO Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 17: System Manager Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 18: Overlay Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 19: Dewarp Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 20: GPIO Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 21: Flash Manager Host Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 22: Sequencer Host Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 23: TX Manager Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 24: Two-Wire Interface ID Address Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 25: Lens Correction Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 26: Transfer Time Estimate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 27: Character Generator Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Table 28: Field, Vertical Blanking, EAV, and SAV States 525/60 Video System . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 29: Field, Vertical Blanking, EAV, and SAV States for 625/50 Video System . . . . . . . . . . . . . . . . . . . . . . . . .63

Table 30: Parallel Input Data Timing Values Using DIN_CLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Table 31: Output Data Ordering in DOUT RGB Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 32: Output Data Ordering in Sensor Stand-Alone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 33: Parallel Digital Output I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 34: Slew Rate for PIXCLK and DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 35: Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 36: Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 37: Power Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 38: FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 39: RESET_BAR Delay Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 40: SPI Data Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Table 41: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 42: Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 43: Video DAC Electrical Characteristics–Single-Ended Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 44: Video DAC Electrical Characteristics–Differential Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 45: Digital I/O Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 46: Power Consumption – Condition 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Table 47: Power Consumption – Condition 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Table 48: NTSC Signal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Table 49: Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Table 50: Equivalent Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Table 51: V Pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

MT9V137 DS- Rev. E Pub. 4/15 EN 9©Semiconductor Components Industries, LLC,2015.

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

List of Tables

Table 52: Two-Wire Serial Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

MT9V137 DS- Rev. E Pub. 4/15 EN 10 ©Semiconductor Components Industries, LLC,2015.

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

General Description

The ON Semiconductor MT9V137 is a VGA-format, single-chip CMOS active-pixel

digital image sensor for surveillance applications. It captures high-quality color images

at VGA resolution and outputs NTSC or PAL interlaced composite video.

The VGA CMOS image sensor features ON Semiconductor’s breakthrough low-noise

CMOS imaging technology that achieves near-CCD image quality (based on signal-to-

noise ratio and low-light sensitivity) while maintaining the inherent size, cost, low

power, and integration advantages of ON Semiconductor's advanced active pixel CMOS

process technology.

The MT9V137 is a complete camera-on-a-chip. It incorporates sophisticated camera

functions on-chip and is programmable through a simple two-wire serial interface or by

an attached SPI Flash memory that contains setup information that may be loaded auto-

matically at startup.

The MT9V137 performs sophisticated processing functions including color recovery,

color correction, sharpening, programmable gamma correction, auto black reference

clamping, auto exposure, 50Hz/60Hz flicker avoidance, lens shading correction, auto

white balance (AWB), and on-the-fly defect identification and correction.

The MT9V137 outputs interlaced-scan images at 30 or 25 fps, supporting both NTSC and

PAL video formats. The image data can be output on one or two output ports:

• Composite analog video (single-ended and differential output support)

• Parallel 8-, 10-bit digital

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Architecture

MT9V137 DS- Rev. E Pub. 4/15 EN 11 ©Semiconductor Components Industries, LLC,2015.

Architecture

Internal Block Diagram

Figure 1: Internal Block Diagram

Note: The active array is smaller than the sensor array.

Image Flow Processor

Color & Gamma Correction

Color Space Conversion

Edge Enhancement

Camera Control

AW B

Overlay

Graphics

Generation

¼” VGA ROI

@ 60 Frames/s

640 x 480 Active Array

VideoEncoder

DAC

SPI & 2W I/F

Interface

SPI

4 2

NTSC/

PAL

BT-656

2.8V 1. 8V

Two-Wire I/F

Lens Shading

Correction

MT9V137 DS- Rev. E Pub. 4/15 EN 12 ©Semiconductor Components Industries, LLC,2015.

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

System Block Diagram

The system block diagram will depend on the application. The system block diagram in

Figure 2 shows all components; optional peripheral components are highlighted. The

optional microcontroller controls the MT9V137 sensor using the two-wire serial bus.

Optional components will vary by application. For further details, see the MT9V137

Figure 2: System Block Diagram

SPI Serial Data

Flash

10Kb - 16 MB

LP Filter

MHz

DAC _POS

μC 2WIRE I/F

Composite

Video

PAL /NTSC

VAA (2.8V )

VAA_PIX (2.8V)

VDD (1.8V)

EXTCLK

4.7 kΩ

DAC_REF

2.8V

DAC _NEG

LDO

VDD_IO (2.8V)

CCIR 656/

GPO

Optional

XTAL

75Ω

VDD_PLL (2.8V)

VDD_DAC (2.8V)

RESET_BAR

PIXCLK

FRAME _VALID

LINE _VALID

DOUT [7:0]

DOUT_LSB0,1

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

System Block Diagram

MT9V137 DS- Rev. E Pub. 4/15 EN 13 ©Semiconductor Components Industries, LLC,2015.

Crystal Usage

As an alternative to using an external oscillator, a fundamental 27 MHz crystal may be

connected between EXTCLK and XTAL. Two small loading capacitors of 15–22pF of NPO

dielectric should be added as shown in Figure 3.

ON Semiconductor does not recommend using the crystal option for surveillance appli-

cations above 85°C. A crystal oscillator with temperature compensation is recom-

mended.

Figure 3: Using a Crystal Instead of an External Oscillator

When using Xtal as the clock source, the internal inverter circuit has a 100K bias resistor

in parallel to Xtal, which can be connected or disconnected by register 0x0014 bit[14].

The clockin_bias_en bit is set to 1 by default.

EXTCLK

XTAL

18pF

NPO

27.000 MHz

Sensor

NPO

MT9V137 DS- Rev. E Pub. 4/15 EN 14 ©Semiconductor Components Industries, LLC,2015.

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Pin Descriptions and Assignments

Table 1: Pin Descriptions

Pin Number Pin Name Type Description

Clock and Reset

9 EXTCLK Input Master input clock (27MHz): This either can be a square-wave generated from

an oscillator (in which case the XTAL input must be left unconnected) or

connected directly to a crystal.

10 XTAL Output If EXTCLK is connected to one pin of a crystal, this signal is connected to the

other pin; otherwise this signal must be left unconnected.

12 RESET_BAR Input Asynchronous active-low reset: When asserted, the device will return all

interfaces to their reset state. When released, the device will initiate the boot

sequence.

17 SCLK Input These two signals implement serial communications protocol for access to

the internal register set and memory.

18 SDATA Input/OD

16 SADDR Input This signal controls the device ID that will respond to serial communication

commands.

Two-wire serial interface device ID selection:

0: 0x90

1: 0xBA

SPI Interface

22 SPI_SCLK Output Clock output for interfacing to an external SPI memory such as Flash/

EEPROM. Tristated when RESET_BAR is asserted.

21 SPI_SDI Input Data in from SPI device. This signal has an internal pull-up resistor.

20 SPI_SDO Output Data out to SPI device. Tristated when RESET_BAR is asserted.

19 SPI_CS_N Output Chip selects to SPI device. Tristated when RESET_BAR is asserted.

(Parallel) Pixel Data Output

32 FRAME_VALID Input/Output Pixel data from the MT9V137 can be routed out on this interface and

processed externally.

To save power, these signals are driven to a constant logic level unless the

parallel pixel data output or alternate (GPIO) function is enabled for these

pins.

This interface is disabled by default.

The slew rate of these outputs is programmable.

These signals can also be used as general purpose input/outputs.

31 LINE_VALID Input/Output

33 PIXCLK Output

39, 40, 41,

42, 43, 44,

45, 46

DOUT[7:0] Output

38 DOUT_LSB1 Input/Output When the sensor core is running in bypass mode, it will generate 10 bits of

output data per pixel. These two pins make the two LSB of pixel data

available externally. Leave DOUT_LSB1 unconnected if not used. To save

power, these signals are driven to a constant logic level unless the sensor core

is running in bypass mode or the alternate function is enabled for these pins.

The slew rate of these outputs is programmable. For analog output, the

DOUT_LSB0 cannot be left unconnected, and must be strapped to select either

NTSC or PAL mode. For more information, see Table 14, “GPIO Bit

Descriptions,” on page 40.

37 DOUT_LSB0 Input/Output

Composite Video Output

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Pin Descriptions and Assignments

MT9V137 DS- Rev. E Pub. 4/15 EN 15 ©Semiconductor Components Industries, LLC,2015.

6 DAC_POS Output Positive video DAC output in differential mode.

Video DAC output in single-ended mode.

This interface is enabled by default using NTSC/PAL signalling. For

applications where composite video output is not required, the video DAC can

be placed in a power-down state under software control.

4 DAC_NEG Output Negative video DAC output in differential mode. Connect to AGND in single-

ended mode.

2 DAC_REF Output External reference resistor for the video DAC.

Manufacturing Test Interface

27 TDI Input JTAG Test pin (Reserved for Test Mode)

26 TDO Output JTAG Test pin (Reserved for Test Mode)

25 TMS Input JTAG Test pin (Reserved for Test Mode)

24 TCK Input JTAG Test pin (Reserved for Test Mode)

23 TRST_N Input Connect to GND

Power

8, 14, 35, 48 DGND Supply Digital ground.

3 GND_DAC Supply Video DAC GND

1, 7, 15, 34 VDD Supply Supply for VDD core: 1.8V nominal.

13, 36, 47 VDD_IO Supply Supply for digital IOs: 2.8V nominal.

DD_DAC Supply Supply for video DAC: 2.8V nominal.

11 VDD_PLL Supply Supply for PLL: 2.8V nominal.

29 AGND Supply Analog ground.

28 VAA Supply Analog power: 2.8V nominal.

30 VAA_PIX Supply Analog pixel array power: 2.8V nominal. Must be at same voltage potential as

VAA.

Table 1: Pin Descriptions (continued)

Pin Number Pin Name Type Description

MT9V137 DS- Rev. E Pub. 4/15 EN 16 ©Semiconductor Components Industries, LLC,2015.

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Pin Descriptions and Assignments

Pin Assignments

Figure 4: Pin Assignments

Table 2: Reset/Default State of Interfaces

Name Reset State Default State Notes

EXTCLK Clock running or stopped Clock running Input

XTAL N/A N/A Input

RESET_BAR Asserted De-asserted Input

SCLK N/A N/A Input. Must always be driven to a valid logic

level.

SDATA High impedance High impedance Input/Output. A valid logic level should be

established by pull-up resistor.

SADDR N/A N/A Input. Must always be driven to a valid logic

level. Must be permanently tied to VDD_IO or

GND.

SPI_SCLK High impedance. Driven, logic 0 Output. Output enable is R0x0032[9].

SPI_SDI Internal pull-up enabled. Internal pull-up enabled Input. Internal pull-up is permanently

enabled.

SPI_SDO High impedance Driven, logic 0 Output enable is R0x0032[9].

SPI_CS_N High impedance Driven, logic 1 Output enable is R0x0032[9].

123456 48474645

44 43

19 20 21 22 23 24 25 26 27 28 29 30

VDD

GND

EXTCLK

XTAL

_PLL

RESET_BAR

VDD_IO

GND

VDD

SADDR

SCLK

SDATA

DOUT4

DOUT5

DOUT6

DOUT7

DOUT_LSB1

DOUT_LSB0

GND

PIXCLK

FRAME_VALID

LINE_VALID

SPI_CS_N

SPI_SD0

SPI_SDI

SPI_CLK

TRST_N

TCK

TMS

TDO

TDI

VAA

AGND

_PIX

DAC_POS

VDD_DAC

DAC_NEG

GND_DAC

DAC_REF

VDD

GND

VDD-IO

DOUT0

DOUT1

DOUT2

DOUT3

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Pin Descriptions and Assignments

MT9V137 DS- Rev. E Pub. 4/15 EN 17 ©Semiconductor Components Industries, LLC,2015.

Notes: 1. The reason for defining the default state as logic 0 rather than high impedance is this: when wired

in a system (for example, on our demo boards), these outputs will be connected, and the inputs to

which they are connected will want to see a valid logic level. No current drain should result from

driving these to a valid logic level (unless there is a pull-up at the system level).

2. These pads have their input circuitry powered down, but they are not output-enabled. Therefore,

they can be left floating but they will not drive a valid logic level to an attached device.

FRAME_VALID High impedance High impedance Input/Output. This interface disabled by

default. Input buffers (used for GPIO function)

powered down by default, so these pins can

be left unconnected (floating). After reset,

these pins are powered up, sampled, then

powered down again as part of the auto-

configuration mechanism. See Note 2.

LINE_VALID

PIXCLK High impedance Driven, logic 0

Output. This interface disabled by default.

See Note 1.

DOUT7

DOUT6

DOUT5

DOUT4

DOUT3

DOUT2

DOUT1

DOUT0

DOUT_LSB1 High impedance High impedance Input/Output. This interface disabled by

default. Input buffers (used for GPIO function)

powered down by default, so these pins can

be left unconnected (floating). After reset,

these pins are powered-up, sampled, then

powered down again as part of the auto-

configuration mechanism. For analog output,

the DOUT_LSB0 cannot be left unconnected,

and must be strapped to select either NTSC or

PAL mode

DOUT_LSB0 High impedance Driven, logic 0

DAC_POS High impedance Driven Output. Interface disabled by hardware reset

and enabled by default when the device starts

streaming.

DAC_NEG

DAC_REF

TDI Internal pull-up enabled Internal pull-up enabled Input. Internal pull-up means that this pin can

be left unconnected (floating).

TDO High impedance High impedance Output. Driven only during appropriate parts

of the JTAG shifter sequence.

TMS Internal pull-up enabled Internal pull-up enabled Input. Internal pull-up means that this pin can

be left unconnected (floating).

TCK Internal pull-up enabled Internal pull-up enabled Input. Internal pull-up means that this pin can

be left unconnected (floating).

TRST_N N/A N/A Input. Must always be driven to a valid logic

level. Must be driven to GND for normal

operation.

Table 2: Reset/Default State of Interfaces (continued)

Name Reset State Default State Notes

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MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

SOC Description

Detailed Architecture Overview

Sensor Core

The sensor consists of a pixel array, an analog readout chain, a 10-bit ADC with programmable

gain and black offset, and timing and control as illustrated in Figure 4.

Figure 5: Sensor Core Block Diagram

Pixel Array Structure

The sensor core pixel array is configured as 744 columns by 512 rows, as shown in

Figure 5. This includes black rows and columns.

Figure 6: Pixel Array Description

The black row data are used internally for the automatic black level adjustment.

However, these black rows can also be read out by setting the sensor to raw data output

mode.

There are 744 columns by 512 rows of optically-active pixels that include a pixel

boundary around the VGA (640 x 480) image to avoid boundary effects during color

interpolation and correction.

Communication

Bus

to IFP

10-Bit Data

to IFP

Sync

Signals

Clock

Control Register

Analog Processing

Active Pixel

Sensor (APS)

Array Timing and Control

ADC

active border rows

black row

black rows

black columns

active border rows

active border columns

Active pixel array

640 x 480

(not to scale)

Pixel logical address = (743, 511)

Pixel logical address = (0, 0)

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

SOC Description

MT9V137 DS- Rev. E Pub. 4/15 EN 19 ©Semiconductor Components Industries, LLC,2015.

The one additional active column and two additional active rows are used to enable

horizontally and vertically mirrored readout to start on the same color pixel.

Figure 6 illustrates the process of capturing the image. The original scene is flipped and

mirrored by the sensor optics. Sensor readout starts at the lower right corner. The image

is presented in true orientation by the output display.

Figure 7: Image Capture Example

SCENE

(Front view)

OPTICS

IMAGE CAPTURE

IMAGE RENDERING

Start Readout

Row by Row

IMAGE SENSOR

(Rear view)

Start Rasterization

Process of Image Gathering and Image Display

DISPLAY

(Front view)

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MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Sensor Pixel Array

The active pixel array is 640 x 480 pixels. In addition, there are rows and columns for lens

alignment and demosaic.

Not shown in Figure 7 are pixels for black level calibration.

Figure 8: Sensor Pixel Array

The range of adjustment is from Row 0 to 22 and Column 0 to 30. There are 4 rows/

columns needed to calculate the RGB values. The window should be moved only at even

numbers.

Figure 9: Pixel Color Pattern Detail (top right corner)

Lens Alignment Pixels - 16 Columns

Lens Alignment Pixels - 12 Rows

Lens Alignment Pixels - 16 Columns

Demosaic Pixels - 4 Columns

Demosaic Pixels - 4 Rows

Active Pixels

640 Rows, 480 Columns

Black Pixels

Column Readout Direction

...

Row

Readout

Direction

First Active

Border

Pixel

(64, 0)

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Sensor Pixel Array

MT9V137 DS- Rev. E Pub. 4/15 EN 21 ©Semiconductor Components Industries, LLC,2015.

Output Data Format

The sensor core image data are read out in progressive scan order. Valid image data are

surrounded by horizontal and vertical blanking, shown in Figure 9.

For NTSC output, the horizontal size is stretched from 640 to 720 pixels. The vertical size

is 243 pixels per field; 240 image pixels and 3 dark pixels that are located at the bottom of

the image field.

For PAL output, the horizontal size is also stretched from 640 to 720 pixels. The vertical

size is 288 pixels per field.

Figure 10: Spatial Illustration of Image Readout

P0,0 P0,1 P0,2.....................................P0,n-1 P0,n

P2,0 P2,1 P2,2.....................................P2,n-1 P2,n

00 00 00 .................. 00 00 00

Pm-2,0 Pm-2,1.....................................Pm-2,n-1 Pm-2,n

Pm,0 Pm,1.....................................Pm,n-1 Pm,n

00 00 00 .................. 00 00 00

00 00 00 ..................................... 00 00 00

Valid Image Odd Field Horizontal

Blanking

Vertical Even Blanking Vertical/Horizontal

Blanking

P1,0 P1,1 P1,2.....................................P1,n-1 P1,n

P3,0 P3,1 P3,2.....................................P3,n-1 P3,n

00 00 00 .................. 00 00 00

Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n

Pm+1,0 Pm+1,1..................................Pm+1,n-1 Pm+1,n

00 00 00 .................. 00 00 00

00 00 00 ..................................... 00 00 00

Valid Image Even Field Horizontal

Blanking

Vertical Odd Blanking Vertical/Horizontal

Blanking

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MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Sensor Pixel Array

Image Flow Processor

Image and color processing in the MT9V137 are implemented as an image flow

processor (IFP) coded in hardware logic. During normal operation, the embedded

microcontroller will automatically adjust the operation parameters. The IFP is broken

down into different sections, as outlined in Figure 10.

Figure 11: Color Pipeline

Test Pattern

Generator

Black

Level

Subtraction

Color Correction

Aperture

Correction

Gamma

Correction

(12-to-8 Lookup)

Statistics

Engine

Color Kill

Output

Formatting

YUV to RGB

Raw Data

10/12-Bit

RGB

RAW 10

8-bit

RGB

8-bit

YUV

Parallel

Output

Interface

RGB to YUV

Digital Gain Control

Lens Shading

Correction

Defect Correction,

Noise Reduction,

Color Interpolation

MUX

IFP

Parallel Output Mux

Pixel Array

ADC

Analog Output Mux

NTSC/PAL

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Sensor Pixel Array

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Test Patterns

During normal operation of the MT9V137, a stream of raw image data from the sensor

core is continuously fed into the color pipeline. For test purposes, this stream can be

replaced with a fixed image generated by a special test module in the pipeline. The

module provides a selection of test patterns sufficient for basic testing of the pipeline.

Test patterns are accessible by programming a register and are shown in Figure 11. ON

Semiconductor recommends disabling the MCU before enabling test patterns.

Figure 12: Color Bar Test Pattern

Test Pattern Example

Flat Field

Vertical Ramp

Color Bar

Vertical Stripes

Pseudo-Random

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MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Sensor Pixel Array

NTSC/PAL Test Pattern Generation

There is a built-in standard EIA (NTSC) and EBU (PAL) color bars to support hue and

color saturation characterization. Each pattern consists of seven color bars (white,

yellow, cyan, green, magenta, red, and blue). The Y, Cb and Cr values for each bar are

detailed in Tables 4 and 5.

The test pattern is invoked through a Host Command call to the TX Manager. See the

MT9V137 Host Command Specification.

Figure 13: Color Bars

CCIR-656 Format

The color bar data is encoded in 656 data streams. The duration of the blanking and

active video periods of the generated 656 data are summarized in the following tables.

Table 3: EIA Color Bars (NTSC)

Nominal Range White Yellow Cyan Green Magenta Red Blue

Y 16 to 235 180 162 131 112 84 65 35

Cb 16 to 240 128 44 156 72 184 100 212

Cr 16 to 240 128 142 44 58 198 212 114

Table 4: EBU Color Bars (PAL)

Nominal Range White Yellow Cyan Green Magenta Red Blue

Y 16 to 235 235 162 131 112 84 65 35

Cb 16 to 240 128 44 156 72 184 100 212

Cr 16 to 240 128 142 44 58 198 212 114

Table 5: NTSC

Line Numbers Field Description

1-3 2 Blanking

4-19 1 Blanking

20-263 1 Active video

264-265 1 Blanking

266-282 2 Blanking

283-525 2 Active Video

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Sensor Pixel Array

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Black Level Subtraction and Digital Gain

Image stream processing starts with black level subtraction and multiplication of all

pixel values by a programmable digital gain. Both operations can be independently set

to separate values for each color channel (R, Gr, Gb, B). Independent color channel

digital gain can be adjusted with registers. Independent color channel black level adjust-

ments can also be made. If the black level subtraction produces a negative result for a

particular pixel, the value of this pixel is set to 0.

Positional Gain Adjustments (PGA)

Lenses tend to produce images whose brightness is significantly attenuated near the

edges. There are also other factors causing fixed pattern signal gradients in images

captured by image sensors. The cumulative result of all these factors is known as image

shading. The MT9V137 has an embedded shading correction module that can be

programmed to counter the shading effects on each individual R, Gb, Gr, and B color

signal.

The Correction Function

The correction functions can then be applied to each pixel value to equalize the

response across the image as follows:

(EQ 1)

where P are the pixel values and f is the color dependent correction functions for each

color channel.

Color Interpolation

In the raw data stream fed by the sensor core to the IFP, each pixel is represented by a

10-bit integer number, which can be considered proportional to the pixel's response to a

one-color light stimulus, red, green, or blue, depending on the pixel's position under the

color filter array. Initial data processing steps, up to and including the defect correction,

preserve the one-color-per-pixel nature of the data stream, but after the defect correc-

tion it must be converted to a three-colors-per-pixel stream appropriate for standard

color processing. The conversion is done by an edge-sensitive color interpolation

module. The module pads the incomplete color information available for each pixel

with information extracted from an appropriate set of neighboring pixels. The algorithm

used to select this set and extract the information seeks the best compromise between

preserving edges and filtering out high frequency noise in flat field areas. The edge

threshold can be set through register settings.

Table 6: PAL

Line Numbers Field Description

1-22 1 Blanking

23-310 1 Active video

311-312 1 Blanking

313-335 2 Blanking

336-623 2 Active video

624-625 2 Blanking

Pcorrected(row,col)=Psensor(row,col)*f(row,col)

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MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Sensor Pixel Array

Color Correction and Aperture Correction

To achieve good color fidelity of the IFP output, interpolated RGB values of all pixels are

subjected to color correction. The IFP multiplies each vector of three pixel colors by a

3 x 3 color correction matrix. The three components of the resulting color vector are all

sums of three 10-bit numbers. Since such sums can have up to 12 significant bits, the bit

width of the image data stream is widened to 12 bits per color (36 bits per pixel). The

color correction matrix can be either programmed by the user or automatically selected

by the auto white balance (AWB) algorithm implemented in the IFP. Color correction

should ideally produce output colors that are corrected for the spectral sensitivity and

color crosstalk characteristics of the image sensor. The optimal values of the color

correction matrix elements depend on those sensor characteristics and on the spectrum

of light incident on the sensor. The color correction variables can be adjusted through

To increase image sharpness, a programmable 2D aperture correction (sharpening filter)

is applied to color-corrected image data. The gain and threshold for 2D correction can

be defined through register settings.

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Sensor Pixel Array

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Gamma Correction

The MT9V137 IFP includes a block for gamma correction that can adjust its shape based

on brightness to enhance the performance under certain lighting conditions. Two

custom gamma correction tables may be uploaded corresponding to a brighter lighting

condition and a darker lighting condition. At power-up, the IFP loads the two tables with

default values. The final gamma correction table used depends on the brightness of the

scene and takes the form of an interpolated version of the two tables.

The gamma correction curve (as shown in Figure 13) is implemented as a piecewise

linear function with 19 knee points, taking 12-bit arguments and mapping them to 8-bit

output. The abscissas of the knee points are fixed at 0, 64, 128, 256, 512, 768, 1024, 1280,

1536, 1792, 2048, 2304, 2560, 2816, 3072, 3328, 3584, 3840, and 4096. The 8-bit ordinates

are programmable through IFP registers.

Figure 14: Gamma Correction Curve

RGB to YUV Conversion

For further processing, the data is converted from RGB color space to YUV color space.

Color Kill

To remove high-or low-light color artifacts, a color kill circuit is included. It affects only

pixels whose luminance exceeds a certain preprogrammed threshold. The U and V

values of those pixels are attenuated proportionally to the difference between their lumi-

nance and the threshold.

YUV Color Filter

As an optional processing step, noise suppression by one-dimensional low-pass filtering

of Y and/or UV signals is possible. A 3- or 5-tap filter can be selected for each signal.

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MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Sensor Pixel Array

YUV-to-RGB/YUV Conversion and Output Formatting

The YUV data stream emerging from the scaling module can either exit the color pipe-

line as-is or be converted before exit to an alternative YUV or RGB data format.

Output Format and Timing

YUV/RGB Data Ordering

The MT9V137 supports swapping YCbCr mode, as illustrated in Table 8.

The RGB output data ordering in default mode is shown in Table 9. The odd and even

bytes are swapped when luma/chroma swap is enabled. R and B channels are bit-wise

swapped when chroma swap is enabled.

Uncompressed 10-Bit Bypass Output

Raw 10-bit Bayer data from the sensor core can be output in bypass mode in two ways:

• Using 8 data output signals (DOUT[7:0]) and GPIO[1:0]. The GPIO signals are the least

significant 2 bits of data.

• Using only 8 signals (DOUT[7:0]) and a special 8 + 2 data format, shown in Table 10.

Readout Formats

Progressive format is used for raw Bayer output.

Table 7: YCbCr Output Data Ordering

Mode Data Sequence

Default (no swap) CbiYiCriYi+1

Swapped CbCr CriYiCbiYi+1

Swapped YC YiCbiYi+1 Cri

Swapped CbCr, YC YiCriYi+1 Cbi

Table 8: RGB Ordering in Default Mode

Mode (Swap Disabled) Byte D7D6D5D4D3D2D1D0

565RGB Odd R7R6R5R4R3G7G6G5

Even G4G3G2B7B6B5B4B3

555RGB Odd 0 R7R6R5R4R3G7G6

Even G5G4G3B7B6B5B4B3

444xRGB Odd R7R6R5R4G7G6G5G4

Even B7B6B5B4 0 0 0 0

x444RGB Odd 0 0 0 0 R7R6R5R4

Even G7G6G5G4B7B6B5B4

Table 9: 2-Byte Bayer Format

Byte Bits Used Bit Sequence

Odd bytes 8 data bits D9D8D7D6D5D4D3D2

Even bytes 2 data bits + 6 unused bits 0 0 0 0 0 0 D1D0

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Sensor Pixel Array

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Output Formats

ITU-R BT.656 and RGB Output

The MT9V137 can output processed video as a standard ITU-R BT.656 (CCIR656) stream,

an RGB stream, or as unprocessed Bayer data. The ITU-R BT.656 stream contains YCbCr

4:2:2 data with fixed embedded synchronization codes. This output is typically suitable

for subsequent display by standard video equipment or JPEG/MPEG compression.

Colorpipe data (pre-lens correction and overlay) can also be output in YCbCr 4:2:2 and a

variety of RGB formats in 640 by 480 progressive format in conjunction with

LINE_VALID and FRAME_VALID.

The MT9V137 can be configured to output 16-bit RGB (565RGB), 15-bit RGB (555RGB),

and two types of 12-bit RGB (444RGB). Refer to Table 28 and Table 29 on page 66 for

details.

Bayer Output

Unprocessed Bayer data are generated when bypassing the IFP completely—that is, by

simply outputting the sensor Bayer stream as usual, using FRAME_VALID, LINE_VALID,

and PIXCLK to time the data. This mode is called sensor stand-alone mode.

Output Ports

Composite Video Output

The composite video output DAC is external-resistor-programmable and supports both

single-ended and differential output. The DAC is driven by the on-chip video encoder

output.

Parallel Output

Parallel output uses either 8-bit or 10-bit output. Eight-bit output is used for ITU-R

BT.656 and RGB output. Ten-bit output is used for raw Bayer output.

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MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Usage Modes

How a camera based on the MT9V137 will be configured depends on what features are

used. In the simplest case, only an MT9V137 plus an external flash memory, or an 8-bit

microcontroller (µC) might be sufficient. Flash sizes vary depending on the data for

registers, firmware, and overlay data—somewhere between 10Kb to 16MB. The two-wire

bus is adequate since only high-level commands are used to invoke overlays, load regis-

ters from memory, or set up lens correction parameters. Overlay data can alternatively

be issued by the external µC if the rate of refreshing data is deemed adequate. If there are

no commands in the Flash image the device can be in auto configuration mode by which

the sensor is set up according to the status of pins FRAME_VALID, LINE_VALID and

DOUT_LSB0. For further information, see “Auto-Configuration” on page 35.

In the simplest case no Flash memory or µC is required, as shown in Figure 14. This is

truly a single chip operation.

Note: Because mandatory patches must be loaded, the Auto-Config mode is not recom-

mended.

Figure 15: Auto-Config Mode

The MT9V137 can be configured by a serial Flash through the SPI Interface.

Figure 16: Flash Mode

Analog Out

Digital Out

Auto-Config Mode

LSB0

Hi = PAL

Lo = NTSC

MT9V137

SPI

Serial

Flash

LSB0

Hi = PAL

Lo = NTSC

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Usage Modes

MT9V137 DS- Rev. E Pub. 4/15 EN 31 ©Semiconductor Components Industries, LLC,2015.

In some applications, button or user interface keypad can trigger overlay images being

called by the C as shown in Figure 20.

Figure 17: Host Mode with Flash

Overlay information may also be passed by the µC without a need for a Flash memory.

However, because the data transfer rate is limited over the two-wire serial bus, the

update rate may be slower. However, if overlay images are preloaded into the four on-

chip buffers, they may be turned on and off or move location at the frame rate as shown

in Figure 18.

Figure 18: Host Mode

MT9V137

SPI

8/16bit μC

two-wire

Button or

user interface

keypad

LSB0

Hi = PAL

Lo = NTSC

8/16bit μC

two-wire

Button

or user interface

keypad LSB0

Hi = PAL

Lo = NTSC

MT9V137

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MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

External Signal Processing

An external signal processor can take data from ITU656 or raw Bayer output format and

post-process or compress the data in various formats.

Figure 19: External Signal Processing Block Diagram

Device Configuration

After power is applied and the device is out of reset by de-asserting the RESET_BAR pin,

it will enter a boot sequence to configure its operating mode. There are essentially four

modes, two when Flash is present and two when Flash is not present. Figure 22: “Power-

Up Sequence – Configuration Options Flow Chart,” on page 36 contains more details on

the configuration options.

If Flash is present and:

• A valid Flash device identifier is detected AND the Flash device contains valid config-

uration records, then

– Disable Auto-Config

– Parse Flash Content

– Load Flash Configuration ->Flash Configuration Mode

• A valid Flash device identifier is detected BUT the Flash device DOES NOT contain

valid configuration records, then

– Enter Auto Configuration.

If Flash is not present and:

• SPI_SDI == 0, then

– Enter Host Configuration.

• SPI_SDI != 0, then

– Enter Auto Configuration

SPI

Serial data

Flash

10Kb to 16MB

27 MHz

VIDEO_P

CVBS

PAL/NTSC

EXTCLK

VIDEO_N

DOUT [7:0]

PIXCLK

Signal processor

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

External Signal Processing

Auto-Configuration

The device supports an auto-configuration feature. During system start-up, the device

first detects whether an SPI Flash device is attached to the MT9V137. If not, it will then

sample the state of a number of GPI inputs including FRAME_VALID, LINE_VALID and

DOUT_LSB0. For more information, see Table 13, “GPIO Bit Descriptions,” on page 37.

The state of these inputs then determines the configuration of a number of subsystems

of the device such as readout mode, pedestal and video format, respectively.

The auto-configuration feature can be disabled by grounding the SPI_DIN pin. The

device samples the state of this pin during the Flash device detection process. If no SPI

Flash device is detected (read device ID of 0x00 or 0xFF), OR the SPI_DIN pin is

grounded, then auto-configuration is disabled.

Flash Configuration Mode

If a valid Flash is detected (by reading device ID other than 0x00 or 0xFF) and the flash

device contains valid configuration records, then these configuration records are

processed.

Host Configuration

This mode is entered if the SPI_DIN pin is grounded. The SOC performs no configura-

tion, and remains idle waiting for configuration and instruction from the host.

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

External Signal Processing

Power Sequence

In power-up, the core voltage (1.8V) must trail the IO (2.8V) by a positive number. All

2.8V rails can be turned on at the same time or follow the power-up sequence in Figure

52: “Power Up Sequence,” on page 72.

In power down, the sequence is reversed. The core voltage (1.8V) must be turned off

before any 2.8V. Refer to Figure 53: “Power Down Sequence,” on page 73 for details.

Figure 20: Power-Up Sequence – Configuration Options Flow Chart

Supported SPI Devices

Table 11 lists supported Flash devices. Devices not compatible will require a firmware

patch. Contact ON Semiconductor for additional support.

Table 10: SPI Flash Devices

Type Density Manufacturer Device Speed

(MHz) Standard Temp Range

(°F) Supported

Flash 8 MB Atmel AT26DF081A 70 JEDEC/Device

–20 to +85 Yes

Flash 1 MB ST M25P10-AVMB3 50 –40 to +125 Yes

Power Up

/RESET

Flash

Header?

Auto Configuration:

FRAME_VALID,

LINE_VALID,

OUT

_LSB0

SPI _SDI = 0?

Wait for Host

Command

Wait for Host

Command

Disable Auto -Config

Parse Flash Content

Wait for Host

Command

yes

FRAME_VALID

LINE_VALID

OUT

_LSB0

Normal

1: Horizontal Mirror

0 No Pedestal

1: Pedestal

0: NTSC

1: PAL

Disable Auto-Config

Flash

Configuration:

Host

Configuration :

Host

Configuration:

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

External Signal Processing

Supported SPI Commands

The SPI commands shown in Table 12 are supported by the MT9V137.

Table 11: SPI Commands Supported

Command Value

Read Array 0x03

Block Erase 0xD8

Chip Erase 0xC7

Read Status 0x05

Write status 0x01

Byte Page Program 0x02

Write Enable 0x06

Write Disable 0x04

Read Manufacturer and Device

0x9F

(Fast) Read Array 0x0B

Table 12: GPIO Bit Descriptions

GPI[2]

(DOUT_LSB0) GPI[1]

(FRAME_VALID) GPI[0]

(LINE_VALID)

Low (“0”) NTSC Normal No pedestal

High (“1”) PAL Horizontal mirror Pedestal

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

External Signal Processing

Host Command Interface

ON Semiconductor’s sensors and SOCs contain numerous registers that are accessed

through a two-wire interface with speeds up to 400 kHz.

The MT9V137, in addition to writing or reading straight to/from registers or firmware

variables, has a mechanism to write higher level commands, the Host Command Inter-

face (HCI). Once a command has been written through the HCI, it will be executed by on

chip firmware and the results are reported back. In general, registers shall not be

accessed with the exception of registers that are marked for “User Access.”

Flash memory is also available to store commands for later execution. Under DMA

control, a command is written into the SOC and executed.

For a complete spec on host commands, refer to the MT9V137 Host Command Interface

Specification.

Figure 21: Interface Structure

Host Command to FW

Response from FW

15 0bit

command register

Addr 0x40

Addr 0xFC00

Addr 0xFC0E

Addr 0xFC02

Addr 0xFC04

Addr 0xFC06

Addr 0xFC08

Addr 0xFC0A

Addr 0xFC0C

door bell

15 0bit

Parameter 0

Parameter 7

cmd_handler_params_pool_0

cmd_handler_params_pool_1

cmd_handler_params_pool_2

cmd_handler_params_pool_3

cmd_handler_params_pool_4

cmd_handler_params_pool_5

cmd_handler_params_pool_6

cmd_handler_params_pool_7

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

External Signal Processing

Host Command Process Flow

Command Flow

The host issues a command by writing (through a two-wire interface bus) to the

command register. All commands are encoded with bit 15 set, which automatically

generates the host command (doorbell) interrupt to the microprocessor.

Assuming initial conditions, the host first writes the command parameters (if any) to the

parameters pool (in the command handler's logical page), then writes the command to

command register. The interrupt handler then signals the command handler task to

process the command.

If the host wishes to determine the outcome of the command, it must poll the command

completed processing the command. The contents of the command register indicate the

command's result status. If the command generated response parameters, the host can

now retrieve these from the parameters pool.

Read Command

Doorb e ll

bit clear ?

Command has

para meters?

Yes

Write parameters

Parameter Pool

Yes

Write co mmand

Command registe r

Issue

Command

Host could insert an

optional delay here

Host could insert an

optional delay here

Wait f o r a

response?

Read Command

registe r

Doorbell bit

clear?

Yes

Command

has response

parameters ?

Yes

Read response

parameters from

Parameter Pool

Yes

At th is point

Command Registe r

contains response code

Done

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

External Signal Processing

Note: The host must not write to the parameters pool, nor issue another command, until

the previous command completes. This is true even if the host does not care about the

result of the previous command. Therefore, the host must always poll the command

issuing a command.

For a complete command list and further information consult the Host Command Inter-

face Specification.

An example of how (using DevWare) a command may be initiated in the form of a

“Preset” follows.

Set Parallel Mode - Normal (Overlay i656)

All DevWare presets supplied by ON Semiconductor poll and test the doorbell bit after

issuing the command. Therefore there is no need to check if the doorbell bit is clear

before issuing the next command.

REG= 0xFC00, 0x1000 // CMD_HANDLER_PARAMS_POOL_0

REG= 0x0040, 0x8801 // issue command

// POLL COMMAND_REGISTER::DOORBELL => 0x0

Summary of Host Commands

Table 14 on page 40 through Table 20 on page 43 show summaries of the host

commands. The commands are divided into the following sections:

– System Manager

–Overlay

– Dewarp (or Lens Distortion Correction)

–GPIO Host interface

– Flash Manager Host

– Patch Loader Interface

– TX Manager

Following is a summary of the Host Interface commands. The description gives a quick

orientation. The “Type” column shows if it is an asynchronous or synchronous

command. For a complete list of all commands including parameters, consult the Host

Command Interface Specification document.

Table 13: System Manager Commands

System Manager

Host Command Value Type Description

Set State 0x8100 Asynchronous Request the system enter a new state

Get State 0x8101 Synchronous Get the current state of the system

Table 14: Overlay Host Commands

Overlay Host Command Value Type Description

Enable Overlay 0x8200 Synchronous Enable or disable the overlay subsystem

Get Overlay State 0x8201 Synchronous Retrieve the state of the overlay subsystem

Set Calibration 0x8202 Synchronous Set the calibration offset

Set Bitmap Property 0x8203 Synchronous Set a property of a bitmap

Get Bitmap Property 0x8204 Synchronous Get a property of a bitmap

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

External Signal Processing

Set String Property 0x8205 Synchronous Set a property of a character string

Load Buffer 0x8206 Asynchronous Load an overlay buffer with a bitmap (from Flash)

Load Status 0x8207 Synchronous Retrieve status of an active load buffer operation

Write Buffer 0x8208 Synchronous Write directly to an overlay buffer

Read Buffer 0x8209 Synchronous Read directly from an overlay buffer

Enable Layer 0x820A Synchronous Enable or disable an overlay layer

Get Layer Status 0x820B Synchronous Retrieve the status of an overlay layer

Set String 0x820C Synchronous Set the character string

Load String 0x820E Asynchronous Load a character string (from Flash)

Table 15: GPIO Host Commands

GPIO Host Command Value Type Description

Set GPIO Property 0x8400 Synchronous Set a property of one or more GPIO pins

Get GPIO Property 0x8401 Synchronous Retrieve a property of a GPIO pin

Set GPO State 0x8402 Synchronous Set the state of a GPO pin or pins

Get GPIO State 0x8403 Synchronous Get the state of a GPI pin or pins

Set GPI Association 0x8404 Synchronous Associate a GPI pin state with a Command Sequence stored in SPI Flash

Table 16: Flash Manager Host Commands

Flash Manager

Host Command Value Type Description

Get Lock 0x8500 Asynchronous Request the Flash Manager access lock

Lock Status 0x8501 Synchronous Retrieve the status of the access lock request

Release Lock 0x8502 Synchronous Release the Flash Manager access lock

Config 0x8503 Synchronous Configure the Flash Manager and underlying SPI Flash subsystem

Read 0x8504 Asynchronous Read data from the SPI Flash

Write 0x8505 Asynchronous Write data to the SPI Flash

Erase Block 0x8506 Asynchronous Erase a block of data from the SPI Flash

Erase Device 0x8507 Asynchronous Erase the SPI Flash device

Query Device 0x8508 Asynchronous Query device-specific information

Status 0x8509 Synchronous Obtain status of current asynchronous operation

Table 17: Sequencer Host Commands

Sequencer Host

Command Value Type Description

Set Encoding Mode 0x8603 Synchronous Set the encoding mode

Enable Horizontal Flip 0x8604 Synchronous Enable or disable horizontal flip

Set Flicker Frequency 0x8605 Synchronous Set the flicker frequency

Refresh Mode 0x8606 Synchronous Refresh the Sequencer mode/context

Table 14: Overlay Host Commands

Overlay Host Command Value Type Description

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

External Signal Processing

Table 18: TX Manager Host Commands

TX Manager Host

Command Value Type Description

Config DAC 0x8800 Synchronous Configure the Video DAC

Set Parallel Mode 0x8801 Synchronous Configure the Parallel output port

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Slave Two-Wire Serial Interface

The two-wire serial interface bus enables read/write access to control and status regis-

ters within the MT9V137. This interface is designed to be compatible with the MIPI Alli-

ance Standard for Camera Serial Interface 2 (CSI-2) 1.0, which uses the electrical

characteristics and transfer protocols of the two-wire serial interface specification.

The interface protocol uses a master/slave model in which a master controls one or

more slave devices. The sensor acts as a slave device. The master generates a clock

(SCLK) that is an input to the sensor and used to synchronize transfers.

Data is transferred between the master and the slave on a bidirectional signal (SDATA).

SDATA is pulled up to VDD_IO off-chip by a pull-up resistor in the range of 1.5 to 4.7k

resistor.

Protocol

Data transfers on the two-wire serial interface bus are performed by a sequence of low-

level protocol elements, as follows:

• a start or restart condition

• a slave address/data direction byte

• a 16-bit register address

• an acknowledge or a no-acknowledge bit

•data bytes

• a stop condition

The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with

a start condition, and the bus is released with a stop condition. Only the master can gen-

erate the start and stop conditions.

The SADDR pin is used to select between two different addresses in case of conflict with

another device. If SADDR is LOW, the slave address is 0x90; if SADDR is HIGH, the slave

address is 0xBA. See Table 21 below.

Start Condition

A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.

At the end of a transfer, the master can generate a start condition without previously

generating a stop condition; this is known as a “repeated start” or “restart” condition.

Data Transfer

Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of

data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer

mechanism is used for the slave address/data direction byte and for message bytes.

One data bit is transferred during each SCLK clock period. SDATA can change when SCLK

is low and must be stable while SCLK is HIGH.

Table 19: Two-Wire Interface ID Address Switching

SADDR Two-Wire Interface Address ID

00x90

10xBA

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Slave Two-Wire Serial Interface

Slave Address/Data Direction Byte

Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data

transfer direction. A “0” in bit [0] indicates a write, and a “1” indicates a read. The default

slave addresses used by the MT9V137 are 0x90 (write address) and 0x91 (read address).

Alternate slave addresses of 0xBA (write address) and 0xBB (read address) can be

selected by asserting the SADDR input signal.

Message Byte

Message bytes are used for sending register addresses and register write data to the slave

device and for retrieving register read data. The protocol used is outside the scope of the

two-wire serial interface specification.

Acknowledge Bit

Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the

SCLK clock period following the data transfer. The transmitter (which is the master when

writing, or the slave when reading) releases SDATA. The receiver indicates an acknowl-

edge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is

LOW and must be stable while SCLK is HIGH.

No-Acknowledge Bit

The no-acknowledge bit is generated when the receiver does not drive SDATA low during

the SCLK clock period following a data transfer. A no-acknowledge bit is used to termi-

nate a read sequence.

Stop Condition

A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Slave Two-Wire Serial Interface

Typical Operation

A typical READ or WRITE sequence begins by the master generating a start condition on

the bus. After the start condition, the master sends the 8-bit slave address/data direction

byte. The last bit indicates whether the request is for a READ or a WRITE, where a “0”

indicates a WRITE and a “1” indicates a READ. If the address matches the address of the

slave device, the slave device acknowledges receipt of the address by generating an

acknowledge bit on the bus.

If the request was a WRITE, the master then transfers the 16-bit register address to which

a WRITE will take place. This transfer takes place as two 8-bit sequences and the slave

sends an acknowledge bit after each sequence to indicate that the byte has been

received. The master will then transfer the 16-bit data, as two 8-bit sequences and the

slave sends an acknowledge bit after each sequence to indicate that the byte has been

received. The master stops writing by generating a (re)start or stop condition. If the

request was a READ, the master sends the 8-bit write slave address/data direction byte

and 16-bit register address, just as in the write request. The master then generates a

(re)start condition and the 8-bit read slave address/data direction byte, and clocks out

the register data, 8 bits at a time. The master generates an acknowledge bit after each 8-

bit transfer. The data transfer is stopped when the master sends a no-acknowledge bit.

Single READ from Random Location

Figure 24 shows the typical READ cycle of the host to MT9V137. The first two bytes sent

by the host are an internal 16-bit register address. The following 2-byte READ cycle sends

the contents of the registers to host.

Figure 22: Single READ from Random Location

Single READ from Current Location

Figure 25 shows the single READ cycle without writing the address. The internal address

will use the previous address value written to the register.

Figure 23: Single Read from Current Location

S = start condition

P = stop condition

Sr = restart condition

A = acknowledge

A = no-acknowledge

slave to master

master to slave

Slave Address 0

S A Reg Address[15:8] A Reg Address[7:0] Slave Address A

A 1Sr Read Data

[15:8] P

Previous Reg Address, N Reg Address, M M+1

Read Data

[7:0]

Slave Address 1S A Read Data

[15:8] Slave Address A1SP Read Data

[15:8] P

Previous Reg Address, N Reg Address, N+1 N+2

Read Data

[7:0]

ARead Data

[7:0]

MT9V137: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Slave Two-Wire Serial Interface

Sequential READ, Start from Random Location

This sequence (Figure 26) starts in the same way as the single READ from random loca-

tion (Figure 24 on page 46). Instead of generating a no-acknowledge bit after the first

byte of data has been transferred, the master generates an acknowledge bit and

continues to perform byte READs until “L” bytes have been read.

Figure 24: Sequential READ, Start from Random Location

Sequential READ, Start from Current Location

This sequence (Figure 27) starts in the same way as the single READ from current loca-

tion (Figure 25). Instead of generating a no-acknowledge bit after the first byte of data

has been transferred, the master generates an acknowledge bit and continues to

perform byte reads until “L” bytes have been read.

Figure 25: Sequential READ, Start from Current Location

Single Write to Random Location

Figure 28 shows the typical WRITE cycle from the host to the MT9V137. The first 2 bytes

indicate a 16-bit address of the internal registers with most-significant byte first. The

following 2 bytes indicate the 16-bit data.

Figure 26: Single WRITE to Random Location

Read Data

(15:8)

Read Data

(15:8)

Read Data

(7:0)

Slave Address 0

S Sr

AReg Address[15:8] AReg Address[7:0] ARead Data

Slave Address

Previous Reg Address, N Reg Address, M

M+1 M+2

M+1

M+3

M+L-2 M+L-1 M+L

A P

Read Data

(15:8)

Read Data

(7:0)

Read Data

(15:8)

Read Data

(7:0)

Read Data

(7:0)

ARead Data Read Data

Previous Reg Address, N N+1 N+2 N+L-1 N+L

Read DataSlave Address AA1 AS

Read Data

(15:8)

Read Data

(7:0) ARead Data

(15:8)

Read Data

(7:0) ARead Data

(15:8)

Read Data

(7:0)

Read Data

(15:8)

Read Data

(7:0)

Slave Address 0

SAReg Address[15:8] AReg Address[7:0] AP

Pre vio us Reg Address, N Reg Address, M M+1

Write Dat a