June 2003
2003 Fairchild Semiconductor Corporation FDS6612A Rev D (W)
FDS6612A
Single N-Channel, Logic-Level, PowerTrench MOSFET
General Description
This N-Channel Logic Level MOSFET is produced
using Fairchild Semiconductor’s advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain
superior switching performance.
These devices are well suited for low voltage and
battery powered applications where low in-line power
loss and fast switching are required.
Features
• 8.4 A, 30 V. RDS(ON) = 22 mΩ @ VGS = 10 V
RDS(ON) = 30 mΩ @ VGS = 4.5 V
• Fast switching speed
• Low gate charge
• High performance trench technology for extremely
low RDS(ON)
• High power and current handling capability
S
D
S
S
SO-8
D
D
D
G
DDDD
SSSG
Pin 1
SO-8
4
3
2
1
5
6
7
8
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol Parameter Ratings Units
VDSS Drain-Source Voltage 30 V
VGSS Gate-Source Voltage ±20 V
IDDrain Current – Continuous (Note 1a) 8.4 A
– Pulsed 40
Power Dissipation for Single Operation (Note 1a) 2.5
PD
(Note 1b) 1.0W
TJ, TSTG Operating and Storage Junction Temperature Range –55 to +150 °C
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W
RθJA Thermal Resistance, Junction-to-Ambient (Note 1b)125
RθJC Thermal Resistance, Junction-to-Case (Note 1) 25
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
FDS6612A FDS6612A 13’’ 12mm 2500 units
FDS6
6
12
A
FDS6612A Rev D (W)
Electrical Characteristics TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS Drain–Source Breakdown Voltage VGS = 0 V, ID = 250 µA30 V
∆BVDSS
∆TJ
Breakdown Voltage Temperature
Coefficient ID = 250 µA, Referenced to 25°C26 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 1µA
VDS = 24 V, VGS = 0 V, TJ=55°C10 µA
IGSS Gate–Body Leakage VGS = ±20 V, VDS = 0 V ±100 nA
On Characteristics (Note 2)
VGS(th)Gate Threshold Voltage VDS = VGS, ID = 250 µA11.9 3V
∆VGS(th)
∆TJ
Gate Threshold Voltage
Temperature Coefficient ID = 250 µA, Referenced to 25°C–4.4 mV/°C
RDS(on) Static Drain–Source
On–Resistance VGS = 10 V, ID = 8.4 A
VGS = 4.5 V, ID = 7.2 A
VGS= 10 V, ID = 8.4 A, TJ=125°C
19
24
25
22
30
37
mΩ
ID(on) On–State Drain Current VGS = 10 V, VDS = 5 V 20 A
gFS Forward Transconductance VDS = 15 V, ID = 8.4 A30 S
Dynamic Characteristics
Ciss Input Capacitance 560 pF
Coss Output Capacitance 140 pF
Crss Reverse Transfer Capacitance
VDS = 15 V, V GS = 0 V,
f = 1.0 MHz 55 pF
RGGate Resistance VGS = 15 mV, f = 1.0 MHz 2.5 Ω
Switching Characteristics (Note 2)
td(on) Turn–On Delay Time 7 14 ns
trTurn–On Rise Time 5 10 ns
td(off) Turn–Off Delay Time 22 35 ns
tfTurn–Off Fall Time
VDD = 15 V, ID = 1 A,
VGS = 10 V, RGEN = 6 Ω
3 6 ns
QgTotal Gate Charge 5.4 7.6 nC
Qgs Gate–Source Charge 1.7 nC
Qgd Gate–Drain Charge
VDS = 15 V, ID = 8.4 A,
VGS = 5 V
1.9 nC
Drain–Source Diode Characteristics and Maximum Ratings
ISMaximum Continuous Drain–Source Diode Forward Current 2.1 A
VSD Drain–Source Diode Forward
Voltage VGS = 0 V, IS = 2.1 A (Note 2) 0.771.2 V
trr Diode Reverse Recovery Time 19 nS
Qrr Diode Reverse Recovery Charge IF = 8.4 A, diF/dt = 100 A/µs 9nC
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) 50°C/W when mounted
on a 1in2 pad of 2 oz
copper
b) 125°C/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2 Test: Pulse Width < 300µs, Duty Cycle < 2.0%
FDS6
6
12
A
FDS6612A Rev D (W)
Typical Characteristics
0
10
20
30
40
00.5 11.5 22.5 3
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
VGS = 10V 4.5V
3.5V
3.0V
6.0V
4.0V
0.8
1
1.2
1.4
1.6
1.8
2
0 10 20 30 40
ID, DRAIN CURRENT (A)
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
VGS = 3.5V
4.5V
5.0V
10V
4.0V
6.0V
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.6
0.8
1
1.2
1.4
1.6
-50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
ID = 8.4A
VGS = 10V
0
0.02
0.04
0.06
0.08
0.1
2 4 6 8 10
VGS, GATE TO SOURCE VOLTAGE (V)
RDS(ON), ON-RESISTANCE (OHM)
ID = 4.2A
TA = 125oC
TA = 25oC
Figure 3. On-Resistance Variation with
Temperature. Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
0
10
20
30
40
1.5 22.5 33.5 44.5
VGS, GATE TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
TA = 125oC
-55oC
25oC
VDS = 5V
0.0001
0.001
0.01
0.1
1
10
100
0 0.2 0.4 0.6 0.8 1 1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
IS, REVERSE DRAIN CURRENT (A)
VGS = 0V
TA = 125oC
25oC
-55oC
Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDS6
6
12
A
FDS6612A Rev D (W)
Typical Characteristics
0
2
4
6
8
10
0246810 12
Qg, GATE CHARGE (nC)
VGS, GATE-SOURCE VOLTAGE (V)
ID = 8.4A
VDS = 10V
15V
20V
0
200
400
600
800
0 5 10 15 20 25 30
VDS, DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
Coss
Crss
f = 1 MHz
VGS = 0 V
Ciss
Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.
0.01
0.1
1
10
100
0.01 0.1 1 10 100
VDS, DRAIN-SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
DC
10s 1s
100ms
100
µ
s
RDS(ON) LIMIT
VGS = 10V
SINGLE PULSE
RθJA = 125oC/W
TA = 25oC
10ms
1ms
0
10
20
30
40
50
0.001 0.01 0.1 110 100
t1, TIME (sec)
P(pk), PEAK TRANSIENT POWER (W)
SINGLE PULSE
RθJA = 125oC/W
TA = 25oC
Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.
0.001
0.01
0.1
1
0.0001 0.001 0.01 0.1 1 10 100 1000
t1, TIME (sec)
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
RθJA(t) = r(t) * RθJA
RθJA = 125oC/W
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
t1t2
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
D = 0.5
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
FDS6
6
12
A
FDS6612A Rev D (W)
PSPICE Electrical Model N-Channel
.SUBCKT FDS6612A 2 1 3
*NOM TEMP=25 DEG C
*REV A - JULY 2003
CA 12 8 1E-9
CB 15 14 4.0E-10
CIN 6 8 5.1E-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 34.2
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LGATE 1 9 3.84E-9
LDRAIN 2 5 1.00E-9
LSOURCE 3 7 4E-9
RLGATE 1 9 38.4
RLDRAIN 2 5 10
RLSOURCE 3 7 40
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 8E-3
RGATE 9 20 4.2
RSLC1 5 51 RSLCMOD 1E-6
RSLC2 5 50 1E3
RSOURCE 8 7 RSOURCEMOD 7.5E-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1E-6*105),3))}
.MODEL DBODYMOD D (IS=7E-15 RS=6.1E-3 N=0.84 TRS1=1.7E-3 TRS2=1.0E-6
+ CJO=3.2E-10 TT=10E-9 M=0.5 IKF=0.3 XTI=3.0)
.MODEL DBREAKMOD D (RS=1E-1 TRS1=1.12E-3 TRS2=1.25E-6)
.MODEL DPLCAPMOD D (CJO=14E-11 IS=1E-30 N=10 M=0.34)
.MODEL MWEAKMOD NMOS (VTO=1.82 KP=0.05 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=42 RS=.1)
.MODEL MMEDMOD NMOS (VTO=2.1 KP=6 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=4.2)
.MODEL MSTROMOD NMOS (VTO=2.55 KP=50 IS=1E-30 N=10 TOX=1 L=1U W=1U)
.MODEL RBREAKMOD RES (TC1=0.83E-3 TC2=1E-7)
.MODEL RDRAINMOD RES (TC1=6E-3 TC2=5E-6)
.MODEL RSLCMOD RES (TC1=2.5E-3 TC2=4.5E-6)
.MODEL RSOURCEMOD RES (TC1=1.0E-3 TC2=1E-6)
.MODEL RVTHRESMOD RES (TC1=-2.013E-3 TC2=-7E-6)
.MODEL RVTEMPMOD RES (TC1=-1.5E-3 TC2=1E-6)
.MODEL S1AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-1.3 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-0.5 VOFF=-1.3)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
FDS6
6
12
A
FDS6612A Rev D (W)
RTHERM6
RTHERM8
RTHERM7
RTHERM5
RTHERM4
RTHERM3
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
7
JUNCTION
AMBIENT
8
th
RTHERM2
RTHERM1
CTHERM7
CTHERM8
SPICE Thermal Model
.SUBCKT FDS6612A_THERM TH TL
*THERMAL MODEL SUBCIRCUIT
*REV A - JULY 2003
*MIN PAD RJA
CTHERM1 TH 80.005
CTHERM2 870.05
CTHERM3 760.10
CTHERM4 650.35
CTHERM5 540.45
CTHERM6 430.50
CTHERM7 320.55
CTHERM8 2TL 3.00
RTHERM1 TH 8 5.000
RTHERM2 8 7 6.250
RTHERM3 7 6 7.500
RTHERM4 6 5 8.750
RTHERM5 5 4 10.625
RTHERM6 4 3 11.875
RTHERM7 3 2 31.250
RTHERM8 2 TL 43.750
.ENDS
FDS6
6
12
A
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY , FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS P ATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF F AIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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