General Description
The MAX5322 dual, 12-bit, serial-interface, digital-to-ana-
log converter (DAC) provides bipolar ±5V to ±10V out-
puts from ±12V to ±15V analog power-supply voltages, or
unipolar 5V to 10V outputs from a single 12V to 15V ana-
log power-supply voltage.
The MAX5322 features excellent linearity with both inte-
gral nonlinearity (INL) and differential nonlinearity (DNL)
guaranteed to ±1 LSB (max). The device also features a
fast 10µs to 0.5 LSB settling time, and a hardware-shut-
down feature that reduces current consumption to 2.8µA.
The output goes to midscale at power-up in bipolar
mode (0V), and to zero scale at power-up in unipolar
mode (0V). A clear input (CLR) asynchronously clears
the DAC register and sets the outputs to 0V. The outputs
can be asynchronously updated with the load DAC
(LDAC) input.
The device features a fast 10MHz SPI™-/QSPI™-
/MICROWIRE™-compatible serial interface that operates
with 3V or 5V logic. Additional features include a serial-
data output (DOUT) for daisy chaining and read-back
functions. The MAX5322 requires external reference volt-
ages of 2V to 5.25V and is available in a 28-pin SSOP
package that operates over the extended (-40°C to
+85°C) temperature range.
Applications
Features
♦Unipolar or Bipolar Output-Voltage Ranges
Unipolar: 0 to +2 x VREF (Single or Dual Supply)
Bipolar: -2 x VREF to +2 x VREF (Dual Supply)
♦Guaranteed INL ≤±1 LSB (max)
♦Guaranteed Monotonic: DNL ≤±1 LSB (max)
♦10µs Settling Time to 0.5 LSB
♦Low 2.8µA Shutdown Current
♦Fast 10MHz SPI-/QSPI-/MICROWIRE-Compatible
Serial Interface
♦Power-On Reset Sets DAC Output to 0V
♦Schmitt Trigger Inputs for Direct
Optocoupler Interface
♦Serial-Data Output Allows Daisy-Chaining
of Devices
♦28-Pin SSOP (8mm x 10mm)
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3150; Rev 2; 10/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX5322EAI -40°C to +85°C 28 SSOP
OUTA
SGNDA
REFA
2R
2R
12-BIT
DAC A
A1
A2
SW1
SW2
SW3
12
OUTB
SGNDB
2R
2R
12-BIT
DAC B
A3
A4
SW4
SW5
SW6
12
REFB
2R
2R 2R
2R
INPUT
REGISTERS
DAC
REGISTERS
DIN
SCLK
SERIAL INTERFACE
AND CONTROL
16-BIT SHIFT REGISTER
12 12
CS
UNI/BIPB
UNI/BIPA
SHDN
DOUT
DIGITAL
POWER
VCC
DGND
ANALOG
POWER
VSS
VDD
AGND
MAX5322
CLR
LDAC
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Motor Control
Industrial Process
Controls
Industrial Automation
Automatic Test
Equipment (ATE)
Analog I/O Boards
Data-Acquisition Systems
Functional Diagram
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS (DUAL SUPPLY)
(VDD = +15V ±5%, VSS = -15V ±5%, VCC = +5V ±10%, AGND = DGND = SGND_ = 0V, VREF_ = 5V, RLOAD = 2kΩ, CLOAD = 250pF,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND..........................................................-0.3V to +17V
VSS to AGND ..........................................................-17V to +0.3V
VDD to VSS ..........................................................................+34V
VCC to DGND ...........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
SGND_ to AGND ...................................................-0.3V to +0.3V
SCLK, DIN, CS, SHDN, UNI/BIP_, CLR,
LDAC, DOUT to DGND ..........................-0.3V to (VCC + 0.3V)
OUT_ to AGND.................................(VSS - 0.3V) to (VDD + 0.3V)
REF_ to AGND..........................................................-0.3V to +6V
Maximum Current into REF_ .............................................±10mA
Maximum Current into Any Pin Excluding REF_...............±50mA
Continuous Power Dissipation (TA= +70°C)
28-Pin SSOP (derate 9.5mW/°C above +70°C) ........761.9mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC ACCURACY
Resolution N 12 Bits
Integral Nonlinearity INL ±1 LSB
Differential Nonlinearity DNL Guaranteed monotonic ±1 LSB
Bipolar, code = 800hex ±2
Zero-Scale Error Unipolar, code = 000hex ±2LSB
Bipolar 0.9
Zero-Scale Temperature
Coefficient Unipolar 0.09
ppm
FSR/°C
Bipolar (output unloaded) ±2
Gain Error Unipolar (output unloaded) ±2LSB
Bipolar (output unloaded) 2
Gain-Error Temperature
Coefficient Unipolar (output unloaded) 2
ppm
FSR/°C
ANALOG OUTPUTS (OUTA, OUTB)
Output Voltage Range (VSS + 1.5V) < VOUT < (VDD - 1.5V) -2 x
VREF
+2 x
VREF V
Resistive Load to GND RLOAD 2kΩ
Capacitive Load to GND CLOAD 250 pF
DC Output Resistance 0.5 Ω
SGND INPUTS (SGNDA, SGNDB)
Input Impedance 92 kΩ
REFERENCE INPUTS (REFA, REFB)
Reference Voltage Input Range 2.00 5.25 V
Input Resistance RREF Code = 555hex, worst-case code 15 22 kΩ
Reference Bandwidth VREF = 200mVP-P + 5VDC 200 kHz
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
_______________________________________________________________________________________ 3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (SCLK, DIN, CS, SHDN, UNI/BIPA, UNI/BIPB, CLR, LDAC)
+2.7V ≤ VCC ≤ +3.6V 0.7 x VCC
Input Voltage High VIH +4.5V ≤ VCC ≤ +5.5V 2.4 V
+2.7V ≤ VCC ≤ +3.6V 0.8
Input Voltage Low VIL +4.5V ≤ VCC ≤ +5.5V 0.8 V
+2.7V ≤ VCC ≤ +3.6V 10
Input Capacitance C +4.5V ≤ VCC ≤ +5.5V 10 pF
0 ≤ all digital inputs ≤ VCC,
+2.7V ≤ VCC ≤ +3.6V ±1
Input Current (Note 1)
0 ≤ all digital inputs ≤ VCC,
+4.5V ≤ VCC ≤ +5.5V ±1
µA
DIGITAL OUTPUT (DOUT)
Output Voltage High VOH ISOURCE = 2mA VCC -
0.5 V
Output Voltage Low VOL ISINK = 2mA 0.4 V
Tri-State Leakage Current 0.1 µA
Tri-State Capacitance 10 pF
DYNAMIC PERFORMANCE
Voltage Output Slew Rate 2.5 V/µs
Output Settling Time To ±0.5 LSB of full scale, code 000 to
code FFF 10 µs
Digital Feedthrough CS = high, fSCLK = 10MHz, VOUT = 0V 10 nV-s
DAC-to-DAC Crosstalk 2.5 nV-s
Output-Noise Spectral Density at
10kHz 130 nV/√Hz
POWER SUPPLIES
Positive Analog-Supply Voltage VDD 10.80 15.75 V
Negative Analog-Supply Voltage VSS -10.80 -15.75 V
Positive Digital-Supply Voltage VCC 2.7 5.5 V
Positive Analog-Supply Current IDD Output unloaded, VOUT = 0 2.8 8 mA
Negative Analog-Supply Current ISS Output unloaded, VOUT = 0 -1.5 -8 mA
Digital-Supply Current ICC All digital inputs = 0 or VCC 200 µA
Positive analog supply 0.0006
Power-Supply Rejection Ratio
(Note 2) PSRR Negative analog supply 0.03 LSB/V
Positive analog supply 2.8 50
Negative analog supply 4 50Shutdown Current
Digital supply 4 10
µA
ELECTRICAL CHARACTERISTICS (DUAL SUPPLY) (continued)
(VDD = +15V ±5%, VSS = -15V ±5%, VCC = +5V ±10%, AGND = DGND = SGND_ = 0V, VREF_ = 5V, RLOAD = 2kΩ, CLOAD = 250pF,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (SINGLE SUPPLY)
(VDD = +15V ±5%, VSS = 0V, VCC = +5V ±10%, AGND = DGND = SGND_ = 0V, VREF_ = 5V, RLOAD = 10kΩ, CLOAD = 250pF,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC ACCURACY
Resolution N 12 Bits
Integral Nonlinearity INL (Note 3) ±1 LSB
Differential Nonlinearity DNL Guaranteed monotonic ±1 LSB
Unipolar Zero-Scale Error ±2 LSB
Unipolar Zero-Scale Temperature
Coefficient 0.09 ppm
FSR/°C
Gain Error No load ±2 LSB
Gain-Error Temperature
Coefficient No load 2 ppm
FSR/°C
ANALOG OUTPUTS (OUTA, OUTB)
Output Voltage Range 0+2 x
VREF V
Resistive Load to GND RLOAD 10 kΩ
Capacitive Load to GND CLOAD 250 pF
DC Output Resistance 0.5 Ω
SGND INPUTS (SGNDA, SGNDB)
Input Impedance 92 kΩ
REFERENCE INPUTS (REFA, REFB)
Reference Voltage Input Range 2.00 5.25 V
Input Resistance Code = 555hex, worst-case code 15 22 kΩ
Reference Input Bandwidth VREF = 200mVP-P + 5VDC 150 kHz
DIGITAL INPUTS (SCLK, DIN, CS, SHDN, UNI/BIPA, UNI/BIPB, CLR, LDAC)
+2.7V ≤ VCC ≤ +3.6V 0.7 x
VCC
Input Voltage High VIH
+4.5V ≤ VCC ≤ +5.5V 2.4
V
+2.7V ≤ VCC ≤ +3.6V 0.8
Input Voltage Low VIL +4.5V ≤ VCC ≤ +5.5V 0.8 V
+2.7V ≤ VCC ≤ +3.6V 10
Input Capacitance CIN +4.5V ≤ VCC ≤ +5.5V 10 pF
0 ≤ VIN ≤ VCC, +2.7V ≤ VCC ≤ +3.6V ±1
Input Current IIN 0 ≤ VIN ≤ VCC, +4.5V ≤ VCC ≤ +5.5V ±1 µA
DIGITAL OUTPUT (DOUT)
Output Voltage High VOH ISOURCE = 2mA VCC -
0.5 V
Output Voltage Low VOL ISINK = 2mA 0.4 V
Tri-State Leakage Current 0.1 µA
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (SINGLE SUPPLY) (continued)
(VDD = +15V ±5%, VSS = 0V, VCC = +5V ±10%, AGND = DGND = SGND_ = 0V, VREF_ = 5V, RLOAD = 10kΩ, CLOAD = 250pF,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Tri-State Capacitance 10 pF
DYNAMIC PERFORMANCE
Voltage Output Slew Rate 2.5 V/µs
Output Settling Time To ±0.5 LSB of full scale 10 µs
Digital Feedthrough CS = high, fSCLK = 10MHz, VOUT = 0V 10 nV-s
DAC-to-DAC Crosstalk 2.5 nV-s
Output-Noise Spectral Density at
10kHz 130 nV/√Hz
POWER SUPPLIES
Positive Analog Supply Voltage VDD 10.80 15.75 V
Negative Analog Supply Voltage VSS 0V
Positive Digital Supply Voltage VCC 2.7 5.5 V
Positive Analog Supply Current IDD Output unloaded, VOUT = 0 2.5 8 mA
Negative Analog Supply Current ISS Output unloaded, VOUT = 0 -0.5 -8 mA
Digital Supply Current ICC All digital inputs = 0 or VCC 9 200 µA
Power-Supply Rejection Ratio PSRR 0.001 LSB/V
Analog supply 2.8 5
Shutdown Current Digital supply 2.8 5 µA
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
6 _______________________________________________________________________________________
TIMING CHARACTERISTICS
(VDD = +15V, VSS = -15V or 0V, VCC = +2.7V to +5.5V, AGND = DGND = SGND_ = 0, VREF_ = 5V, RLOAD = 2kΩ, ,CLOAD = 250pF,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Frequency 10 MHz
SCLK Clock Period tCP 100 ns
SCLK Pulse-Width High tCH For nondaisy-chain use 45 ns
For nondaisy-chain use 45
SCLK Pulse-Width Low tCL For daisy-chain use 98 ns
CS Fall to SCLK Rise Setup Time tCSS 40 ns
+2.7V ≤ VCC ≤ +3.6V 15
SCLK Rise to CS Rise Hold Time tCSH +4.5V ≤ VCC ≤ +5.5V 10 ns
DIN Setup Time tDS 20 ns
DIN Hold Time tDH 10 ns
LDAC Pulse Width tLD 50 ns
+2.7V ≤ VCC ≤ +3.6V 100
CS Rise to LDAC Low Setup Time tLDS +4.5V ≤ VCC ≤ +5.5V 50 ns
CLOAD = 20pF, +2.7V ≤ VCC ≤ +3.6V 100
SCLK Fall to DOUT Valid
Propagation Delay tDO1 CLOAD = 20pF, +4.5V ≤ VCC ≤ +5.5V 80 ns
SCLK Rise to CS Fall Delay tCS0 10 ns
CS Low to DOUT Valid Time tCSE CLOAD = 20pF 120 ns
CS High to DOUT Disabled Time tCSD 120 ns
CS Rise to SCLK Rise Hold Time tCS1 50 ns
+2.7V ≤ VCC ≤ +3.6V 200
CS Pulse-Width High tCSW +4.5V ≤ VCC ≤ +5.5V 100 ns
CLR Pulse-Width Low tCLR 50 ns
Note 1: Output unloaded, digital inputs = VCC or DGND.
Note 2: ∆VDD = 15.5V to 14.5V, ∆VSS = -15.5V to -14.5V, input code = 14hex to FFFhex
Note 3: Accuracy is guaranteed from code 14hex to FFFhex
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
_______________________________________________________________________________________ 7
INTERGRAL NONLINEARITY
vs. INPUT CODE
MAX5322 toc01
INPUT CODE (DECIMAL)
INL (LSB)
307220481024
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0 4096
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE
MAX5322 toc02
REFERENCE VOLTAGE (V)
INL (LSB)
5.04.53.5 4.03.02.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
2.0 5.5
DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
MAX5322 toc03
INPUT CODE (DECIMAL)
DNL (LSB)
307220481024
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0 4096
DIFFERENTIAL NONLINEARITY
vs. REFERENCE VOLTAGE
MAX5322 toc04
REFERENCE VOLTAGE (V)
DNL (LSB)
5.04.53.5 4.03.02.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
2.0 5.5
BIPOLAR INL vs. TEMPERATURE
MAX5322 toc05
TEMPERATURE (°C)
INL (LSB)
603510-15
0
0.2
0.4
-0.1
0.1
0.3
0.5
-0.2
-40 85
WORST CASE
BIPOLAR DNL vs. TEMPERATURE
MAX5322 toc06
TEMPERATURE (°C)
DNL (LSB)
603510-15
0.1
0.2
0.3
0.4
0.5
0
-40 85
WORST CASE
UNIPOLAR SETTLING TIME
(CLOAD = 250pF, RLOAD = 10kΩ)
MAX5322 toc07
t = 10.0µs/div
A
B
0
A: CS, 5.0V/div
B: OUT, 2.0V/div
CS
5V/div
2V/div
VOUT
BIPOLAR SETTLING TIME
(CLOAD = 250pF, RLOAD = 2kΩ)
MAX5322 toc08
t = 10.0µs/div
A
B
0
A: CS, 5.0V/div
B: OUT, 5.0V/div
CS
VOUT
5V/div
5V/div
BIPOLAR MAJOR CARRY GLITCH
ENERGY, CLOAD = 250pF
MAX5322 toc09
t = 4.00µs/div
5V/div
100mV/div
CS
VOUT
Typical Operating Characteristics
(VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND_ = 0, VREF_ = +5.0V,
output unloaded, TA= +25°C, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
8 _______________________________________________________________________________________
BIPOLAR MAJOR CARRY GLITCH
CLOAD = 10pF
MAX5322 toc10
t = 4.00µs/div
5V/div
100mV/div
CS
VOUT
UNIPOLAR ZERO-SCALE VOLTAGE
vs. TEMPERATURE
MAX5322 toc11
TEMPERATURE (°C)
VOUT (mV)
6035-15 10
43
44
45
46
47
48
49
50
42
-40 85
CODE = 0X014hex
BIPOLAR ZERO-SCALE VOLTAGE
vs. TEMPERATURE
MAX5322 toc12
TEMPERATURE (°C)
VOUT (mV)
603510-15
0.5
1.0
1.5
2.0
2.5
0
-40 85
CODE = 0X800hex
UNIPOLAR FULL-SCALE VOLTAGE
vs. TEMPERATURE
MAX5322 toc13
TEMPERATURE (°C)
VOUT (V)
603510-15
9.995
9.996
9.997
9.998
9.999
10.000
9.994
-40 85
CODE = 0XFFFhex
POSITIVE BIPOLAR FULL-SCALE VOLTAGE
vs. TEMPERATURE
MAX5322 toc14
TEMPERATURE (°C)
VOUT (V)
603510-15
9.995
9.996
9.997
9.998
9.994
9.993
9.992
-40 85
CODE = 0XFFFhex
NEGATIVE BIPOLAR FULL-SCALE VOLTAGE
vs. TEMPERATURE
MAX5322 toc15
TEMPERATURE (°C)
VOUT (V)
603510-15
-9.995
-9.996
-9.997
-9.998
-9.994
-9.993
-9.992
-40 85
CODE = 0X000hex
UNIPOLAR SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5322 toc16
VDD (V)
IDD (mA)
14.813.812.811.8
1
2
3
4
5
0
10.8 15.
8
VSS = 0V
BIPOLAR POSITIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5322 toc17a
VDD (V)
IDD (mA)
14.813.812.811.8
1
2
3
4
5
0
10.8 15.8
VSS = -15V
BIPOLAR NEGATIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5322 toc17b
VSS (V)
ISS (mA)
-11.8-12.8-13.8-14.8
-4
-3
-2
-1
0
-5
-15.8 -10.8
VDD = 15V
Typical Operating Characteristics (continued)
(VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND_ = 0, VREF_ = +5.0V,
output unloaded, TA= +25°C, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
_______________________________________________________________________________________ 9
UNIPOLAR SUPPLY CURRENT
vs. TEMPERATURE
MAX5322 toc18
TEMPERATURE (°C)
IDD (mA)
603510-15
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
-40 85
VSS = 0V
BIPOLAR POSITIVE SUPPLY CURRENT
vs. TEMPERATURE
MAX5322 toc19A
TEMPERATURE (°C)
IDD (mA)
603510-15
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
-40 85
BIPOLAR NEGATIVE SUPPLY CURRENT
vs. TEMPERATURE
MAX5322 toc19B
TEMPERATURE (°C)
ISS (mA)
603510-15
-4.5
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0
-5.0
-40 85
BIPOLAR SHUTDOWN CURRENT
vs. TEMPERATURE
MAX5322 toc20
TEMPERATURE (°C)
SHUTDOWN CURRENT (µA)
6035-15 10
-2
-1
0
1
2
3
4
5
-3
-40 85
ICC
IDD
ISS
UNIPOLAR SHUTDOWN CURRENT
vs. TEMPERATURE
MAX5322 toc21
TEMPERATURE (°C)
SHUTDOWN CURRENT (µA)
6035-15 10
0
1
2
3
4
5
-1
-40 85
ICC
IDD
UNIPOLAR OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX5322 toc22B
IOUT (mA)
VOUT (V)
1.00.80.60.40.2
0.055
0.065
0.075
0.085
0.095
0.105
0.115
0.125
0.135
0.045
01.2
CODE = 014hex
BIPOLAR OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX5322 toc23A
IOUT (mA)
VOUT (V)
-4-8-16 -12
-10.000
-9.995
-9.990
-9.985
-9.980
-9.975
-9.970
-9.965
-10.005
-20 0
CODE = 000hex
BIPOLAR OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX5322 toc23B
IOUT (mA)
VOUT (V)
161248
10.000
9.995
9.990
9.985
9.980
9.975
9.970
9.960
9.965
10.005
020
CODE = FFFhex
Typical Operating Characteristics (continued)
(VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND_ = 0, VREF_ = +5.0V,
output unloaded, TA= +25°C, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
UNIPOLAR OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX5322 toc22A
IOUT (mA)
VOUT (V)
161284
9.965
9.970
9.975
9.980
9.985
9.990
9.995
10.000
10.005
9.960
020
CODE = FFFhex
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
10 ______________________________________________________________________________________
BIPOLAR REFERENCE INPUT RESISTANCE
vs. INPUT CODE
MAX5322 toc25
INPUT CODE (DECIMAL)
REF INPUT RESISTANCE (kΩ)
307220481024
10
20
30
40
50
60
70
80
90
100
0
0 4096
BIPOLAR REFERENCE
INPUT BANDWIDTH
MAX5322 toc27
FREQUENCY (kHz)
RESPONSE (dB)
1001010.1
-15
-10
-5
0
5
-20
0.01 1000
200mVP-P INTO REF_
UNIPOLAR STARTUP RESPONSE,
CLOAD = 10pF
MAX5322 toc28A
t = 10.0µs/div
VDD
VCC
VREF
VOUT
20V/div
5V/div
5V/div
2V/div
UNIPOLAR STARTUP RESPONSE,
CLOAD = 230pF
MAX5322 toc28B
t = 10.0µs/div
VDD
VCC
VREF
VOUT
20V/div
5V/div
5V/div
1V/div
BIPOLAR STARTUP RESPONSE,
CLOAD = 10pF
MAX5322 toc29A
t = 10.0µs/div
VDD
VCC
VSS
VOUT
20V/div
5V/div
10V/div
2V/div
BIPOLAR STARTUP RESPONSE,
CLOAD = 230pF
MAX5322 toc29B
t = 10.0µs/div
VDD
VCC
VSS
VOUT
5V/div
20V/div
10V/div
1V/div
Typical Operating Characteristics (continued)
(VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND_ = 0, VREF_ = +5.0V,
output unloaded, TA= +25°C, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
UNIPOLAR REFERENCE INPUT RESISTANCE
vs. INPUT CODE
MAX5322 toc24
INPUT CODE (DECIMAL)
REF INPUT RESISTANCE (kΩ)
307220481024
10
20
30
40
50
60
70
80
90
100
0
0 4096
UNIPOLAR REFERENCE
INPUT BANDWIDTH
MAX5322 toc26
FREQUENCY (kHz)
RESPONSE (dB)
1001010.1
-15
-10
-5
0
5
-20
0.01 1000
200mVP-P INTO REF_
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
______________________________________________________________________________________ 11
MAX5322 toc32A
t = 40.0µs/div
VOUT
UNIPOLAR
SOFTWARE-SHUTDOWN RESPONSE
CS
5V/div
5V/div
MAX5322 toc32B
t = 40.0µs/div
VOUT
BIPOLAR
SOFTWARE-SHUTDOWN RESPONSE
CS
5V/div
10V/div
DAC-TO-DAC CROSSTALK
MAX5322 toc33
OUTB
OUTA
0V
1mV/div
0V
5V/div
t = 100µs/div
MAX5322 toc30
t = 100µs/div
VOUT
UNIPOLAR RELEASE FROM
HARDWARE SHUTDOWN RESPONSE
VSHDN
5V/div
2V/div
MAX5322 toc31
t = 100µs/div
VOUT
BIPOLAR RELEASE FROM
HARDWARE SHUTDOWN RESPONSE
VSHDN
5V/div
2V/div
Typical Operating Characteristics (continued)
(VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND_ = 0, VREF_ = +5.0V,
output unloaded, TA= +25°C, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
12 ______________________________________________________________________________________
PIN NAME FUNCTION
1, 2, 13–16,
27, 28 N.C. No Connection. Not internally connected.
3 UNI/BIPB
DAC B Output-Mode Selection Input. Selects unipolar or bipolar output. Logic high = unipolar, logic
low = bipolar. In unipolar mode, the analog output range is 0 to 2 x VREF. In bipolar mode, the analog
output range is (-2 x VREF) to (+2 x VREF).
4SHDN Active-Low Shutdown Input. Pulling SHDN low forces the DAC buffers into high impedance. Drive
SHDN high for normal operation.
5LDAC Active-Low Load DAC Input. DAC A and DAC B are updated with information in the input register on
the LDAC falling edge.
6CLR Acti ve- Low Asynchr onous C l ear D AC Inp ut. P ul l i ng C LR l ow cl ear s al l D AC s and i np ut r eg i ster s; r esets
al l outp uts to zer o.
7 DGND Digital Ground
8V
CC Digital Power Input. Connect VCC to a +2.7V to +5.5V power supply. Bypass VCC to DGND with a 10µF
and 0.1µF capacitor in parallel as close to the device as possible.
9DOUT
Serial-Data Output. Data is clocked out on SCLK’s falling edge. DOUT is high impedance when CS is
high. Data shifted into DIN appears at DOUT 16.5 clock cycles later.
10 SCLK Serial-Clock Input. SCLK clocks data in and out of the serial interface.
11 DIN Serial-Data Input. Data is clocked in on the rising edge of SCLK.
12 CS Active-Low Chip-Select Input. Data is not clocked into DIN unless CS is low.
17 UNI/BIPA
DAC A Output-Mode Selection. Selects unipolar or bipolar output. Logic high = unipolar, logic low =
bipolar. In unipolar mode, the analog output range is 0 to 2 x VREF. In bipolar mode, the analog output
range is (-2 x VREF) to (+2 x VREF).
18 OUTA DAC A Output
19 SGNDA DAC A Sense Ground. Connect to AGND.
20 REFA Reference Input for DAC A
21 VDD Positive Analog-Power Input. Connect VDD to a +10.8V to +15.75V power supply. Bypass VDD to
AGND with a 10µF and 0.1µF capacitor in parallel as close to the device as possible.
22 REFB DAC B Reference Input
23 AGND Analog Ground
24 SGNDB DAC B Sense Ground. Connect to AGND.
25 OUTB DAC B Output
26 VSS
Negative Analog-Power Input. For single-supply operation, connect VSS to AGND. For dual-supply
operation, connect VSS to a -10.8V to -15.75V power supply and bypass VSS to AGND with a 10µF and
0.1µF capacitor in parallel, as close to the device as possible.
Pin Description
Detailed Description
The MAX5322 dual, 12-bit DAC operates from either
single or dual analog supplies. Dual ±12V to ±15V
power supplies provide bipolar ±5V to ±10V outputs, or
unipolar 0V to 10V outputs. Single 12V to 15V analog
power supplies only provide unipolar 0 to 10V outputs.
The reference inputs accept voltages from 2V to 5.25V.
The DAC features INL and DNL less than ±1 LSB (max),
a fast 10µs settling time, and a hardware shutdown
mode that reduces current consumption to 2.8µA. The
device features a 10MHz SPI-/QSPI-/MICROWIRE-com-
patible serial interface that operates with 3V or 5V logic,
an asynchronous load input, and a serial-data output.
The device offers a CLR that sets the DAC outputs to 0V.
Figure 1 shows the functional diagram of the MAX5322.
Serial Interface
An SPI-/QSPI-/MICROWIRE-compatible serial interface
allows complete control of the DAC through a 16-bit
control word. The first 4 bits form the control bits that
determine register loading and software shutdown
functions. The last 12 bits form the DAC data. The 16-
bit word is entered MSB first.
Table 1 shows the serial-data control-word format.
Table 2 shows the interface commands. The MAX5322
can be programmed while in shutdown.
The serial interface contains five registers: a 16-bit shift
register, two 12-bit input registers, and two 12-bit DAC
registers (Figure 1). The shift register accepts data
from the serial interface. The input registers act as
holding registers for data going to the DAC registers
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
______________________________________________________________________________________ 13
CONTROL BITS DATA BITS
MSB LSB
C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 1. Control-Word Format
16-BIT SERIAL WORD
CONTROL BITS DATA BITS
C3 C2 C1 C0 D11–D0
FUNCTION
0 0 0 0 XXXXXXXXXXXX No operation (NOP).
0 0 0 1 12-bit DAC data Load both DAC registers and both input registers from the shift register.
(Start both DACs with new data.)
0 0 1 0 12-bit DAC data Load input register A from the shift register; DAC registers are unchanged.
0 0 1 1 12-bit DAC data Load input register B from the shift register; DAC registers are unchanged.
0 1 0 0 12-bit DAC data Load DAC register A and input register A from the shift register.
0 1 0 1 12-bit DAC data Load DAC register B and input register B from the shift register.
0 1 1 0 XXXXXXXXXXXX Update DAC register A from input register A (no data sent).
0 1 1 1 XXXXXXXXXXXX Update DAC register B from input register B (no data sent).
1 0 0 0 XXXXXXXXXXXX Shut down DAC A (provided SHDN = 1).
1 0 0 1 XXXXXXXXXXXX Shut down DAC B (provided SHDN = 1).
1 0 1 0 XXXXXXXXXXXX Update both DAC registers from their respective input registers.
(Start both DACs with data previously stored in the input register.)
1 0 1 1 XXXXXXXXXXXX Shut down both DACs (provided SHDN = 1).
1 1 0 0 XXXXXXXXXXXX Power up DAC A (no change to any registers).
1 1 0 1 XXXXXXXXXXXX Power up DAC B (no change to any registers).
1 1 1 0 XXXXXXXXXXXX Power up both DACs (no change to any registers).
1 1 1 1 XXXXXXXXXXXX Not used.
Table 2. Serial-Interface Programming Commands
X= Don’t care.
Note: The DACs can be programmed in shutdown mode.
MAX5322
and isolate the shift register from the DAC registers.
The DAC registers control the DAC ladder and thus the
output voltage. Any update to a DAC register updates
the respective output voltage.
Data in the shift register is transferred to the input regis-
ters during the appropriate software command only.
Data in the input registers is transferred to the DAC
registers in two ways: using the software command, or
through external logic control using the asynchronous
load input (LDAC). Table 2 shows the software com-
mands that transfer the data from the shift register to
the input and/or DAC registers. The CLR, an external
logic control, asynchronously forces all outputs to 0V, in
both unipolar and bipolar modes. Interface timing is
shown in Figures 2 and 3.
Wait a minimum of 100ns after CS goes high before
implementing LDAC or CLR. If either of these logic
inputs activates during a data transfer, the incoming
data is corrupted and needs to be reloaded. For soft-
ware control only, tie LDAC and CLR high.
DAC Architecture
The MAX5322 uses an inverted DAC ladder architec-
ture to convert the digital input into an analog output
voltage. The digital input controls weighted switches
that connect the DAC-ladder nodes to either REFA
(REFB) or GND (Figure 4). The sum of the weights pro-
duces the analog equivalent of the digital-input word
and is then buffered at the output.
External Reference and Transfer
Functions
Connect an external reference of 2V to 5.25V to REFA
and REFB. Set the output voltage range with the refer-
ence and the input code by using the equations below.
Unipolar output voltage:
V LSB CODE
OUT UNI UNI_ =×
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
14 ______________________________________________________________________________________
SCLK
DIN
COMMAND EXECUTED
98 16 (1)1
C2C3 D0C1 C0 D11 D10 D9 D6 D5 D4 D3 D2 D1D8 D7
CS
Figure 2. Serial-Interface Signals
SCLK
DIN
DOUT
tCS0 tCSS tCP tCSH tCS1
tCSW
tCSD
tLDS
tLD
tCH
tDS
tCSE tDO1
tDH
tCL
MSB LSB
CS
LDAC
Figure 3. Serial-Interface Timing Diagram
where:
Bipolar output voltage:
where:
where VOUT_UNI is the unipolar output voltage, VOUT_BIP
is the bipolar output voltage, LSBUNI is the unipolar LSB
step size, LSBBIP is the bipolar LSB step size, VREF is
the reference voltage, and CODE is the decimal equiva-
lent of the binary, 12-bit, DAC input code.
In either case, a 000hex input code produces the mini-
mum output (-2 x VREF for bipolar and zero for unipo-
lar), an 800hex input code produces the midscale
output (zero for bipolar and VREF for unipolar), and a
FFFhex input code produces the full-scale output (2 x
VREF for bipolar and unipolar).
Output Amplifiers
The output-amplifier section can be configured as either
unipolar or bipolar by the UNI/BIP logic input. With
UNI/BIPA (UNI/BIPB) forced low, SW1 (SW4) and SW2
(SW5) in Figure 1 are closed, and SW3 (SW6) is open.
This configuration channels the DAC output through two
output stages to generate the ±2 x VREF output swing.
The first amplifier generates the ±VREF voltage range and
the second amplifier gains it up by two. When configured
for bipolar operation, the MAX5322 must be driven with
dual ±12V to ±15V power supplies.
With UNI/BIPA (UNI/BIPB) forced high, switches SW1
(SW4) and SW2 (SW5) are open and SW3 (SW6) is
closed. This configuration channels the DAC output
through only a single gain stage to generate a 0 to 2 x
VREF output swing.
Daisy-Chaining
SPI-/QSPI-/MICROWIRE-compatible devices can be
daisy-chained to reduce I/O lines from the host controller
(Figure 7). Daisy-chain devices by connecting the DOUT
of one device to the DIN of the next, and connect the
SCLK of all devices to a common clock. Data is shifted
out of DOUT 16.5 clock cycles after it is shifted into DIN,
and is available on the rising edge of the 17th clock
cycle. The SPI-/QSPI-/MICROWIRE-compatible serial
interface normally works at up to 10MHz, but must be
slowed to 6MHz if daisy-chaining. DOUT is high imped-
ance when CS is high.
Shutdown
Shutdown is controlled by software commands or by the
SHDN logic input. The SHDN logic input may be imple-
mented at any time. The SPI-/QSPI-/MICROWIRE-com-
patible serial interface remains fully functional, and the
device is programmable while shutdown. When shut
down, the MAX5322 supply current reduces to 2.8µA
LSB V
BIP REF
=×4
212
V LSB CODE V
OUT BIP BIP REF_( )( )=×−×2
LSB V
UNI REF
=×2
212
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
______________________________________________________________________________________ 15
RRR
2R 2R 2R 2R2R
D0 D11D10D1
REFA
AGND
01010101
OUTA
CONTROL LOGIC
2R 2R
2R
2R
SGNDA
DAC REGISTER A
SW1
SW2
SW3
MAX5322
UNI/BIPA
Figure 4. Basic Inverted DAC Ladder
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
16 ______________________________________________________________________________________
(max), DOUT is high impedance, and OUTA and OUTB
are pulled to SGNDA and SGNDB, respectively, through
the internal feedback resistors of the output amplifier
(Figure 1). When coming out of shutdown, or during
device power-up, allow 350µs for the output to stabilize.
Applications Information
Power Supplies
A single supply of +12V to +15V is required to realize an
output swing of 0 to 10V. A dual supply of ±12V to ±15V
is required to realize an output swing of ±10V, and allows
unipolar, 0 to +10V output if UNI/BIP_ is forced high. A
+3V to +5V digital power supply and two +2.000V to
+5.250V external reference voltages are also required.
Always bring up the reference voltages last; the other
power supplies do not require sequencing.
Power-Supply Bypassing and
Ground Management
Bypass VDD and VSS with 1.0µF and 0.1µF capacitors to
AGND, and bypass VCC with a 1.0µF and 0.1µF capaci-
tors to DGND. Minimize trace lengths to reduce induc-
tance. Digital and AC transient signals on AGND or
DGND can create noise at the output. Connect AGND
and DGND to the highest quality ground available. Use
proper grounding techniques, such as a multilayer board
with a low-inductance ground plane or star connect all
ground return paths back to AGND. Carefully lay out the
traces between channels to reduce AC cross coupling
and crosstalk. Wire-wrapped boards, sockets, and
breadboards are not recommended.
BINARY DAC CODE ANALOG OUTPUT
MSB LSB UNIPOLAR (UNI/BIP_ = HIGH) BIPOLAR (UNI/BIP_ = LOW)
1111 1111 1111 +2 x VREF (4095 / 4096) +2 x VREF (2047 / 2048)
1000 0000 0001 +2 x VREF (2049 / 4096) +2 x VREF (1 / 2048)
1000 0000 0000 +2 x VREF (2048 / 4096) = VREF 0
0111 1111 1111 +2 x VREF (2047 / 4096) -2 x VREF (1 / 2048)
0000 0000 0001 +2 x VREF (1 / 4096) -2 x VREF (2047 / 2048)
0000 0000 0000 0 -2 x VREF (2048 / 2048) = -2 x VREF
Table 3. Output Voltage as Input Code Examples
hex DIGITAL INPUT CODE (LSB)
-2048
-2047
-2046
-2045
+2047
+2046
+2045
+2044
+1
0
-1
ANALOG OUTPUT VOLTAGE (LSB)
001
000
002
003
7FF
800
801
FFC
FFD
FFF
FFE
4 x VREF
1 LSB = 4 x VREF
4096
Figure 6. Bipolar Transfer Function
hex DIGITAL INPUT CODE (LSB)
0
1
2
3
4095
4094
4093
4092
2049
2048
2047
ANALOG OUTPUT VOLTAGE (LSB)
001
000
002
003
7FF
800
801
FFC
FFD
FFF
FFE
2 x VREF
1 LSB = 2 x VREF
4096
Figure 5. Unipolar Transfer Function
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
______________________________________________________________________________________ 17
MAX5322 MAX5322 MAX5322
TO OTHER
SERIAL DEVICES
DIN
SCLK
DOUT DIN
SCLK
DOUT DIN
SCLK
DOUT
SCLK
DIN
CS
CS CS CS
Figure 7. Daisy-Chaining Devices
Chip Information
TRANSISTOR COUNT: 5914
PROCESS: BiCMOS
Pin Configuration
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
N.C.
N.C.
VSS
OUTB
SGNDB
AGND
N.C.
REFB
VDD
REFA
SGNDA
OUTA
UNI/BIPA
N.C.
N.C.
N.C.
CS
DIN
SCLK
DOUT
VCC
DGND
CLR
LDAC
SHDN
UNI/BIPB
N.C.
N.C.
SSOP
TOP VIEW
MAX5322
MAX5322
±10V, Dual, 12-Bit, Serial, Voltage-Output DAC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
SSOP.EPS
PACKAGE OUTLINE, SSOP, 5.3 MM
1
1
21-0056 C
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
7.90
H
L
0∞
0.301
0.025
8∞
0.311
0.037
0∞
7.65
0.63
8∞
0.95
MAX
5.38
MILLIMETERS
B
C
D
E
e
A1
DIM
A
SEE VARIATIONS
0.0256 BSC
0.010
0.004
0.205
0.002
0.015
0.008
0.212
0.008
INCHES
MIN MAX
0.078
0.65 BSC
0.25
0.09
5.20
0.05
0.38
0.20
0.21
MIN
1.73 1.99
MILLIMETERS
6.07
6.07
10.07
8.07
7.07
INCHES
D
D
D
D
D
0.239
0.239
0.397
0.317
0.278
MIN
0.249
0.249
0.407
0.328
0.289
MAX MIN
6.33
6.33
10.33
8.33
7.33
14L
16L
28L
24L
20L
MAX N
A
D
eA1 L
C
HE
N
12
B
0.068
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
