CY74FCT162823CTPVCT - Texas Instruments

18-Bit Registers

CY74FCT16823T

CY74FCT162823T

SCCS062B - August 1994 - Revised September 2001

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modiﬁed to remove devices not offered.

Features

•I

off supports partial-power-down mode operation

• Edge-rate control circuitry for signiﬁcantly improved

noise characteristics

• Typical output skew < 250 ps

• ESD > 2000V

• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)

packages

• Industrial temperature range of −40˚C to +85˚C

•V

CC = 5V ± 10%

CY74FCT16823T Features:

• 64 mA sink current, 32 mA source current

• Typical VOLP (ground bounce) <1.0V at VCC = 5V,

TA = 25˚C

CY74FCT162823T Features:

• Balanced 24 mA output drivers

• Reduced system switching noise

•Typical VOLP (ground bounce) <0.6V at VCC = 5V,

TA = 25˚C

Functional Description

The CY74FCT16823T and the CY74FCT162823T 18-bit bus

interface registers are designed for use in high-speed,

low-power systems needing wide registers and parity. 18-bit

operationisachieved byconnecting the control linesof the two

9-bit registers. Flow-through pinout and small shrink

packaging aids in simplifying board layout.

This device is fully speciﬁed for partial-power-down

applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backﬂow through the device

when it is powered down.

The CY74FCT16823T is ideally suited for driving

high-capacitance loads and low-impedance backplanes.

The CY74FCT162823T has 24-mA balanced output drivers

with current limiting resistors in the outputs. This reduces the

need for external terminating resistors and provides for

minimal undershoot and reduced ground bounce. The

CY74FCT162823T is ideal for driving transmission lines.

Logic Block Diagrams

Pin Configuration

1CLR

SSOP/TSSOP

Top View

1CLR

1D1

1OE

1Q1

1Q2

GND

VCC

GND

FCT16823-1

1CLK

1CLKEN

1Q1

TO 8 OTHER CHANNELS

GND

1D1

1D2

1D3

1D4

1CLK

GND

1D5

1D6

1D7

1D9

VCC

GND

2D1

2D2

2D4

GND

2D5

2D6

2D7

2D8

VCC

2CLK

1CLKEN

1D8

2D3

2D9

2CLKEN

2CLR

2D2

2OE

2CLK

2CLKEN

2Q1

TO 8 OTHER CHANNELS

1Q3

1Q4

1Q5

1Q7

1Q8

1Q9

1Q6

2Q1

2Q2

2Q3

2Q4

2Q6

2Q7

2Q8

2Q5

2Q9

GND

VCC

GND

2OE

2CLR

FCT16823-2 FCT16823-3

CY74FCT16823T

CY74FCT162823T

Maximum Ratings[3, 4]

(Above which the useful life may be impaired. For user

guidelines, not tested.)

Storage Temperature .....................................−55°C to +125°C

Ambient Temperature with

Power Applied..................................................−55°C to +125°C

DC Input Voltage .................................................−0.5V to +7.0V

DC Output Voltage ..............................................−0.5V to +7.0V

DC Output Current

(Maximum Sink Current/Pin)...........................−60 to +120 mA

Power Dissipation..........................................................1.0W

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Notes:

1. H = HIGH Voltage Level.

L = LOW Voltage Level.

X = Don’t Care.

Z = HIGH Impedance.

=LOW-to-HIGH transition.

2. Output level before indicated steady-state input conditions were established.

3. Operationbeyondthelimitsset forth mayimpairtheusefullifeof thedevice.Unlessotherwisenoted,theselimitsare overtheoperatingfree-airtemperaturerange.

4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.

Pin Description

Name Description

D Data Inputs

CLK Clock Inputs

CLKEN Clock Enable Inputs (Active LOW)

CLR Asynchronous Clear Inputs (Active LOW)

OE Output Enable Inputs (Active LOW)

Q Three-State Outputs

Function Table[1]

Inputs Outputs

OE CLR CLKEN CLK D Q Function

H X X X X Z High Z

L L X X X L Clear

L H H X X Q[2] Hold

H H L L Z Load

H H L H Z

L H L L L

L H L H H

Operating Range

Range Ambient

Temperature VCC

Industrial −40°C to +85°C 5V ± 10%

CY74FCT16823T

CY74FCT162823T

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ.[5] Max. Unit

VIH Input HIGH Voltage 2.0 V

VIL Input LOW Voltage 0.8 V

VHInput Hysteresis[6] 100 mV

VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 mA −0.7 −1.2 V

IIH Input HIGH Current VCC=Max., VI=VCC ±1µA

IIL Input LOW Current VCC=Max., VI=GND ±1µA

IOZH HighImpedanceOutput Current

(Three-State Output pins) VCC=Max., VOUT=2.7V ±1µA

IOZL HighImpedanceOutput Current

(Three-State Output pins) VCC=Max., VOUT=0.5V ±1µA

IOS Short Circuit Current[7] VCC=Max., VOUT=GND −80 −140 −200 mA

IOOutput Drive Current[7] VCC=Max., VOUT=2.5V −50 −180 mA

IOFF Power-Off Disable VCC=0V, VOUT≤4.5V[8] 1µA

Output Drive Characteristics for CY74FCT16823T

Parameter Description Test Conditions Min. Typ.[5] Max. Unit

VOH Output HIGH Voltage VCC=Min., IOH=−3 mA 2.5 3.5 V

VCC=Min., IOH=−15 mA 2.4 3.5

VCC=Min., IOH=−32 mA 2.0 3.0

VOL Output LOW Voltage VCC=Min., IOL=64 mA 0.2 0.55 V

Output Drive Characteristics for CY74FCT162823T

Parameter Description Test Conditions Min. Typ.[5] Max. Unit

IODL Output LOW Voltage[7] VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA

IODH Output HIGH Voltage[7] VCC=5V, VIN=VIH or VIL, VOUT=1.5V −60 −115 −150 mA

VOH Output HIGH Voltage VCC=Min., IOH=−24 mA 2.4 3.3 V

VOL Output LOW Voltage VCC=Min., IOL=24 mA 0.3 0.55 V

Capacitance[9] (TA = +25˚C, f = 1.0 MHz)

Parameter Description Test Conditions Typ.[5] Max. Unit

CIN Input Capacitance VIN = 0V 4.5 6.0 pF

COUT Output Capacitance VOUT = 0V 5.5 8.0 pF

Notes:

5. Typical values are at VCC= 5.0V, TA= +25˚C ambient.

6. This input is speciﬁed but not tested.

7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample

and hold techniques are preferable in order to minimize internal chip heating and more accurately reﬂect operational values. Otherwise prolonged shorting

of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence ofparameter

tests, IOS tests should be performed last.

8. Tested at +25˚C.

9. This parameter is speciﬁed but not tested.

CY74FCT16823T

CY74FCT162823T

Power Supply Characteristics

Parameter Description Test Conditions[10] Min. Typ.[5] Max. Unit

ICC Quiescent Power Supply

Current VCC=Max. VIN<0.2V

VIN>VCC−0.2V — 5 500 µA

∆ICC Quiescent Power Supply

Current (TTL inputs HIGH) VCC=Max. VIN=3.4V[11] — 0.5 1.5 mA

ICCD Dynamic Power Supply

Current[12] VCC=Max.,

One Input Toggling,

50% Duty Cycle,

Outputs Open,

OE=CLKEN=GND

VIN=VCC or

VIN=GND — 75 120 µA/

MHz

ICTotal Power Supply Current[13] VCC=Max.,

f0=10 MHz,

50% Duty Cycle,

Outputs Open,

One Bit Toggling,

OE=CLKEN=GND

at f1=5 MHz

VIN=VCC or

VIN=GND — 0.8 1.7 mA

VIN=3.4V or

VIN=GND — 1.3 3.2

VCC=Max.,

at f1=2.5 MHz,

50% Duty Cycle,

Outputs Open,

Eighteen Bits Toggling,

OE=CLKEN=GND

f0=10 MHz

VIN=VCC or

VIN=GND — 4.2 7.1[14]

VIN=3.4V or

VIN=GND — 9.2 22.1[14]

Notes:

10. For conditions shown as Max. or Min., use appropriate value speciﬁed under Electrical Characteristics for the applicable device type.

11. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.

12. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

13. IC=I

QUIESCENT + IINPUTS + IDYNAMIC

IC=I

CC+∆ICCDHNT+ICCD(f0/2 + f1N1)

ICC = Quiescent Current with CMOS input levels

∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)

DH= Duty Cycle for TTL inputs HIGH

NT= Number of TTL inputs at DH

ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)

f0= Clock frequency for registered devices, otherwise zero

f1= Input signal frequency

N1= Number of inputs changing at f1

All currents are in milliamps and all frequencies are in megahertz.

14. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.

CY74FCT16823T

CY74FCT162823T

Switching Characteristics Over the Operating Range[15]

CY74FCT16823AT

CY74FCT162823AT

Parameter Description Condition[16] Min. Max. Unit Fig.No.[16]

tPLH

tPHL Propagation Delay CLK to Q CL=50 pF

RL=500Ω1.5 10.0 ns 1, 5

CL=300 pF[17]

RL=500Ω1.5 20.0

tPHL Propagation Delay CLR to Q CL=50 pF

RL=500Ω1.5 14.0 ns 1, 5

tPZH

tPZL Output Enable Time OE to Q CL=50 pF

RL=500Ω1.5 12.0 ns 1, 7, 8

CL=300 pF[17]

RL=500Ω1.5 23.0

tPHZ

tPLZ Output Disable Time OE to Q CL=5 pF[17]

RL=500Ω1.5 7.0 ns 1, 7, 8

CL=50 pF

RL=500Ω1.5 8.0

tSU Set-Up Time HIGH or LOW, D to CLK CL=50 pF

RL=500Ω3.0 — ns 4

tHHold Time HIGH or LOW, D to CLK 1.5 — ns 4

tSU Set-Up Time HIGH or LOW, CLKEN to CLK 3.0 — ns 9

tHHold Time HIGH or LOW CLKEN to CLK 0.0 — ns 9

tWCLK Pulse Width HIGH or LOW 6.0 — ns 5

tWCLR Pulse Width LOW 6.0 — ns 5

tREM Recovery Time CLR to CLK 6.0 — ns 6

tSK(O) Output Skew[18] — 0.5 ns —

Switching Characteristics Over the Operating Range[15]

CY74FCT16823CT

CY74FCT162823CT

Parameter Description Condition[16] Min. Max. Unit Fig.No.[16]

tPLH

tPHL Propagation Delay

CLK to Q CL=50 pF

RL=500Ω1.5 6.0 ns 1, 5

CL=300 pF[17]

RL=500Ω1.5 12.5

tPHL Propagation Delay

CLR to Q CL=50 pF

RL=500Ω1.5 6.1 ns 1, 5

tPZH

tPZL Output Enable Time

OE to Q CL=50 pF

RL=500Ω1.5 5.5 ns 1, 7, 8

CL=300 pF[17]

RL=500Ω1.5 12.5

tPHZ

tPLZ Output Disable Time

OE to Q CL=5 pF[17]

RL=500Ω1.5 5.2 ns 1, 7, 8

CL=50 pF

RL=500Ω1.5 6.5

CY74FCT16823T

CY74FCT162823T

tSU Set-Up Time

HIGH or LOW, D to CLK CL=50 pF

RL=500Ω2.0 — ns 4

tHHold Time

HIGH or LOW, D to CLK 1.5 — ns 4

tSU Set-Up Time

HIGH or LOW, CLKEN to CLK 3.0 — ns 9

tHHold Time HIGH or LOW

CLKEN to CLK 0.0 — ns 9

tWCLK Pulse Width

HIGH or LOW 3.3 — ns 5

tWCLR Pulse Width LOW 3.3 — ns 5

tREM Recovery Time

CLR to CLK 6.0 — ns 6

tSK(O) Output Skew[18] — 0.5 ns —

Notes:

15. Minimum limits are speciﬁed but not tested on Propagation Delays.

16. See “Parameter Measurement Information” in the General Information section.

17. These limits are speciﬁed but not tested.

18. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.

Switching Characteristics Over the Operating Range[15] (continued)

CY74FCT16823CT

CY74FCT162823CT

Parameter Description Condition[16] Min. Max. Unit Fig.No.[16]

Ordering Information CY74FCT16823

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

6.0 CY74FCT16823CTPACT Z56 56-Lead (240-Mil) TSSOP Industrial

CY74FCT16823CTPVC/PVCT O56 56-Lead (300-Mil) SSOP

10.0 CY74FCT16823ATPACT Z56 56-Lead (240-Mil) TSSOP Industrial

Ordering Information CY74FCT162823

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

6.0 74FCT162823CTPACT Z56 56-Lead (240-Mil) TSSOP Industrial

CY74FCT162823CTPVC O56 56-Lead (300-Mil) SSOP

74FCT162823CTPVCT O56 56-Lead (300-Mil) SSOP

10.0 74FCT162823ATPACT Z56 56-Lead (240-Mil) TSSOP Industrial

CY74FCT16823T

CY74FCT162823T

Package Diagrams

56-Lead Shrunk Small Outline Package O56

56-Lead Thin Shrunk Small Outline Package Z56

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