Approximate Scale 1:1
A8424
Description
The A8424 charges photoflash capacitors for digital cameras,
camcorders, and DSC combos. An integrated 55 V DMOS
switch drives the transformer in a flyback topology, optimizing
the design for 2-cell Li+ battery input. An integrated IGBT driver
with separate source and sink pins allows high performance
red-eye reduction implementation.
The A8424 offers a programmable peak switch current limit,
from 0.5 to 1.5 A, user-adjustable using a resistor to ground.
A proprietary control scheme optimizes the capacitor charging
time. Low quiescent current and low shutdown current further
improve system efficiency and extend battery life.
The A8424 is available in a 16-contact 3 mm × 3 mm TQFN
package with exposed pad for enhanced thermal performance.
This small, very thin profile (0.75 mm nominal overall height)
package is ideal for space-constrained applications. It is lead
(Pb) free, with 100% matte-tin leadframe plating.
Applications include:
SLR camera flash
Digital camcorder/DSC combo flash
2 Li+ input strobe
A8424-DS, Rev. 1
Features and Benefits
Wide battery voltage range: 1.5 to 11 V
Integrated 55 V DMOS switch in very thin profile
3 mm × 3 mm × 0.75 mm nominal height package
User-adjustable peak current limit, from 0.5 to 1.5 A
Output voltage sensing on primary side; no resistor divider
required
>75% efficiency
Fast charging time
Charge complete indication
Flexible, high current IGBT driver
Independent IGBT driver supply
Separate sink and source pins with 6 pull-up and
20 pull-down
Interlocked trigger pins improve noise immunity
No primary-side Schottky diode needed
High Current Photoflash Capacitor Charger
with IGBT Driver for 2 Li+ Batteries
Package: 16-contact TQFN (suffix ES)
Typical Application
+
SW
Battery Input
1.5 to 11 V
Bias Input
3.0 to 5.5 V
C2 100 μF
315 V
1 : 10
C1
D1
ISET
VIN VBAT
TLIM
CHARGE
DONE
GND
100 k
GSOURCE
TRIGGER1
VDRV
IGBT Driver
IGBT Gate
GSINK
VPULLUP
TRIGGER2
VOUT Detect
ISW sense
DONE
RSET
Control
Block
COUT
High Current Photoflash Capacitor Charger
with IGBT Driver for 2 Li+ Batteries
A8424
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Selection Guide
Part Number Packing*
A8424EESTR-T Tape and reel, 1500 pieces/reel
*Contact Allegro for additional packing options.
Absolute Maximum Ratings*
Characteristic Symbol Notes Rating Units
SW Pin VSW –0.3 to 55 V
VBAT Pin VBAT –0.3 to 12 V
VIN Pin VIN –0.3 to 7 V
Remaining Pins –0.3 to VIN + 0.3 V V
Operating Ambient Temperature TARange E –40 to 85 ºC
Maximum Junction TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
*With respect to GND.
Thermal Characteristics
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RJA On 4-layer PCB, based on JEDEC standard 47 ºC/W
*Additional thermal information available on Allegro website.
Number Name Function
1 GSOURCE IGBT gate drive – source connection
2 GSINK IGBT gate drive – sink connection
3 VIN Input voltage; connect to a 3.0 to 5.5 V voltage source
4 GND Ground connection
5 CHARGE Pull high to initiate charging; pull low to enter low-power standby mode
6, 7 NC No connection
8 TRIGGER2 IGBT input trigger 2; internally ANDed with TRIGGER1 pin
9SW
Drain connection of internal power MOSFET switch; connect to the other
terminal of the transformer primary winding
10 TRIGGER1 IGBT input trigger 1; internally ANDed with TRIGGER2 pin
11 ¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯ Pulls low when output reaches target value and CHARGE pin is high; goes
high during charging or whenever the CHARGE pin is low
12 TLIM
Sets time limit for minimum pulse width (secondary-side conduction time);
apply logic high for shorter pulses or logic low for longer pulses; see Selection
of Transformer section for details
13 VBAT Battery voltage; connect to the same power supply as used for transformer
primary winding
14 VSEL
Output voltage selection; use in conjunction with transformers of differing turns
ratios (N = 8, 9, or 10) to achieve desired output voltage and optimal efficiency
(this feature is not yet finalized)
15 ISET Sets the maximum switch current; connect an external resistor to GND to set
the target peak current; see Circuit Description section for details
16 VDRV Supply for IGBT gate driver
– EP Exposed pad for enhanced thermal dissipation (not connected electrically)
Pin-out Diagram
Terminal List Table
(Top View)
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
VDRV
ISET
VSEL
VBAT
CHARGE
NC
NC
TRIGGER2
TLIM
DONE
TRIGGER1
SW
GSOURCE
GSINK
VIN
GND
EP
High Current Photoflash Capacitor Charger
with IGBT Driver for 2 Li+ Batteries
A8424
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
S
R
Q
Q
㧙
18 s
HL
TriggeredޓTimer
VBAT
ISET
CHARGE
TRIGGER2
VDRV
GND
GSOURCE
SW
DCMޓDetector
ILIM Comparator
TRIGGER1
VSEL
VIN
GSINK
TLIM
18 s
tON(max)
tOFF(max)
S
R
Q
Q
㧙
Enable
One-Shot
RC
VSW 㧙
㧗
㧙
㧗
㧙
VBAT
DONE
DMOS
Exposed Pad
ISET
Buffer
VDS Ref
Vth
Gain
High Current Photoflash Capacitor Charger
with IGBT Driver for 2 Li+ Batteries
A8424
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS typical values valid at VIN = VBAT= 3.6 V, RSET = 33.2 kΩ, ISWlim = 1.0 A, and TA=25°C, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
VBAT Pin Voltage Range1VBAT 1.5 – 11 V
VIN Pin Voltage Range1VIN 3.0 – 5.5 V
UVLO Enable Threshold VINUV VIN rising 2.55 2.65 2.75 V
UVLO Hysteresis VINUVhys – 150 – mV
Switch Current Limit2ISWlimMAX Maximum, RSET = 22.1 k1.35 1.5 1.65 A
ISWlimMIN Minimum, RSET = 66 k– 0.5 – A
SW Current Limit to ISET Current Ratio ISWlim/ISET RSET = 22.1 k, CHARGE = high – 27.5 – kA/A
ISET Pin Voltage While Charging VSET RSET = 33.2 k, CHARGE = high – 1.2 – V
ISET Pin Internal Resistance RSET(INT) – 330 –
Switch On-Resistance RSWDS(on) VIN = 3.6 V, ID = 800 mA, TA = 25°C – 0.3 –
Switch Leakage Current1ISWlk VSW = VBAT(MAX), in shutdown – – 1 A
VIN Pin Supply Current IIN
Shutdown (CHARGE = low, TRIGGER = low) – 0.01 1 A
Charging done (CHARGE = high, ¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯
= low) – 25 100 A
Charging (CHARGE = high, TRIGGER = low) – 2 – mA
VBAT Pin Supply Current IBAT
Shutdown (CHARGE = high, TRIGGER = low) – 0.01 1 A
Charging done – – 1 A
Charging (CHARGE = high, TRIGGER = low) – – 50 uA
CHARGE Pin Input Current ICHARGE VCHARGE = VIN –36–A
CHARGE Pin Input Voltage High1ICHARGE(H) Over input supply range, VIN 1.4 – – V
CHARGE Pin Input Voltage Low1ICHARGE(L) Over input supply range, VIN – – 0.4 V
CHARGE Pin Pull-down Resistor RCHARGE – 100 – k
Maximum Switch-off Timeout toffMAX – 18 – s
Maximum Switch-on Timeout tonMAX – 18 – s
¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯
Pin Output Leakage Current1IDONElk ––1 A
¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯
Pin Output Low Voltage1VDONEL 32 A into ¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯
pin – – 100 mV
Output Comparator Trip Voltage (measured as
VSW – VBAT)1VOUTTRIP
VSEL = GND 31 31.5 32 V
VSEL = open – 35 – V
VSEL = VIN – 39.4 – V
Output Comparator Overdrive VOUTOV 200 ns pulse width (90% to 90%) TLIM = high – 200 400 mV
Minimum dV/dt for ZVS Comparator dV/dt Measured at SW pin – 20 – V/s
TLIM Pin Input Voltage VTLIM
TLIM = high 1.4 – – V
TLIM = low – – 0.4 V
Continued on the next page …
High Current Photoflash Capacitor Charger
with IGBT Driver for 2 Li+ Batteries
A8424
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
IGBT Driver
VDRV Pin IGBT Driver Supply Voltage1VDRV 3 – 5.5 V
TRIGGERx Pins Input Current ITRIG VTRIGGER = VIN – 36 – A
TRIGGERx Pins High Input Voltage1VTRIG(H) Over input supply range, VIN 1.4 – – V
TRIGGERx Pins Low Input Voltage1VTRIG(L) Over input supply range, VIN – – 0.4 V
TRIGGERx Pins Pull-down Resistor RTRIGPD – 100 – k
GSOURCE On-Resistance to VDRV RSrcDS(on) VDRV = 3.6 V, VGSOURCE= 1.8 V – 5 –
GSINK On-Resistance to GND RSnkDS(on) VDRV = 3.6 V, VGSINK= 1.8 V – 20 –
Propagation Delay (Rising) tdr
Connect GSOURCE to GSINK, RGATE = 12 ,
CLOAD = 6500 pF, VDRV = 3.6 V
– 30 – ns
Propagation Delay (Falling) tdf – 140 – ns
Output Rise Time tr– 80 – ns
Output Fall Time tf– 320 – ns
1Specifications over the range TA= –40°C to 85°C; guaranteed by design and characterization.
2Current limit guaranteed by design and correlation to static test. Refer to Application Information section for peak current in actual circuits.
ELECTRICAL CHARACTERISTICS (continued) typical values valid at VIN = VBAT= 3.6 V, RSET = 33.2 kΩ, ISWlim = 1.0 A, and TA=25°C,
unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
High Current Photoflash Capacitor Charger
with IGBT Driver for 2 Li+ Batteries
A8424
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Performance Characteristics
Charging Time at Various Peak Current Levels
Common Parameters
Symbol Parameter Units/Division
C1 VOUT 50 V
C2 IIN 100 mA
t time 1 s
Conditions Parameter Value
VIN 3.6 V
VBAT 5 V
COUT 100 F/
330 V UCC
Transformer = TDK LD5T565630T-003,
LP
= 10.5 H, N = 10.2
t
Conditions Parameter Value
RSET 45 k
ISWlim 0.8 A
IIN
VOUT
t
Conditions Parameter Value
RSET 33.2 k
ISWlim 1.0 A
IIN
VOUT
t
IIN
VOUT
Conditions Parameter Value
RSET 22.1 k
ISWlim 1.5 A
C1
C2
C1
C1
C1
C2
tCHARGE
tCHARGE
tCHARGE
C1
C2
C1
C2 C2
C2
High Current Photoflash Capacitor Charger
with IGBT Driver for 2 Li+ Batteries
A8424
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1234567891011
Charge Time versus Battery Voltage
V
IN
= 3 V, C
OUT
= 100 F UCC, T
A
=22°C
D1 Diode BAV23S; Transformer Kijima-Musen SBL-5.6-1
V
BAT
(V)
Time (s)
22.1 1.5
33.2 1
45 0.77
55 0.65
R
SET
(k)
I
P
(A)
COUT= 100 F. For larger or smaller capacitances, charging time
scales proportionally.
This data was obtained using a Kijima-Musen SBL-5.6-1 transformer
(LP = 9.8 H, N = 10.2). Highest efficiency is achieved at high battery
voltage and large peak current (1 to 1.5 A). At lower current (< 1 A),
switching frequency increases and so do switching losses. Therefore a
transformer with higher primary inductance is preferred when operating
at lower current.
The average input current decreases with higher VBAT. .
Performance Characteristics
0 to 325 Volts
R
SET
(k)
I
P
(A)
55 0.65
45 0.77
33.2 1
22.1 1.5
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
1.0 2.0 4.03.0 7.06.05.0 9.08.0 10.0 11.0
V
BAT
(V)
I
IN
(A)
Average Input Current versus Battery Voltage
V
IN
= 3 V, Transformer L
p
= 10 H, C
OUT
= 100 F UCC
58
60
62
64
66
68
70
72
74
76
78
80
82
1234567891011
22.1 1.5
33.2 1
45 0.77
55
0.65
R
SET
(k)
I
P
(A)
Efficiency versus Battery Voltage
Efficiency (%)
V
IN
= 3 V, C
OUT
= 100 F UCC, T
A
=22°C
D1 Diode BAV23S; Transformer Kijima-Musen SBL-5.6-1
High Current Photoflash Capacitor Charger
with IGBT Driver for 2 Li+ Batteries
A8424
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Explanation of Events
A Start charging process by pulling CHARGE pin high, provided that VIN is above the UVLO level.
Triggering (T1) is locked during the charging process (CHARGE and ¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯
pins are both high).
B Charging stops when VOUT reaches the target voltage level. Triggering (T2) is enabled after
completion of charging (CHARGE pin is high and ¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯
pin is low).
C Start a new charging process with a low-to-high transition at the CHARGE pin.
D Pull the CHARGE pin low to put the controller into the low-power standby mode. Triggering (T3) is
always enabled when CHARGE is low.
E Charging does not start, because VIN is below the UVLO level when the CHARGE pin goes high.
F After VIN goes above the UVLO level, another low-to-high transition at the CHARGE pin is required
to start the charging process.
Timing and IGBT Interlock Function
VOUT
CHARGE
VIN
TRIGGER
IGBTDRV
SW
ABC DE F
UVLO
Target VOUT
T3T1
DONE
T2
IGBT Drive Timing Definition
GSOURCE
or GSINK
TRIGGER
tdr trtdf tf
50%
10%
90%
50%
10%
90%
The two TRIGGER signals are internally ANDed together. As
shown in the timing diagram, below, triggering is prohibited dur-
ing the initial charging process. This prevents premature firing
of the flash before the output capacitor has been charged to its
target voltage. Refer to the section IGBT Gate Driver Interlock
for details.
High Current Photoflash Capacitor Charger
with IGBT Driver for 2 Li+ Batteries
A8424
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Circuit Description
The A8424 is a photoflash capacitor charger control
IC with a high current limit (up to 1.5A) and low
RDS(on) (0.35 maximum). The IC also integrates
an IGBT driver for strobe operation of the flash tube,
dramatically saving board space in comparison with
discrete solutions for strobe flash operation.
The IC is turned on by a low-to-high signal on the
CHARGE pin. When the charging cycle is initiated,
the primary current ramps up linearly at a rate deter-
mined by the battery voltage and the primary side
inductance. When the primary current reaches the set
limit, the internal MOSFET is turned off immediately
to allow the energy to be pushed into the photoflash
capacitor through the secondary winding. The sec-
ondary current drops linearly as the output capacitor
is charged. The charging cycle starts again when the
transformer flux is reset or after a predetermined time
period (18 s maximum off-time) has passed, which-
ever occurs first.
The peak switch current limit is determined by a resis-
tor, RSET, connected between the ISET pin and GND.
The value of RSET can be between 22 and 66 k.
This generates an ISET current between 18 and 55 A,
which corresponds to a desired peak switch current in
a range from 0.5 to 1.5 A.
Smart Current Limit (Optional)
With the help of some simple external logic, the
user can change the charging current according to
the battery voltage. For example, assume that ISET is
normally 50 A (for ISWlim = 1.5 A). Referring to the
following illustration, when the battery voltage drops
below 2.5 V, the signal at BL (battery-low) should go
high. The resistor RBL, connecting BL to the ISET
RSET
ISET
BL RBL
pin, then injects 20 A into RSET. This effectively
reduces ISET current to 30 A (for ISWLIM = 0.9 A). If
necessary, BL can also be connected to the TLIM pin
to reduce the minimum pulse width. The disadvantage
of this method is that 20 A flows continuously while
BL is high.
In another example of a possible application, we
can make use of a PTC thermistor to decrease the
switch current limit when the board temperature
exceeds 65°C. Referring to the following figure,
R3 is a PTC type thermistor such as the Murata
PRF18BG471QB1RB.
R1
52.3 k
R2
37.2 k
R3
470
ISET
RSET
+t°
In this configuration, the peak currents at various PCB
temperatures are as follows:
TPCB
(°C)
R3
(k)
RSET
(k)
Ipeak
(A)
25 0.470 22.0 1.5
65 4.7 23.3 1.4
80 47.0 32.3 1.0
Application Information
High Current Photoflash Capacitor Charger
with IGBT Driver for 2 Li+ Batteries
A8424
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Selection of Transformer
1. The transformer turns ratio (N = NS / NP) deter-
mines the output voltage, according to the following
formula:
VOUT = K × N – Vd , (1)
where K is 31.5 (when VSEL is connected to GND),
and Vd is the forward drop of the output diode
(approximately 2 V).
2. The primary inductance, LP , determines the on-time
of the switch, as follows:
t
on = –LP / R × ln (1 – ISWlim × R / VBAT) , (2)
where R is the total resistance in the primary current
path (including RSWDS(on) and the DC resistance of the
transformer).
If VBAT is much larger than ISWlim × R, then ton can be
approximated using the following formula:
ton = ISWlim × LP / VBAT . (3)
3. The secondary inductance, LS, determines the off-
time of the switch, as follows:
toff = (ISWlim /
N ) × LS /
VOUT . (4)
Because LS
/ LP = N × N:
toff = (ISWlim × LP × N ) / VOUT . (5)
The minimum pulse width for toff determines the
minimum primary inductance required for the trans-
former. For example, if ISWlim = 0.7 A, N = 10, and
VOUT = 315 V, then LP must be at least 9 H in order
to keep toff at 200 ns or longer. In general, choosing a
transformer with larger LP results in higher efficiency
(because the higher the value of LP , the lower the
switch frequency, and hence the lower the switching
loss). But transformers with higher LP ratings also
require more windings and larger magnetic cores.
Therefore a trade-off must be made between trans-
former size and efficiency.
In order to provide greater design flexibility with
different transformer, the TLIM pin can be used to
select between two minimum pulse width settings,
200 and 400 ns. When operating at low current or
when using a transformer with low inductance, the SW
pulse width is very narrow, so TLIM should be pulled
high to enable the IC to operate down to toff = 200 ns.
Conversely, when the SW pulse width is wider than
400 ns, it is generally better to pull TLIM low. This
is because when operating at high current, leakage
inductance and other parasitics may cause excessive
peaking of the SW waveform. Setting TLIM to low
reduces the effects of peaking and provides a more
accurate target voltage in this case. The relationship
between toff and switch output is shown in figure 1.
The A8424 has an additional feature that allows wider
choices of transformers. The VSEL pin selects the val-
ues of K corresponding to values of N. For the target
output voltage of approximately 315 V, the values of
K would be:
NK
10 31.5
935
8 39.4
By using transformers with lower turns ratios, an effi-
ciency gain of 1% to 2% can be expected typically.
For example, if VSEL is open and a transformer of
N = 9 is used, then applying equation 1, the final out-
put voltage will be:
VOUT = K × N – Vd = 35 × 9 – 2 313 V .
High Current Photoflash Capacitor Charger
with IGBT Driver for 2 Li+ Batteries
A8424
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Is desired, VSEL can also be used to achieve a higher
output voltage. For example, if we use a transformer
with N = 10 but set K = 35, then the final output voltage
would be approximately 348 V instead.
Selection of Switching Current Limit
The A8424 features continuously adjustable peak
switching current between 0.5 and 1.5 A. This is done
by selecting the value of the external resistor RSET
(connected between the ISET pin and GND), which
determines the ISET bias current, and therefore the
switching current limit, ISWlim.
To the first order approximation, ISWlim is related to
ISET and RSET by the following equation:
ISWlim = ISET × K
= (VSET × RSET ) × K , (6)
where K 28000 when the IC bias voltage, VIN , is
3.6 V.
In real applications, the switching current limit is
affected by bias voltage, battery voltage, and the
transformer primary inductance, LP . If necessary, the
following expressions can be used to determine ISWlim
more accurately:
ISET = VSET / (RSET + RSET(INT) – K × RG(INT)
) , (7)
where RSET(INT) is the internal resistance of the ISET
pin (330 typical), RG(INT) is the internal resistance
of the bonding wire for the GND pin (27 m typical),
and:
ISWlim = ISET × (K' + VIN × K")
+ (VBAT / LP ) × td , (8)
where K' = 24350, K" = 1040, and td = delay in SW
turn-off (0.12 s typical).
Figure 2 shows the relationship between RSET and
ISWlim at different bias voltages, VIN, when battery
voltage, VBAT, is fixed at 3.6 V.
Figure 3 shows the relation between RSET and ISWlim
at different battery voltages, when bias voltage is fixed
at 3.6 V). Note that the spread is inversely propor-
tional to the primary inductance of transformer used.
Figure 1. Relationship of toff and switch output.
VSW
VSW
VBAT
ISW
ISW
ton toff
Vrtf
tneg
VBAT
High Current Photoflash Capacitor Charger
with IGBT Driver for 2 Li+ Batteries
A8424
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Peak Current Limit versus ISET Resistance
VIN = 3.6 V, Transformer LP = 10 H, TA = 22°C
R
SET
(k)
I
SWlim
(A)
V
BAT
= 8.0 V
V
BAT
= 5.3 V
V
BAT
= 3.6 V
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
20 25 30 35 40 45 50 55 60 65 70 75
Peak Current Limit versus ISET Resistance
VBAT = 3.6 V, Transformer LP = 10 H, TA=22°C
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
20 25 30 35 40 45 50 55 60 65 70 75
R
SET
(k)
I
SWlim
(A)
V
IN
= 5.0 V
V
IN
= 3.6 V
V
IN
= 3.0 V
Figure 3. Chart of current versus limit settings, at fixed bias voltage
Figure 2. Chart of current versus limit settings, at fixed battery voltage
High Current Photoflash Capacitor Charger
with IGBT Driver for 2 Li+ Batteries
A8424
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Fast Charging and Timer Modes
The A8424 achieves fast charging time and high
efficiency by operating in discontinuous conduction
mode (DCM) with zero-voltage-switching (ZVS). This
operation is shown in figure 4.
The IC operates in Timer mode when beginning to
charge a completely discharged photoflash capacitor,
usually when the output voltage, VOUT, is less than
approximately 40 V (depending on the inductance of
transformer used). Timer mode has a fixed switch-
ing period of approximately 18 s. One advantage of
Timer mode is that it limits the initial battery current
surge and thus acts as a “soft-start,” as shown in fig-
ure 5.
As soon as sufficient voltage has built up at the output
capacitor, the IC changes into Fast-Charging mode.
Timer
Mode
Fast Charging Mode
VOUT
CHARGE
VBAT
IIN
t = 500 ms/div; VOUT =50 V/div; IIN =100 mA/div; VIN = 3.6 V; VBAT = 5.0 V;
RSET = 22.1 kΩ (IP ≈ 1.5 A); COUT = 100 μF/300 V; Transformer T-19-083
Figure 4. Relationship of Timer mode and Fast Charging mode
Figure 5. Timer mode (CCM), VOUT < 40 V
Figure 6. Fast-charging mode (DCM), VOUT > 35 V
t = 0.5 μs/div, VIN = 3.6 V, VBAT = 5 V, VOUT = 85 V
Figure 7. Zero-voltage switching
Fast-Charging Mode (variable period)
Minimum-Voltage Switching
VOUT
VSW
VBAT
IIN
Timer Mode (fixed period)
VOUT
VSW
VBAT
IIN
t = 1 μs/div, VIN = 3.6 V, VBAT = 5 V, VOUT = 35 V, Transformer LP= 10 μH
t = 2 μs/div; VIN = 3.6 V; VBAT = 5 V; VOUT = 30 V; Transformer LP= 10 μH
Zero-Voltage Switching
VOUT
VSW
VBAT
IIN
High Current Photoflash Capacitor Charger
with IGBT Driver for 2 Li+ Batteries
A8424
14
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
As shown in figure 6, in this mode the next switch-
ing cycle starts after the secondary-side current has
stopped flowing, and the switch voltage has dropped
to a minimum value. A special dV/dt detection circuit
is used to allow minimum-voltage switching, even
if the SW voltage does not drop to zero volts. This
enables fast-charging to start earlier than previously
possible, thereby reducing the overall charging time.
When output voltage is high enough (such that the
reflected voltage, Vr = VOUT/ N, is greater than VBAT ),
true zero-voltage switching is achieved, which further
improves efficiency as well as reducing switching
noises (figure 7).
Components Recommendation
Selection of the flyback transformer should be based
on the peak current, according to the following table:
IPeak Range
(A) Supplier Part Number
LP
(H) N
0.5 to 1.5 Tokyo Coil T-16-024A 12.8 10.25
0.6 to 1.2 TDK LDT565630T-003 10.5 10.2
0.75 to 1.0 TDK LDT565620ST-203 8.2 10.2
IGBT Gate Driver Application
The integrated IGBT driver is used to drive an external
flash trigger IGBT. Separate GSOURCE and GSINK
pins allow the user to adjust IGBT turn-on and turn-
off rise times. For the Electrical Characteristics table
in this document, IGBT drive timing is defined with
the GSOURCE and GSINK pins connected together,
and supplying a load comprising a 12 resistor and a
6500 pF capacitor.
IGBT Gate Driver Interlock
The TRIGGER1 and TRIGGER2 pins are ANDed
together inside the IC to control the IGBT gate driver.
If only one trigger pin is used, the other trigger pin
must be tied to the VIN pin to ensure that the unused
trigger pin is at logic high.
Triggering is disabled (locked) during charging. This
is to prevent switching noise from interfering with the
IGBT driver. After the CHARGE pin goes high (at the
start of a charging cycle), the IC must wait for comple-
tion of the charging cycle (D
¯¯
¯
¯
¯
O
¯
¯
¯
N
¯
¯
E
¯
goes low) before
triggering can be enabled, according to the following
chart:
Conditions Resulting State
IGBT Gate Driver
CHARGE ¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯
Low Don’t Care Enabled
High High Disabled
High Low Enabled
The IGBT gate driver is always enabled when the
CHARGE pin is low.
It is up to the system-level programming to ensure that
a trigger signal is not applied without sufficient volt-
age at the output capacitor.
High Current Photoflash Capacitor Charger
with IGBT Driver for 2 Li+ Batteries
A8424
15
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package ES, 3 mm x 3 mm 16-Contact TQFN
with Exposed Thermal Pad
C0.08
17X
ATerminal #1 mark area
BExposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
For reference only
(reference JEDEC MO-220WEED)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
CReference land pattern layout (reference IPC7351
QFN50P300X300X80-17W4M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
16
2
1
A
16
1
2
PCB Layout Reference View
B1.70
1.70
1.70
1.70
0.30
1
16 0.50
0.90
3.10
3.10
C
C
SEATING
PLANE
0.25 +0.05
–0.07
0.40 +0.15
–0.10
0.50 0.75 ±0.05
3.00 ±0.15
3.00 ±0.15
D
DCoplanarity includes exposed thermal pad and terminals
High Current Photoflash Capacitor Charger
with IGBT Driver for 2 Li+ Batteries
A8424
16
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Copyright ©2006-2012, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
Revision History
Revision Revision Date Description of Revision
Rev. 1 April 19, 2012 Finalize RJA , update Selection Guide, and
miscellaneous format changes
