5-557
FAST AND LS TTL DATA
QUAD 2-PORT REGISTER
The SN54/74LS398 and SN54/74LS399 are Quad 2-Port Registers. They
are the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit
edge-triggered register . A Common Select input selects between two 4-bit in-
put ports (data sources). The selected data is transferred to the output register
on the LOW-to-HIGH transition of the Clock input. The SN54/74LS398 fea-
tures both Q and Q inputs, while the SN54/74LS399 has only Q outputs.
•Select From Two Data Sources
•Fully Positive Edge-Triggered Operation
•Both True and Complemented Outputs on SN54/74LS398
•Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
SN54/74LS398
SN54/74LS399
PIN NAMES LOADING (Note a)
HIGH LOW
S Common Select Input 0.5 U.L. 0.25 U.L.
CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L.
I0a–I0d Data Inputs From Source 0 0.5 U.L. 0.25 U.L.
I1a–I0d Data Inputs From Source 1 0.5 U.L. 0.25 U.L.
Qa–QdRegister True Outputs (Note b) 10 U.L. 5 (2.5) U.L.
Qa–QdRegister Complementary Outputs
(Note b) 10 U.L. 5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
SN54/74LS398
SN54/74LS399
QUAD 2-PORT REGISTER
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
SN74LSXXXD SOIC
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16 1
16
1
16 1
D SUFFIX
SOIC
CASE 751B-03
20
1
J SUFFIX
CERAMIC
CASE 732-03
20 1
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
5-558
FAST AND LS TTL DATA
SN54/74LS398 • SN54/74LS399
FUNCTIONAL BLOCK DIAGRAM
IOA
S
IIA
IOB
IIB
IOC
IIC
IOD
IID
S
S
S
S
R
R
R
R
QA
QA
QB
QB
QC
QC
QD
QD
*
*
*
*
* SN54/74LS398 only
FUNCTIONAL DESCRIPTION
The SN54 /74LS398 and SN54/74LS399 are high-speed
Quad 2-Port Registers. They select four bits of data from two
sources (Ports) under the control of a common Select Input
(S). The selected data is transferred to a 4-Bit Output Register
synchronous with the LOW-to-HIGH transition of the Clock in-
put (CP). The 4-Bit RS type output register is fully edge-trig-
gered. The Data inputs (I) and Select inputs (S) must be stable
only a setup time prior to and hold time after the LOW-to-HIGH
transition of the Clock input for predictable operation. The
SN54/74LS398 has both Q and Q Outputs available.
FUNCTION TABLE
INPUTS OUTPUTS
S I0I1Q Q*
I I X L H
I h X H L
h X I L H
h X h H L
*SN54/74LS398 only
I = LOW Voltage Level one setup time pior to the LOW-to-HIGH clock transition
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
5-559
FAST AND LS TTL DATA
SN54/74LS398 • SN54/74LS399
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54
74 4.5
4.75 5.0
5.0 5.5
5.25 V
TAOperating Ambient Temperature Range 54
74 –55
025
25 125
70 °C
IOH Output Current — High 54, 74 –0.4 mA
IOL Output Current — Low 54
74 4.0
8.0 mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54 0.7
V
Guaranteed Input LOW Voltage for
All Inputs
VIL
Input LOW Voltage
74 0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54 2.5 3.5 V
V
CC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOH
Output HIGH Voltage
74 2.7 3.5 V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74 0.25 0.4 V IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
74 0.35 0.5 V IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
IIH
Input HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 13 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
tPLH
tPHL Propagation Delay,
Clock to Output Q 18
21 27
32 ns VCC = 5.0 V
CL = 15 pF
5-560
FAST AND LS TTL DATA
SN54/74LS398 • SN54/74LS399
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
tWClock Pulse Width 20 ns
VCC = 5.0 V
tsData Setup Time 25 ns
VCC = 5.0 V
tsSelect Setup Time 45 ns
VCC = 5.0 V
thHold Time, Any Input 0 ns
DEFINITIONS OF TERMS
SETUP TIME(ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME(th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative Hold Time indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
AC WAVEFORMS
Figure 1 Figure 2
Figure 3
*The shaded areas indicate when the input is permitted to change for predictable output performance.
5-561
FAST AND LS TTL DATA
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5-562
FAST AND LS TTL DATA
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