PTMA180402EL
PTMA180402FL
Confidential, Limited Internal Distribution
All published data at TCASE = 25°C unless otherwise indicated
ESD: Electrostatic discharge sensitive device—observe handling precautions!
Data Sheet 1 of 12 Rev. 09, 2011-12-13
PTMA180402EL
Package H-33265-8
Wideband RF LDMOS Integrated Power Amplifi er
40 W, 1800 – 2000 MHz
Description
The PTMA180402EL and PTMA180402FL are matched, wideband
40-watt, 2-stage, LDMOS integrated amplifi ers intended for use in all
typical modulation formats from 1800 to 2000 MHz. These devices
are offered in thermally-enhanced ceramic packages for cool and
reliable operation.
Features
• Designed for wide RF and modulation bandwidths
and low memory effects
• On-chip matching, integrated input DC block,
50-ohm input and > 5-ohm output
• Typical single-carrier CDMA performance at
1960 MHz, 28 V
- Average output power = 4 W
- Linear gain = 30 dB
- Effi ciency = 14%
- Adjacent channel power = –53 dBc
• Typical 2-tone performance, 1960 MHz, 28 V
- Output power (PEP) = 50 W at IM3 = –30 dBc
- Effi ciency = 33%
• Capable of handling 10:1 VSWR @ 28 V, 40 W
(CW) output power
• Integrated ESD protection. Meets HBM Class 1B
(minimum), per JESD22-A114F
• High-performance, thermally-enhanced packages,
Pb-free and RoHS compliant, with solder-friendly
plating
*See Infi neon distributor for future availability.
PTMA180402FL
Package H-34265-8
Broadband Performance
VDD = 28 V, IDQ1 = 110 mA, IDQ1 = 330 mA
5
10
15
20
25
30
35
1700 1800 1900 2000 2100 2200
Frequency (MHz)
Gain (dB)
-30
-25
-20
-15
-10
-5
0
Return Loss (dB)
Gain
Return Loss
PTMA180402EL
PTMA180402FL
Confidential, Limited Internal Distribution
Data Sheet 2 of 12 Rev. 09, 2011-12-13
RF Characteristics
CDMA Measurements (tested in Infi neon test fi xture)
VDD = 28 V, IDQ1 = 110 mA, IDQ2 = 335 mA, POUT = 4 W average, ƒ = 1960 MHz
Characteristic Symbol Min Typ Max Unit
Gain Gps 28.5 30 — dB
Drain Efficiency ηD 13 14 — %
Adjacent Channel Power Ratio ACPR — –53 –50 dBc
DC Characteristics
Stage 1 Characteristics Conditions Symbol Min Typ Max Unit
Drain Leakage Current VDS = 28 V, VGS = 0 V IDSS — — 1.0 µA
V
DS = 63 V, VGS = 0 V IDSS — — 10.0 µA
Gate Leakage Current VGS = 10 V, VDS = 0 V IGSS — — 1.0 µA
On-state Resistance VGS = 10 V, VDS = 0.1 V RDS(on) — 1.6 — Ω
Operating Gate Voltage VDS = 28 V, IDQ = 160 mA VGS 2.0 2.5 3.0 V
Stage 2 Characteristics Conditions Symbol Min Typ Max Unit
Drain-source Breakdown Voltage VGS = 0 V, IDS = 10 mA V(BR)DSS 65 — — V
Drain Leakage Current VDS = 28 V, VGS = 0 V IDSS — — 1.0 µA
V
DS = 63 V, VGS = 0 V IDSS — — 10.0 µA
Gate Leakage Current VGS = 10 V, VDS = 0 V IGSS — — 1.0 µA
On-state Resistance VGS = 10 V, VDS = 0.1 V RDS(on) — 0.21 — Ω
Operating Gate Voltage VDS = 28 V, IDQ = 330 mA VGS 2.0 2.5 3.0 V
Data Sheet 3 of 12 Rev. 09, 2011-12-13
PTMA180402EL
PTMA180402FL
Confidential, Limited Internal Distribution
Maximum Ratings
Parameter Symbol Value Unit
Drain-Source Voltage VDSS 65 V
Gate-Source Voltage VGS –0.5 to +12 V
Junction Temperature TJ 200 °C
Storage Temperature Range TSTG –40 to +150 °C
Overall Thermal Resistance (TCASE = 70°C) 1st Stage RθJC
5.0 °C/W
POUT = 40 W, IDQ1 = 160 mA, IDQ2 = 330 mA 2nd Stage RθJC 1.1 °C/W
Ordering Information
Type and Version Package Type Package Description Shipping
PTMA180402EL V1 H-33265-8 Themally-enhanced, slotted fl ange Tray
PTMA180402EL V1 R50 H-33265-8 Themally-enhanced, slotted fl ange Tape
PTMA180402FL V1 H-34265-8 Themally-enhanced, earless fl ange Tray
PTMA180402FL V1 R50 H-34265-8 Themally-enhanced, earless fl ange Tape
Typical Performance (data taken in a production test fixture)
Two-tone at Selected Frequencies
VDD = 28 V, IDQ1 = 130 mA, IDQ2 = 330 mA
0
5
10
15
20
25
30
35
40
30 35 40 45
Output Power, avg. (dBm)
PAE (%)
-60
-55
-50
-45
-40
-35
-30
-25
-20
IMD3 (dBc)
Efficiency
IMD3
ƒ = 1930 MHz
ƒ = 1960 MHz
ƒ = 1990 MHz
CW Performance
VDD = 28 V, IDQ1 = 110 mA, IDQ2 = 330 mA
27
28
29
30
31
32
30 35 40 45 50
Output Power (dBm)
Gain (dB)
0
10
20
30
40
50
Gain
Efficiency
ƒ = 1930 MHz
ƒ = 1960 MHz
ƒ = 1990 MHz
Power Added Efficiency (%)
PTMA180402EL
PTMA180402FL
Confidential, Limited Internal Distribution
Data Sheet 4 of 12 Rev. 09, 2011-12-13
Typical Performance (cont.)
IS-95 at Selected Frequencies
VDD = 28 V, IDQ1 = 160 mA, IDQ2 = 330 mA
-65
-60
-55
-50
-45
-40
-35
0 2 4 6 8 10
Output Power (W)
ACPR (dBc)
0
5
10
15
20
25
ACPR
Efficiency
Power Added Efficiency (%)
ƒ = 1930 MHz
ƒ = 1960 MHz
ƒ = 1990 MHz
IS-95 at Selected Temperatures
VDD = 28 V, IDQ1 = 160 mA, IDQ2
= 330 mA,
ƒ = 1960 MHz
-5
5
15
25
35
0 2 4 6 8 10
Output Power, avg. (W)
Gain (dB),
Power Added Efficiency (%)
-65
-60
-55
-50
-45
-40
Gain
PAE
+25ºC
–25ºC
+90ºC
ACPR
Adj. Ch. Power Ratio (dBc)
WCDMA Performance
VDD = 28 V, IDQ1 = 160 mA, IDQ2 = 330 mA,
Test Mode 1 w/64 DPCH, PAR = 7.5 dB
-55
-50
-45
-40
-35
-30
1357911
Output Power (W)
ACPR (dBc)
0
5
10
15
20
25
ACPR
Efficiency
Power Added Efficiency (%)
ƒ = 1930 MHz
ƒ = 1960 MHz
ƒ = 1990 MHz
Gate – Source Voltage vs. Temperature
VDD = 28 V, IDQ1 = 110 mA, IDQ2 = 335 mA
0.85
0.90
0.95
1.00
1.05
1.10
1.15
-30 -10 10 30 50 70 90
Temperature (°C)
Normalized Gate – Source
Voltage (threshold), V
Slope = –1.3 mV/°C
Data Sheet 5 of 12 Rev. 09, 2011-12-13
PTMA180402EL
PTMA180402FL
Confidential, Limited Internal Distribution
Typical Performance (cont.)
PTMA180402EL
PTMA180402FL
Confidential, Limited Internal Distribution
Data Sheet 6 of 12 Rev. 09, 2011-12-13
Broadband Circuit Impedance
0.1
0.3
0.5
0.2
0.4
0.1
-
W
AV
E
LE
N
GT
H
S
W
AV
E
LE
N
G
TH
S
T
O
W
AR
D
L
OA
D
-
0
.0
1700 MHz
2200 MHz
Z Load
Z0 = 50 Ω
Frequency Z Load Ω
MHz R jX
1700 8.89 –3.62
1800 7.27 –2.99
1900 6.26 –2.13
2000 5.59 –1.19
2100 5.14 –0.27
2200 4.89 0.67
Data Sheet 7 of 12 Rev. 09, 2011-12-13
PTMA180402EL
PTMA180402FL
Confidential, Limited Internal Distribution
Reference Circuit
Reference circuit schematic for ƒ = 1930 – 1990 MHz
Circuit Assembly Specifications
DUT PTMA180402EL or PTMA180402FL LDMOS Integrated Power Amplifi er
Test Fixture Part No. LTN/PTMA180402EFL
PCB Rogers 4350, 0.76 mm [.030"] thick, 1 oz. copper, εr = 3.48
Find Gerber fi les for this test fi xture on the Infi neon Web site at http://www.infi neon.com/rfpower
Microstrip Electrical Characteristics at 1960 MHz Dimensions: L x W (mm) Dimensions: L x W (in.)
1 0.224 λ, 49.8 Ω 20.75 x 1.70 0.817 x 0.067
2 0.022 λ, 10.4 Ω 1.85 x 13.00 0.073 x 0.512
3 0.027 λ, 10.4 Ω 2.26 x` 13.00 0.089 x 0.512
4 0.035 λ, 34.1 Ω 3.18 x 3.00 0.125 x 0.118
5 0.048 λ, 34.1 Ω 4.29 x 3.00 0.169 x 0.118
6 0.153 λ, 44.5 Ω 14.07 x 2.03 0.554 x 0.080
7 0.046 λ, 49.8 Ω 4.27 x 1.70 0.168 x 0.067
8, 9 0.136 λ, 61.1 Ω 12.83 x 1.19 0.505 x 0.047
VD2
l1PTMA18040
J1 J2
VD1
C2
10µF
C1
100µF
50V
C4
0.1µF
C5
12pF
C19
12pF
C22
10µF
C20
0.1µF
C23
100µF
50V
C31
12pF
C24
12pF
C25
0.1µF
C27
10µF
C28
100µF
50V
DUT
1
2
3
5
6
7
48
C30
2.7pF
l2l4l5l6l7
l8
VG1
C6
10µF
C8
0.1µF
C9
12pF
C11
1µF
C12
0.1µF
C13
12pF
G2V
C3
1µF
C7
1µF
C10
10µF
C21
1µF
C26
1µF
C14
12pF
C15
0.1µF
C16
1µF
C17
10µF
C18
100µF
50V
C29
2.2pF
l3
l9
PTMA180402EL
PTMA180402FL
Confidential, Limited Internal Distribution
Data Sheet 8 of 12 Rev. 09, 2011-12-13
Reference Circuit (cont.)
Reference circuit asembly diagram* (not to scale)*
Component Description Suggested P/N or Comment
Supplier
C1, C18, C23, C28 Electrolytic capacitor, 100 µF, 50 V Digi-Key PCE3718CT-ND
C2, C6, C10, C17, C22, C27 Ceramic capacitor, 10 µF Murata GRM422Y5V106Z050AL
C3, C7, C11, C16, C21, C26 Ceramic capacitor, 1 µF Digi-Key 445-1411-2-ND
C4, C8, C12, C15, C20, C25 Capacitor, 0.1 µF Digi-Key 399-1267-2-ND
C5, C9, C13, C14, C19, C24, Ceramic capacitor, 12 pF ATC 600S120JT
C31
C29 Ceramic capacitor, 2.2 pF ATC 600S2R2CT
C30 Ceramic capacitor, 2.7 pF ATC 600S2R7BT
Data Sheet 9 of 12 Rev. 09, 2011-12-13
PTMA180402EL
PTMA180402FL
Confidential, Limited Internal Distribution
Package Specifications
Package H-33265-8 Outline
Diagram Notes—unless otherwise specifi ed:
1. Interpret dimensions and tolerances per ASME Y14.5M-1994.
2. Pins: S = source; see page 11 for complete list and diagram.
3. Lead thickness: 0.127±0.025 [.005±0.001]
4. Gold plating less than 0.25 micron [10 microinch].
5. All tolerances ± 0.127 [.005] unless specifi ed otherwise.
6. Exposed metal plane on bottom of ceramic insulator.
7. Primary dimensions are mm. Alternate dimensions are inches.
15.24±0.51
[.600±.020]
2. 5 4± 0. 5 1
[.100±.020]
(45° X 2.03 [.08])
C
L
L
C
C
L
1. 0 2
[.040]
10.16
[.400]
SPH 1.57
[.062]
3.68±.38
[.145±.015]
10.16
[.400]
7. 1 1
[.280]
4X R 0.63 [.025] MAX
4X R 0.13 [.05] MAX
9. 5 5
[.376]
REF
2X 2.21
[.087]
0. 7 6
[.030]
6X 0.406
[.016]
2X 3.48
[.137]
2X 4. 57
[.180]
123 4
8
567
9.78
[.385]
[.600]
S
20.32
[.800]
2X R 1.59
[R.063]
4X R 1.52
[R.060]
6.
L
C
L
C
(2.73
[.107])
H-33265 -8_po _12- 13-2011 _old inf o
PTMA180402EL
PTMA180402FL
Confidential, Limited Internal Distribution
Data Sheet 10 of 12 Rev. 09, 2011-12-13
Package Specifications (cont.)
Package H-34265-8 Outline
Diagram Notes—unless otherwise specifi ed:
1. Interpret dimensions and tolerances per ASME Y14.5M-1994.
2. Pins: S = source; see page 11 for complete list and diagram.
3. Lead thickness: 0.127±0.025 [.005±0.001]
4. Gold plating less than 0.25 micron [10 microinch].
5. All tolerances ± 0.127 [.005] unless specifi ed otherwise.
6. Primary dimensions are mm. Alternate dimensions are inches.
15.24±0.51
[.600±.020]
2.54±0.51
[.100±.020]
L
C
C
L
10.16
[.400]
7. 1 1
[.280]
4X R 0.63 [.025] MAX
4X R 0.13 [.05] MAX
9.5 5
[.376]
REF
2X 2.21
[.087]
0. 7 6
[.030]
6X 0.406
[.016]
2X 3. 4 8
[.137]
2X 4.57
[.180]
12 3 4
8
56 7
(45° X 2.03 [.08])
S
C
L
1.02
[.040]
10.16
[.400]
10.16
[.400]
SPH 1.57
[.062]
3.68±.38
[.145±.015]
H- 34265- 8_po_12- 13- 2011_ ood inf o
Data Sheet 11 of 12 Rev. 09, 2011-12-13
PTMA180402EL
PTMA180402FL
Confidential, Limited Internal Distribution
Pin # Function
S (fl ange, see Package Outlines) Source
1 Drain 1
2 FET_D
3 FET_G
4 RF In
5 Gate 1
6 Gate 2
7 NC
8 RF Out/D2
Package Specifications (cont.)
Pin Diagram for PTMA180402EL and PTMA180402FL
Packages H-33265-8 and H-34265-8
Find the latest and most complete information about products and packaging at the Infi neon Internet page
http://www.infi neon.com/rfpower
Edition 2011-12-13
Published by
Infi neon Technologies AG
81726 Munich, Germany
© 2006 Infi neon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics.
With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the
application of the device, Infi neon Technologies hereby disclaims any and all warranties and liabilities of any kind,
including without limitation, warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infi neon Technologies Offi ce (www.infi neon.com/rfpower).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in question,
please contact the nearest Infi neon Technologies Offi ce.
Infi neon Technologies components may be used in life-support devices or systems only with the express written approval of In-
fi neon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device
or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be
implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is
reasonable to assume that the health of the user or other persons may be endangered.
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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or +1 408 776 0600 International
PTMA180402EFL V1
Page Subjects (major changes since last revision)
Data Sheet – DRAFT ONLY 12 of 12 Rev. P09-B, 2011-12-13
Revision History: 2011-12-13 Data Sheet
Previous Version: 2009-08-31, Data Sheet
2 Separated the DC table into two stages, for clarity.