September 2004
Preliminary Information
Copyright © Alliance Semiconductor. All rights reserved.
®
AS9C25256M2036L
AS9C25128M2036L
2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
9/30/04; v.1.3 Alliance Semiconductor P. 1 of 30
Features
• True Dual-Port memory cells that allow simulta-
neous access of the same memory location
• Organisation: 262,144/131,072 x 36[1]
• Fully Synchronous, independent operation on
both ports
• Selectable Pipeline or Flow-Through output
mode
• Fast clock speeds in Pipeline output mode: 250
MHz operation (18Gbps bandwidth)
• Fast clock to data access: 2.8ns for Pipeline out-
put mode
• Asynchronous output enable control
•Fast OE access times: 2.8ns
• Double Cycle Deselect (DCD) for Pipeline Out-
put Mode
• 18/17[1]-bit counter with Increment, Hold and
Repeat features on each port
• Dual Chip enables on both ports for easy depth
expansion
• Interrupt and Collision Detection Features
• 2.5 V power supply for the core
• LVTTL compatible, selectable 3.3V or
2.5V power supply for I/Os, addresses,
clock and control signals on each port
• Snooze modes for each port for standby
operation
• 15mA typical standby current in power
down mode
• Available in 256-pin Ball Grid Array
(BGA), 208-pin Plastic Quad Flatpack
(PQFP) and 208-pin fine pitch Ball Grid
Array (fpBGA)
• Supports JTAG features compliant with
IEEE 1149.1
Selection guide
Feature -250 -200 -166 -133 Units
Minimum cycle time 4 5 6 7.5 ns
Maximum Pipeline clock frequency 250 200 166 133 MHz
Maximum Pipeline clock access time 2.8 3.4 3.6 4.2 ns
Maximum flow-through clock frequency 150 133 100 83 MHz
Maximum flow-through clock access time 6.5 7.5 10 12 ns
Maximum operating current TBD 350 300 260 mA
Maximum snooze mode current 18181818mA
Note:
1. AS9C25256M2036L/AS9C25128M2036L
AS9C25256M2036L
AS9C25128M2036L
9/30/04, v.1.3 Alliance Semiconductor P. 2 of 30
®
Dual port logic block diagram
Note:
1. Address A17 is a NC for AS9C25128M2036L
REGISTER BANK
Q
D
REGISTER BANK
Q
D
R/W Control
O/P Control
O/P Control
PL/FT
0
1
REGISTER BANK
QD
0
1
PL/FT
REGISTER BANK
Q
D
REGISTER BANK
Q
D
Mirror
Register
Increment
Logic
Address
Decoding
Interrupt/Collision
Detection
Logic/Registers
Snooze
Logic
JTAG
BE3A-BE0A
True Dual Port
Memory Array
256/128K X36
Address Counter A
CE0A
CE1A
R/WA
OEA
PL/FTA
RPTA
ADSA
INCA
A17[1]A-A0A
CE0A
CE1A
R/WA
PL/FTA
INTA
COLA
CLKA
ZZA
TDI
TDO
REGISTER BANK
QD
REGISTER BANK
QD
R/W Control
O/P Control O/P Control
PL/FT
0
1
REGISTER BANK
Q
D
0
1
PL/FT
REGISTER BANK
QD
REGISTER BANK
QD
Mirror
Register
Increment
Logic
Address
Decoding
Snooze
Logic
BE3B-BE0B
Address Counter B
CE0B
CE1B
R/WB
PL/FTB
RPTB
ADSB
INCB
A17[1]B-A0B
CE0B
CE1B
R/WB
PL/FTB
INTB
COLB
CLKB
ZZB
TMS
TRST
TCK
DQ35A-DQ0ADQ35B-DQ0B
QoutA<35:0> QoutB<35:0>
DinB<35:0>
DinA<35:0>
OPTB
CLKB
OPTA
CLKA
OEB
OPTAOPTB
AS9C25256M2036L
AS9C25128M2036L
9/30/04, v.1.3 Alliance Semiconductor P. 3 of 30
®
General Description
The AS9C25256M2036L/AS9C25128M2036L is a high-speed CMOS 9/4.5-Mbit synchronous Dual-Port Static Random Access Memory
device, organized as 262,144/131,072 x 36 bits. It incorporates a selectable Flow-Through/Pipeline output feature for user flexibility. Clock-
to-data valid time is 2.8ns at 250 MHz for “Pipeline output” mode of operation.
Each port contains an 18/17 bit linear burst counter on the input address register that can loop through the whole address sequence. After
externally loading the counter with the initial address, it can be Incremented or Held for the next cycle. A new address can also be Loaded or
the “Previous Loaded” address can be re-accessed (Repeated) using counter controls (More description to follow). The Registers on control,
data, and address inputs provide minimal setup and hold times.
The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. A particular port can write
to a certain location while another port is reading from the same location, but the validity of read data is not guaranteed. However, the
reading port is informed about the possible collision through its collision alert signal. The result of writing to the same location by more than
one port at the same time is undefined.
The Asynchronous Output Enable input pin allows asynchronous disabling of output buffers at any given time. The Byte Enable inputs
allow individual byte read/write operations (refer Byte Control Truth Table). An automatic power down feature, controlled by CE0 and CE1,
permits the on-chip circuitry of each port to enter a very low standby power mode.
AS9C25256M2036L/AS9C25128M2036L can support an operating voltage of either 3.3V or 2.5V on either or both ports, which is
controlled by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V. This device is available in 256-pin Ball Grid
Array (BGA), 208-pin fine pitch Ball Grid Array (fpBGA) and 208-pin Plastic Quad Flatpack (PQFP)
Address Counter
The AS9C25256M2036L/AS9C25128M2036L carries an internal 18/17 bit address counter for each port which can loop through the entire
memory array. The Address counter features are discussed below:
Load: Any required external address can be loaded on to the counter. This feature is similar to normal address load in conventional
memories.
Increment: The address counter has the capability to internally increment the address value, potentially covering the entire memory array.
Once the whole address space is completed, the counter will wrap around. The address counter is not initailized on Power-up, hence a known
location has to be loaded before Increment operation.
Hold: The value of the counter register can be held for an unlimited number of clock cycles by de-asserting ADS, INC, and RPT inputs.
Repeat: The previously loaded address (loaded using a valid Load operation) can be re-accessed by asserting RPT input. A separate 18/17
bit register called “Mirror register” is used to hold the last loaded address.This register is not initialized on Power-up, hence a known
location has to be loaded before Repeat operation (Refer Counter control truth table for details).
AS9C25256M2036L
AS9C25128M2036L
9/30/04, v.1.3 Alliance Semiconductor P. 4 of 30
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Ball Assignment - 256-ball BGA
Note:
1. Address A17 is a NC for AS9C25128M2036L
12345678910111213141516
A NC TDI NC A17[1]AA14AA11AA8ABE2ACE1AOEAINCAA5AA2AA0ANC NC A
B DQ18ANC TDO NC A15AA12AA9A BE3ACE0AR/WARPTAA4AA1AVDD DQ17ANC B
C DQ18BDQ19AVSS A16AA13AA10AA7ABE1ABE0ACLKAADSAA6AA3AOPTADQ17BDQ16AC
D DQ20BDQ19BDQ20APL/FTAVDDQAVDDQAVDDQBVDDQBVDDQAVDDQAVDDQBVDDQBVDD DQ15BDQ15ADQ16BD
E DQ21BDQ21ADQ22AVDDQAVDD VDD INTAVSS VSS VSS VDD VDD VDDQBDQ13ADQ14ADQ14BE
F DQ23ADQ22BDQ23BVDDQAVDD NC COLAVSS VSS VSS VSS VDD VDDQBDQ12BDQ13BDQ12AF
G DQ24BDQ24ADQ25AVDDQBVSS VSS VSS VSS VSS VSS VSS VSS VDDQADQ10ADQ11ADQ11BG
H DQ26ADQ25BDQ26BVDDQBVSS VSS VSS VSS VSS VSS VSS VSS VDDQADQ9BDQ9ADQ10BH
J DQ27ADQ28BDQ27BVDDQAZZBVSS VSS VSS VSS VSS VSS ZZAVDDQBDQ8BDQ7BDQ8AJ
K DQ29BDQ29ADQ28AVDDQAVSS VSS VSS VSS VSS VSS VSS VSS VDDQBDQ6BDQ6ADQ7AK
L DQ30ADQ31BDQ30BVDDQBVDD NC COLBVSS VSS VSS VSS VDD VDDQADQ5ADQ4BDQ5BL
M DQ32BDQ32ADQ31AVDDQBVDD VDD INTBVSS VSS VSS VDD VDD VDDQADQ3BDQ3ADQ4AM
N DQ33ADQ34BDQ33BPL/FTBVDDQBVDDQBVDDQAVDDQAVDDQBVDDQBVDDQAVDDQAVDD DQ2ADQ1BDQ2BN
P DQ35BDQ34ATMS A16BA13BA10BA7BBE1BBE0BCLKBADSBA6BA3BDQ0ADQ0BDQ1AP
R DQ35ANC TRST NC A15BA12BA9BBE3BCE0BR/WBRPTBA4BA1BOPTBNC NC R
TNCTCKNC
A17[1]BA14BA11BA8BBE2BCE1BOEBINCBA5BA2BA0BNC NC T
12345678910111213141516
AS9C25256M2036L/AS9C25128M2036L
B - 256
Top view
AS9C25256M2036L
AS9C25128M2036L
9/30/04, v.1.3 Alliance Semiconductor P. 5 of 30
®
Ball Assignment - 208-ball fpBGA
Note:
1. Address A17 is a NC for AS9C25128M2036L
1234567891011121314151617
A DQ19ADQ18AVSS TDO COLAA16AA12AA8ABE1AVDD CLKAINCAA4AA0AOPTADQ17AVSS A
B DQ20BVSS DQ18BTDI A17[1]AA13AA9ABE2ACE0AVSS ADSAA5AA1ANC VDDQBDQ16ADQ15BB
C VDDQADQ19BVDDQBPL/FTAINTAA14AA10ABE3ACE1AVSS R/WAA6AA2AVDD DQ16BDQ15AVSS C
D DQ22AVSS DQ21ADQ20AA15AA11AA7ABE0AVDD OEARPTAA3AVDD DQ17BVDDQADQ14ADQ14BD
E DQ23ADQ22BVDDQBDQ21BDQ12ADQ13BVSS DQ13AE
F VDDQADQ23BDQ24AVSS VSS DQ12BDQ11AVDDQBF
G DQ26AVSS DQ25ADQ24BDQ9AVDDQADQ10ADQ11BG
H VDD DQ26BVDDQBDQ25BVDD DQ9BVSS DQ10BH
J VDDQAVDD VSS ZZBZZAVDD VSS VDDQBJ
K DQ28BVSS DQ27BVSS DQ7BVDDQADQ8BVSS K
L DQ29BDQ28AVDDQBDQ27ADQ6BDQ7AVSS DQ8AL
M VDDQADQ29ADQ30BVSS VSS DQ6ADQ5BVDDQBM
N DQ31AVSS DQ31BDQ30ADQ3BVDDQADQ4BDQ5AN
P DQ32BDQ32AVDDQBDQ35BTRST A16BA12BA8BBE1BVDD CLKBINCBA4BDQ2ADQ3AVSS DQ4AP
R VSS DQ33ADQ34BTCK A17[1]BA13BA9BBE2BCE0BVSS ADSBA5BA1BNC VDDQADQ1BVDDQBR
T DQ33BDQ34AVDDQATMS INTBA14BA10BBE3BCE1BVSS R/WBA6BA2BVSS DQ0BVSS DQ2BT
U VSS DQ35APL/FTBCOLBA15BA11BA7BBE0BVDD OEBRPTBA3B A0BVDD OPTBDQ0ADQ1AU
1234567891011121314151617
AS9C25256M2036L/AS9C25128M2036L
F - 208
Top view
AS9C25256M2036L
AS9C25128M2036L
9/30/04, v.1.3 Alliance Semiconductor P. 6 of 30
®
Pin Assignment - 208-pin PQFP
Note:
1. Address A17 is a NC for AS9C25128M2036L
VSS
VDDQB
DQ18B
DQ18A
VSS
PL/FTA
COLA
INTA
NC
NC
A17[1]A
A16A
A15A
A14A
A13A
A12A
A11A
A10A
A9A
A8A
A7A
BE3A
BE2A
BE1A
BE0A
CE1A
CEOA
VDD
VDD
VSS
VSS
CLKA
OEA
R/WA
ADSA
INCA
RPTA
A6A
A5A
A4A
A3A
A2A
A1A
A0A
VDD
VDD
NC
OPTA
DQ17A
DQ17B
VDDQB
VSS
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
DQ19A1 156 DQ16A
DQ19B2 155 DQ16B
DQ20A3 154 DQ15A
DQ20B4 153 DQ15B
VDDQA5152 VSS
VSS 6 151 VDDQA
DQ21A7 150 DQ14A
DQ21B8 149 DQ14B
DQ22A9 148 DQ13A
DQ22B10 147 DQ13B
VDDQB11 146 VSS
VSS 12 145 VDDQB
DQ23A13 144 DQ12A
DQ23B14 143 DQ12B
DQ24A15 142 DQ11A
DQ24B16 141 DQ11B
VDDQA17 140 VSS
VSS 18 139 VDDQA
DQ25A19 138 DQ10A
DQ25B20 137 DQ10B
DQ26A21 136 DQ9A
DQ26B22 135 DQ9B
VDDQB23 134 VSS
ZZB24 133 VDDQB
VDD 25 132 VDD
VDD 26 131 VDD
VSS 27 130 VSS
VSS 28 129 VSS
VDDQA29 128 ZZA
VSS 30 127 VDDQA
DQ27B31 126 DQ8B
DQ27A32 125 DQ8A
DQ28B33 124 DQ7B
DQ28A34 123 DQ7A
VDDQB35 122 VSS
VSS 36 121 VDDQB
DQ29B37 120 DQ6B
DQ29A38 119 DQ6A
DQ30B39 118 DQ5B
DQ30A40 117 DQ5A
VDDQA41 116 VSS
VSS 42 115 VDDQA
DQ31B43 114 DQ4B
DQ31A44 113 DQ4A
DQ32B45 112 DQ3B
DQ32A46 111 DQ3A
VDDQB47 110 VSS
VSS 48 109 VDDQB
DQ33B49 108 DQ2B
DQ33A50 107 DQ2A
DQ34B51 106 DQ1B
DQ34A52 105 DQ1A
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
VSS
VDDQA
DQ35B
DQ35A
PL/FTB
NC
COLB
INTB
NC
NC
A17[1]B
A16B
A15B
A14B
A13B
A12B
A11B
A10B
A9B
A8B
A7B
BE3B
BE2B
BE1B
BE0B
CE1B
CE0B
VDD
VDD
VSS
VSS
CLKB
OEB
R/WB
ADSB
INCB
RPTB
A6B
A5B
A4B
A3B
A2B
A1B
A0B
VDD
VSS
NC
OPTB
DQ0A
DQ0B
VDDQA
VSS
AS9C25256M2036L/AS9C25128M2036L
P - 208
Top view
AS9C25256M2036L
AS9C25128M2036L
9/30/04, v.1.3 Alliance Semiconductor P. 7 of 30
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Signal description
Notes:
1. Subscript 'x' represents 'A' for Port A and 'B' for Port B.
2. OPTx,VDDQx and VDD must be set to appropriate operating levels before applying inputs on the I/Os and controls for that port.
3. OPTx = VDD (2.5V) implies that corresponding port's I/Os, addresses, clock, and controls will operate at 3.3V level and VDDQx must be supplied at 3.3V.
OPTx = VSS (0V) implies that corresponding port's I/Os, addresses, clock, and controls will operate at 2.5V level and VDDQx must be supplied at 2.5V.
Each port can independently operate on either of the VDDQ levels.
4. If unused JTAG inputs may be left unconnected.
5. JTAG is not supported in PQFP package.
6. Address A17 is a NC forAS9C25128M2036L
Signal
I/O Properties Description NotesPort A Port B
CLKA CLKB ICLOCK
Clock. Each port has an independent Clock input that can be of different frequencies.
All inputs except OEx and ZZx are synchronous to the corresponding port’s clock and
must meet setup and hold time about the rising edge of the clock.
1
A0A - A17A A0B - A17B I SYNC External Address. Sampled on the rising edge of corresponding port clock 6
DQ0A - DQ35ADQ0B - DQ35B I/O SYNC Bidirectional data pins
CE0A, CE1A CE0B, CE1B I SYNC Chip enable inputs. Active low and high, respectively. Sampled on the rising edge of
corresponding port clock.
R/WAR/WB I SYNC Read/Write enable. Drive this pin LOW to write to, or HIGH to Read from the
memory array.
BE0A - BE3A BE0B - BE3BI SYNC
Byte Enable Inputs. Active low. Asserting these signals enables Read and Write
operations to the corresponding bytes of the memory array. (Refer Byte Control
Truth Table)
ADSAADSB I SYNC Address Strobe Enable.Active low. Loads external address onto the counter. (Refer
Counter Control Truth Table)
INCAINCB I SYNC Address Counter Increment. Active low. Increments the counter value. (Refer
Counter Control Truth Table)
RPTARPTB I SYNC Address Counter Repeat. Active low. Reloads the counter with the previously loaded
external address.(Refer Counter Control Truth Table)
OEAOEB I ASYNC Asynchronous output enable. I/O pins are driven when the OE is low and the chip is
in Read mode. A high on OE tristates the I/O pins.
ZZAZZB I ASYNC Snooze Mode Input. Places the device in low power mode. Data is retained. This pin
has an internal pull-down and can be floating.
PL/FTAPL/FTB ISTATIC
Pipeline/Flow-Through Select. When low, enables single register flow-through
mode. When high, enables double register Pipeline mode. This pin has an internal
pull-up and can be left floating to operate in pipeline mode.
OPTAOPTB ISTATIC
VDDQx Option. OPTx selects the operating voltage levels for the I/Os, addresses,
clock, and controls on that port. This pin has an internal pull-up and can be left
floating to operate in 3.3V mode.
1,2,3
INTAINTB O SYNC Interrupt Flag. Used for message passing between two ports. (Refer Interrupt Logic
Truth Table)
COLACOLB O SYNC Collision Alert Flag. Used to indicate collision during simultaneous memory access
to the same location by both the ports (Refer Collision Detection Truth Table)
VDDQAVDDQB IPOWER
Power to I/O bus. Can be 3.3V or 2.5V depending on OPTx input. 1,2,3
VDD I POWER Power Inputs (To be connected to 2.5V Power supply) 2
VSS I GROUND Ground Inputs (To be connected to Ground supply)
TCK I CLOCK
(JTAG) JTAG Test Clock Input. All JTAG signals except TRST are synchronous to this clock. 4,5
TDI I SYNC
(JTAG)
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected
registers. 4,5
TDO O SYNC
(JTAG)
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is
normally tristated except when the captured data is shifted out of the JTAG TAP. 5
TMS I SYNC
(JTAG)
JTAG Test Mode Select Input. It controls the JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK. 4,5
TRST I
ASYNC
(JTAG) JTAG Test Reset Input. Asynchronous input used to initialize TAP controller. 4,5
AS9C25256M2036L
AS9C25128M2036L
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Byte control truth table[1,2,3,4,5]
Notes:
1. L = low, H = high
2. CE0 = L, CE1 = H (Chip in Select mode)
3. R/W = H for a Read operation, R/W = L for a Write operation
4. Byte 3 - DQ[35:27], Byte 2 - DQ[26:18], Byte 1 - DQ[17:9], Byte 0 - DQ[8:0]
5. More than one byte enable may be simultaneously asserted
Read/write control truth table[1,4]
Notes:
1. L = low, H = high, X = don't care
2. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H)
3. BEn refers to any one of the 4 byte controls [n= 3,2,1 or 0] and DQn refers to the corresponding Byte
4. Snooze de-asserted (ZZ=L)
5. True in flow-through mode. For Pipeline mode there will be a 1 cycle latency [refer timing diagrams]
6. For a write command issued before the completion of a read command, OE must be HIGH before the input data setup time and held HIGH throughout the input data hold time.
7. All DQs are tristated on power-up
8. OE should be asserted (OE = L) (Refer Read timing waveform)
9. In pipeline mode the DQs are HighZ-ed in the same cycle if R/W=L
Counter control truth table[1,2,5,6]
Notes:
1. L = low, H = high, X = don't care
2. Cycle can be Read, Write or Deselect (Controlled by appropriate setting of R/W, CE0, CE1 and BEn)
3. ADS, INC, RPT are independent of all other memory controls including R/W, CE0,CE1 and BEn (i.e Counter works independent of R/W, CE0,CE1 and BEn)
4. The 'Mirror register' used for the Repeat operation is loaded with External address during every valid ADS access. “Am” refers to the mirror register content.
5. Clock to the counter is disabled during Snooze mode (True for both ports).
6. The counter and the mirror registers are not initialized on Power-up (refer Counter description).
BE3BE2BE1BE0CLK Mode
H H H H L to H All Bytes Deselected - NOP
H H H L L to H Read or Write Byte 0
H H L H L to H Read or Write Byte 1
H L H H L to H Read or Write Byte 2
L H H H L to H Read or Write Byte 3
CE[2] R/W BEn[3] CLK Operation DQn[0:8][3,7]
H X X L to H Chip Deselect Hi-Z[5,9]
L X H L to H Byte Deselect Hi-Z[5,9]
L L L L to H Byte Write Din[6]
L H L L to H Byte Read Qout[5,8]
CLK ADS[3] INC[3] RPT[3]
External
Address
Previous
Address
Accessed
Mirror
Register
Content[4]
Address
Accessed Operation
L to H L X H An X An An Load[4]
L to H H L H X An Am An + 1 Increment
L to H H H H X An Am An Hold
L to H X X L X X Am Am Repeat
AS9C25256M2036L
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Package Thermal Resistance
Notes:
1. This parameter is sampled.
Capacitance[1] (TA = +25 °C, F = 1.0 Mhz)[2]
Notes:
1. Sampled, not 100% tested
2. TA stands for 'Ambient temperature'.
3. L = 0V; H = 3V
Absolute maximum ratings[1]
Notes:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating for extended
periods may affect reliability.
Description Conditions Symbol Typical Units
Thermal Resistance (junction to
ambient)[1] Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
BGA θJA TBD °C/W
fpBGA θJA TBD °C/W
PQFP θJA TBD °C/W
Thermal Resistance (junction to
top of case)[1] θJC TBD °C/W
Parameter Symbol Signals Test Condition[3]
B G A
(Max)
f p B G A
(Max)
P Q F P
(Max) Unit
Input Capacitance CIN
Address and
Control pins VIN = L to H or H to L TBD TBD TBD pF
Output Capacitance COUT Flag Output pins VOUT = L to H or H to L TBD TBD TBD pF
I/O Capacitance CI/O I/O pins VI/O = L to H or H to L TBD TBD TBD pF
Rating
Parameter Symbol Min Max Unit
Core supply voltage relative to VSS VDD -0.5 3.6 V
I/O supply voltage relative to VSS VDDQ -0.3 3.9 V
Input and I/O voltage relative to VSS VIN -0.3 VDDQ + 0.3 V
Power Dissipation PD-TBDW
Short circuit output current IOUT -TBD mA
Storage Temperature TSTG -65 150 °C
Storage Temperature under Bias TBIAS -55 125 °C
Junction Temperature TJN -TBD°C
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Recommended operating Temperature
Recommended operating conditions
Notes:
1. OPT pin for a given port must be set to VSS(0V) to operate at VDDQ = 2.5V levels on the I/Os, addresses, clock and controls of that port.
2. OPT pin for a given port must be set to VDD(2.5V) to operate at VDDQ = 3.3V levels on the I/Os, addresses, clock and controls of that port.
DC Electrical Characteristics (VDD = 2.5 V ± 100 mV)
Notes:
1. Outputs disabled (High-Z condition).
Grade Ambient Temperature (TA)
Commercial 0°C to 70°C
Industrial -40°C to 85°C
VDDQ = 2.5V[1] VDDQ = 3.3V[2]
Parameter Symbol Min Typ Max Min Typ Max Unit
Core Supply Voltage VDD 2.4 2.5 2.6 2.4 2.5 2.6 V
I/O supply Voltage VDDQ 2.4 2.5 2.6 3.15 3.3 3.45 V
Ground VSS 000000 V
VDDQ = 2.5V VDDQ = 3.3V
Parameter Symbol Test Conditions Min Max Test Conditions Min Max Units
Input Leakage
Current |ILI|VDDQ = Max;
0V < VIN < VDDQ -2
VDDQ = Max;
0V < VIN < VDDQ -2µA
PL/FT and ZZ Input
Leakage Current |ILI|VDD = Max;
0V < VIN < VDD -2
VDD = Max;
0V < VIN < VDD -2µA
Output Leakage
Current[1] |ILO|OE>=VIH;
0V < VOUT < VDDQ -2OE>=VIH;
0V < VOUT < VDDQ -2µA
Input high (logic 1)
voltage
(Address, Control,
Clock & Data Inputs)
VIH - 1.7 VDDQ + 0.1V - 2 VDDQ + 0.15V V
Input high voltage
(ZZ,OPT,PL/FT) VIH - VDD - 0.2V VDD + 0.1V - VDD - 0.2V VDD + 0.1V V
Input low (logic 0)
voltage (Address,
Control, Clock &
Data Inputs)
VIL - -0.3 0.7 - -0.3 0.8 V
Input low voltage
(ZZ,OPT,PL/FT)VIL - -0.3 0.2 - -0.3 0.2 V
Output low voltage VOL
IOL = +2mA;
VDDQ = Min -0.4
IOL = +4mA;
VDDQ = Min -0.4V
Output high voltage VOH
IOH = -2mA;
VDDQ = Min 2.0 - IOH = -4mA;
VDDQ = Min 2.4 - V
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®
IDD operating conditions and maximum limits[4] (VDD = 2.5 V ± 100 mV)
Notes:
1. f=fMax implies address and controls (except OE) are cycling at maximum clock frequency using AC test conditions (Refer AC test conditions).
2. f = 0 implies address and controls are static. Corresponding current numbers indicated are true for both CMOS (VIN > VDDQ - 0.2V or VIN < 0.2V)
and TTL (VIN > VIH or VIN < VIL) level inputs.
3. CEA and CEB are internal signals (CEx = L implies CE0x < VIL and CE1x > VIH, CEx = H implies CE0x > VIH or CE1x < VIL).
4. Subscript 'x' represents 'A' for Port A and 'B' for Port B.
5. “A” and “B” are interchangeable.
Parameter Symbol Test Conditions -250 -200 -166 -133 Units
Typ Max Typ Max Typ Max Typ Max
Operating current
(Both ports active)
Pipeline mode --
(PL/FT > VIH)ICC
Both ports enabled (CEA = CEB = L[3]),
Outputs disabled (IOUT = 0mA), ZZA = ZZB < VIL,
f=fMax[1]
TBD TBD TBD 350 TBD 300 TBD 260 mA
Operating current
(Both ports active)
Flow-through mode
(PL/FT < VIL)
TBD TBD TBD TBD TBD TBD TBD TBD mA
Standby current
(Both ports) ISB1
Both ports disabled (CEA = CEB = H),
ZZA = ZZB < VIL,
f=fMax[1]
TBD TBD TBD 105 TBD 90 TBD 80 mA
Standby current
(One port) ISB2
One port enabled (CEA = L and CEB = H)[5],
Active port's outputs disabled, ZZA = ZZB < VIL,
f=fMax[1]
TBD TBD TBD 265 TBD 225 TBD 190 mA
Full standby current
(Both ports) ISB3
Both ports disabled (CEA = CEB = H),
ZZA = ZZB < VIL,
f=0[2]
20 25 20 25 20 25 20 25 mA
Full standby current
(One port) ISB4
One port in Snooze (ZZA > VIH, ZZB < VIL, and
CEB = L)[5],
Active port's outputs disabled,
f=fMax[1]
TBD TBD TBD 265 TBD 225 TBD 190 mA
Snooze mode
current IZZ
Both ports in Snooze (ZZA = ZZB > VIH),
f=fMax[1] 15 18 15 18 15 18 15 18 mA
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®
AC timing characteristics[1,2,5,6] (VDD = 2.5 ± 100mV)
Notes:
1. All timings are same for both ports.
2. These values are valid for either level of VDDQ (2.5V/3.3V)
3. A particular port will operate in Pipeline output mode if PL/FT = VDD and in flow-through output mode if PL/FT = 0V. Each port can independently operate in any of these
modes.
4. Output Enable (OE) is an asynchronous input.
5. PL/FT and OPT should be treated as DC signals and should reach steady state before normal operation.
6. Refer AC Test Conditions to view the test conditions used for these measurements.
7. This parameter has to be taken care to avoid collision during simultaneous memory access of the same location.
8. To avoid bus contention, at a given voltage and temperature tLZC is more than tHZC (True in both Pipeline and flow-through output mode).
Parameter Symbol -250 -200 -166 -133 Unit Notes
Min. Max. Min. Max. Min. Max. Min. Max.
Clock
Cycle Time (Pipeline) tCYCP 4-5-6-7.5 -ns 3
Clock High Pulse Width (Pipeline) tCHP 1.7 -2-2.4 -3-ns 3
Clock Low Pulse Width (Pipeline) tCLP 1.7 -2-2.4 -3-ns 3
Cycle Time (Flow-Through) tCYCF 6.5 -7.5 -10 -12 -ns 3
Clock High Pulse Width (Flow-Through) tCHF 1.7 -2-2.4 -3-ns 3
Clock Low Pulse Width (Flow-Through) tCLF 1.7 -2-2.4 -3-ns 3
Output
Clock access time (Pipeline) tCDP -2.8 -3.4 -3.6 -4.2 ns 3
Output Data Hold from Clock High (Pipeline) tOHP 1-1-1-1-ns
Clock High to Output Low-Z (Pipeline) tLZCP 1-1-1-1-ns 3,8
Clock High to Output High-Z (Pipeline) tHZCP 12.813.413.614.2ns 3,8
Clock access time (Flow-Through) tCDF -6.5 -7.5 -10 -12 ns 3
Output Data Hold from Clock High (Flow-Through) tOHF 1-1-1-1-ns
Clock High to Output Low-Z (Flow-Through) tLZCF 1-1-1-1-ns 3,8
Clock High to Output High-Z (Flow-Through) tHZCF 12.813.413.614.2ns 3,8
Output Enable to Data Valid tOE -2.8 -3.4 -3.6 -4.2 ns 4
Output Enable Low to Output Low-Z tLZOE 1-1-1-1-ns 4
Output Enable High to Output High-Z tHZOE 12.813.413.614.2ns 4
Setup
Address Setup to Clock High tAS 1.2 -1.5 -1.7 -1.8 -ns
Chip Enable Setup to Clock High tCES 1.2 -1.5 -1.7 -1.8 -ns
Byte Enable Setup to Clock High tBS 1.2 -1.5 -1.7 -1.8 -ns
R/W Setup to Clock High tWS 1.2 -1.5 -1.7 -1.8 -ns
Input Data Setup to Clock High tDS 1.2 -1.5 -1.7 1.8 -ns
ADS Setup to Clock High tADSS 1.2 -1.5 -1.7 -1.8 -ns
INC Setup to Clock High tINCS 1.2 -1.5 -1.7 -1.8 -ns
RPT Setup to Clock High tRPTS 1.2 -1.5 -1.7 -1.8 -ns
Hold
Address Hold from Clock High tAH 0.3 -0.5 -0.5 -0.5 -ns
Chip Enable Hold from Clock High tCEH 0.3 -0.5 -0.5 -0.5 -ns
Byte Enable Hold from Clock High tBH 0.3 -0.5 -0.5 -0.5 -ns
R/W Hold from Clock High tWH 0.3 -0.5 -0.5 -0.5 -ns
Input Data Hold from Clock High tDH 0.3 -0.5 -0.5 -0.5 -ns
ADS Hold from Clock High tADSH 0.3 -0.5 -0.5 -0.5 -ns
INC Hold from Clock High tINCH 0.3 -0.5 -0.5 -0.5 -ns
RPT Hold from Clock High tRPTH 0.3 -0.5 -0.5 -0.5 -ns
Flag
Interrupt Flag Set Time tSINT -6-6-6-7ns
Interrupt Flag Reset Time tRINT -6-6-6-7ns
Collision Flag Set Time tSCOL -2.8 -3.4 -3.6 -4.2 ns
Collision Flag Reset Time tRCOL -2.8 -3.4 -3.6 -4.2 ns
Port-to-Port Delay
Clock-to-Clock Delay tCCO 3.0 -3.5 -4-5-ns 7
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®
Timing waveform of read cycle[7]
Notes:
1. Both Flow-through and Pipeline Outputs indicated. A particular port is configured in Flow-through mode if PL/FT for that port is driven low,
and in Pipeline mode if PL/FT is driven high or left unconnected.
2. Parameters tCYC, tCH and tCL are different in Flow-through and Pipeline modes of operation (Refer AC Timing characteristics).
3. CE is an internal signal.CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H).
Timings indicated for CE hold good for CE0 and CE1
4. BEn refers to any one of the 4 byte controls [n= 3,2,1 or 0] and DATA OUT refers to the corresponding Byte.
5. Counter set in “Load” mode (ADS = L,INC = X,RPT = H).
6. OE is an asynchronous input.
7. All timings are similar for both ports.
8. Read with Byte disabled. Data is not read out.Bus in High-Z condition.
CLK
CE
[3]
ADDRESS
[5]
OE
[6]
BEn
[4]
R/W
[Pipeline Mode]
t
CEH
t
CES
Q1
A1 A2
t
CYC
[2]
t
CL
t
CH
t
AS
t
AH
t
BS
t
BH
A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
Q10
Read
(A1)
t
CDP
t
OHP
t
HZCP
t
LZCP
t
HZOE
t
LZOE
DATA OUT
[1]
Q1 Q2 Q8
Read
(A2) Dsel Read[8]
(A4) Dsel Read
(A6) Read
(A7)
Read
(A8) Dsel Read
(A10) Dsel Read
(A12)
Don’t care Undefined
t
OE
t
WS
t
WH
t
LZOE
Q6
[Pipeline Mode]
Q1 Q10
t
CDF
t
OHF
t
HZCF
t
LZCF
t
HZOE
t
LZOE
Q1 Q2 Q8
t
OE
t
LZOE
Q6
OE
[6]
[Flow-through Mode]
[Flow-through Mode]
DATA OUT
[1]
Q12
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®
Timing wave form read/write cycle[7]
Notes:
1. Both Flow-through and Pipeline Inputs/Outputs indicated.A particular port is configured in Flow-through mode if PL/FT for that port is driven low,
and in Pipeline mode if PL/FT is driven high or left unconnected.
2. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline modes of operation.(Refer AC Timing characteristics)
3. CE is an internal signal.CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H).
Timings indicated for CE hold good for CE0 and CE1
4. BEn refers to any one of the 4 byte controls [n= 3,2,1 or 0] and DATA OUT refers to the corresponding Byte.
5. Counter set in “Load” mode (ADS = L,INC = X,RPT = H).
6. OE is an asynchronous input.
7. All timings are similar for both ports.
8. Invalid write. Memory Content of the selected location may get corrupted and should be re-written before future readback.
9. Write (A11) is invalid in Pipeline mode and Write (A8) is invalid in Flow-through mode. Memory Content of the selected location may get corrupted and should be re-written
before future readback.
CLK
CE
[3]
ADDRESS
[5]
OE
[6]
BEn
[4]
R/W
DATA IN
[1]
DATA IN
[1]
[Flow-through Mode]
[Pipeline Mode]
DATA OUT
[1]
DATA OUT
[1]
t
CEH
t
CES
D3 D6
Q1 Q2
Q1
A1 A2
t
CYC
[2]
t
CL
t
CH
t
AS
t
AH
t
BS
t
BH
t
WS
t
WH
t
CDP
t
LZCP
t
CDF
t
LZCF
t
OHF
t
HZCF
t
HZOE
t
DS
t
DH
t
DH
t
DS
A3 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
D8
Q9
D3 D6 D11
Q4 Q7 Q9
Read
(A1)
Read
(A2)
Write[8] Write
(A3) (A5)
Read Read Read
(A7)
Write[9]
(A8)
Read
(A9) Dsel Write[9]
(A11)
(A4)
Write
(A6)
[Pipeline Mode]
[Flow-through Mode]
t
HZCP
t
HZOE
Don’t care Undefined
OE
[6]
[Flow-through Mode]
[Pipeline Mode]
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®
Timing waveform of address counter[6]
Notes:
1. Both Flow-through and Pipeline Outputs indicated. A particular port is configured in Flow-through mode if PL/FT for that port is driven low,
and in Pipeline mode if PL/FT is driven high or left unconnected.
2. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline modes of operation (Refer AC Timing characteristics).
3. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H).
Timings indicated for CE hold good for CE0 and CE1.
4. These cycles indicate that Counter works independent of all memory controls including R/W,CE and BEn.
5. If a Hold operation is performed for a Read access, the Data-out is held valid for the subsequent clock cycle also.
6. All timings are similar for both ports.
CLK
CE
[3]
R/W
[Pipeline Mode]
DATA OUT
[1]
[Flow-through Mode]
t
CEH
t
CES
t
CYC[2]
t
CL
t
CH
Write
(A1)
DATA OUT
[1]
Incr
A1
ADDRESS
A1 A1+1 A1+2 A1+2 A1+1 A1+2 A1+2 A2 A2+1 A2+1 A2
A1
D1
D1+1 D1+2 D1+2
Q1 Q1+1 Q3 Q4
Q1 Q1+1
Q4
DATA IN
RPT
INC
ADS
ADDRESS
INTERNAL
Hold Rept
t
WH
t
WS
t
AS
t
AH
t
ADSS
t
ADSH
t
INCS
t
INCH
t
RPTS
t
RPTH
t
DS
t
DH
t
HZCF
t
OHF
t
CDF
t
LZCF
t
LZCP
t
CDP
t
OHP
t
HZCP
A2
Q1+2
Q1+2
Don’t care Undefined
[4]
[5]
[5]
Load Incr
WriteWrite
Write Read Read Read Read
Incr Incr Hold Load
(A2)
Dsel Dsel Dsel Dsel
Rept
Hold
Incr
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Mailbox Interrupts
The AS9C25256M2036L/AS9C25128M2036L has an Inbuilt Mailbox Logic that can be used for communication between the two ports.
One memory location is assigned as mail box (message center) for each port. The location 3FFFE (HEX) is assigned as the message center
for Port A and 3FFFF (HEX) for Port B (IFFFE and IFFFF for AS9C25128M2036L). The port A interrupt flag (INTA) is asserted when the
port B writes to memory location 3FFFE (HEX) (IFFFE for AS9C25128M2036L). The port A clears the interrupt flag by reading the address
location 3FFFE (HEX) (IFFFE for AS9C25128M2036L). Likewise, the port B interrupt flag (INTB) is asserted when the port A writes to
memory location 3FFFF (HEX)(IFFFF for AS9C25128M2036L) and to clear the interrupt flag (INTB), the port B must read the memory
location 3FFFF (IFFFF for AS9C25128M2036L) (Refer Interrupt Logic Truth Table).
The interrupt flag is asserted in a flow-through mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flow-
through mode (i.e., it follows the clock edge of the reading port). Each port can read the other port’s mailbox without de-asserting the
interrupt and each port can write to its own mailbox without asserting the interrupt. If an application does not require message passing, INT
pins can be ignored.
Interrupt logic truth table[1,4]
Notes:
1. L = low, H = high, X = don't care
2. CEx is an internal signal ('x' = 'A' or 'B'). CEx = H implies 'Chip is Deselected' (CE0x = H or CE1x =L), CEx = L implies 'Chip is Selected' (CE0x = L and CE1x =H)
3. Address specified here is the internal address (refer Counter control truth table).
4. Both Interrupt Flags are De-asserted on power-up.
5. Address A17 is a NC for AS9C25128M2036L, hence Interrupt addresses are IFFFF and IFFFE
CLKAR/WACEA[2] A17A-A0A[3,5] CLKBR/WBCEB[2] A17B-A0B[3,5] INTAINTBFunction
L to H L L 3FFFF L to H X X X X L Assert Port B Interrupt Flag
L to H X X X L to H H L 3FFFF X H De-assert Port B Interrupt Flag
L to H X X X L to H L L 3FFFE L X Assert Port A Interrupt Flag
L to H H L 3FFFE L to H X X X H X De-assert Port A Interrupt Flag
AS9C25256M2036L
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®
Interrupt timing wave form[2]
Notes:
1. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline mode of operation and can be different for different ports (Refer AC Timing characteristics).
2. Chip Selected (CE0 = L and CE1 =H). True for both ports.
3. Address indicated is the Internal Address used and is dependent on the Address counter control inputs for that cycle.
4. 3FFFF (IFFFF for AS9C25128M2036L) is the Mailbox for port B and 3FFFE (IFFFE for AS9C25128M2036L) is the Mailbox for port A.
5. “Aa” and “Ab” refer to any other valid address other than 3FFFF or 3FFFE (IFFFF or IFFFE for AS9C25128M2036L).
t
CYC[1]
t
CH[1]
t
CL[1]
CLK
A
R/W
A[2]
t
WS
t
WH
t
AS
t
AH
INT
A
ADDRESS
A[3]
CLK
B
R/W
B[2]
ADDRESS
B[3]
INT
B
3FFFF
t
WH
t
WS
t
CYC[1]
t
CH[1]
t
CL[1]
t
SINT
t
RINT
t
SINT
t
RINT
t
AH
t
AS
3FFFF 3FFFE
3FFFF 3FFFE 3FFFE
Don’t care
[4]
[4]
Aa Aa Aa Aa
Ab Ab Ab Ab
[5]
[5]
Aa
Ab
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Collision detection
Three different cases of collisions can be listed depending on the type of access from two ports:
Simultaneous Read: A true dual-ported memory cell allows data to be read simultaneously from both ports of the device. Hence no data is
corrupted, lost, or incorrectly output, and none of the collision alert flags is asserted.
Simultaneous Write: When both ports are writing simultaneously to the same location, both write operations would fail. Therefore, the
collision flag is asserted on both ports.
Simultaneous Read and Write: When one port is writing and the other port is reading from the same location in the memory, the data
written will be valid. However, the read operation would fail and hence the reading port's collision flag is asserted.
The alert flag (COLx) is asserted on the 3rd (for both pipe-lined and flow-through output mode) rising clock edge of the affected port
following the collision, and remains low for one cycle. On continuous collisions (one or both ports writing during each access), the collision
alert flag will be asserted and de-asserted every alternate cycle.
Collision detection truth table[1,2,4]
Notes:
1. L = low, H = high, X = don't care
2. Chip Selected (CE0 = L and CE1 =H). True for both ports. Collision flag is not affected if any one or both ports are deselected.
3. “MATCH” indicates that internal addresses of both the ports are the same (refer Counter control truth table).
4. Both Collision Flags are De-asserted on power-up.
CLKAR/WACLKBR/WBPort address[3] COLACOLBFunction
L to H H L to H H MATCH H H Both ports reading. Not a valid collision. No
collision flag asserted on either port.
L to H H L to H L MATCH L H Port A reading, Port B writing. Valid collision.
Collision flag asserted on port A.
L to H L L to H H MATCH H L Port B reading, Port A writing. Valid collision.
Collision flag asserted on port B.
L to H L L to H L MATCH L L Both ports writing. Valid collision. Collision
flag asserted on both ports.
L to H L L to H H NO MATCH H H No match. No collision flag asserted on either
port.
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Collision timing waveform[2]
Notes:
1. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline mode of operation and can be different for different ports (Refer AC Timing characteristics).
2. Chip Selected (CE0 = L and CE1 =H). True for both ports.
3. Address indicated is the Internal Address used and is dependent on the Address counter control inputs for that cycle.
4. “Am” refers to matched address. “Aa” and “Ab” refer to any other valid address.
5. During address collision the data validity is guaranteed only if tCCO is greater than the minimum specified (Refer AC timing characteristics).
CLK
A
ADDRESS
A[3]
R/W
A
Am Aa Am Aa Aa Am Aa Am Am Am Am Aa
COL
A
CLK
B
ADDRESS
B[3]
R/W
B
Am Ab Am Ab Ab Am Ab Am Am Am Am Ab
COL
B
t
CH[1]
t
CYC[1]
t
CL[1]
t
WS
t
AS
t
AH
t
CH[1]
t
CL[1]
t
CYC[1]
t
AS
t
AH
t
WS
t
WH
t
CCO
t
SCOL
t
RCOL
t
SCOL
t
RCOL
t
WH
Don’t care
[5]
[4]
[4]
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Depth and Width expansion
AS9C25256M2036L/AS9C25128M2036L has two chipselects (one active high and other active low) for simple depth expansion. This
permits easy upgrade from 256/128K depth to 512K/256K depth without extra logic. Two such parts can also be combined to obtain an
expanded width of 72 bits or wider.
Notes:
1. A<0:17> for AS9C25256M2036L, A<0:16> for AS9C25128M2036L
2. A<0:18> for AS9C25256M2036L, A<0:17> for AS9C25128M2036L
3. A<18> for AS9C25256M2036L, A<17> for AS9C25128M2036L
Timing waveform of multi device read[4,5,6]
Notes:
1. Parameters tCYC, tCH and tCL are different in Flow-through and Pipeline mode of operation (Refer AC Timing characteristics).
2. A<0:17> for AS9C25256M2036L, A<0:16> for AS9C25128M2036L
3. A<18> for AS9C25256M2036L, A<17> for AS9C25128M2036L
4. Refer to the above block diagram for the assumed setup.
5. One Bank is assumed to have two AS9C25256M2036L/AS9C25128M2036Ls combined to have an expanded width of 72 bits. Two such Banks are used for depth expansion.
6. All BEn's = L, Counter set in “Load” mode (ADS = L, INC = X, RPT = H), OE =L.
RPT
INC
ADS
OE
BE<0:3>
R/W
CLK
CE1
CE0
RPT
INC
ADS
OE
BE<0:3>
R/W
CLK
CE1
CE0
A<0:17>
[1]
DQ<0:35>
A<0:17>
[1]
DQ<0:35>
A<0:17>
[1]
A<0:17>
[1]
DQ<0:35>
DQ<36:71>
A<0:17>
[1]
A<0:17>
[1]
DQ<0:35>
DQ<36:71>
A<18>
[3]
A<18>
[3]
Clock
Clock
Data
Address
Controller
Microprocessor
BANK 1 BANK 0
256/128Kx36
DPSRAM
256/128Kx36
DPSRAM
DQ<0:71>
A<0:18>
[2]
t
CH
t
CL
t
CYC[1]
CLK
R/W
A[18]
[3]
DATA OUT [0:71]
[Pipeline Mode]
(BANK 0)
(BANK 1)
DATA OUT [0:71]
A[0:17]
[2]
[Flow-through Mode]
[Pipeline Mode]
DATA OUT [0:71]
(BANK 0)
DATA OUT [0:71]
[Flow-through Mode]
(BANK 1)
t
AS
t
AH
t
WS
t
WH
A1 A2 A3 A4 A5 A6 A7 A8
t
CDP
t
OHP
t
HZCP
t
LZCP
Q1 Q2 Q4
Q3
t
CDP
t
OHP
t
HZCP
t
LZCP
t
CDF
t
OHF
t
HZCF
t
LZCF
Q4
Q1 Q2
Q3
t
CDF
t
OHF
t
HZCF
Q5 Q6
Read
(Bank0) (Bank0)
Read
(Bank1)
Read Read Read Read
(Bank0) (Bank1) (Bank1)
Read
(Bank0)
t
LZCF
Q5 Q6
Don’t care Undefined
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Snooze mode
Snooze mode is a low-current, power-down mode in which the corresponding port is deselected and its current is reduced to a
very low value. Both ports are equipped with independent SNOOZE inputs (ZZ). During Snooze mode, all inputs of the port
except ZZ are internally disabled and all its Outputs go to High-Z.
ZZ is an asynchronous, active HIGH input that causes the selected port to enter Snooze mode. If both ports go into Snooze mode,
the device is deselected and current is reduced to IZZ. When ZZA and ZZB become a logic HIGH, IZZ is guaranteed after the
setup time tSCZZ is met.
Any READ or WRITE operation pending when the port enters Snooze mode is not guaranteed to complete. Therefore, Snooze
mode must not be initiated until valid pending operations are completed. Similarly during the time tRCZZ, when the port is
transitioning out of snooze mode, only DESELECT cycles should be given.
Snooze mode electrical characteristics
Snooze mode timing waveform[1,3]
Notes:
1. During Snooze mode, all dynamic inputs are disabled (except JTAG inputs). During JTAG operations, ZZx must be held Low in order to capture the parallel inputs of the bound-
ary scan register. All static inputs (i.e. PL/FTx,OPTx) and ZZx themselves are not affected during snooze mode.
2. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H).
3. All timings are same for Port A and Port B.
4. Minimum of two deselect cycles should be given before asserting snooze and minimum of two deselect cycles should be given after de-asserting snooze to guarantee data
integrity.
5. Select cycles indicated before and after Snooze are Read cycles. They can also be Write cycles.
Description Conditions Symbol Min Max Units
SNOOZE MODE Current ZZA = ZZB >= VIH IZZ 15 18 mA
ZZ active to input ignored tSCZZ - 2 cycle
ZZ inactive to input sampled tRCZZ 2 - cycle
ZZ active to enter Snooze Current tSIZZ - 2 cycle
ZZ inactive to exit Snooze Current tRIZZ 0 - cycle
CLK
t
CH
t
CYC
t
CL
Don’t care
t
CEH
t
CES
t
SIZZ
t
RIZZ
IZZ
t
SCZZ
ZZ setup cycles
t
RCZZ
ZZ recovery cycles
High-Z
CE
[2,4]
ZZ
I
Supply
OUTPUTS
[5]
INPUTS
(Except ZZ)
(Qout)
t
HZC
t
LZC
Undefined
Val i d Valid
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AC test conditions
Input Pulse Level (Address and Controls) GND to 3.0V/GND to 2.4V
Input Pulse Levels (I/Os) GND to 3.0V/GND to 2.4V
Input Rise/Fall Times 2V/ns
Input Timing Reference Levels 1.5V/1.25V
Output Reference levels 1.5V/1.25V
Output Load (for tLZC, tHZC, tLZOE, tHZOE)Fig. C
Output Load (for all other measurements) Fig. B
Thevenin equivalent:
GND 10%
90% 90%
10%
+3.0/2.4 V
Figure A: Input Waveform
D
OUT
Z0 = 50 Ω50 Ω
V
L
= 1.5/1.25 V
+3.3/2.5 V;
5 pF*
GND
Figure B: Output Load (A)
Figure C: Output Load (B)
* Including scope and jig capacitance
10 pF*
319
Ω /
1667
Ω
353
Ω /
1538
Ω
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IEEE 1149.1 Serial boundary scan (JTAG)
The SRAM incorporates a serial boundary scan Test Access Port (TAP). All JTAG pins operate using JEDEC standard 2.5V I/O logic levels.
In order to operate the device without using the JTAG feature, all JTAG pins may be left unconnected. On power-up, the device will start in
a reset state which will not interfere with normal device operation.
TAP Controller block diagram
Note:
1. x = 149
JTAG timing waveform
Selection
Circuitry
Selection
Circuitry
31 30 29 012
...
Boundary Scan Register1
Identification Register
Bypass Register
Instruction Register
x[1] 012
012
0
.. . ..
TDI
TMS
TCK
TDO
TAP Controller
3
TEST CLK
TRST
t
JCYC
TCK
TMS/TDI
TDO
t
JCH
t
JCL
t
JIS
t
JIH
t
JOH
t
JCD
t
JRS
t
JRR
Don’t care Undefined
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TAP AC electrical characteristics[2]
Notes:
1. tJCS and tJCH refer to the setup and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in the figure TAP AC output load equivalent.
TAP AC test conditions & output load equivalent
TAP DC electrical characteristics and operating conditions (VDD=2.5V ± 100 mV)
Description Symbol Min Max Units
Clock
Clock cycle time tJCYC 100 - ns
Clock frequency fJTAG - 10 MHz
Clock high time tJCH 40 - ns
Clock low time tJCL 40 - ns
Output Times
TCK low to TDO unknown tJOH 0 - ns
TCK low to TDO valid tJCD -20ns
Setup Times
TMS/TDI setup tJIS 10 - ns
Capture setup tJCS[1] 10 - ns
Hold Times
TMS/TDI hold tJIH 10 - ns
Capture hold tJCH[1] 10 - ns
Reset Times
JTAG Reset tJRS 50 - ns
JTAG Reset Recovery tJRR 50 - ns
Description Symbol Conditions Min Max Units
Input high (logic 1) voltage VIH 1.7 VDD + 0.3 V
Input low (logic 0) voltage VIL -0.3 0.7 V
Input leakage current |ILI| VDD = Max; 0V < VIN < VDD 0 10 µA
Output leakage current |ILO| Outputs disabled, 0V < VOUT < VDDQ (DQx)0 10µA
Output low voltage VOLC I
OLC = 100µA 0.2 V
Output low voltage VOLT I
OLT = 2mA 0.7 V
Output high voltage VOHC I
OHC = -100µA 2.1 V
Output high voltage VOHT IOHT = -2mA 1.7 V
TDO
50Ω
ZO=50Ω
1.25V
20pF
Input pulse levels Vss to 2.5V
Input rise and fall times 1V/ns
Input timing reference levels 1.25V
Output reference levels 1.25V
Test load termination supply voltage 1.25V
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Identification register definitions
Scan register sizes
Instruction codes
Instruction field Value Description
Revision number (31:28) TBD Version Number
Device depth (27:12) TBD ALSC part number
JEDEC ID code (11:1) 00001010010 Manufacturer Identity Code
(ALSC)
Indicator Bit (0) 1 ID Register presence indicator
Register name Bit size
Instruction Register (IR) 4
Bypass Register (BYR) 1
Identification Register (IDR) 32
Boundary Scan Register (BSR) 150
Instruction Code Description Selected Reg
EXTEST 0000 Forces contents of the BSR onto the device outputs. BSR
SAMPLE/PRELOAD 0001 Samples the I/O ring contents. Preloads test data into the
BSR. BSR
IDCODE 0010 Loads the IDR with the vendor ID code and places the
register between TDI and TDO. IDR
CLAMP 0011 Forces contents of the BSR onto the device outputs. BYR
HIGHZ 0100 Forces all device 2-state and 3-state outputs to High-Z. BYR
RESERVED 0101 - 1110 Reserved states. Do not use. BYR
BYPASS 1111 Places the BYR between TDI and TDO. BYR
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Package Diagram: 256-ball Ball Grid Array (BGA)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
A1 corner index
All measurements are in
mm.
Min Typ Max
A1.00
B16.95 17.00 17.05
C15.00
D16.95 17.00 17.05
E15.00
F0.36
G0.35 0.50
H1.60
I0.40 0.50 0.60
J0.70
0.35 ~ 0.50
1.60 MAX
0.36
0.70
0.35 Z
Top View Bottom View
Side View
A
B
C
A
E
D
D
FH
G
0.20 Z
+
12345678910111213141516
++
+
+
+
+
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
/ 0.50±0.10 (256X)
Ø 0.15
Ø 0.25 Z
Z
XY
Detail of Solder Ball
I
M
M
oo
oo
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
J
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Package Diagram: 208-ball fine pitch Ball Grid Array (fpBGA)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
ooooooooooooooooo
ooooooooooooooooo
ooooooooooooooooo
ooooooooooooooooo
oooo oooo
oooo oooo
oooo oooo
oooo oooo
oooo oooo
oooo oooo
oooo oooo
oooo oooo
oooo oooo
ooooooooooooooooo
ooooooooooooooooo
ooooooooooooooooo
ooooooooooooooooo
ooooooooooooooooo
/ 0.45±0.05 (208X)
Ø 0.08
Ø 0.15
A1 corner index
All measurements are in
mm.
Min Typ Max
A0.80
B14.95 15.00 15.05
C12.80
D14.95 15.00 15.05
E12.80
F0.26
G0.25 0.40
H1.40
I0.40 0.45 0.50
J0.70
Z
Z
XY
0.25 ~ 0.40
1.40 MAX
0.26
0.70
0.20 Z
Top View Bottom View
Side View Detail of Solder Ball
A
B
C
A
E
D
D
FH
G I
0.15 Z
M
M
+
1234567891011121314151617
o
++
+
+
+
+
17
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
o
oo
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
J
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Package Diagram: 208-pin Plastic Quad Flat Pack (PQFP)
PQFP
Min Typ Max
A1 0.25
A2 3.20 3.32 3.60
b0.17 0.20 0.27
c0.11 0.15 0.23
D28.00 nominal
E28.00 nominal
e0.50 nominal
Hd 31.20 nominal
He 31.20 nominal
L0.73 0.88 1.03
L1 1.60 nominal
α0° 7°
Dimensions in millimeters
A1 A2
L1
L
c
He E
Hd
D
b
e
α
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Ordering Information
Part Numbering Guide
1. Alliance Semiconductor prefix
2. Speciality Memory
3. Operating Voltage: 25 - VDD = 2.5V
4. Device depth: 256 - 256K; 128 - 128K
5. M20 - Multiport - 2port, SSRAM, DCD
6. I/O width - 36
7. I/O interface: L - LVTTL
8. Clock speed (MHz)
9. Package Type: P - PQFP, B - BGA, F - fpBGA
10. Operating Temperature: C - Commercial (00C to 700C); I -Industrial (-400C to 850C)
Package & Width -250 -200 -166 -133
256K X 36
BGA X 36 AS9C25256M2036L - 250BC AS9C25256M2036L - 200BC AS9C25256M2036L -166BC AS9C25256M2036L - 133BC
AS9C25256M2036L - 250BI AS9C25256M2036L - 200BI AS9C25256M2036L - 166BI AS9C25256M2036L - 133BI
fpBGA X 36 AS9C25256M2036L - 250FC AS9C25256M2036L - 200FC AS9C25256M2036L - 166FC AS9C25256M2036L - 133FC
AS9C25256M2036L - 250FI AS9C25256M2036L - 200FI AS9C25256M2036L - 166FI AS9C25256M2036L - 133FI
PQFP X 36 AS9C25256M2036L - 250PC AS9C25256M2036L - 200PC AS9C25256M2036L - 166PC AS9C25256M2036L - 133PC
AS9C25256M2036L - 250PI AS9C25256M2036L - 200PI AS9C25256M2036L - 166PI AS9C25256M2036L - 133PI
128K X 36
BGA X 36 AS9C25128M2036L - 250BC AS9C25128M2036L - 200BC AS9C25128M2036L -166BC AS9C25128M2036L - 133BC
AS9C25128M2036L - 250BI AS9C25128M2036L - 200BI AS9C25128M2036L - 166BI AS9C25128M2036L - 133BI
fpBGA X 36 AS9C25128M2036L - 250FC AS9C25128M2036L - 200FC AS9C25128M2036L - 166FC AS9C25128M2036L - 133FC
AS9C25128M2036L - 250FI AS9C25128M2036L - 200FI AS9C25128M2036L - 166FI AS9C25128M2036L - 133FI
PQFP X 36 AS9C25128M2036L - 250PC AS9C25128M2036L - 200PC AS9C25128M2036L - 166PC AS9C25128M2036L - 133PC
AS9C25128M2036L - 250PI AS9C25128M2036L - 200PI AS9C25128M2036L - 166PI AS9C25128M2036L - 133PI
AS 9C 25 256 M20 36 L-XXX P or B or F C/I
1234567 8 9 10
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Preliminary Information
Part Number: AS9C25256M2036L
AS9C25128M2036L
Document Version: v.1.3
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
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AS9C25256M2036L
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®
