Features * 300 MHz - 333 MHz To Be Confirmed-PC603e Processor Core Implementing the * * * * * * * * PowerPC(R) Architecture 32-bit PCI Interface Operating at up to 66 MHz Memory Controller Offering SDRAM Support up to 133 MHz Operation, Support up to 2 GB General Purpose I/O and ROM Interface Support Two Channel DMA Controller that Supports Chaining Messaging Unit with I2O Messaging Support Capability Industry-standard I2C Interface Programmable Interrupt Controller with Multiple Timers and Counters 16550-compatible DUART Description The PC8245 combines a PC603e core microprocessor with a PCI bridge. The PCI support on the PC8245 will allow system designers to rapidly design systems using peripherals already designed for PCI and the other standard interfaces. The PC8245 also integrates a high-performance memory controller which supports various types of ROM and SDRAM. The PC8245 is the second of a family of products that provides system-level support for industry standard interfaces with a PC603e processor core. Integrated Processor Family PC8245 Product Specification This document describes pertinent electrical and physical characteristics of the PC8245. For functional characteristics of the processor, refer to the Motorola's documentation "MPC8245 Integrated Processor User's Manual" (MPC8245UM/D). Screening/Quality/Packaging This product is manufactured in full compliance with: * Upscreening based upon Atmel standards * Military temperature range (Tc = -55C, Tc = +125C) * Core power supply: 2.0 100 mV * * I/O power supply: 3.3V 0.3V 352 Tape Ball Grid Array (TBGA) TP suffix TBGA352 Tape Ball Grid Array Rev. 2171D-HIREL-06/04 General Description Block Diagram The PC8245 integrated processor is comprised of a peripheral logic block and a 32-bit superscalar PowerPC 603e core, as shown in Figure 1. Figure 1. Block Diagram PC8245 (64-bit) Two-instruction fetch Processor Core Block Additional features: * Prog I/O with Watchpoint * JTAG/COP Interface * Power Management Processor PLL Branch Processing Instruction Unit Unit (BPU) (64-bit) Two-instruction dispatch System Register Unit (SRU) Floating Point Unit (FPU) Load/Store Unit (LSU) Integer Unit (IU) Data MMU 64-bit Instruction MMU 16-Kbyte Instruction Cache 16-Kbyte Data Cache Peripheral Logic Bus Peripheral Logic Block Message Unit (with I2O) DMA Controller I2C 5 IRQs/ 16 Serial Interrupts Address (32-bit) Data (64-bit) Data Path ECC Controller Central Control Unit Memory Controller Performance Monitor I2C Controller Memory/ROM/PortX Address and Control SDRAM_SYNC_IN DLL Peripheral Logic PLL EPIC Interrupt Controller /Timers Data Bus (32- or 64-bit) with 8-bit Parity or ECC SDRAM Clocks PCI_SYNC_IN Configuration Registers DUART PCI Bus Interface Unit Watchpoint Facility Address Translator PCI Arbiter 32-bit Five Request/ PCI Interface Grant Pairs 2 Fanout Buffers PCI Bus Clocks Oscillator Input PC8245 2171D-HIREL-06/04 PC8245 The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART), memory controller, DMA controller, EPIC interrupt controller, a message unit (and I2O interface), and a I2C inteface controller. The processor core is a full-featured, high-performance processor with floating-point support, memory management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power management features. The integration reduces the overall packaging requirements and the number of discrete devices required for an embedded system. The PC8245 contains an internal peripheral logic bus that interfaces the processor core to the peripheral logic. The core can operate at a variety of frequencies, allowing the designer to trade-off performance for power consumption. The processor core is clocked from a separate PLL, which is referenced to the peripheral logic PLL. This allows the microprocessor and the peripheral logic block to operate at different frequencies, while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus (depending on memory data bus width) and a 32-bit address bus along with control signals that enable the interface between the processor and peripheral logic to be optimized for performance. PCI accesses to the PC8245 memory space are passed to the processor bus for snooping when snoop mode is enabled. The processor core and peripheral logic are general-purpose in order to serve a variety of embedded applications. The PC8245 can be used as either a PCI host or PCI agent controller. General Parameters The following list provides a summary of the general parameters of the PC8245: Technology0.25 m CMOS, five-layer metal Die size 49.2 mm2 Transistor count4.5 million Logic designFully static Packages Surface-mount 352 tape ball grid array (TBGA) Core power supply:2.0V 100 mV DC (nominal; see Table "Recommended Operating Conditions" on page 12 for details I/O power supply3.0 to 3.6V DC Features Major features of the PC8245 are as follows: * Processor core - High-performance, superscalar processor core - Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit (LSU), system register unit (SRU), and a branch processing unit (BPU) - 16-Kbyte instruction cache - 16-Kbyte data cache - Lockable L1 caches -- entire cache or on a per-way basis up to three of four ways - Dynamic power management -- supports 60x nap, doze, and sleep modes 3 2171D-HIREL-06/04 * Peripheral logic Peripheral Logic Bus - Supports various operating frequencies and bus divider ratios - 32-bit address bus, 64-bit data bus - Supports full memory coherency - Decoupled address and data buses for pipelining of peripheral logic bus accesses - Store gathering on peripheral logic bus-to-PCI writes Memory interface - Supports up to 2 Gbytes of SDRAM memory - High-bandwidth data bus (32- or 64-bit) to SDRAM - Programmable timing supporting SDRAM - Supports 1 to 8 banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices - Write buffering for PCI and processor accesses - Supports normal parity, read-modify-write (RMW), or ECC - Data-path buffering between memory interface and processor - Low-voltage TTL logic (LVTTL) interfaces - 272 Mbytes of base and extended ROM/Flash/PortX space - Base ROM space supports 8-bit data path or same size as the SDRAM data path (32- or 64-bit) - Extended ROM space supports 8-, 16-, 32-bit gathering data path, 32- or 64bit (wide) data path - PortX: 8-, 16-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with programmable address strobe timing, data ready input signal (DRDY), and 4 chip selects 32-bit PCI interface - Operates up to 66 MHz - PCI 2.2-compliant - PCI 5.0V tolerance - Support for dual address cycle (DAC) for 64-bit PCI addressing (master only) - Support for PCI locked accesses to memory - Support for accesses to PCI memory, I/O, and configuration spaces - Selectable big- or little-endian operation - Store gathering of processor-to-PCI write and PCI-to-memory write accesses - Memory prefetching of PCI read accesses - Selectable hardware-enforced coherency - PCI bus arbitration unit (five request/grant pairs) - PCI agent mode capability - Address translation with two inbound and outbound units (ATU) - Some internal configuration registers accessible from PCI Two-channel integrated DMA controller (writes to ROM/PortX not supported) 4 PC8245 2171D-HIREL-06/04 PC8245 - Supports direct mode or chaining mode (automatic linking of DMA transfers) - Supports scatter gathering -- read or write discontinuous memory - 64-byte transfer queue per channel - Interrupt on completed segment, chain, and error - Local-to-local memory - PCI-to-PCI memory - Local-to-PCI memory - PCI memory-to-local memory Message unit - Two doorbell registers - Two inbound and two outbound messaging registers - I2O message interface Two-wire interface controller with full master/slave support that accepts broadcast messages Embedded programmable interrupt controller (EPIC) - Five hardware interrupts (IRQs) or 16 serial interrupts - Four programmable timers with cascade Two (dual) universal asynchronous receiver/transmitters (UARTs) Integrated PCI bus and SDRAM clock generation Programmable PCI bus and memory interface output drivers * System level performance monitor facility * Debug features - Memory attribute and PCI attribute signals - Debug address signals - MIV signal: marks valid address and data bus cycles on the memory bus - Programmable input and output signals with watchpoint capability - Error injection/capture on data path - IEEE 1149.1 (JTAG)/test interface 5 2171D-HIREL-06/04 Pinout Listing Table 1 provides the pinout listing for the PC8245, 352 TBGA package. Table 1. PC8245 Pinout Listing Signal Name Pin Number Type Power Supply Output Driver Type Notes PCI Interface Signals C/BE[3:0] P25 K23 F23 A25 I/O OVDD DRV_PCI (6)(15) DEVSEL H26 I/O3 OVDD DRV_PCI (8)(15) FRAME J24 I/O OVDD DRV_PCI (8)(15) IRDY K25 I/O OVDD DRV_PCI (8)(15) LOCK J26 Input OVDD - (8) AD[31:0] V25 U25 U26 U24 U23 T25 T26 R25 R26 N26 N25 N23 M26 M25 L25 L26 F24 E26 E25 E23 D26 D25 C26 A26 B26 A24 B24 D19 B23 B22 D22 C22 I/O3 OVDD DRV_PCI (6)(15) PAR G25 I/O OVDD DRV_PCI (15) GNT[3:0] W25 W24 W23 V26 Output OVDD DRV_PCI (6)(15) GNT4/DA5 W26 Output OVDD DRV_PCI (7)(14)(15) REQ[3:0] Y25 AA26 AA25 AB26 Input OVDD - (6)(12) REQ4/DA4 Y26 I/O OVDD - (12)(14) PERR G26 I/O OVDD DRV_PCI (8)(15)(18) SERR F26 I/O OVDD DRV_PCI (8)(15)(16) STOP H25 I/O OVDD DRV_PCI (8)(15) TRDY K26 I/O OVDD DRV_PCI (8)(15) INTA AC26 Output OVDD DRV_PCI (15)(16) IDSEL P26 Input OVDD - MDL[0:31] AD17 AE17 AE15 AF15 AC14 AE13 AF13 AF12 AF11 AF10 AF9 AD8 AF8 AF7 AF6 AE5 B1 A1 A3 A4 A5 A6 A7 D7 A8 B8 A10 D10 A12 B11 B12 A14 I/O GVDD DRV_STD_MEM (5)(6) MDH[0:31] AC17 AF16 AE16 AE14 AF14 AC13 AE12 AE11 AE10 AE9 AE8 AC7 AE7 AE6 AF5 AC5 E4 A2 B3 D4 B4 B5 D6 C6 B7 C9 A9 B10 A11 A13 B13 A15 I/O GVDD DRV_STD_MEM (6) DQM[0:7] AB1 AB2 K3 K2 AC1 AC2 K1 J1 Output GVDD DRV_MEM_CTRL (6) CS[0:7] Y4 AA3 AA4 AC4 M2 L2 M1 L1 Output GVDD DRV_MEM_CTRL (6) FOE H1 I/O GVDD DRV_MEM_CTRL (3)(4) RCS0 N4 Output GVDD DRV_MEM_CTRL (3)(4) RCS1 N2 Output GVDD DRV_MEM_CTRL Memory Interface Signals 6 PC8245 2171D-HIREL-06/04 PC8245 Table 1. PC8245 Pinout Listing (Continued) Type Power Supply Output Driver Type Notes AF20 I/O OVDD - (10)(14) RCS3/TRIG_OUT AC18 Output GVDD DRV_MEM_CTRL (14) SDMA[1:0] W1 W2 I/O GVDD DRV_MEM_CTRL (3)(4)(6) SDMA[11:2] N1 R1 R2 T1 T2 U4 U2 U1 V1 V3 Output GVDD DRV_MEM_CTRL (6) DRDY B20 Input OVDD - (9)(14) SDMA12/SRESET B16 I/O GVDD DRV_MEM_CTRL (10)(14) SDMA13/TBEN B14 I/O GVDD DRV_MEM_CTRL (10)(14) SDMA14/CHKSTOP_IN D14 I/O GVDD DRV_MEM_CTRL (10)(14) SDBA1 P1 Output GVDD DRV_MEM_CTRL SDBA0 P2 Output GVDD DRV_MEM_CTRL PAR[0:7] AF3 AE3 G4 E2 AE4 AF4 D2 C2 I/O GVDD DRV_STD_MEM (6) SDRAS AD1 Output GVDD DRV_MEM_CTRL (3) SDCAS AD2 Output GVDD DRV_MEM_CTRL (3) CKE H2 Output GVDD DRV_MEM_CTRL (3)(4) WE AA1 Output GVDD DRV_MEM_CTRL AS Y1 Output GVDD DRV_MEM_CTRL IRQ0/S_INT C19 Input OVDD - IRQ1/S_CLK B21 I/O OVDD DRV_PCI IRQ2/S_RST AC22 I/O OVDD DRV_PCI IRQ_3/S_FRAME AE24 I/O OVDD DRV_PCI IRQ_4/ L_INT A23 I/O OVDD DRV_PCI Signal Name Pin Number RCS2/TRIG_IN (3)(4) EPIC Control Signals Two-wire Interface Control Signals SDA AE20 I/O OVDD DRV_STD_MEM (10)(16) SCL AF21 I/O OVDD DRV_STD_MEM (10)(16) SOUT1/PCI_CLK0 AC25 Output GVDD DRV_PCI_CLK (13)(14) SIN1/PCI_CLK1 AB25 I/O GVDD DRV_PCI_CLK (13)(14) SOUT2/RTS1/PCI_CLK2 AE26 Output GVDD DRV_PCI_CLK (13)(14) SIN2/CTS1/PCI_CLK3 AF25 I/O GVDD DRV_PCI_CLK (13)(14) PCI_CLK0/SOUT1 AC25 Output GVDD DRV_PCI_CLK (13)(14) PCI_CLK1/SIN1 AB25 I/O GVDD DRV_PCI_CLK (13)(14) PCI_CLK2/RTS1/SOUT2 AE26 Output GVDD DRV_PCI_CLK (13)(14) PCI_CLK3/CTS1/SIN2 AF25 I/O GVDD DRV_PCI_CLK (13)(14) DUART Control Signals Clock Out Signals 7 2171D-HIREL-06/04 Table 1. PC8245 Pinout Listing (Continued) Type Power Supply Output Driver Type Notes AF26 Output GVDD DRV_PCI_CLK (13)(14) PCI_SYNC_OUT AD25 Output GVDD DRV_PCI_CLK PCI_SYNC_IN AB23 Input GVDD - SDRAM_CLK [0:3] D1 G1 G2 E1 Output GVDD DRV_MEM_CTRL or DRV_MEM_CLK (6)(21) SDRAM_SYNC_OUT C1 Output GVDD DRV_MEM_CTRL or DRV_MEM_CLK (21) SDRAM_SYNC_IN H3 Input GVDD - CKO/DA1 B15 Output OVDD DRV_STD_MEM (14) OSC_IN AD21 Input OVDD - (19) HRST_CTRL A20 Input OVDD - HRST_CPU A19 Input OVDD - MCP A17 Output OVDD DRV_STD_MEM NMI D16 Input OVDD - SMI A18 Input OVDD - (10) SRESET/SDMA12 B16 I/O GVDD DRV_MEM_CTRL (10)(14) TBEN/SDMA13 B14 I/O GVDD DRV_MEM_CTRL (10)(14) QACK/DA0 F2 Output OVDD DRV_STD_MEM (3)(4)(14) CHKSTOP_IN/SDMA14 D14 I/O GVDD DRV_MEM_CTRL (10)(14) TRIG_IN/RCS2 AF20 I/O OVDD - (10)(14) TRIG_OUT/RCS3 AC18 Output GVDD DRV_MEM_CTRL (14) MAA[0:2] AF2 AF1 AE1 Output GVDD DRV_STD_MEM (3)(4)(6) MIV A16 Output OVDD - (24) PMAA[0:1] AD18 AF18 Output OVDD DRV_STD_MEM (3)(4)(6)(15) PMAA[2] AE19 Output OVDD DRV_STD_MEM (4)(6)(15) I/O OVDD DRV_STD_MEM (6)(14)(20) Signal Name Pin Number PCI_CLK4/DA3 Miscellaneous Signals (3)(4)(17) Test/Configuration Signals PLL_CFG[0:4]/DA[10:6] A22 B19 A21 B18 B17 TEST0 AD22 Input OVDD - (1)(9) DRDY B20 Input OVDD - (9)(10)(14) RTC Y2 Input GVDD - (11) TCK AF22 Input OVDD - (9)(12) TDI AF23 Input OVDD - (9)(12) TDO AC21 Output OVDD - (24) TMS AE22 Input OVDD - (9)(12) TRST AE23 Input OVDD - (9)(12) 8 PC8245 2171D-HIREL-06/04 PC8245 Table 1. PC8245 Pinout Listing (Continued) Type Power Supply Output Driver Type AA2 AA23 AC12 AC15 AC24 AC3 AC6 AC9 AD11 AD14 AD16 AD19 AD23 AD4 AE18 AE2 AE21 AE25 B2 B25 B6 B9 C11 C13 C16 C23 C4 C8 D12 D15 D18 D21 D24 D3 F25 F4 H24 J25 J4 L24 L3 M23 M4 N24 P3 R23 R4 T24 T3 V2 V23 W3 Ground - - LVDD AC20 AC23 D20 D23 G23 P23 Y23 Reference voltage 3.3V, 5.0V LVDD - GVDD AB3 AB4 AC10 AC11 AC8 AD10 AD13 AD15 AD3 AD5 AD7 C10 C12 C3 C5 C7 D13 D5 D9 E3 G3 H4 K4 L4 N3 P4 R3 U3 V4 Y3 Power for Memory Drivers 3.3V GVDD - OVDD AB24 AD20 AD24 C14 C20 C24 E24 G24 J23 K24 M24 P24 T23 Y24 PCI/Stnd 3.3V OVDD - VDD AA24 AC16 AC19 AD12 AD6 AD9 C15 C18 C21 D11 D8 F3 H23 J3 L23 M3 R24 T4 V24 W4 Power for Core 1.8/2.0V VDD - (22) No Connect D17 - - - (23) AVDD C17 Power for PLL (CPU Core Logic) 1.8/2.0V AVDD - (22) AVDD2 AF24 Power for PLL (Peripheral Logic) 1.8/2.0V AVDD2 - (22) Signal Name Pin Number Notes Power and Ground Signals GND Debug/Manufacturing Pins DA0/QACK F2 Output OVDD DRV_STD_MEM (3)(4)(14) DA1/CKO B15 Output OVDD DRV_STD_MEM (14) DA2 C25 Output OVDD DRV_PCI (2) DA3/PCI_CLK4 AF26 Output GVDD DRV_PCI_CLK (14) DA4/REQ4 Y26 I/O OVDD - (12)(14) DA5/GNT4 W26 Output OVDD DRV_PCI (7)(14)(15) DA[10:6]/PLL_CFG[0:4] A22 B19 A21 B18 B17 I/O OVDD DRV_STD_MEM (6)(14)(20) DA[11] AD26 Output OVDD DRV_PCI (2) DA[12:13] AF17 AF19 Output OVDD DRV_STD_MEM (2)(6) DRV_MEM_CTRL (2)(6) DA[14:15] F1 J2 Output GVDD Notes: 1. Place a pull-up resistor of 120 or less on the TEST0 pin. 2. Treat these pins as no connects (NC) unless using debug address functionality. 9 2171D-HIREL-06/04 3. This pin has an internal pull-up resistor which is enabled only when the PC8245 is in the reset state. The value of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is read into configuration bits during reset. 4. This pin is a reset configuration pin. 5. DL[0] is a reset configuration pin and has an internal pull-up resistor which is enabled only when the PC8245 is in the reset state. The value of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is read into configuration bits during reset. 6. Multi-pin signals such as AD[31:0] or MDL[0:31] have their physical package pin numbers listed in order, corresponding to the signal names. Example: AD0 is on pin C22, AD1 is on pin D22, ..., AD31 is on pin V25. 7. GNT4 is a reset configuration pin and has an internal pull-up resistor which is enabled only when the PC8245 is in the reset state. 8. Recommend a weak pull-up resistor (2 k - 10 k) be placed on this PCI control pin to LVDD. 9. VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 4 on page 23. 10. Recommend a weak pull-up resistor (2 k - 10 k) be placed on this pin to OVDD. 11. Recommend a weak pull-up resistor (2 k - 10 k) be placed on this pin to GVDD. 12. This pin has an internal pull-up resistor which is enabled at all times. The value of the internal pull-up resistor is not guaranteed, but is sufficient to prevent unused inputs from floating. 13. External PCI clocking source or fan-out buffer may be required for system if using the PC8245 DUART functionality since PCI_CLK[0:3] are not available in DUART mode. Only PCI_CLK4 is available in DUART mode. 14. This pin is a multiplexed signal and appears more than once in this table. 15. This pin is affected by programmable PCI_HOLD_DEL parameter. 16. This pin is an open drain signal. 17. This pin can be programmed to be driven (default) or can be programmed (in PMCR2) to be open drain. 18. This pin is a sustained three-state pin as defined by the PCI Local Bus Specification. 19. OSC_IN utilizes the 3.3V PCI interface driver which is 5V tolerant, see Table "Recommended Operating Conditions" on page 12 for details. 20. PLL_CFG[0:4] signals are sampled a few clocks after the negation of HRST_CPU and HRST_CTRL. 21. SDRAM_CLK[0:3] and SDRAM_SYNC_OUT signals use DRV_MEM_CTRL for chip Rev 1.1 (A). These signals use DRV_MEM_CLK for chip Rev 1.2 (B). 22. The 266 and 300 MHz part offerings can be ran at a source voltage of 1.8 100 mV or 2.0 100 mV. Note that source voltage should be 2.0 100 mV for 333- and 350-MHz parts. 23. This pin was formally LAVDD on the PC8240. It is a no connect on the PC8245. This should not pose a problem when replacing an PC8240 with an PC8245. 24. The driver capability of this pin is hardwired to 40 and cannot be changed. 10 PC8245 2171D-HIREL-06/04 PC8245 Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the PC8245. DC Electrical Characteristics This section covers ratings, conditions, and other characteristics. Absolute Maximum Ratings The tables in this section describe the PC8245 DC electrical characteristics. Following table provides the absolute maximum ratings. Absolute Maximum Ratings Symbol Characteristic(1) VDD Value Unit Supply Voltage - CPU Core and Peripheral Logic -0.3 to 2.1 V GVDD Supply Voltage - Memory Bus Drivers -0.3 to 3.6 V OVDD Supply Voltage - PCI and Standard I/O Buffers -0.3 to 3.6 V AVDD/AVDD2 Supply Voltage - PLLs -0.3 to 2.1 V LVDD Supply Voltage - PCI Reference -0.3 to 5.4 V -0.3 to 3.6 V -65 to 150 C (2) VIN Input Voltage TSTG Storage Temperature Range Notes: 1. Functional and tested operating conditions are given in Table. Absolute maximum ratings are stress ratings only and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. PCI inputs with LVDD = 5V 5% V DC may be correspondingly stressed at voltages exceeding LVDD + 0.5V DC. 11 2171D-HIREL-06/04 Recommended Operating Conditions Following table provides the recommended operating conditions for the PC8245. Recommended Operating Conditions Symbol Characteristic(1)(6) VDD Supply Voltage OVDD Recommended Value Unit Notes 2.0 100 mV V (5) I/O Buffer supply for PCI and Standard 3.3 0.3 V (5) GVDD Supply Voltages for Memory Bus Drivers 3.3 5 % V (7) AVDD CPU PLL Supply Voltage 2.0 100 mV V (5) AVDD2 PLL Supply Voltage - Peripheral Logic 2.0 100 mV V (5) 5.0 5 % V (2)(8)(9) LVDD PCI Reference 3.3 0.3 V (3)(8)(9) 0 to 3.6 or 5.75 V (2)(3) VIN Input Voltage 0 to 3.6 V (4) Tc Tcase -55 to 125 C PCI Inputs Notes: 12 All Other Inputs 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 2. PCI pins are designed to withstand LVDD + 0.5V DC when LVDD is connected to a 5.0V DC power supply. 3. PCI pins are designed to withstand LVDD + 0.5V DC when LVDD is connected to a 3.3V DC power supply. 4. Caution: Input voltage (VIN) must not be greater than the supply voltage (VDD/AVDD/AVDD2) by more than 2.5V at all times including during power-on reset. Input voltage (VIN) must not be greater than GVDD/OVDD by more than 0.6V at all times including during power-on reset. 5. Caution: OVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8V at any time including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 6. Caution: VDD/AVDD/AVDD2 must not exceed OVDD by more than 0.6V at any time including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 7. Caution: GVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8V at any time including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 8. Caution: LVDD must not exceed VDD/AVDD/AVDD2 by more than 5.4V at any time including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 9. Caution: LVDD must not exceed OVDD by more than 3.0V at any time including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. PC8245 2171D-HIREL-06/04 PC8245 Figure 2 shows supply voltage sequencing and separation cautions. DC Power Supply Voltage Figure 2. Supply Voltage Sequencing and Separation Cautions LVdd at 5V 5V See Note (1) 10 9 10 3.3V GVdd_OVdd/(LVdd at 3.3V ----) 9 2.0V 7 6.8 Vdd/AVdd/AVdd2 Vdd Stable 100 s PLL Relock Time (3) 0 Voltage Regulator Delay (2) Power Supply Ramp Up (2) HRST_CPU & HRST_CTRL asserted 255 external memory Clock cycles (3) Time Reset Configuration Pins 9 external memory clock cycles setup time (4) HRST_CPU, HRST_CTRL Notes: Maximum rise time must be less than one external memory clock cycle (5) VM = 1.4V 1. Numbers associated with waveform separations correspond to caution numbers listed in Table "Recommended Operating Conditions" on page 12. 2. Refer to section for additional information. 3. Refer to Table 7 on page 25 for additional information on PLL Relock and reset signal assertion timing requirements. 4. Refer to Table 9 on page 31 for additional information on reset configuration pin setup timing requirements. 5. HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle for the device to be in the non-reset state. 13 2171D-HIREL-06/04 Figure 3 shows the undershoot and overshoot voltage of the memory interface of the PC8245. Figure 3. Overshoot/Undershoot Voltage 4V GVdd_OVvdd + 5% VIH VIL GVdd_OVdd GND/GNDRING GND/GNDRING - 0.3V Not to exceed 10% of tSDRAM_CLK GND/GNDRING Q - 1.0V Thermal Characteristics Table 2 provides the package thermal characteristics for the PC8245. For further information, see Section "Thermal Management Information" on page 15. Table 2. Thermal Characterization Data Symbol Characteristic RJA Junction-to-ambient natural convection (Single-layer board--1s) RJMA Junction-to-ambient natural convection (Four-layer board--2s2p)(1)(3) RJMA RJMA Junction-to-ambient (at 200 ft/min) (Single-layer board--1s) RJB Junction-to-Board RJC Junction-to-Case(5) JT Notes: 14 (6) Junction-to-package top (natural convection) Value Unit 16.1 C/W 12.0 C/W (1)(3) 11.6 C/W (1)(3) 9.0 C/W 4.8 C/W 1.8 C/W 1.0 C/W Junction-to-ambient (at 200 ft/min)(Four layer board--2s2p) (4) (1)(2) 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate used for case temperature. 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as PsiJT. PC8245 2171D-HIREL-06/04 PC8245 Thermal Management Information This section provides thermal management information for the tape ball grid array (TBGA) package for air-cooled applications. Depending on the application environment and the operating frequency, heat sinks may be required to maintain junction temperature within specifications. Proper thermal control design is primarily dependent upon the system-level design: the heat sink, airflow, and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods: adhesive, spring clip to holes in the printed-circuit board or package, or mounting clip and screw assembly; see Figure 4. Figure 4. Package Exploded Cross-Sectional View with Several Heat Sink Options Heat Sink TBGA Package Heat Sink Clip Adhesive or Thermal Interface Material Die Printed-Circuit Board Option Figure 5 depicts the die junction-to-ambient thermal resistance for four typical cases: * A heat sink is not attached to the TBGA package and there exists a high board-level thermal loading from adjacent components. * A heat sink is not attached to the TBGA package and there exists a low board-level thermal loading from adjacent components. * A heat sink (for example, ChipCoolers #HTS255-P) is attached to the TBGA package and there exists high board-level thermal loading from adjacent components. * A heat sink (for example, ChipCoolers #HTS255-P) is attached to the TBGA package and there exists low board-level thermal loading from adjacent components. 15 2171D-HIREL-06/04 Figure 5. Die Junction-to-Ambient Resistance Die Junction-to-Ambient Thermal Resistance (C/W) 18 No heat sink and high thermal board-level loading of adjacent components No heat sink and low thermal board-level loading of adjacent components Attached heat sink and high thermal board-level loading of adjacent components Attached heat sink and low thermal board-level loading of adjacent components 16 14 12 10 8 6 4 2 0 0.5 1 1.5 2 2.5 Airflow Velocity (m/s) 16 PC8245 2171D-HIREL-06/04 PC8245 The board designer can choose between several types of heat sinks to place on the PC8245. There are several commercially available heat sinks for the PC8245 provided by the following vendors: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com 603-224-9988 Alpha Novatech 473 Sapena Ct. #15 Santa Clara, CA 95054 Internet: www.alphanovatech.com 408-749-7601 The Bergquist Company 800-347-4572 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com International Electronic Research Corporation (IERC) 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com 818-842-7277 Tyco Electronics Chip CoolersTM P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com 800-522-6752 Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com 603-635-5102 Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Other heat sinks offered by Aavid Thermalloy, Alpha Novatech, The Bergquist Company, IERC, Chip Coolers, and Wakefield Engineering offer different heat sink-to-ambient thermal resistances, and may or may not need airflow. 17 2171D-HIREL-06/04 Internal Package Conduction Resistance For the TBGA, cavity down, packaging technology, shown in Figure 6 , the intrinsic conduction thermal resistance paths are as follows: * the die junction-to-case thermal resistance, * the die junction-to-ball thermal resistance. Figure 6 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. Figure 6. TBGA Package with Heat Sink Mounted to a Printed-Circuit Board External Re sistance Radiation Convection Heat Sink Thermal Interface Material Mold Cap Die Junction Die/Substrate/C5 Solder Balls Internal Resistance Printed-Circuit Board External Resistance Radiation Convection (Note the internal versus external package resistance) For this die-up, wire-bond TBGA package, heat generated on the active side of the chip is conducted mainly through the mold cap, the heat sink attach material (or thermal interface material), and finally through the heat sink where it is removed by forced-air convection. Adhesives and Thermal Interface Materials A thermal interface material is recommended between the top of the mold cap and the bottom of the heat sink to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 7 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. Heat sinks are attached to the package by means of a spring clip to holes in the printedcircuit board (see Figure 7). Therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. Of course, the selection of any thermal interface material depends on many factors: thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc. 18 PC8245 2171D-HIREL-06/04 PC8245 Figure 7. Thermal Performance of Select Thermal Interface Material Silicone Sheet (0.006 inch) Bare Joint Floroether Oil Sheet (0.007 inch) Graphite/Oil Sheet (0.005 inch) Synthetic Grease Specific Thermal Resistance (K-in.2/W) 2 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 Contact Pressure (PSI) 19 2171D-HIREL-06/04 The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. There are several commercially-available thermal interfaces and adhesive materials provided by the following vendors: Heat Sink Usage Chomerics, Inc. 77 Dragon Ct. Woburn, MA 01888-4014 Internet: www.chomerics.com 781-935-4850 Dow-Corning Corporation Dow-Corning Electronic Materials 2200 W. Salzburg Rd. Midland, MI 48686-0997 Internet: www.dow.com 800-248-2481 Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com 888-642-7674 Thermagon Inc. 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com 888-246-9050 An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJA x PD) where TA = ambient temperature for the package (C) RJA = junction-to-ambient thermal resistance (C/W) PD = power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Unfortunately, two values are in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the TBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed-circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed as the sum of a junctionto-case thermal resistance and a case-to-ambient thermal resistance: RJA = RJC + RCA where RJA = junction-to-ambient thermal resistance (C/W) RJC = junction-to-case thermal resistance (C/W) RCA = case-to-ambient thermal resistance (C/W) 20 PC8245 2171D-HIREL-06/04 PC8245 RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on the printed-circuit board, or the thermal dissipation on the printed-circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: TT = thermocouple temperature atop the package (C) JT = thermal characterization parameter (C/W) PD = power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-tocase thermal resistance. In many cases, it is appropriate to simulate the system environment using a computational fluid dynamics thermal simulation tool. In such a tool, the simplest thermal model of a package which has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed-circuit board. References Semiconductor Equipment and Materials International 805 East Middlefield Rd. Mountain View, CA 94043 (415) 964-5111 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. 21 2171D-HIREL-06/04 Power Characteristics Table 3 provides power consumption data for the PC8245. Table 3. Power Consumption PCI Bus Clock/Memory Bus Clock CPU Clock Frequency (MHz) Mode 66/66/266 66/133/266 66/66/300 66/100/300 33/83/333 66/133/333 Unit Notes Typical 1.7 (1.5) 2.0 (1.8) 1.8 (1.7) 2.0 (1.8) 2.0 2.3 W (1)(5) Max - FP 2.2 (1.9) 2.4 (2.1) 2.3 (2.)) 2.5 (2.2) 2.6 2.8 W (1)(2) Max - INT 1.8 (1.6) 2.1 (1.8) 2.0 (1.8) 2.1 (1.8) 2.2 2.4 W (1)(3) Doze 1.1 (1.0) 1.4 (1.3) 1.2 (1.1) 1.4 (1.3) 1.6 W (1)(4)(6) Nap 0.4 (0.4) 0.7 (0.7) 0.4 (0.4) 0.6 (0.6) 0.5 0.7 W (1)(4)(6) Sleep 0.2 (0.2) 0.4 (0.4) 0.2 (0.4) 0.3 (0.3) 0.3 0.4 W (1)(4)(6) 1.4 I/O Power Supplies(10) Mode Minimum Maximum Unit Notes Typ - OVDD 134 (121) 334 (301) mW (7)(8) Typ - GVDD 324 (292) 800 (720) mW (7)(9) Notes: 22 1. The values include VDD, AVDD, and AVDD2 but do not include I/O supply power, see Section "Power Supply Sizing" on page 49, for information on OVDD and GVDD supply power. Values shown in parenthesis ( ) indicate power consumption at VDD/AVDD/AVDD2 = 1.8V 2. Maximum - FP power is measured at VDD = 2.1V with dynamic power management enabled while running an entirely cacheresident, looping, floating-point multiplication instruction. 3. Maximum - INT power is measured at VDD = 2.1V with dynamic power management enabled while running entirely cacheresident, looping, integer instructions. 4. Power saving mode maximums are measured at VDD = 2.1V while the device is in doze, nap, or sleep mode. 5. Typical power is measured at VDD = AVDD = 2.0V, OVDD = 3.3V where a nominal FP value, a nominal INT value, and a value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit boundaries to local memory are averaged. 6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled 7. The typical minimum I/O power values were results of the PC8245 performing cache resident integer operations at the slowest frequency combination of 33:66:200 (PCI:Mem:CPU) MHz 8. The typical maximum OVDD value resulted from the PC8245 operating at the fastest frequency combination of 66:100:350 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeros to PCI memory. 9. The typical maximum GVDD value resulted from the PC8245 operating at the fastest frequency combination of 66:100:350 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeros on 64-bit boundaries to local memory. 10. Power consumption of PLL supply pins (AVDD and AVDD2) < 15 mW. Guaranteed by design and is not tested. PC8245 2171D-HIREL-06/04 PC8245 DC Electrical Characteristics Static Characteristics Table 4 provides the DC electrical characteristics for the PC8245 at recommended operating conditions (see Table "Recommended Operating Conditions" on page 12). Table 4. DC Electrical Specifications Value Conditions(3) Characteristics (1) Symbol Min Max Unit Input High Voltage PCI only VIH 0.65 x OVDD LVDD V Input Low Voltage PCI only VIL - 0.3 x OVDD V Input High Voltage All other pins (GVDD = 3.3V) VIH 2.0 3.3 V Input Low Voltage All inputs except PC_SYNC_IN VIL GND 0.8 V PCI_SYNC_IN Input High Voltage CVIH 2.4 - V PCI_SYNC_IN Input Low Voltage CVIL GND 0.4 V 0.5V VIN 2.7V at LVDD = 4.75 IL - 70 A Input Leakage Current(4) All others LVDD = 3.6V GVDD 3.465 IL - 10 A Output High Voltage IOH = Driver Dependent(2) (GVDD = 3.3V) VOH 2.4 - V Output Low Voltage IOL = Driver Dependent(2) (GVDD = 3.3V) VOL - 0.4 V Capacitance(2) VIN = 0V, f = 1 MHz CIN - 7.0 pF (4) Input Leakage Current using DRV_PCI driver Notes: for pins 1. See Table 1 on page 6 for pins with internal pull-up resistors. 2. See Table 5 on page 24 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin as listed in Table 1 on page 6. 3. These specifications are for the default driver strengths indicated in Table 5 on page 24. 4. Leakage current is measured on input and output pins in the high-impedance state. The leakage current is measured for nominal OVDD/LVDD and VDD or both OVDD/LVDD and VDD must vary in the same direction. 23 2171D-HIREL-06/04 Output Driver Characteristic Table 5 on page 24 provides information on the characteristics of the output drivers referenced in Table 1 on page 6. The values are preliminary estimates from an IBIS model and are not tested. Table 5. Drive Capability of PC8245 Output Pins(5) Driver Type Programmable Output Impedance () Supply Voltage (V) IOH IOL Unit Notes 36.6 18.0 mA (2)(4)(6) 18.6 9.2 mA (2)(4)(6) 12.0 12.4 mA (1)(3) 40 (default) 6.1 6.3 mA (1)(3) 6 (default) 89.0 42.3 mA (2)(4) 36.6 18.0 mA (2)(4) 20 DRV_STD_MEM 40 (default) OVDD = 3.3V 20 DRV_PCI DRV_MEM_CTRL DRV_PCI_CLK DRV_MEM_CLK Notes: 1. 2. 3. 4. 5. 6. 20 GVDD = 3.3V (2)(4) 40 18.6 9.2 mA For DRV_PCI, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.33V label by interpolating between the 0.3V and 0.4V table entries' current values which corresponds to the PCI VOH = 2.97 = 0.9 x OVDD (OVDD = 3.3V) where table entry voltage = OVDD - PCI VOH. For all others with GVDD or OVDD = 3.3V, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.9V table entry which corresponds to the VOH = 2.4V where table entry voltage = GVDD/OVDD - VOH. For DRV_PCI, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at 0.33V = PCI VOL = 0 x OVDD (OVDD = 3.3V) by interpolating between the 0.3V and 0.4V table entries. For all others with GVDD or OVDD = 3.3V, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at the 0.4V table entry. See driver bit details for output driver control register (0x72) in the "MPC8245 Integrated Processor User's Manual". See Chip Errata No. 19 in the PC8245/PC8241 RISC Microprocessor Chip Errata's Motorola. AC Electrical Characteristics This section provides the AC electrical characteristics for the PC8245. After fabrication, functional parts are sorted by maximum processor core frequency as shown in Table 6 and tested for conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus (PCI_SYNC_IN) clock frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold by maximum processor core frequency. See "Ordering Information" on page 56. Table 7 provides the operating frequency information for the PC8245 at recommended operating conditions (see Table "Recommended Operating Conditions" on page 12) with LVDD = 3.3V 0.3V. 24 PC8245 2171D-HIREL-06/04 PC8245 Table 6. Operating Frequency 266 MHz 300 MHz 333 MHz 350 MHz Characteristic VDD/AVDD/AVDD2 = 2.0 100 mV Processor Frequency (CPU) 100 - 266 100 - 300 100 - 333 100 - 350 MHz Memory Bus Frequency 50 - 133 50 - 100(3) 50 - 133 50 - 100(3) MHz (2) VDD/AVDD/AVDD2 = 2.0 100 mV Unit PCI Input Frequency 25 - 66 MHz Notes: 1. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the resulting peripheral logic/memory bus frequency and CPU (core) frequencies do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section "PLL Configuration" on page 45 for valid PLL_CFG[0:4] settings and PCI_SYNC_IN frequencies. 2. See Table 16 on page 45 and Table 17 on page 47 for more details on VCO limitations for memory and CPU VCO frequencies of various PLL configurations. 3. There are no available PLL_CFG[0:4] settings which support 133 MHz memory interface operation at 300 MHz CPU and at 350 MHz operation, since the multipliers do not allow a 300:133 and 350:133 ratio relation. However, running these parts are slower speeds may produce ratios that will run above 100 MHz. See Table 16 on page 45 for the PLL settings. Clock AC Specifications Table 7 provides the Clock AC timing specifications at recommended operating conditions, as defined in Section "Input AC Timing Specifications" on page 31. These specifications are for the default driver strengths indicated in Table 5 on page 24. At recommended operating conditions (see Table "Recommended Operating Conditions" on page 12) with LVDD = 3.3V 0.3V Table 7. Clock AC Timing Specifications Num Characteristics and Conditions Min Max Unit Notes 1a Frequency of Operation (PCI_SYNC_IN) 25 66 MHz 2, 3 PCI_SYNC_IN Rise and Fall Times - 2.0 ns 4 PCI_SYNC_IN Duty Cycle Measured at 1.4V 40 60 % 5a PCI_SYNC_IN Pulse Width High Measured at 1.4V 6 9 ns (2) 5b PCI_SYNC_IN Pulse Width Low Measured at 1.4V 6 9 ns (2) 7 PCI_SYNC_IN Jitter - 150 ps 8a PCI_CLK[0:4] Skew (Pin-to-Pin) - 250 ps 8b SDRAM_CLK[0:3] Skew (Pin-to-Pin) - 190 ps (3) 10 Internal PLL Relock Time - 100 s (2)(4)(5) 15 DLL Lock Range with DLL_EXTEND = 0 Disabled (Default) (N x TCLK - Tdp(max)) Tloop (N x TCLK - Tdp(min)) ns (6) 16 DLL Lock Range with DLL_EXTEND = 1 Enabled ((N - 0.5) x TCLK - Tdp(max)) Tloop ((N - 0.5) TCLK - Tdp(min)) ns (6) 17 Frequency of Operation (OSC_IN) 25 66 MHz 19 OSC_IN Rise and Fall Times - 5 ns 20 OSC_IN Duty Cycle Measured at 1.4V 40 60 % 21 OSC_IN Frequency Stability - 100 ppm Notes: (1) (7) 1. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4V. 25 2171D-HIREL-06/04 2. Specification value at maximum frequency of operation. 3. Pin-to-pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides any intentional skew added to the clocking signals from the variable length DLL synchronization feedback loop, that is, the amount of variance between the internal sys_logic_clk and the SDRAM_SYNC_IN signal after the DLL is locked. While pin-to-pin skew between SDRAM_CLKs can be measured, the relationship between the internal sys_logic_clk and the external SDRAM_SYNC_IN cannot be measured and is guaranteed by design. 4. Relock time is guaranteed by design and characterization. Relock time is not tested. 5. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after a stable VDD and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRST_CPU/HRST_CTRL must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence. 6. DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (1 or 2). TCLK is the period of one SDRAM_SYNC_OUT clock cycle in ns. Tloop is the propagation delay of the DLL synchronization feedback loop (PC board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner) corresponds to approximately 1 ns of delay. Tfix0 is a fixed delay inherent in the design when the DLL is at tap point 0 and the DLL is contributing no delay; Tfix0 equals approximately 3 ns. See Figure 9 through Figure 12 for DLL locking ranges. 7. Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise and fall times are not tested. Figure 8. PCI_SYNC-IN Input Clock Timing Diagram 1 5a 5b 2 3 CVIH PCI_SYNC_IN VM VM VM CVIL VM = Midpoint Voltage (1.4V) Table 8. Tdp(max) and Tdp(min) Mode Tdp (min) Tdp (max) Unit Normal tap delay: Bit 2 (DLL_MAX_DELAY) at offset 0 x 76 is cleared 7.58 12.97 ns Maximum tap delay: Bit 2 (DLL_MAX_DELAY) at offset 0 x 76 is set 8.28 17.57 ns Figure 9 through Figure 12 show the DLL locking range loop delay vs. frequency of operation.These graphs define the areas of DLL locking for various modes. The grey areas represent where the DLL will lock. Note also that the DLL_MAX_DELAY bit can lengthen the amount of time through the delay line. This is accomplished by increasing the time between each of the 128 tap points in the delay line. Although this increased time makes it easier to guarantee that the reference clock will be within the DLL lock range, it also means there may be slightly more jitter in the output clock of the DLL, should the phase comparator shift the clock between adjacent tap points. 26 PC8245 2171D-HIREL-06/04 PC8245 Figure 9. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 1 and Normal Tap Delay 30 N=1 27.5 25 Tclk SDRAM_OUT Period (ns) 22.5 20 17.5 15 12.5 10 N=2 7.5 0 1 2 3 4 Tloop Propagation Delay Time (ns) 27 2171D-HIREL-06/04 Figure 10. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 1 and Tap Max Delay 30 N=1 27.5 25 Tclk SDRAM_OUT Period (ns) 22.5 20 17.5 15 12.5 10 N=2 7.5 0 1 2 3 4 Tloop Propagation Delay Time (ns) 28 PC8245 2171D-HIREL-06/04 PC8245 Figure 11. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 0 and Normal Tap Delay 25 Tclk SDRAM_OUT Period (ns) 22.5 20 17.5 15 N=1 12.5 10 N=2 7.5 0 1 2 3 4 Tloop Propagation Delay Time (ns) 29 2171D-HIREL-06/04 Figure 12. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 0 and Normal Tap Delay 25 Tclk SDRAM_OUT Period (ns) 22.5 20 N=1 17.5 15 12.5 10 N=2 7.5 0 1 2 3 4 Tloop Propagation Delay Time (ns) 30 PC8245 2171D-HIREL-06/04 PC8245 Input AC Timing Specifications Table 9 provides the input AC timing specifications at recommended operating conditions (see Table "Recommended Operating Conditions" on page 12) with LVDD = 3.3V 0.3V. See Figure 13 and Figure 14. Table 9. Input AC Timing Specifications Num Characteristic Min Max Unit Notes 10a PCI Input Signals Valid to PCI_SYNC_IN (Input Setup) 3.0 - ns (1)(3) 10b Memory Input Signals Valid to SDRAM_SYNC_IN (Input Setup) 10b0 Tap 0, Register Offset <0x77>, Bits 5:4 = 0b10 2.6 - 10b1 Tap 1, Register Offset <0x77>, Bits 5:4 = 0b11 1.9 - ns (2)(3)(6) 10b2 Tap 2, Register Offset <0x77>, Bits 5:4 = 0b00 (Default) 1.2 - 10b3 Tap 3, Register Offset <0x77>, Bits 5:4 = 0b01 0.5 - 10c Epic, Misc. Debug Input Signals Valid to SDRAM_SYNC_IN (Input Setup) 3.0 - ns (2)(3) 10d Two-wire interface Input Signals Valid to SDRAM_SYNC_IN (Input Setup) 3.0 - ns (2)(3) 10e Mode Select Inputs Valid to HRST_CPU/HRST_CTRL (Input Setup) 9 x TCLK - ns (2)(3)(4)(5) 11 Tos - SDRAM_SYNC_IN to sys_logic_clk offset time 0.65 1.0 ns (7) 11a SDRAM_SYNC_IN to Memory Signal Inputs Invalid (Input Hold) 11a0 Tap 0, Register Offset <0x77>, Bits 5:4 = 0b10 0 - 11a1 Tap 1, Register Offset <0x77>, Bits 5:4 = 0b11 0.7 - ns (2)(3)(6) 11a2 Tap 2, Register Offset <0x77>, Bits 5:4 = 0b00 (Default) 1.4 - 11a3 Tap 3, Register Offset <0x77>, Bits 5:4 = 0b01 2.1 - 11b HRST_CPU/HRST_CTRL to Mode Select Inputs Invalid (Input Hold) 0 - ns (2)(3)(5) 11c PCI_SYNC_IN to Inputs Invalid (Input Hold) 1.0 - ns (1)(2)(3) Notes: 1. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 x OVDD of the signal in question for 3.3V PCI signaling levels. See Figure 14. 2. All memory and related interface input signal specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the VM = 1.4V of the rising edge of the memory bus clock, SDRAM_SYNC_IN. SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 13. 3. Input timings are measured at the pin. 4. TCLK is the time of one SDRAM_SYNC_IN clock cycle. 5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the VM = 1.4V of the rising edge of the HRST_CPU/HRST_CTRL signal. See Figure 15. 6. The memory interface input setup and hold times are programmable to four possible combinations by programming bits 5:4 of register offset <0x77> to select the desired input setup and hold times. 7. Tos represents a timing adjustment for SDRAM_SYNC_IN with respect to sys_logic_clk. Due to the internal delay present on the SDRAM_SYNC_IN signal with respect to the sys_logic_clk inputs to the DLL, the resulting SDRAM clocks become offset by the delay amount. The feedback trace length of SDRAM_SYNC_OUT to SDRAM_SYNC_IN must be shortened by this amount relative to the SDRAM clock output trace lengths to maintain phase-alignment of the memory clocks with respect to sys_logic_clk. Note that the DLL locking range graphs of Figure 9 through Figure 12 compensate for Tos and there is no additional requirement to shorten Tloop by the duration of Tos. Refer to Motorola Application Note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines, for more details on accommodating for the problem of Tos and trace measurements in general. 31 2171D-HIREL-06/04 Figure 13. Input - Output Timing Diagram Referenced to SDRAM_SYNC_IN PCI_SYNC_IN VM sys_logic_clk VM VM VM Tos SDRAM_SYNC_IN (After DLL Locks if no compensation for Tos is made) Shown in 2:1 Mode VM 10b-d 11a 12b-d 2.0 V 2.0 V 0.8 V 0.8 V 13b 14b Memory Inputs/Outputs Output Timing Input Timing Notes: VM = midpoint voltage (1.4V). 11a = input hold time of SDRAM_SYNC_IN to memory. 12b-d = SDRAM_SYNC_IN to output valid timing. 13b = output hold time for non-PCI signals. 14b = SDRAM-SYNC_IN to output high-impedance timing for non-PCI signals. Tos = offset timing required to align sys_logic_clk with SDRAM_SYNC_IN. The SDRAM_SYNC_IN signal is adjusted by the DLL to accommodate for internal delay. This causes SDRAM_SYNC_IN to be seen before sys_logic_clk once the DLL locks, if no other accommodation is made for the delay. 10b-d = input signals valid timing. Figure 14. Input - Output Timing Diagram Referenced to PCI_SYNC_IN PCI_SYNC_IN OVdd/2 OVdd/2 OVdd/2 10a 12a 11c PCI INPUTS/OUTPUTS 14a 0.615*OVdd 0.4*OVdd Input Timing 32 13a 0.285*OVdd Output Timing PC8245 2171D-HIREL-06/04 PC8245 Figure 15. Input Timing Diagram for Mode Select Signals HRST_CPU/HRST_CTRL VM 10e 11b 2.0V MODE PINS 0.8V VM = Midpoint Voltage (1.4V) Output AC Timing Specification Table 10 provides the processor bus AC timing specifications for the PC8245 at recommended operating conditions (see Table "Recommended Operating Conditions" on page 12) with LVDD = 3.3V 0.3V. See Figure 13 on page 32. All output timings assume a purely resistive 50 load (see Figure 16 on page 34). Output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system. These specifications are for the default driver strengths indicated in Table 5 on page 24. Table 10. Output AC Timing Specifications Num Characteristics Min Max Unit Notes 12a PCI_SYNC_IN to Output Valid, see Figure 17 on page 35 12a0 Tap 0, PCI_HOLD_DEL = 00, [MCP,CKE] = 11, 66 MHz PCI (Default) - 6.0 12a1 Tap 1, PCI_HOLD_DEL = 01, [MCP,CKE] = 10 - 6.5 12a2 Tap 2, PCI_HOLD_DEL = 10, [MCP,CKE] = 01, 33 MHz PCI - 7.0 ns (1)(3) 12a3 Tap 3, PCI_HOLD_DEL = 11, [MCP,CKE] = 00 - 7.5 12b SDRAM_SYNC_IN to Output Valid (Memory Control and Data Signals) - 4.5 ns (2) 12c SDRAM_SYNC_IN to Output Valid (For All Others) - 7.0 ns (2) 12d SDRAM_SYNC_IN to Output Valid (For Two-wire interface) - 5.0 ns (2) 12e SDRAM_SYNC_IN to Output Valid (ROM/Flash/PortX) - 6.0 ns (2) 13a Output Hold (PCI), see Figure 17 13a0 Tap 0, PCI_HOLD_DEL = 00, [MCP,CKE] = 11, 66 MHz PCI (Default) 2.0 - 13a1 Tap 1, PCI_HOLD_DEL = 01, [MCP,CKE] = 10 2.5 - ns (1)(3)(4) 13a2 Tap 2, PCI_HOLD_DEL = 10, [MCP,CKE] = 01, 33 MHz PCI 3.0 - 13a3 Tap 3, PCI_HOLD_DEL = 11, [MCP,CKE] = 00 3.5 - 13b Output Hold (All Others) 1.0 - ns (2) 14a PCI_SYNC_IN to Output High Impedance (For PCI) - 14.0 ns (1)(3) 14b SDRAM_SYNC_IN to Output High Impedance (For All Others) - 4.0 ns (2) Notes: 1. All PCI signals are measured from GVDD_OVDD/2 of the rising edge of PCI_SYNC_IN to 0.285 x OVDD or 0.615 x OVDD of the signal in question for 3.3V PCI signaling levels. See Figure 14 on page 32. 2. All memory and related interface output signal specifications are specified from the VM = 1.4V of the rising edge of the memory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0V) of the signal in question. SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 13 on page 32. 33 2171D-HIREL-06/04 3. PCI bused signals are composed of the following signals: LOCK, IRDY, C/BE[3:0], PAR, TRDY, FRAME, STOP, DEVSEL, PERR, SERR, AD[31:0], REQ[4:0], GNT[4:0], IDSEL, INTA. 4. In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both 33 and 66 MHz PCI systems, the PC8245 has a programmable output hold delay for PCI signals (the PCI_SYNC_IN to output valid timing is also affected). The initial value of the output hold delay is determined by the values on the MCP and CKE reset configuration signals; the values on these two signals are inverted then stored as the initial settings of PCI_HOLD_DEL = PMCR2[5:4] (power management configuration register 2 <0x72>), respectively. Since MCP and CKE have internal pull-up resistors, the default value of PCI_HOLD_DEL after reset is 0b00. Further output hold delay values are available by programming the PCI_HOLD_DEL value of the PMCR2 configuration register. See Figure 17 on page 35. Figure 16. AC Test Load for the PC8245 Output measurements are made at the device pin OUTPUT Z0 = 50 RL = 50 34 OVDD/2 for PCI OVDD/2 for Memory PC8245 2171D-HIREL-06/04 PC8245 Figure 17. PCI_HOLD_DEL Affect on Output Valid and Hold Time PCI_SYNC_IN 12a, 8 ns for 33 MHz PCI PCI_HOLD_DEL = 10 0Vdd/2 0Vdd/2 13a, 2.1 ns for 33 MHz PCI PCI_HOLD_DEL = 10 PCI INPUTS/OUTPUTS 33 MHz PCI 12a0, 5.5 ns for 66 MHz PCI PCI_HOLD_DEL = 00 13a0, 1 ns for 66 MHz PCI PCI_HOLD_DEL = 00 PCI INPUTS/OUTPUTS 66 MHz PCI As PCI_HOLD_DEL values decrease PCI INPUTS and OUTPUTS As PCI_HOLD_DEL values increase OUTPUT VALID Note: OUTPUT HOLD Diagram not to scale 35 2171D-HIREL-06/04 I2C AC Timing Specifications Table 11 provides the I2C interface input AC timing specifications for the PC8245 at recommended operating conditions (see Table "Recommended Operating Conditions" on page 12) with LVDD = 3.3V 0.3V. Table 11. I2C interface Input AC Timing Specifications Number Characteristics Min Max Unit Notes 1 Start condition hold time 4.0 - CLKs (1)(2) 2 Clock low period (time before the PC8245 will drive SCL low as a transmitting slave after detecting SCL low as driven by an external master.) 8.0 + (16 x 2FDR[4:2]) x (5 4({FDR[5],FDR[1]} == b'10) 3({FDR[5],FDR[1]} == b'11) 2({FDR[5],FDR[1]} == b'00) 1({FDR[5],FDR[1]} == b'01)) - CLKs (1)(2)(4)(5) 3 SCL/SDA rise time (from 0.5V to 2.4V) - 1 ms 4 Data hold time 0 - ns 5 SCL/SDA fall time (from 2.4V to 0.5V) - 1 ms 6 Clock high period (Time needed to either receive a data bit or generate a START or STOP.) 5.0 - CLKs (1)(2)(5) 7 Data setup time 3.0 - ns (3) 8 Start condition setup time (for repeated start condition only) 4.0 - CLKs (1)(2) 9 Stop condition setup time 4.0 - CLKs (1)(2) Notes: 36 (2) 1. Units for these specifications are in SDRAM_CLK units. 2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency divider register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified SCL and SDA are delayed signals from what is seen in real time on the I2C interface bus. The qualified SCL, SDA signals are delayed by the SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay value is added to the value in the table (where this note is referenced). See Figure 19 on page 39. 3. Timing is relative to the Sampling Clock (not SCL). 4. FDR[x] refers to the Frequency Divider Register I2CFDR bit x. 5. Input clock low and high periods in combination with the FDR value in the Frequency Divider Register (I2CFDR) determine the maximum I2C interface input frequency. See Table 12. PC8245 2171D-HIREL-06/04 PC8245 Table 12 provides the I2C Interface Frequency Divider Register (I2CFDR) information for the PC8245. Table 12. PC8245 Maximum I2C Interface Input Frequency Max I2C Interface Input Frequency(1) FDR Hex(2) Divider (Dec)(2)(3) SDRAM_CLK at 33 MHz SDRAM_CLK at 50 MHz SDRAM_CLK at 100 MHz SDRAM_CLK at 133 MHz 20, 21 160, 192 1.13 MHz 1.72 MHz 3.44 MHz 4.58 MHz 22, 23, 24, 25 224, 256, 320, 384 733 1.11 MHz 2.22 MHz 2.95 MHz16 0, 1 288, 320 540 819 1.63 MHz 2.18 MHz 2, 3, 26, 27, 28, 29 384, 448, 480, 512, 640, 768 428 649 1.29 MHz 1.72 MHz 4, 5 576, 640 302 458 917 1.22 MHz 6, 7, 2A, 2B, 2C, 2D 768, 896, 960, 1024, 1280, 1536 234 354 709 943 8, 9 1152, 1280 160 243 487 648 A, B, 2E, 2F, 30, 31 1536, 1792, 1920, 2048, 2560, 3072 122 185 371 494 C, D 2304, 2560 83 125 251 335 E, F, 32, 33, 34, 35 3072, 3584, 3840, 4096, 5120, 6144 62 95 190 253 10, 11 4608, 5120 42 64 128 170 12, 13, 36, 37, 38, 39 6144, 7168, 7680, 8192, 10240, 12288 31 48 96 128 14, 15 9216, 10240 21 32 64 85 16, 17, 3A, 3B, 3C, 3D 12288, 14336, 15360, 16384, 20480, 24576 16 24 48 64 18, 19 18432, 20480 10 16 32 43 1A, 1B, 3E, 3F 24576, 28672, 30720, 32768 8 12 24 32 1C, 1D 36864, 40960 5 8 16 21 1E, 1F 49152, 61440 4 6 12 16 Notes: 1. Values are in kHz unless otherwise specified. 2. FDR Hex and Divider (Dec) values are listed in corresponding order. 3. Multiple Divider (Dec) values will generate the same input frequency, but each Divider (Dec) value will generate a unique output frequency as shown in Table 13. 37 2171D-HIREL-06/04 Table 13 provides the I2C interface output AC timing specifications for the PC8245 at recommended operating conditions (see Table "Recommended Operating Conditions" on page 12) with LVDD = 3.3V 0.3V. Table 13. I2C Interface Output AC Timing Specifications Number Characteristics 1 Start condition hold time 2 Clock low period 3 SCL/SDA rise time (from 0.5V to 2.4V) Min Max Unit Notes (FDR[5] == 0) x (DFDR/16)/2N + (FDR[5] == 1) x (DFDR/16)/2M - CLKs (1)(2)(3) DFDR/2 - CLKs (1)(2)(3) - - ms (4) 8.0 + (16 x 2FDR[4:2]) x (5 4({FDR[5],FDR[1]} == b'10) 3({FDR[5],FDR[1]} == b'11) 2({FDR[5],FDR[1]} == b'00) 1({FDR[5],FDR[1]} == b'01)) - CLKs (1)(2)(3) <5 ns (5) DFDR/2 - CLKs (1)(2)(3) 4 Data hold time 5 SCL/SDA fall time (from 2.4V to 0.5V) 6 Clock high time 7 Data setup time (PC8245 as a master only) (DFDR/2) - (Output data hold time) - CLKs (1)(3) 8 Start condition setup time (for repeated start condition only) DFDR + (Output start condition hold time) - CLKs (1)(2)(3) 9 Stop condition setup time 4.0 - CLKs (1)(2) Notes: 1. Units for these specifications are in SDRAM_CLK units. 2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency divider register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified SCL and SDA are delayed signals from what is seen in real time on the I2C interface bus. The qualified SCL, SDA signals are delayed by the SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay value is added to the value in the table (where this note is referenced). See Figure 19. 3. DFDR is the decimal divider number indexed by FDR[5:0] value. Refer to Table 10-5 in the "MPC8245 Integrated Processor User's Manual". FDR[x] refers to the frequency divider register I2CFDR bit x. N is equal to a variable number that would make the result of the divide (data hold time value) equal to a number less than 16. M is equal to a variable number that would make the result of the divide (data hold time value) equal to a number less than 9. 4. Since SCL and SDA are open-drain type outputs, which the PC8245 can only drive low, the time required for SCL or SDA to reach a high level depends on external signal capacitance and pull-up resistor values. 5. Specified at a nominal 50 pF load. Figure 18. I2C Interface Timing Diagram I 2 SCL VM VM 6 1 4 SDA 38 PC8245 2171D-HIREL-06/04 PC8245 Figure 19. I2C Interface Timing Diagram II 3 5 SCL VH VM VL 8 9 SDA Figure 20. I2C Interface Timing Diagram III DFFSR FILTER CLK (1) 7 SDA INPUT DATA VALID Note 1: DFFSR Filter Clock is the SDRAM_CLK clock times DFFSR value. Figure 21. I2C Interface Timing Diagram IV (Qualified signal) SCL/SDArealtime VM Delay (1) SCL/SDAqualified VM Note 1: The delay is the Local Memory clock times DFFSR times 2 plus 1 Local Memory clock. 39 2171D-HIREL-06/04 EPIC Serial Interrupt Mode AC Timing Specifications Table 14 provides the EPIC serial interrupt mode AC timing specifications for the PC8245 at recommended operating conditions (see Table "Recommended Operating Conditions" on page 12) with GVDD = 3.3V 5% and LVDD = 3.3V 0.3V. Table 14. EPIC Serial Interrupt Mode AC Timing Specifications Number Characteristics Min Max Unit Notes 1 S_CLK Frequency 1/14 SDRAM_SYNC_IN 1/2 SDRAM_SYNC_IN MHz (1) 2 S_CLK Duty Cycle 40 60 % - 3 S_CLK Output Valid Time - 6 ns - 4 Output Hold Time 0 - ns - 5 S_FRAME, S_RST Output Valid Time - 1 sys_logic_clk period + 6 ns (2)(3) 6 S_INT Input Setup Time to S_CLK 1 sys_logic_clk period + 2 - ns (2)(3) 7 S_INT Inputs Invalid (Hold Time) to S_CLK - 0 ns (2) Notes: 1. See the "MPC8245 Integrated Processor User's Manual" for a description of the EPIC interrupt control register (EICR) describing S_CLK frequency programming. 2. S_RST, S_FRAME, and S_INT shown in Figure 22 and Figure 23, depict timing relationships to sys_logic_clk and S_CLK and do not describe functional relationships between S_RST, S_FRAME, and S_INT. See the "MPC8245 Integrated Processor User's Manual" for a complete description of the functional relationships between these signals. 3. The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral logic PLL; sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN feedback loop is implemented and the DLL is locked. See the "MPC8245 Integrated Processor User's Manual" for a complete clocking description. Figure 22. EPIC Serial Interrupt Mode Output Timing Diagram sys_logic_clk3 VM VM VM 3 S_CLK 4 VM VM 5 4 S_FRAME VM VM S_RST 40 PC8245 2171D-HIREL-06/04 PC8245 Figure 23. EPIC Serial Interrupt Mode Input Timing Diagram S_CLK VM 7 6 S_INT IEEE 1149.1 (JTAG) AC Timing Specifications Table 15 provides the JTAG AC timing specifications for the PC8245 while in the JTAG operating mode at recommended operating conditions (see Table "Recommended Operating Conditions" on page 12) with LVDD = 3.3V 0.3V. Timings are independent of the system clock (PCI_SYNC_IN). Table 15. JTAG AC Timing Specifications (Independent of PCI_SYNC_IN) Number Min Max Unit TCK Frequency of Operation 0 25 MHz 1 TCK Cycle Time 40 - ns 2 TCK Clock Pulse Width Measured at 1.5V 20 - ns 3 TCK Rise and Fall Times 0 3 ns 4 TRST Setup Time to TCK Falling Edge 10 - ns 5 TRST Assert Time 10 - ns 6 Input Data Setup Time 5 - ns (2) 7 Input Data Hold Time 15 - ns (2) 8 TCK to Output Data Valid 0 30 ns (3) 9 TCK to Output High Impedance 0 30 ns (3) 10 TMS, TDI Data Setup Time 5 - ns 11 TMS, TDI Data Hold Time 15 - ns 12 TCK to TDO Data Valid 0 15 ns 13 TCK to TDO High Impedance 0 15 ns Notes: Characteristics Notes (1) 1. TRST is an asynchronous signal. The setup time is for test purposes only. 2. Nontest (other than TDI and TMS) signal input timing with respect to TCK. 3. Nontest (other than TDO) signal output timing with respect to TCK. Figure 24. JTAG Clock Input Timing Diagram 1 2 VM TCK 3 2 VM VM 3 VM = Midpoint Voltage 41 2171D-HIREL-06/04 Figure 25. JTAG TRST Timing Diagram TCK 4 TRST 5 Figure 26. JTAG Boundary Scan Timing Diagram TCK 6 DATA INPUTS 7 INPUT VALID DATA 8 DATA OUTPUTS OUTPUT VALID DATA 9 DATA OUTPUTS Figure 27. Test Access Port Timing Diagram TCK 10 TDI, TMS 11 INPUT VALID DATA 12 TDO OUTPUT VALID DATA 13 TDO 42 PC8245 2171D-HIREL-06/04 PC8245 Package Description This section details package parameters, pin assignments, and dimensions. Package Parameters for the PC8245 The PC8245 uses a 35 mm x 35 mm, cavity up, 352-pin tape ball grid array (TBGA) package. The package parameters are as follows:. Package Outline 35 mm x 35 mm Interconnects 352 Pitch 1.27 mm Solder Balls 62 Sn/36 Pb/2 Ag Solder Balls Diameter 0.75 mm Maximum Module Height 1.65 mm Co-planarity Specification 0.15 mm Maximum Force 6.0 lbs. total, uniformly distributed over package (8 grams/ball) 43 2171D-HIREL-06/04 Pin Assignments and Package Dimensions Figure 28 shows the top surface, side profile, and pinout of the PC8245, 352 TBGA package. Figure 28. PC8245 Package Dimensions and Pinout Assignments -FCORNER B -E- -T0.150 T A Min Max 34.8 35.2 34.8 35.2 1.45 1.65 0.60 0.90 1.27 BASIC 0.85 0.95 31.75 BASIC 0.50 0.70 A B C D G H K L Top View 26 24 22 20 18 16 14 12 10 8 6 4 2 25 23 21 19 17 15 13 11 9 7 5 3 1 A C E G J L N R U W B D F H K M K P T V Y AA AB AC AD AE AF C H L Bottom View 352X D K Notes: 44 1. 2. G Drawing not to scale. All measurements are in millimeters (mm). PC8245 2171D-HIREL-06/04 PC8245 PLL Configuration The internal PLLs of the PC8245 are configured by the PLL_CFG[0:4] signals. For a given PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO) frequency of operation for the PCI-to-memory frequency multiplying and the PC603e CPU PLL (VCO) frequency of operation for memory-to-CPU frequency multiplying. The PLL configurations for the PC8245 is shown in Table 16 and Table 17. Table 16. PLL Configurations (266 and 300 MHz Parts) 266 MHz Part(9) Periph Logic/ Mem Bus Clock Range (MHz) 300 MHz Part(9) Multipliers CPU Clock Range (MHz) PCI Clock Input (PCI_ SYNC_IN) Range(1) (MHz) Periph Logic/Mem Bus Clock Range (MHz) CPU Clock Range (MHz) PCI to Mem (Mem VCO) Mem to CPU (CPU VCO) Ref PLL_ CFG [0:4](10)(13) PCI Clock Input (PCI_ SYNC_IN) Range(1) (MHz) 0 00000(12) 25 - 35(5)(16) 75 - 105 188 - 263 25 - 40(5) 75 - 120 188 - 300 3(2) 2.5(2) 1 00001(12) 25 - 29(5) 75 - 88 225 - 264 25 - 33(5) 75 - 99 225 - 297 3(2) 3(2) 2 00010(11) 50(18) - 59(5) 50 - 59 225 - 266 50(18) - 66(1) 50 - 66 225 - 297 1(4) 4.5(2) 3 00011(11)(14) 50(4) - 66(1) 50 - 66 100 - 133 50(4) - 66(1) 50 - 66 100 - 133 1 (Bypass) 2(4) 4 00100(12) 25 - 46(4) 50 - 92 100 - 184 25 - 46(4) 50 - 92 100 - 184 2(4) 2(4) 5 00101 6 00110(15) 7 00111 (14) 8 Reserved Bypass (6) (1) 60 - 66 01000(12) 60(6) - 66(1) 9 01001(19) A Note (20) Bypass Bypass 180 - 198 60 (1) 60 - 66 180 - 198 1 (Bypass) 3(2) 60 - 66 180 - 198 60(6) - 66(1) 60 - 66 180 - 198 1(4) 3(2) 45(6) - 66(1) 90 - 132 180 - 264 45(6) - 66(1) 90 - 132 180 - 264 2(2) 2(2) 01010(12) 25 - 29(5) 50 - 58 225 - 261 25 - 33(5) 50 - 66 225 - 297 2(4) 4.5(2) B 01011(19) 45(3) - 59(5) 68 - 88 204 - 264 45(3) - 66(1) 68 - 99 204 - 297 1.5(2) 3(2) C 01100(12) 36(6) - 46(4) 72 - 92 180 - 230 36(6) - 46(4) 72 - 92 180 - 230 2(4) 2.5(2) D 01101(19) 45(3) - 50(5) 68 - 75 238 - 263 45(3) - 57(5) 68 - 85 238 - 298 1.5(2) 3.5(2) E 01110(12) 30(6) - 44(5) 60 - 88 180 - 264 30(6) - 46(4) 60 - 92 180 - 276 2(4) 3(2) F 01111(19) 25(5) 75 263 25 - 28(5) 75 - 85 263 - 298 3(2) 3.5(2) 10 10000(12) 30(6) - 44(2)(5) 60 - 132 180 - 264 30(6) - 44(2) 60 - 132 180 - 264 3(2) 2(2) 11 10001(19) 25 - 26(5) 100 - 106 250 - 266 25 - 29(2) 100 - 116 250 - 290 4(2) 2.5(2) 12 10010(12) 60(6) - 66(1) 90 - 99 180 - 198 60(6) - 66(1) 90 - 99 180 - 198 1.5(2) 2(2) 13 10011(19) 25(2) 100 300 4(2) 3(2) 14 10100(12) 26(6) - 42(5) 52 - 84 182 - 294 2(4) 3.5(2) 15 10101(19) 27(3) - 30(5) 68 - 75 272 - 300 2.5(2) 4(2) 16 10110(12) 25 - 33(5) 50 - 66 200 - 264 25 - 37(5) 50 - 74 200 - 296 2(4) 4(2) 17 10111(19) 25 - 33(5) 100 - 132 200 - 264 25 - 33(2) 100 - 132 200 - 264 4(2) 2(2) 18 11000(12) 27(3) - 35(5) 68 - 88 204 - 264 27(3) - 40(5) 68 - 100 204 - 300 2.5(2) 3(2) 60 - 66 Not Available 26(6) - 38(5) 52 - 76 182 - 266 Not Available (6) Reserved - 66 45 2171D-HIREL-06/04 Table 16. PLL Configurations (266 and 300 MHz Parts) (Continued) 266 MHz Part(9) Periph Logic/ Mem Bus Clock Range (MHz) 300 MHz Part(9) Multipliers CPU Clock Range (MHz) PCI Clock Input (PCI_ SYNC_IN) Range(1) (MHz) Periph Logic/Mem Bus Clock Range (MHz) CPU Clock Range (MHz) PCI to Mem (Mem VCO) Mem to CPU (CPU VCO) Ref PLL_ CFG [0:4](10)(13) PCI Clock Input (PCI_ SYNC_IN) Range(1) (MHz) 19 11001(19) 36(6) - 53(5) 72 - 106 180 - 265 36(6) - 59(2) 72 - 118 180 - 295 2(2) 2.5(2) 1A 11010(12) 50(18) - 66(1) 50 - 66 200 - 264 50(18) - 66(1) 50 - 66 200 - 264 1(4) 4(2) 1B 11011(19) 33(6) - 44(5) 66 - 88 198 - 264 33(6) - 50(5) 66 - 100 198 - 300 2(2) 3(2) 1C 11100(12) 44(6) - 59(5) 66 - 88 198 - 264 44(6) - 66(1) 66 - 99 198 - 297 1.5(2) 3(2) 1D 11101(12) 48(6) - 66(1) 72 - 99 198 - 248 48(6) - 66(1) 72 - 99 180 - 248 1.5(2) 2.5(2) 1E 11110(8) Not Usable Not Usable Off Off 1F (8) Not Usable Not Usable Off Off Notes: 46 11111 1. Limited by maximum PCI input frequency (66 MHz). 2. Limited by maximum system memory interface operating frequency (100 MHz at 350 MHz CPU). 3. Limited by minimum memory VCO frequency (133 MHz). 4. Limited due to maximum memory VCO frequency (372 MHz). 5. Limited by maximum CPU operating frequency (266 MHz). 6. Limited by minimum CPU VCO frequency (360 MHz). 7. Limited by maximum CPU VCO frequency (800 MHz). 8. In clock off mode, no clocking occurs inside the PC8245 regardless of the PCI_SYNC_IN input. 9. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity. 10. PLL_CFG[0:4] settings not listed (01011, 01101, 01111, 10001, 10011, 10101, 11001, and 11011) are reserved. 11. Multiplier ratios for this PLL_CFG[0:4] setting are different from the PC8240 and are not backwards-compatible. 12. PCI_SYNC_IN range for this PLL_CFG[0:4] setting is different from the PC8240 and may not be fully backwards-compatible. 13. Bits 7- 4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value. 14. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware modeling support. The AC timing specifications given in this document do not apply in PLL bypass mode. 15. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and the processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This mode is intended for hardware modeling support. The AC timing specifications given in this document do not apply in dual PLL bypass mode. 16. Limited by maximum system memory interface operating frequency (133 MHz at 266 MHz CPU). 17. Limited by minimum CPU operating frequency (100 MHz). 18. Limited by minimum memory bus frequency (50 MHz). 19. PCI_SYNC_IN range for this PLL_CFG[0:4] setting does not exist on the PC8240 and may not be fully backwardscompatible. 20. No longer supported. PC8245 2171D-HIREL-06/04 PC8245 Table 17. PLL Configurations (333 and 350 MHz Parts) 333 MHz Part(9) 350 MHz Part(9) Multipliers Ref PLL_ CFG [0:4](10)(13) PCI Clock Input (PCI_ SYNC_IN) Range(1) (MHz) 0 00000(12) 25 - 44(16) 75 - 132 188 - 330 25 - 44(16) 75 - 132 188 - 330 3(2) 2.5(2) 1 00001(12) 25 - 37(5) 75 - 111 225 - 333 25 - 38(5) 75 - 114 225 - 342 3(2) 3(2) 2 00010(11) 50(18) - 66(1) 50 - 66 225 - 297 50(18) - 66(1) 50 - 66 225 - 297 1(4) 4.5(2) 3 00011(11)(14) 50(4) - 66(1) 50 - 66 100 - 133 50(4) - 66(1) 50 - 66 100 - 133 1 (Bypass) 2(4) 4 00100(12) 25 - 46(4) 50 - 92 100 - 184 25 - 46(4) 50 - 92 100 - 184 2(4) 2(4) 5 00101 6 00110(15) 7 (14) Periph Logic/ Mem Bus Clock Range (MHz) CPU Clock Range (MHz) PCI Clock Input (PCI_ SYNC_IN) Range(1) (MHz) Periph Logic/ Mem Bus Clock Range (MHz) CPU Clock Range (MHz) PCI to Mem (Mem VCO) Mem to CPU (CPU VCO) Reserved Bypass (6) 00111 60 (1) 60 - 66 8 01000(12) 60(6) - 66(1) 9 01001(19) A Note(20) Bypass Bypass 180 - 198 60 (1) 60 - 66 180 - 198 1 (Bypass) 3(2) 60 - 66 180 - 198 60(6) - 66(1) 60 - 66 180 - 198 1(4) 3(2) 45(6) - 66(1) 90 - 132 180 - 264 45(6) - 66(1) 90 - 132 180 - 264 2(2) 2(2) 01010(12) 25 - 37(5) 50 - 74 225 - 333 25 - 38(5) 50 - 76 225 - 342 2(4) 4.5(2) B 01011(19) 45(3) - 66(1) 68 - 99 204 - 297 45(3) - 66(1) 68 - 99 204 - 297 1.5(2) 3(2) C 01100(12) 36(6) - 46(4) 72 - 92 180 - 230 36(6) - 46(4) 72 - 92 180 - 230 2(4) 2.5(2) D 01101(19) 45(3) - 63(5) 68 - 95 238 - 333 45(3) - 66(1) 68 - 99 238 - 347 1.5(2) 3.5(2) E 01110(12) 30(6) - 46(4) 60 - 92 180 - 276 30(6) - 46(4) 60 - 92 180 - 276 2(4) 3(2) F 01111(19) 25 - 31(5) 75 - 93 263 - 326 25 - 33(5) 75 - 99 263 - 347 3(2) 3.5(2) 10 10000(12) 30(6) - 44(2) 60 - 132 180 - 264 30(6) - 44(2) 60 - 132 180 - 264 3(2) 2(2) 11 10001(19) 25 - 33(2) 100 - 132 250 - 330 25 - 33(2) 100 - 132 250 - 330 4(2) 2.5(2) 12 10010(12) 60(6) - 66(1) 90 - 99 180 - 198 60(6) - 66(1) 90 - 99 180 - 198 1.5(2) 2(2) 13 10011(19) 25 - 27(5) 100 - 108 300 - 324 25 - 29(5) 100 - 116 300 - 348 4(2) 3(2) 14 10100(12) 26(6) - 47(4) 52 - 94 182 - 329 26(6) - 47(4) 52 - 94 182 - 329 2(4) 3.5(2) 15 10101(19) 27(3) - 33(5) 68 - 83 272 - 332 27(3) - 34(5) 68 - 85 272 - 340 2.5(2) 4(2) 16 10110(12) 25 - 41(5) 50 - 82 200 - 328 25 - 43(5) 50 - 86 200 - 344 2(4) 4(2) 17 10111(19) 25 - 33(2) 100 - 132 200 - 264 25 - 33(2) 100 - 132 200 - 264 4(2) 2(2) 18 11000(12) 27(3) - 44(5) 68 - 110 204 - 330 27(3) - 46(5) 68 - 115 204 - 345 2.5(2) 3(2) 19 11001(19) 36(6) - 66(1) 72 - 132 180 - 330 36(6) - 66(1) 72 - 132 180 - 330 2(2) 2.5(2) 1A 11010(12) 50(18) - 66(1) 50 - 66 200 - 264 50(18) - 66(1) 50 - 66 200 - 264 1(4) 4(2) 1B 11011(19) 33(6) - 55(5) 66 - 110 198 - 330 33(6) - 58(5) 66 - 116 198 - 348 2(2) 3(2) 1C 11100(12) 44(6) - 66(1) 66 - 99 198 - 297 44(6) - 66(1) 66 - 99 198 - 297 1.5(2) 3(2) - 66 (6) Reserved - 66 47 2171D-HIREL-06/04 Table 17. PLL Configurations (333 and 350 MHz Parts) (Continued) 333 MHz Part(9) 350 MHz Part(9) Multipliers Ref PLL_ CFG [0:4](10)(13) PCI Clock Input (PCI_ SYNC_IN) Range(1) (MHz) 1D 11101(12) 48(6) - 66(1) 1E 11110(8) Not Usable Not Usable Off Off 1F 11111(8) Not Usable Not Usable Off Off Notes: 48 Periph Logic/ Mem Bus Clock Range (MHz) 72 - 99 CPU Clock Range (MHz) PCI Clock Input (PCI_ SYNC_IN) Range(1) (MHz) Periph Logic/ Mem Bus Clock Range (MHz) CPU Clock Range (MHz) PCI to Mem (Mem VCO) Mem to CPU (CPU VCO) 180 - 248 48(6) - 66(1) 72 - 99 180 - 248 1.5(2) 2.5(2) 1. Limited by maximum PCI input frequency (66 MHz). 2. Limited by maximum system memory interface operating frequency (100 MHz at 350 MHz CPU). 3. Limited by minimum memory VCO frequency (133 MHz). 4. Limited due to maximum memory VCO frequency (372 MHz). 5. Limited by maximum CPU operating frequency (266 MHz). 6. Limited by minimum CPU VCO frequency (360 MHz). 7. Limited by maximum CPU VCO frequency (800 MHz). 8. In clock off mode, no clocking occurs inside the PC8245 regardless of the PCI_SYNC_IN input. 9. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity. 10. PLL_CFG[0:4] settings not listed (01011, 01101, 01111, 10001, 10011, 10101, 11001, and 11011) are reserved. 11. Multiplier ratios for this PLL_CFG[0:4] setting are different from the PC8240 and are not backwards-compatible. 12. PCI_SYNC_IN range for this PLL_CFG[0:4] setting is different from the PC8240 and may not be fully backwards-compatible. 13. Bits 7-4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value. 14. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware modeling support. The AC timing specifications given in this document do not apply in PLL bypass mode. 15. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and the processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This mode is intended for hardware modeling support. The AC timing specifications given in this document do not apply in dual PLL bypass mode. 16. Limited by maximum system memory interface operating frequency (133 MHz at 333 MHz CPU). 17. Limited by minimum CPU operating frequency (100 MHz). 18. Limited by minimum memory bus frequency (50 MHz). 19. PCI_SYNC_IN range for this PLL_CFG[0:4] setting does not exist on the PC8240 and may not be fully backwardscompatible. 20. No longer supported. PC8245 2171D-HIREL-06/04 PC8245 System Design Information This section provides electrical and thermal design recommendations for successful application of the PC8245. PLL Power Supply Filtering The AVDD and AVDD2 power signals are provided on the PC8245 to provide power to the peripheral logic/memory bus PLL and the PC603e processor PLL. To ensure stability of the internal clocks, the power supplied to the AVDD and AVDD2 input signals should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLLs. Two separate circuits similar to the one shown in Figure 29 using surface mount capacitors with minimum effective series inductance (ESL) is recommended for AVDD and AVDD2 power signal pins. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over using multiple values. The circuits should be placed as close as possible to the respective input signal pins to minimize noise coupled from nearby circuits. Routing directly as possible from the capacitors to the input signal pins with minimal inductance of vias is important. Figure 29. PLL Power Supply Filter Circuit 10 k Vdd AVdd, AVdd2 2.2 F 2.2 F Low ESL surface mount capacitors GND Power Supply Sizing The power consumption numbers provided in Table 3 on page 22 do not reflect power from the OVDD and GVDD power supplies which are non-negligible for the PC8245. In typical application measurements, the OVDD power ranged from 200 to 500 mW and the GVDD power ranged from 300 to 600 mW. The ranges' low-end power numbers were results of the PC8245 performing cache resident integer operations at the slowest frequency combination of 33:66:200 (PCI:Mem:CPU) MHz. The OVDD high end range's value resulted from the PC8245 operating at the fastest frequency combination of 66:100:350 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeros to PCI memory. The GVDD high-end range's value resulted from the PC8245 operating at the fastest frequency combination of 66:100:350 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeros on 64-bit boundaries to local memory. Decoupling Recommendations Due to its dynamic power management feature, the large address and data buses, and its high operating frequencies, the PC8245 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the PC8245 system, and the PC8245 itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pin of the PC8245. It is also recommended that these decoupling capacitors receive their power from separate VDD, OVDD, GVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. These capacitors should have a value of 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603, oriented such that connections are made along the length of the part. 49 2171D-HIREL-06/04 In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors: 100 - 330 F (AVX TPS tantalum or Sanyo OSCON). Connection Recommendations To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active-low inputs should be tied to OVDD. Unused active-high inputs should be connected to GND. All NC (no connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, OVDD, GVDD, LVDD, and GND pins of the PC8245. The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then returned to the PCI_SYNC_IN input of the PC8245. The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then returned to the SDRAM_SYNC_IN input of the PC8245. The trace length may be used to skew or adjust the timing window as needed. See Motorola application notes AN1849/D and AN2164/D for more information on this topic. Note that there is an SDRAM_SYNC_IN to PCI_SYNC_IN time requirement. (See Table 9 on page 31.) Pull-up/Pull-down Resistor Requirements The data bus input receivers are normally turned off when no read operation is in progress; therefore, they do not require pull-up resistors on the bus. The data bus signals are: MDH[0:31], MDL[0:31], and PAR[0:7]. If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (MDL[0:31] and PAR[4:7]) will be disabled, and their outputs will drive logic zeros when they would otherwise normally be driven. For this mode, these pins do not require pull-up resistors and should be left unconnected by the system to minimize possible output switching. The TEST0 pin requires a pull-up resistor of 120 or less connected to OVDD. It is recommended that RTC have weak pull-up resistors (2 k - 10 k) connected to GVDD_OVDD. It is recommended that the following signals be pulled up to OVDD with weak pull-up resistors (2 k - 10 k): SDA, SCL, SMI, SRESET/SDMA12, TBEN/SDMA13, CHKSTOP_IN/SDMA14, TRIG_IN/RCS2, and DRDY. It is recommended that the following PCI control signals be pulled up to LVDD with weak pull-up resistors (2 k - 10 k): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, and TRDY. The resistor values may need to be adjusted stronger to reduce induced noise on specific board designs. The following pins have internal pull-up resistors enabled at all times: REQ[3:0], REQ4/DA4, TCK, TDI, TMS, and TRST. See Table 1 on page 6 for more information. The following pins have internal pull-up resistors enabled only while device is in the reset state: GNT4/DA5, MDL0, FOE, RCS0, SDRAS, SDCAS, CKE, AS, MCP, MAA[0:2], PMAA[0:2], and QACK/DA0. See Table 1 on page 6 for more information. 50 PC8245 2171D-HIREL-06/04 PC8245 The following pins are reset configuration pins: GNT4/DA5, MDL[0], FOE, RCS0, CKE, AS, MCP, QACK/DA0, MAA[0:2], PMAA[0:2], SDMA[1:0], MDH[16:31], and PLL_CFG[0:4]/DA[10:15]. These pins are sampled during reset to configure the device. The PLL_CFG[0:4] signals are sampled a few clocks after the negation of HRST_CPU and HRST_CTRL. Reset configuration pins should be tied to GND via 1 k pull-down resistors to ensure a logic zero level is read into the configuration bits during reset if the default logic-one level is not desired. Any other unused active low input pins should be tied to a logic-one level via weak pullup resistors (2 k - 10 k) to the appropriate power supply listed in Table 1 on page 6. Unused active high input pins should be tied to GND via weak pull-down resistors (2 k - 10 k). PCI Reference Voltage - LVDD The PC8245 PCI reference voltage (LVDD) pins should be connected to 3.3 0.3V power supply if interfacing the PC8245 into a 3.3V PCI bus system. Similarly, the LVDD pins should be connected to 5.0V 5% power supply if interfacing the PC8245 into a 5V PCI bus system. For either reference voltage, the PC8245 always performs 3.3V signaling as described in the PCI Local Bus Specification (Rev. 2.2). The PC8245 tolerates 5V signals when interfaced into a 5V PCI bus system. PC8245 Compatibility with PC8240 The PC8245 AC timing specifications are backwards-compatible with those of the PC8240, except for the requirements of item 11 in Table 9 on page 31. Timing adjustments are needed as specified for T O S (SDRAM_SYNC_IN to sys_logic_clk offset) time requirements. The PC8245 does not support the SDRAM flow-through memory interface. The nominal core VDD power supply changes from 2.5V on the PC8240 to 1.8/2.0V on the PC8245. See Table "Recommended Operating Conditions" on page 12 for details. The PC8245 PLL_CFG[0:4] setting 0x02 (0b00010) has a different `PCI to Mem' and `Mem to CPU' multiplier ratio than the same setting on the PC8240, and thus, is not backwards-compatible. See Table 16 on page 45 for details. The PC8245 PLL_CFG[0:4] settings 0x08 (0b01000), 0x0C (0b01100), 0x12 (0b10010), 0x18 (0b11000), 0x1C (0b11100), and 0x1D (0b11101) are capable of accepting a subset of the PCI_SYNC_IN input frequency range of that of the PC8240, and thus, may not be fully backwards-compatible. See Table 16 on page 45 for details. There are two additional reset configuration signals on the PC8245 which are not used as reset configuration signals on the PC8240: SDMA0 and SDMA1. The SDMA0 reset configuration pin selects between the PC8245 DUART or the PC8240 backwards compatible mode PCI_CLK[0:4] functionality on these multiplexed signals. The default state (logic 1) of SDMA0 selects the PC8240 backwards compatible mode of PCI_CLK[0:4] functionality while a logic 0 state on the SDMA0 signal selects DUART functionality. Note if using the DUART mode, four of the five PCI clocks, PCI_CLK[0:3], are not available. The SDMA1 reset configuration pin selects between PC8245 extended ROM functionality or PC8240 backwards-compatible functionality on the multiplexed signals: TBEN, CHKSTOP_IN, SRESET, TRIG_IN, and TRIG_OUT. The default state (logic 1) of SDMA1 selects the PC8240 backwards compatible mode functionality, while a logic 0 state on the SDMA1 signal selects extended ROM functionality. Note if using the extended ROM mode, TBEN, CHKSTOP_IN, SRESET, TRIG_IN, and TRIG_OUT functionality are not available. 51 2171D-HIREL-06/04 The driver names and capability of the pins for the PC8245 and that of the PC8240 vary slightly. Please refer to the Drive Capability table (for the ODCR register at 0x73) in the PC8240 Integrated Processor Hardware Specifications and Table 5 on page 24 for more details. The programmable PCI output valid and output hold feature controlled by bits in the power management configuration register 2 (PMCR2) <0x72> has changed slightly in the PC8245. For the PC8240, three bits, PMCR2[6:4] = PCI_HOLD_DEL, are used to select one of eight possible PCI output timing configurations. PMCR2[6:5] are software controllable but initially are set by the reset configuration state of the MCP and CKE signals, respectively; PMCR2[4] can be changed by software. The default configuration for PMCR2[6:4] = 0b110 since the MCP and CKE signals have internal pull-up resistors, but this default configuration does not select 33 or 66 MHz PCI operation output timing parameters for the PC8240; this choice is made by software. For the PC8245, only 2 bits in the power management configuration register 2 (PMCR2), PMCR2[5:4] = PCI_HOLD_DEL, control the variable PCI output timing. PMCR2[5:4] are software controllable but initially are set by the inverted reset configuration state of the MCP and CKE signals, respectively. The default configuration for PMCR2[5:4] = 0b00 since the MCP and CKE signals have internal pull-up resistors and the values from these signals are inverted; this default configuration selects 66 MHz PCI operation output timing parameters. There are four programmable PCI output timing configurations on the PC8245, see Table 10 on page 33 for details. Voltage sequencing requirements for the PC8245 are similar to those for the PC8240; however, there are two changes which are applicable for the PC8245. First, there is an additional requirement for the PC8245 that the non-PCI input voltages (VIN) must not be greater than GVDD or OVDD by more than 0.6V at all times including during power-on reset (see caution 5 in Table "Recommended Operating Conditions" on page 12). Second, for the PC8245, LV DD must not exceed OV DD by more than 3.0V at any time including during power-on reset (see caution 10 in Table "Recommended Operating Conditions" on page 12); the allowable separation between LVDD and OVDD is 3.6V for the PC8240. There is no LAVDD input voltage supply signal on the PC8245 since the SDRAM clock delay-locked loop (DLL) has power supplied internally. Signal D17 should be treated as a no connect for the PC8245. 52 PC8245 2171D-HIREL-06/04 PC8245 JTAG Configuration Signals Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical. The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 30 on page 54 allows the COP to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be tied to HRESET so that it is asserted when the system reset signal (HRESET) is asserted ensuring that the JTAG scan chain is initialized during power-on. The COP header shown in Figure 30 on page 54 adds many benefits -- breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features are possible through this interface -- and can be as inexpensive as an unpopulated footprint for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). There is no standardized way to number the COP header shown in Figure 30 on page 54; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 30 on page 54 is common to all known emulators. 53 2171D-HIREL-06/04 Figure 30. COP Connector Diagram PC8245 From Target Board Sources (if any) (6) SRESET SRESET HRESET HRST_CPU HRST_CTRL 13 11 HRESET 10 k 10 k SRESET 10 k 1 2 3 4 5 6 7 8 9 10 11 12 13 Key No pin 15 16 10 k 4 OVdd OVdd OVdd OVdd TRST TRST GND 6 15 Key 14 COP Header 1 k 10 k (3) 1 3 7 CHKSTOP_IN TMS TDO TDI TCK 2 NC 10 NC 12 NC OVdd OVdd 10 k (4) 9 OVdd 10 k (2) 5 8 COP Connector Physical Pin Out VDD_SENSE OVdd CHKSTOP_IN (7) TMS TDO TDI TCK QACK (1) 16 Notes: 54 1. QACK is an output on the PC8245 and is not required at the COP header for emulation. 2. RUN/STOP normally found on pin 5 of the COP header is not implemented on the PC8245. Connect pin 5 of the COP header to OVDD with a 1 k pull-up resistor. 3. CKSTP_OUT normally found on pin 15 of the COP header is not implemented on the PC8245. Connect pin 15 of the COP header to OVDD with a 10 k pull-up resistor. 4. Pin 14 is not physically present on the COP header. 5. Component not populated. 6. SRESET functions as output SDMA12 in extended ROM mode. 7. CHKSTOP_IN functions as output SDMA14 in extended ROM mode. PC8245 2171D-HIREL-06/04 PC8245 Document Revision History Table 19 provides a revision history for this hardware specification. Table 18. Revision History Revision Number Substantive Change(s) 2171A Alpha site release 2171B Updated document template. Section "Output Driver Characteristic" on page 24 -- Changed the driver type names in Table 2 on page 14 to match with the names used in the "MPC8245 User's Manual". Section "Pinout Listing" on page 6 -- Updated driver type names for signals in Table 1 on page 6 to match with names used in the "MPC8245 Integrated Processor User's Manual". Section "Recommended Operating Conditions" on page 12 -- Updated Table 6 on page 25 to refer to new PLL Tables for VCO limits. Section "Output AC Timing Specification" on page 33 -- Added item 12e to Table 10 on page 33 for SDRAM_SYNC_IN to Output Valid timing. Section "Package Parameters for the PC8245" on page 43 -- Updated Solder Balls information to 62Sn/36PB/2Ag. Section "PLL Configuration" on page 45 -- Updated PLL Table 16 on page 45 and Table 17 on page 47 and appropriate notes to reflect changes of VCO ranges for memory and CPU frequencies. Section "System Design Information" on page 49 -- Updated voltage sequencing requirements in Table "Recommended Operating Conditions" on page 12 and removed Section "Power Supply Sizing" on page 49. Section "JTAG Configuration Signals" on page 53 -- Updated TRST information and Figure 30 on page 54. New Section "Power Supply Sizing" on page 49 -- Updated the range of I/O power consumption numbers for OVDD and GVDD to correct values as in Table 3 on page 22. Updated fastest frequency combination to 66:100:350 MHz. Section "Thermal Management Information" on page 15 -- Updated list for Heat Sink and Thermal Interface vendors. Section "Ordering Information" on page 56 -- Changed format of Ordering Information section. Added tables to reflect part number specifications also available. 2171C Globally changed EPIC to PIC Section "Output Driver Characteristic" on page 24 -- Note 5: Changed register reference from 0x72 to 0x73 Section "Power Characteristics" on page 22 -- Table 3: Updated power dissipation numbers based on latest characterization data Section "Thermal Characteristics" on page 14 -- Table 2 on page 14: Updated table to show more thermal specifications. Section "AC Electrical Characteristics" on page 24 -- Table 6 on page 25: Updated minimum memory bus value to 50 MHz. Section "Clock AC Specifications" on page 25 -- Changed equations for DLL locking range based on characterization data. Added updates and reference to AN2164 for note 6. Added table defining Tdp parameters. Labeled N value in Figure 9 on page 27 through Figure 12 on page 30. Section "Input AC Timing Specifications" on page 31 -- Table 9 on page 31: Changed bit definitions for tap points. Updated note on Tos and added reference to AN2164 for note 7. Updated Figure 13 on page 32 to show significance of Tos. Section "I2C AC Timing Specifications" on page 36 -- Added column for SDRAM_CLK at 133 MHz Sections "Package Parameters for the PC8245" on page 43 and "Pin Assignments and Package Dimensions" on page 44 -- Corrected packaging information to state TBGA packaging. Section "Pinout Listing" on page 6 -- Corrected some signals in Table 15 on page 41 which were missing overbars in the Rev 1.0 release of the document. Section "PLL Configuration" on page 45 -- Updated note 10 of Table 16 on page 45 and Table 17 on page 47. Section "Decoupling Recommendations" on page 49 -- Changed sentence recommendation regarding decoupling capacitors. Section "Ordering Information" -- Updated format of tables in Ordering Information section. 2171D Product specification release subsequent to product qualification 55 2171D-HIREL-06/04 Differences with Commercial Part Table 19. Differences with commercial part Temperature range Commercial Part Industrial Part Military Part Tc = 0 to 105C Tc = -40 to 110C Tc = -55C to 125C Ordering Information PC8245 M TP U 300 D Type (PCX8245 if prototype) Revision Level Temperature Range: Tcase M: -55C, +125C Package TP: TBGA Maximum Internal Processor Speed(1) 300: 300 MHz 333: 333 MHz Screening Level(1) U: Upscreening Note: 1. For availability of the different versions, contact your ATMEL sale office. 56 PC8245 2171D-HIREL-06/04 PC8245 Definitions Datasheet Status Description Table 20. Datasheet Status Datasheet Status Validity Objective specification This datasheet contains target and goal specifications for discussion with the customer and application validation Before design phase Target specification This datasheet contains target or goal specifications for product development Valid during the design phase Preliminary specification -site This datasheet contains preliminary data. Additional data may be published at a later date and could include simulation results Valid before characterization phase Preliminary specification -site This datasheet also contains characterization results Valid before the industrialization phase Product specification This datasheet contains final product specifications Valid for production purposes Limiting Values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stresses above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability Application Information Where application information is given, it is advisory and does not form part of the specification Life Support Applications These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. 57 2171D-HIREL-06/04 PC8245 Table of Contents Features ................................................................................................1 Description ...........................................................................................1 Screening/Quality/Packaging ............................................................. 1 General Description .............................................................................2 Block Diagram ...................................................................................................... 2 General Parameters ............................................................................................. 3 Features ................................................................................................................ 3 Pinout Listing ........................................................................................................ 6 Electrical and Thermal Characteristics ...............................................................11 DC Electrical Characteristics ..................................................................... 11 Absolute Maximum Ratings ................................................................................ 11 Recommended Operating Conditions ................................................................. 12 Thermal Characteristics ...................................................................................... 14 Thermal Management Information............................................................. 15 Internal Package Conduction Resistance .................................................. 18 Adhesives and Thermal Interface Materials ............................................... 18 Power Characteristics ......................................................................................... 22 DC Electrical Characteristics ............................................................23 Static Characteristics ........................................................................................... 23 Output Driver Characteristic ............................................................................... 24 AC Electrical Characteristics .............................................................................. 24 Clock AC Specifications ............................................................................. 25 Input AC Timing Specifications .................................................................. 31 Output AC Timing Specification ................................................................. 33 I2C AC Timing Specifications ...................................................................... 36 EPIC Serial Interrupt Mode AC Timing Specifications ............................... 40 IEEE 1149.1 (JTAG) AC Timing Specifications ......................................... 41 Package Description .........................................................................43 Package Parameters for the PC8245 ................................................................. 43 Pin Assignments and Package Dimensions ....................................................... 44 PLL Configuration ............................................................................................... 45 System Design Information ................................................................................. 49 PLL Power Supply Filtering........................................................................ 49 Power Supply Sizing .................................................................................. 49 Decoupling Recommendations .................................................................. 49 Connection Recommendations .................................................................. 50 Pull-up/Pull-down Resistor Requirements ................................................. 50 PCI Reference Voltage - LVDD .................................................................. 51 i 2171D-HIREL-06/04 PC8245 Compatibility with PC8240 ........................................................... 51 JTAG Configuration Signals ....................................................................... 53 Document Revision History ..............................................................55 Differences with Commercial Part ...................................................56 Ordering Information .........................................................................56 Definitions ..........................................................................................57 Datasheet Status Description ............................................................................. 57 Life Support Applications .................................................................................... 57 ii PC8245 2171D-HIREL-06/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Literature Requests www.atmel.com/literature Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. (c) Atmel Corporation 2004. All rights reserved. Atmel (R) and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries. Motorola (R) is the registered trademark of Motorola, Inc. PowerPC (R) is the registered trademark of IBM Corp. Other terms and product names may be the trademarks of others. Printed on recycled paper. 2171D-HIREL-06/04 iv PC8245 2171D-HIREL-06/04