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Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet PSoC 62 MCU PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet General Description PSoC(R) 6 MCU is a high-performance, ultra-low-power and secure MCU platform, purpose-built for IoT applications. The CY8C62x6/7 product line, based on the PSoC 6 MCU platform, is a combination of a high-performance microcontroller with low-power flash technology, digital programmable logic, high-performance analog-to-digital conversion and standard communication and timing peripherals. Features 32-bit Dual CPU Subsystem Segment LCD Drive (R) 150-MHz Arm Cortex(R)-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit (MPU) 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU User-selectable core logic operation at either 1.1 V or 0.9 V Active CPU current slope with 1.1-V core operation Cortex-M4: 40 A/MHz Cortex-M0+: 20 A/MHz Active CPU current slope with 0.9-V core operation Cortex-M4: 22 A/MHz Cortex-M0+: 15 A/MHz Two DMA controllers with 16 channels each Memory Subsystem Low-Power 1.7-V to 3.6-V Operation Six power modes for fine-grained power management Deep Sleep mode current of 7 A with 64-KB SRAM retention On-chip Single-In Multiple Out (SIMO) DC-DC buck converter, <1 A quiescent current Backup domain with 64 bytes of memory and real-time clock Flexible Clocking Options On-chip crystal oscillators (16 to 35 MHz, and 32 kHz) Phase-locked loop (PLL) for multiplying clock frequencies 8-MHz Internal Main Oscillator (IMO) with 2% accuracy Ultra-low-power 32-kHz Internal Low-speed Oscillator (ILO) Frequency-locked loop (FLL) for multiplying IMO frequency Quad SPI (QSPI)/Serial Memory Interface (SMIF) Execute-In-Place (XIP) from external quad SPI Flash On-the-fly encryption and decryption 4-KB cache for greater XIP performance with lower power Supports single, dual, quad, dual-quad, and octal interfaces with throughput up to 640 Mbps Cypress Semiconductor Corporation Document Number: 002-18449 Rev. *J Serial Communication * Nine run-time configurable serial communication blocks (SCBs) 2 Eight SCBs: configurable as SPI, I C, or UART 2 One Deep Sleep SCB: configurable as SPI or I C USB full-speed device interface Audio Subsystem Two pulse density modulation (PDM) channels and one I2S channel with time division multiplexed (TDM) mode Timing and Pulse-Width Modulation 1-MB application flash, 32-KB auxiliary flash (AUXflash), and 32-KB supervisory flash (SFlash); read-while-write (RWW) support. Two 8-KB flash caches, one for each CPU. 288-KB SRAM with power and data retention control One-time-programmable (OTP) 1-Kb eFuse array Supports up to 99 segments and up to 8 commons Thirty-two timer/counter/pulse-width modulators (TCPWM) Center-aligned, edge, and pseudo-random modes Comparator-based triggering of Kill signals Programmable Analog 12-bit 1-Msps SAR ADC with differential and single-ended modes and 16-channel sequencer with result averaging Two low-power comparators available in Deep Sleep and Hibernate modes Built-in temperature sensor connected to ADC One 12-bit voltage-mode digital-to-analog converter (DAC) with < 2-s settling time Two opamps with low-power operation modes Up to 100 Programmable GPIOs Two Smart I/OTM ports (16 I/Os) enable Boolean operations on GPIO pins; available during system Deep Sleep Programmable drive modes, strengths, and slew rates Six overvoltage-tolerant (OVT) pins Capacitive Sensing 198 Champion Court Cypress CapSense(R) provides best-in-class signal-to-noise ratio (SNR), liquid tolerance, and proximity sensing Enables dynamic usage of both self and mutual sensing Automatic hardware tuning (SmartSenseTM) * San Jose, CA 95134-1709 * 408-943-2600 Revised June 22, 2020 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Security Built into Platform Architecture ROM-based root of trust via uninterruptible Secure Boot Step-wise authentication of execution images Secure execution of code in execute-only mode for protected routines All Debug and Test ingress paths can be disabled Up to eight Protection Contexts Profiler Eight counters provide event or duration monitoring of on-chip resources Packages 124-BGA 80-WLCSP (in 0.33 and 0.43 mm heights) Thin 80-WLCSP (0.33 mm height) (qualification in process) Cryptography Accelerator Hardware acceleration for symmetric and asymmetric cryptographic methods and hash functions True random number generation (TRNG) function Programmable Digital Twelve programmable logic blocks, each with 8 Macrocells and an 8-bit data path (called universal digital blocks or UDBs) Usable as drag-and-drop Boolean primitives (gates, registers), or as Verilog-programmable blocks Cypress-provided peripheral component library using UDBs to implement functions such as communication peripherals (for example, LIN, UART, SPI, I2C, S/PDIF and other protocols), Waveform Generators, Pseudo-Random Sequence (PRS) generation, and many other functions. Document Number: 002-18449 Rev. *J Page 2 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Contents Development Ecosystem ................................................. 4 PSoC 6 MCU Resources............................................. 4 PSoC Creator .............................................................. 4 ModusToolboxTM IDE and the PSoC 6 SDK ............... 6 Blocks and Functionality ................................................. 7 Functional Description..................................................... 9 CPU and Memory Subsystem ..................................... 9 System Resources .................................................... 11 Programmable Analog Subsystem............................ 13 Programmable Digital................................................ 15 Fixed-Function Digital................................................ 15 GPIO ......................................................................... 16 Special-Function Peripherals .................................... 17 Pinouts ............................................................................ 20 Power Supply Considerations....................................... 32 Electrical Specifications ................................................ 36 Absolute Maximum Ratings....................................... 36 Device-Level Specifications ...................................... 37 Document Number: 002-18449 Rev. *J Analog Peripherals .................................................... Digital Peripherals ..................................................... Memory ..................................................................... System Resources .................................................... Ordering Information...................................................... PSoC 6 MPN Decoder .............................................. Packaging........................................................................ Acronyms ........................................................................ Document Conventions ................................................. Unit of Measure ......................................................... Errata ............................................................................... Revision History ............................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC(R) Solutions ...................................................... Cypress Developer Community................................. Technical Support ..................................................... 43 52 54 55 63 64 65 69 71 71 72 75 76 76 76 76 76 76 Page 3 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Development Ecosystem PSoC 6 MCU Resources Cypress provides a wealth of data at www.cypress.com to help you select the right PSoC device and quickly and effectively integrate it into your design. The following is an abbreviated, hyperlinked list of resources for PSoC 6 MCU: Overview: PSoC Portfolio, PSoC Roadmap Product Selectors: PSoC 6 MCU Application Notes cover a broad range of topics, from basic to advanced level, and include the following: AN221774: Getting Started with PSoC 6 MCU AN210781: Getting Started with PSoC 6 MCU with BLE AN218241: PSoC 6 MCU Hardware Design Guide AN213924: PSoC 6 MCU Device Firmware Update Guide AN215656: PSoC 6 MCU Dual-CPU System Design AN219528: PSoC 6 MCU Power Reduction Techniques AN221111: PSoC 6 MCU Creating a Secure System AN85951: PSoC 4, PSoC 6 MCU CapSense Design Guide Code Examples demonstrate product features and usage, and are also available on Cypress GitHub repositories. Technical Reference Manuals (TRMs) provide detailed descriptions of PSoC 6 MCU architecture and registers. PSoC 6 MCU Programming Specification provides the information necessary to program PSoC 6 MCU nonvolatile memory. Development Tools ModusToolboxTM enables cross platform code development with a robust suite of tools and software libraries CY8CKIT-062-Wi-Fi-BT PSoC 6 WiFi-BT Pioneer Kit: a low-cost hardware platform that enables design and debug of the PSoC 62 CY8C62x6/7 product line, and the CYW4343W Wi-Fi + Bluetooth Combo Chip PSoC 6 CAD libraries provide footprint and schematic support for common tools. BSDL files and IBIS models are also available. Training Videos are available on a wide range of topics including the PSoC 6 MCU 101 series Cypress Developer Community enables connection with fellow PSoC developers around the world, 24 hours a day, 7 days a week, and hosts a dedicated PSoC 6 MCU Community PSoC Creator PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables you to design hardware and firmware systems concurrently, based on PSoC 6 MCU. As shown below, with PSoC Creator, you can: 1. Explore the library of 200+ Components in PSoC Creator 4. Co-design your application firmware and hardware in the PSoC Creator IDE or build project for third-party IDE 2. Drag and drop Component icons to complete your hardware system design in the main design workspace 5. Prototype your solution with the PSoC 6 Pioneer Kits. If a design change is needed, PSoC Creator and Components 3. Configure Components using the Component Configuration enable you to make changes on-the-fly without the need for Tools and the Component datasheets hardware revisions. Document Number: 002-18449 Rev. *J Page 4 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Figure 1. PSoC Creator Schematic Entry and Components Document Number: 002-18449 Rev. *J Page 5 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet ModusToolboxTM IDE and the PSoC 6 SDK ModusToolbox is an Eclipse-based development environment on Windows, macOS, and Linux platforms that includes the ModusToolbox IDE and the PSoC 6 SDK. The ModusToolbox IDE brings together several device resources, middleware, and firmware to build an application. Using ModusToolbox, you can enable and configure device resources and middleware libraries, write C/C++/assembly source code, and program and debug the device. The PSoC 6 SDK is the software development kit for the PSoC 6 MCU. The SDK makes it easier to develop firmware for supported devices without the need to understand the intricacies of the device resources. For additional details on using the Cypress tools, refer to AN221774: Getting Started with PSoC 6 MCU and the documentation and help integrated into ModusToolbox. As Figure 2 shows, with the ModusToolbox IDE, you can: 1. Create a new application based on a list of starter applications, filtered by kit or device, or browse the collection of code examples online. 2. Configure device resources in design.modus to build your hardware system design in the workspace. 3. Add software components or middleware. 4. Develop your application firmware. Figure 2. ModusToolbox IDE Resources and Middleware Document Number: 002-18449 Rev. *J Page 6 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Blocks and Functionality Figure 3 shows the major subsystems and a simplified view of their interconnections. The color coding shows the lowest power mode where a block is still functional. For example, the SRAM is functional down to Deep Sleep mode. Figure 3. Block Diagram System Resources System DeepSleep Mode Clocks OVP LVD IMO ECO POR BOD FLL 2x PLL Buck Regulator 2x MCWDT PILO XRES Reset Backup Regs Backup Domain ILO WDT RTC WCO PMIC Control Crypto DES/TDES, AES, SHA, CRC, TRNG, RSA/ECC Accelerator Flash 1024 KB + 32 KB + 32 KB 8 KB cache for each CPU SRAM 288 KB System Interconnect (Multi Layer AHB, IPC, MPU/SMPU) Cortex M4F CPU 150/50 MHz, 1.1/0.9 V SWJ, ETM, ITM, CTI 2x DMA Controller Temperature Sensor CapSense LP Comparator CPU Subsystem Cortex M0+ CPU 100/25 MHz, 1.1/0.9 V SWJ, MTB, CTI 2x Opamp LCD Peripheral Interconnect (MMIO, PPU) System Hibernate Mode DAC 12 bit Programmable Digital : 12x UDB 32x TCPWM SCB 8x I2C, SPI, UART, or LIN I2C or SPI Audio Subsystem DSI Power Peripheral clock (PCLK) System LP/ULP Mode CPUs Active/Sleep 2x Smart I/O Ports Programmable Analog SAR ADC 12 bit I/O Subsystem: Up to 100 GPIOs (including 6 OVT), 124-BGA Package Boundary Scan PSoC 62 MCU CY8C62x6, CY8C62x7 SARMUX Color Key: Power Modes and Domains I2S PDM-PCM Profiler eFuse: 1024 bits QSPI (SMIF) with OTF Encryption /Decryption USB-FS USB PHY ROM 128 KB Document Number: 002-18449 Rev. *J Page 7 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet There are three debug access ports, one each for CM4 and CM0+, and a system port. PSoC 6 MCU devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. All device interfaces can be permanently disabled (device security) for applications concerned about attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when maximum device security is enabled. The security level is settable by the user. Complete debug-on-chip functionality enables full device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. The ModusToolbox and PSoC Creator Integrated Development Environments (IDE) provide fully integrated programming and debug support for these devices. The SWJ (SWD and JTAG) interface is fully compatible with industry-standard third party probes. With the ability to disable debug features, with very robust flash protection, and by allowing customer-proprietary functionality to be implemented in on-chip programmable blocks, PSoC 6 provides a very high level of security. Document Number: 002-18449 Rev. *J Page 8 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Functional Description The following sections provide an overview of the features, capabilities and operation of each functional block identified in the block diagram in Figure 2. For more detailed information, refer to the following three references. Peripheral Driver Library (PDL) Application Programming Interface (API) Reference Manual. PDL provides low-level drivers for each resource in the device, and supports the entire PSoC 6 MCU portfolio. PDL is an element of the PSoC 6 SDK, which is installed as part of ModusToolbox. With ModusToolbox installed, you can access the PDL API reference manual either from the Documentation tab of the Quick Panel, or you can navigate directly to it at <install_directory>\ModusToolbox_<version>\libraries\psoc6sw-<version>\docs. Using PDL should be the primary means of interacting with the PSoC 6 MCU hardware. Architecture Technical Reference Manual (TRM) The architecture TRM provides a detailed description of each resource in the device. This is the next reference to use if it is necessary to understand the operation of the hardware below the software provided by PDL. It describes the architecture and functionality of each resource and explains the operation of each resource in all modes. It provides specific guidance regarding the use of associated registers. Register Technical Reference Manual The register TRM provides a complete list of all registers in the device. It includes the breakdown of all register fields, their possible settings, read/write accessibility, and default states. All registers that have a reasonable use in typical applications have functions to access them from within PDL. Note that ModusToolbox and PDL may provide software default conditions for some registers that are different from and override the hardware defaults. CM0+ is the secondary CPU; it is used to implement system calls and device-level security, safety, and protection features. CM0+ provides a secure, uninterruptible boot function. This guarantees that post boot, system integrity is checked and memory and peripheral access privileges are enforced. CM0+ implements the Armv6-M Thumb instruction set (defined in the Armv6-M Architecture Reference Manual). The CPUs have the following power draw, at VDDD = 3.3 V and using the internal buck regulator: Table 1. Active Current Slope at VDDD = 3.3 V Using the Internal Buck Regulator System Power Mode ULP CPU CPU There are two Arm Cortex CPUs: The Cortex-M4 (CM4) has single-cycle multiply, a floating-point unit (FPU), and a memory protection unit (MPU). It can run at up to 150 MHz. This is the main CPU, designed for a short interrupt response time, high code density, and high throughput. CM4 implements a version of the Thumb instruction set based on Thumb-2 technology (defined in the Armv7-M Architecture Reference Manual). The Cortex-M0+ (CM0+) has single-cycle multiply, and an MPU. It can run at up to 100 MHz; however, for CM4 speeds above 100 MHz, CM0+ and bus peripherals are limited to half the speed of CM4. Thus, for CM4 running at 150 MHz, CM0+ and peripherals are limited to 75 MHz. Document Number: 002-18449 Rev. *J 15 A/MHz 20 A/MHz Cortex-M4 22 A/MHz 40 A/MHz The CPUs can be selectively placed in their Sleep and Deep Sleep power modes as defined by Arm. Both CPUs have nested vectored interrupt controllers (NVIC) for rapid and deterministic interrupt response, and wakeup interrupt controllers (WIC) for CPU wakeup from Deep Sleep power mode. The CPUs have extensive debug support. PSoC 6 has a debug access port (DAP) that acts as the interface for device programming and debug. An external programmer or debugger (the "host") communicates with the DAP through the device serial wire debug (SWD) or Joint Test Action Group (JTAG) interface pins. Through the DAP (and subject to device security restrictions), the host can access the device memory and peripherals as well as the registers in both CPUs. Each CPU offers debug and trace features as follows: CM4 supports six hardware breakpoints and four watchpoints, 4-bit embedded trace macrocell (ETM), serial wire viewer (SWV), and printf()-style debugging through the single wire output (SWO) pin. CM0+ supports four hardware breakpoints and two watchpoints, and a micro trace buffer (MTB) with 4-KB dedicated RAM. CPU and Memory Subsystem PSoC 6 has multiple bus masters, as Figure 2 shows. They are: CPUs, DMA controllers, QSPI, USB, and a Crypto block. Generally, all memory and peripherals can be accessed and shared by all bus masters through multi-layer Arm AMBA high-performance bus (AHB) arbitration. Accesses between CPUs can be synchronized using an inter-processor communication (IPC) block. LP Cortex-M0+ PSoC 6 also has an Embedded Cross Trigger for synchronized debugging and tracing of both CPUs. Interrupts This product line has 147 system and peripheral interrupt sources and supports interrupts and system exceptions on both CPUs. CM4 has 147 interrupt request lines (IRQ), with the interrupt source `n' directly connected to IRQn. CM0+ has 32 interrupts IRQ[31:0] with configurable mapping of one system interrupt source to any of the IRQ[31:0]. Each interrupt supports configurable priority levels (eight levels for CM4 and four levels for CM0+). One system interrupt can be mapped to each of the CPUs' non-maskable interrupts (NMI). Up to 41 interrupt sources are capable of waking the device from Deep Sleep power mode using the WIC. Refer to the technical reference manual for details. Page 9 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet DMA Controllers Memory There are two DMA controllers with 16 channels each, which support CPU-independent accesses to memory and peripherals. The descriptors for DMA channels can be in SRAM or flash. Therefore, the number of descriptors are limited only by the size of the memory. Each descriptor can transfer data in two nested loops with configurable address increments to the source and destination. The size of data transfer per descriptor varies based on the type of DMA channel. Refer to the technical reference manual for detail. PSoC 6 contains flash, SRAM, ROM, and eFuse memory blocks. There is up to 1 MB of application flash, organized in 256-KB sectors. There are also two 32-KB flash sectors: Auxiliary flash (AUXflash), typically used for EEPROM emulation Supervisory flash (SFlash). Data stored in SFlash includes device trim values, Flash Boot code, and encryption keys. After the device transitions into the Secure lifecycle stage, SFlash can no longer be changed. The flash has 128-bit-wide accesses to reduce power. Write operations can be performed at the row level. A row is 512 bytes. Read operations are supported in both Low Power and Ultra-Low Power modes, however write operations may not be performed in Ultra-Low Power mode. Cryptography Accelerator (Crypto) This subsystem consists of hardware implementation and acceleration of cryptographic functions and random number generators. The Crypto subsystem supports the following: Encryption/Decryption Functions Data Encryption Standard (DES) Triple DES (3DES) Advanced Encryption Standard (AES) (128-, 192-, 256-bit) Elliptic Curve Cryptography (ECC) RSA cryptography functions Hashing functions Secure Hash Algorithm (SHA) SHA-1 SHA-224/-256/-384/-512 Message authentication functions (MAC) Hashed message authentication code (HMAC) Cipher-based message authentication code (CMAC) 32-bit cyclic redundancy code (CRC) generator Random number generators Pseudo random number generator (PRNG) True random number generator (TRNG) Protection Units This product line has multiple types of protection units to control erroneous or unauthorized access to memory and peripheral registers. CM4 and CM0+ have Arm MPUs for protection at the bus master level. Other bus masters use additional MPUs. Shared memory protection units (SMPUs) help implement memory protection for memory resources that are shared among multiple bus masters. Peripheral protection units (PPU) are similar to SMPUs but are designed for protecting the peripheral register space. Protection units support memory and peripheral access attributes including address range, read/write, code/data, privilege level, secure/non-secure, and protection context. Flash The flash controller has two caches, one for each CPU. Each cache is 8 KB, with 4-way set associativity. SRAM Up to 256 KB of SRAM is provided. Power control and retention granularity is implemented in 32 KB blocks allowing the user to control the amount of memory retained in Deep Sleep. Memory is not retained in Hibernate mode. ROM The 128-KB ROM, also referred to as the supervisory ROM (SROM), provides code (ROM Boot) for several system functions. The ROM contains device initialization, flash write, security, eFuse programming, and other system-level routines. ROM code is executed only by the CM0+ CPU, in protection context 0. A system function can be initiated by either CPU, or through the DAP. This causes an NMI in CM0+, which causes CM0+ to execute the system function. eFuse A one-time-programmable (OTP) eFuse array consists of 1024 bits, of which 512 are reserved for system use such as die ID, device ID, initial trim settings, device life cycle, and security settings. The remaining bits are available for storing security key information, hash values, unique IDs or similar custom content. Each fuse is individually programmed; once programmed (or "blown"), its state cannot be changed. Blowing a fuse transitions it from the default state of 0 to 1. To program an eFuse, VDDIO0 must be at 2.5 V 5%, at 14 mA. Because blowing an eFuse is an irreversible process, programming is recommended only in mass production under controlled factory conditions. For more information, see PSoC 6 MCU Programming Specifications. Protection units are configured at secure boot to control access privileges and rights for bus masters and peripherals. Up to eight protection contexts (secure boot is in protection context 0) allow access privileges for memory and system resources to be set by the secure boot process per protection context by bus master and code privilege level. Multiple protection contexts are supported on CPUs and other bus masters. Document Number: 002-18449 Rev. *J Page 10 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 2. Address Map for CM4 and CM0+ (continued) Boot Code Two blocks of code, ROM Boot and Flash Boot, are pre-programmed into the device and work together to provide device startup and configuration, basic security features, life-cycle stage management and other system functions. ROM Boot Flash Boot Flash boot is a firmware module stored in SFlash and application flash. It ensures that only a validated application may run on the device. It also ensures that the firmware image has not been modified, such as by a malicious third party. Flash boot: Is validated by ROM Boot Runs after ROM Boot and before the user application Enables system calls Configures the Debug Access Port Launches the user application in the CM0+ (CM4 for single-CPU devices). If the user application cannot be validated, then flash boot ensures that the device is transitioned into a safe state. Memory Map Both CPUs have a fixed address map, with shared access to memory and peripherals. The 32-bit (4 GB) address space is divided into the regions shown in Table 2. Note that code can be executed from the Code and External RAM. Table 2. Address Map for CM4 and CM0+ Address Range 0x0000 0000 - 0x1FFF FFFF 0x2000 0000 - 0x3FFF FFFF Name Use Code Program code region. Data can also be placed here. It includes the exception vector table, which starts at address 0. SRAM Data region. This region is not supported in PSoC 6. All peripheral registers. Code cannot be executed 0x4000 0000 - 0x5FFF FFFF Peripheral from this region. CM4 bit-band in this region is not supported in PSoC 6. 0x6000 0000 - 0x9FFF FFFF External RAM SMIF or Quad SPI, (see the QSPI Interface Serial Memory Interface (SMIF) section). Code can be executed from this region. 0xA000 0000 - 0xDFFF FFFF External Device Not used. Document Number: 002-18449 Rev. *J Name Use Private Provides access to 0xE000 0000 - 0xE00F FFFF Peripheral peripheral registers within Bus the CPU core. 0xE010 0A000 - 0xFFFF FFFF On a device reset, the boot code in ROM is the first code to execute. This code performs the following: Integrity checks of flash boot code Device trim setting (calibration) Setting the device protection units Setting device access restrictions for secure life-cycle states ROM cannot be changed and acts as the Root of Trust in a secure system. Address Range Device Device-specific system registers. The device memory map shown in Table 3 applies to both CPUs. That is, the CPUs share access to all PSoC 6 MCU memory and peripheral registers. Table 3. Internal Memory Address Map for CM4 and CM0+ Address Range Memory Type 0x0000 0000 - 0x0001 FFFF ROM 0x0800 0000 - 0x0804 7FFF SRAM 0x1000 0000 - 0x100F FFFF Application flash Size 128 KB Up to 288 KB Up to 1 MB Auxiliary flash, can be 0x1400 0000 - 0x1400 7FFF used for EEPROM em- 32 KB ulation 0x1600 0000 - 0x1600 7FFF Supervisory flash 32 KB Note that the SRAM is located in the Arm Code region for both CPUs (see Table 2). There is no physical memory located in the CPUs' Arm SRAM regions. System Resources Power System The power system provides assurance that voltage levels are as required for each respective mode and will either delay mode entry (on power-on reset (POR), for example) until voltage levels are as required for proper function or generate resets (brown-out detect (BOD)) when the power supply drops below specified levels. The design guarantees safe chip operation between power supply voltage dropping below specified levels (for example, below 1.7 V) and the reset occurring. There are no voltage sequencing requirements. The VDDD supply (1.7 to 3.6 V) powers an on-chip buck regulator or a low-dropout regulator (LDO), selectable by the user. In addition, both the buck and the LDO offer a selectable (0.9 or 1.1 V) core operating voltage (VCCD). The selection lets users choose between two system power modes: System Low Power (LP) operates VCCD at 1.1 V and offers high performance, with no restrictions on device configuration. System Ultra Low Power (ULP) operates VCCD at 0.9 V for exceptional low power, but imposes limitations on clock speeds. In addition, a backup domain adds an "always on" functionality using a separate power domain supplied by a backup supply (VBACKUP) such as a battery or supercapacitor. It includes a real-time clock (RTC) with alarm feature, supported by a 32.768-kHz watch crystal oscillator (WCO), and power-management IC (PMIC) control. Refer to Power Supply Considerations for more details. Page 11 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Power Modes Clock System PSoC 6 MCU can operate in four system and three CPU power modes. These modes are intended to minimize the average power consumption in an application. For more details on power modes and other power-saving configuration options, see the application note, AN219528: PSoC 6 MCU Low-Power Modes and Power Reduction Techniques and the Architecture TRM, Power Modes chapter. Figure 4 shows that the clock system consists of the following: Power modes supported by PSoC 6 MCUs, in the order of decreasing power consumption, are: System Low Power (LP) - All peripherals and CPU power modes are available at maximum speed System Ultra Low Power (ULP) - All peripherals and CPU power modes are available, but with limited speed CPU Active - CPU is executing code in system LP or ULP mode CPU Sleep - CPU code execution is halted in system LP or ULP mode CPU Deep Sleep - CPU code execution is halted and system Deep Sleep is requested in system LP or ULP mode System Deep Sleep - Only low-frequency peripherals are available after both CPUs enter CPU Deep Sleep mode System Hibernate - Device and I/O states are frozen and the device resets on wakeup CPU Active, Sleep, and Deep Sleep are standard Arm-defined power modes supported by the Arm CPU instruction set architecture (ISA). System LP, ULP, Deep Sleep and Hibernate modes are additional low-power modes supported by PSoC 6 MCU. Internal main oscillator (IMO) Internal low-speed oscillator (ILO) Precision ILO (PILO) Watch crystal oscillator (WCO) External MHz crystal oscillator (ECO) External clock input One phase-locked loop (PLL) One frequency-locked loop (FLL) Clocks may be buffered and brought out to a pin on a smart I/O port. Internal Main Oscillator (IMO) The IMO is the primary source of internal clocking. It is trimmed during testing to achieve the specified accuracy. The IMO default frequency is 8 MHz and tolerance is 2%. Internal Low-speed Oscillator (ILO) The ILO is a very low power oscillator, nominally 32 kHz, which operates in all power modes. The ILO can be calibrated against a higher accuracy clock for better accuracy. Precision ILO (PILO) PILO is a 32.768-kHz clock that can provide a more accurate clock than ILO when periodically calibrated using a high-accuracy clock such as the ECO. Figure 4. Clocking Diagram Path Mux IMO (FLL/PLL) FLL EXTCLK PLL Root Clock Mux (Clks_HF[i] are Root Clocks) Predivider (1/2/4/8) CM4 Clock CLK_HF[0] dsi_in0 Predivider (1/2/4/8) CLK_HF[1] Predivider (1/2/4/8) CLK_HF[2] Predivider (1/2/4/8) CLK_HF[3] Predivider (1/2/4/8) CLK_HF[4] clk_peri Audio dsi_in1 CM0+ Clock Peripheral Clock Dividers ECO CLK_PATH2 ALTHF dsi_out <1:0> SMIF dsi_in2 CLK_PATH3 USB dsi_in3 CLK_PATH4 ILO* clk_ext dsi_in4 CLK_LF WCO* PILO Document Number: 002-18449 Rev. *J Page 12 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet External Crystal Oscillators Reset Figure 5 shows all of the external crystal oscillator circuits for this product line. The component values shown are typical; check the ECO Specifications for the crystal values, and the crystal datasheet for the load capacitor values. The ECO and WCO require balanced external load capacitors. For more information, see the TRM and AN218241, PSoC 6 MCU Hardware Design Considerations. PSoC 6 MCU can be reset from a variety of sources: Power-on reset (POR) to hold the device in reset while the power supply ramps up to the level required for the device to function properly. POR activates automatically at power-up. Brown-out detect (BOD) reset to monitor the digital voltage supply VDDD and generate a reset if VDDD falls below the minimum required logic operating voltage. Figure 5. Oscillator Circuits MHz XTAL CL / 2 WCO_OUT, P0.1 WCO_IN, P0.0 ECO_IN, P12.6 ECO_OUT, P12.7 PSoC 6 Watchdog timer (WDT or MCWDT) to reset the device if firmware fails to service it within a specified timeout period. Software-initiated reset to reset the device on demand using firmware. Logic-protection fault can trigger an interrupt or reset the device if unauthorized operating conditions occur; for example, reaching a debug breakpoint while executing privileged code. Hibernate wakeup reset to bring the device out of the system Hibernate low-power mode. 32.768 kHz XTAL CL / 2 CL / 2 CL / 2 Watchdog Timers (WDT, MCWDT) PSoC 6 MCU has one WDT and two multi-counter WDTs (MCWDTs). The WDT has a 16-bit free-running counter. Each MCWDT has two 16-bit counters and one 32-bit counter, with multiple operating modes. All of the 16-bit counters can generate a watchdog device reset. All of the counters can generate an interrupt on a match event. The WDT is clocked by the ILO. It can do interrupt/wakeup generation in system LP/ULP, Deep Sleep, and Hibernate power modes. The MCWDTs are clocked by LFCLK (ILO or WCO). It can do periodic interrupt/wakeup generation in system LP/ULP and Deep Sleep power modes. Clock Dividers Integer and fractional clock dividers are provided for peripheral use and timing purposes. There are: Eight 8-bit clock dividers Sixteen 16-bit integer clock dividers Four 16.5-bit fractional clock dividers One 24.5-bit fractional clock divider Trigger Routing PSoC 6 MCU contains a trigger multiplexer block. This is a collection of digital multiplexers and switches that are used for routing trigger signals between peripheral blocks and between GPIOs and peripheral blocks. There are two types of trigger routing. Trigger multiplexers have reconfigurability in the source and destination. There are also hardwired switches called "one-to-one triggers", which connect a specific source to a destination. The user can enable or disable the route. Document Number: 002-18449 Rev. *J External reset (XRES) to reset the device using an external input. The XRES pin is active LOW - a logic `1' on the pin has no effect and a logic `0' causes reset. The pin is pulled to logic `1' inside the device. XRES is available as a dedicated pin. Reset events are asynchronous and guarantee reversion to a known state. Some of the reset sources are recorded in a register, which is retained through reset and allows software to determine the cause of the reset. Programmable Analog Subsystem 12-bit SAR ADC The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks at that frequency to do a 12-bit conversion. One of three internal reference voltages may be used for an ADC reference voltage. The references are, VDD, VDD/2, and VREF (nominally 1.2 V and trimmed to 1%). An external reference may also be used, by either driving the VREF pin or routing an external reference to GPIO pin P9.7. These reference options allow ratio-metric readings or absolute readings at the accuracy of the reference used. The input range of the ADC is the full supply voltage between VSS and VDDA/VDDIOA. The SAR ADC may be configured with a mix of single-ended and differential signals in the same configuration. The SAR ADC's sample-and-hold (S/H) aperture is programmable to allow sufficient time for signals with a high impedance to settle sufficiently, if required. System performance will be 65 dB for true 12-bit precision provided appropriate references are used and system noise levels permit it. To improve performance in noisy conditions, an external bypass capacitor for the internal reference amplifier (through the fixed "VREF" pin), may be added. The SAR is connected to a fixed set of pins through an input multiplexer. The multiplexer cycles through the selected channels autonomously (sequencer scan) and does so with zero switching overhead (that is, the aggregate sampling bandwidth is equal to 1 Msps whether it is for a single channel or distributed over several channels). The result of each channel is buffered, so that an interrupt may be triggered only when a full scan of all channels is complete. Also, a pair of range registers can be set to detect and cause an interrupt if an input exceeds a minimum Page 13 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet and/or maximum value. This allows fast detection of out-of-range values without having to wait for a sequencer scan to be completed and the CPU to read the values and check for out-of-range values in software. The SAR can also be connected, under firmware control, to most other GPIO pins via the Analog Multiplexer Bus (AMUXBUS). The SAR is not available in Deep Sleep and Hibernate modes as it requires a high -speed clock (up to 18 MHz). The SAR operating range is 1.71 to 3.6 V. Continuous Time Block mini (CTBm) with Two Opamps Temperature Sensor An on-chip temperature sensor is part of the SAR and may be scanned by the SAR ADC. It consists of a diode, which is biased by a current source that can be disabled to save power. The temperature sensor may be connected directly to the SAR ADC as one of the measurement channels. The ADC digitizes the temperature sensor's output and a Cypress-supplied software function may be used to convert the reading to temperature which includes calibration and linearization. The opamps also support operation in system Deep Sleep mode, with lower performance and reduced power consumption. This block consists of two opamps, which have their inputs and outputs connected to pins and other analog blocks, as Figure 6 shows. They have three power modes (high, medium, and low) and a comparator mode. The opamps can be used to buffer SAR inputs and DAC outputs. The non-inverting inputs of these opamps can be connected to either of two pins, thus allowing independent sensors to be used at different times. The pin selection can be made via firmware. Low-Power Comparators Two low-power comparators are provided, which can operate in all power modes. This allows other analog system resources to be disabled while retaining the ability to monitor external voltage levels during system Deep Sleep and Hibernate modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode (Hibernate) where the system wake-up circuit is activated by a comparator-switch event. Figure 6 shows an overview of the analog subsystem. 12-bit Digital-Analog Converter There is a 12-bit voltage mode DAC on the chip, which can settle in less than 2 s. The DAC may be driven by the DMA controllers to generate user-defined waveforms. The DAC output from the chip can either be the resistive ladder output (highly linear near ground) or a buffered output using an opamp in the CTBm block. Figure 6. Analog Subsystem VSSA OA1 Legend GPIO Switches AMUX Splitter Switches SAR ADC Switches CTBm Switches CTDAC Switches LPCOMP Switches AMUXBUS A AMUXBUS B CapSense Switches Document Number: 002-18449 Rev. *J Page 14 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Programmable Digital Complementary output for PWMs Smart I/O Smart I/O is a programmable logic fabric that enables Boolean operations on signals traveling from device internal resources to the GPIO pins or on signals traveling into the device from external sources. A Smart I/O block sits between the GPIO pins and the high-speed I/O matrix (HSIOM) and is dedicated to a single port. Selectable start, reload, stop, count, and capture event signals for each TCPWM; with rising edge, falling edge, both edges, and level trigger options. The TCPWM has a Kill input to force outputs to a predetermined state. In this device there are: There are two Smart I/O blocks: one on Port 8 and one on Port 9. When Smart I/O is not enabled, all signals on Port 8 and Port 9 bypass the Smart I/O hardware. Smart I/O supports: System Deep Sleep operation Boolean operations without CPU intervention Asynchronous or synchronous (clocked) operation Each Smart I/O block contains a data unit (DU) and eight lookup tables (LUTs). The DU: Performs unique functions based on a selectable opcode. Can source input signals from internal resources, the GPIO port, or a value in the DU register. Each LUT: Has three selectable input sources. The input signals may be sourced from another LUT, an internal resource, an external signal from a GPIO pin, or from the DU. Acts as a programmable Boolean logic table. Can be synchronous or asynchronous. Universal Digital Blocks (UDBs) and Port Interfaces This product line has 12 UDBs; the UDB array also provides a switched digital system interconnect (DSI) fabric that allows signals from peripherals and ports to be routed to and through the UDBs for communication and control. Fixed-Function Digital Timer/Counter/Pulse-width Modulator (TCPWM) Block The TCPWM supports the following operational modes: Timer-counter with compare Timer-counter with capture Quadrature decoding Pulse width modulation (PWM) Pseudo-random PWM PWM with dead time Up, down, and up/down counting modes. Clock prescaling (division by 1, 2, 4, ... 64, 128) Double buffering of compare/capture and period values Underflow, overflow, and capture/compare output signals Supports interrupt on: Terminal count - Depends on the mode; typically occurs on overflow or underflow Capture/compare - The count is captured to the capture register or the counter value equals the value in the compare register Document Number: 002-18449 Rev. *J Eight 32-bit TCPWMs Twenty-four 16-bit TCPWMs Serial Communication Blocks (SCB) This product line has 9 SCBs: Eight can implement either I2C, UART, or SPI. One SCB (SCB #8) can operate in system Deep Sleep mode with an external clock; this SCB can be either SPI slave or I2C slave. I2C Mode: The SCB can implement a full multi-master and slave interface (it is capable of multimaster arbitration). This block can operate at speeds of up to 1 Mbps (Fast Mode Plus). It also supports EZI2C, which creates a mailbox address range and effectively reduces I2C communication to reading from and writing to an array in the memory.The SCB supports a 256-byte FIFO for receive and transmit. The I2C peripheral is compatible with I2C standard-mode, Fast Mode, and Fast Mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. UART Mode: This is a full-feature UART operating at up to 8 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows the addressing of peripherals connected over common Rx and Tx lines. Common UART functions such as parity error, break detect, and frame error are supported. A 256-byte FIFO allows much greater CPU service latencies to be tolerated. SPI Mode: The SPI mode supports full Motorola SPI, TI Secure Simple Pairing (SSP) (essentially adds a start pulse that is used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block supports an EZSPI mode in which the data interchange is reduced to reading and writing an array in memory. The SPI interface operates with a 25-MHz clock. USB Full-Speed Device Interface PSoC 6 incorporates a full-speed USB device interface. The device can have up to eight endpoints. A 512-byte SRAM buffer is provided and DMA is supported. Page 15 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet QSPI Interface Serial Memory Interface (SMIF) A serial memory interface is provided, running at up to 80 MHz. It supports single, dual, quad, dual-quad and octal SPI configurations, and supports up to four external memory devices. It supports two modes of operation: Memory-mapped I/O (MMIO), a command mode interface that provides data access via the SMIF registers and FIFOs Execute in Place (XIP), in which AHB reads and writes are directly translated to SPI read and write transfers. In XIP mode, the external memory is mapped into the PSoC 6 MCU internal address space, enabling code execution directly from the external memory. To improve performance, a 4-KB cache is included. XIP mode also supports AES-128 on-the-fly encryption and decryption, enabling secure storage and access of code and data in the external memory. Input threshold select (CMOS or LVTTL) Hold mode for latching previous state (used for retaining the I/O state in system Hibernate mode) Selectable slew rates for dV/dt-related noise control to improve EMI The pins are organized in logical entities called ports, which are up to 8 pins in width. Data output and pin state registers store, respectively, the values to be driven on the pins and the input states of the pins. Every pin can generate an interrupt if enabled; each port has an interrupt request (IRQ) associated with it. LCD The port 1 pins are capable of overvoltage-tolerant (OVT) operation, where the input voltage may be higher than VDDD. OVT pins are commonly used with I2C, to allow powering the chip OFF while maintaining a physical connection to an operating I2C bus without affecting its functionality. This block drives LCD commons and segments; routing is available to most of the GPIOs. One to eight of the GPIOs must be used for commons, the rest can be used for segments. GPIO pins can be ganged to source or sink higher values of current. GPIO pins, including OVT pins, may not be pulled up higher than the absolute maximum; see Electrical Specifications. The LCD block has two modes of operation: high speed (8 MHz) and low speed (32 kHz). Both modes operate in system LP and ULP modes. Low-speed mode operates with reduced contrast in system Deep Sleep mode - review the number of common and segment lines, viewing angle requirements, and prototype performance before using this mode. During power-on and reset, the pins are forced to the analog input drive mode, with input and output buffers disabled, so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as the high-speed I/O matrix (HSIOM) is used to multiplex between various peripheral and analog signals that may connect to an I/O pin. GPIO Analog performance is affected by GPIO switching noise. In order to get the best analog performance, the following frequency and drive mode constraints must be applied. The DRIVE_SEL values (refer to Table 4) represent drive strengths (see the Architecture and Register TRMs for further detail). This product line has up to 100 GPIOs, which implement: Eight drive strength modes: Analog input mode (input and output buffers disabled) Input only Weak pull-up with strong pull-down Strong pull-up with weak pull-down Open drain with strong pull-down Open drain with strong pull-up Strong pull-up with strong pull-down Weak pull-up with weak pull-down Table 4. DRIVE_SEL Values Ports Max Frequency Ports 0, 1 8 MHz Drive Strength for VDDD 2.7 V Drive Strength for VDDD > 2.7 V DRIVE_SEL 2 DRIVE_SEL 3 Port 2 50 MHz DRIVE_SEL 1 DRIVE_SEL 2 Ports 3 to 10 16 MHz; 25 MHz for SPI DRIVE_SEL 2 DRIVE_SEL 3 Ports 11 to 13 80 MHz for SMIF (QSPI). DRIVE_SEL 1 DRIVE_SEL 2 Ports 9 and 10 Slow slew rate setting for TQFP Packages for ADC performance No restrictions No restrictions Document Number: 002-18449 Rev. *J Page 16 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Special-Function Peripherals CapSense Audio Subsystem Capacitive touch sensors are designed for user interfaces that rely on human body capacitance to detect the presence of a finger on or near a sensor. Cypress CapSense solutions bring elegant, reliable, and simple capacitive touch sensing functions to applications including IoT, industrial, automotive, and home appliances. This subsystem consists of the following hardware blocks: One Inter-IC Sound (I2S) interface Two pulse-density modulation (PDM) to pulse-code modulation (PCM) decoder channels The I2S interface implements two independent hardware FIFO buffers - TX and RX, which can operate in master or slave mode. The following features are supported: The Cypress-proprietary CapSense technology offers the following features: Best-in-class signal-to-noise ratio (SNR) and robust sensing under harsh and noisy conditions Self-capacitance (CSD) and mutual-capacitance (CSX) sensing methods Support for various widgets, including buttons, matrix buttons, sliders, touchpads, and proximity sensors High-performance sensing across a variety of materials Best-in-class liquid tolerance The I2S interface is commonly used to connect with audio codecs, simple DACs, and digital microphones. SmartSense auto-tuning technology that helps avoid complex manual tuning processes The PDM-to-PCM decoder implements a single hardware Rx FIFO that decodes a stereo or mono 1-bit PDM input stream to PCM data output. The following features are supported: Superior immunity against external noise Spread-spectrum clocks for low radiated emissions Gesture and built-in self-test libraries Ultra-low power consumption An integrated graphical CapSense tuner for real-time tuning, testing, and debugging 2 Multiple data formats - I S, left-justified, Time Division Multiplexed (TDM) mode A, and TDM mode B Programmable channel/word lengths - 8/16/18/20/24/32 bits Internal/external clock operation. Up to 192 ksps Interrupt mask events - trigger, not empty, full, overflow, underflow, watchdog Configurable FIFO trigger level with DMA support Programmable data output word length - 16/18/20/24 bits Programmable gain amplifier (PGA) for volume control - from -12 dB to +10.5 dB in 1.5 dB steps Configurable PDM clock generation. Range from 384 kHz to 3.072 MHz ADC Droop correction and configurable decimation rate for sampling; up to 48 ksps The CapSense subsystem slope ADC offers the following features: Programmable high-pass filter gain Selectable 8- or 10-bit resolution Interrupt mask events - not empty, overflow, trigger, underflow Configurable FIFO trigger level with DMA support Selectable input range: GND to VREF and GND to VDDA on any GPIO input The PDM-to-PCM decoder is commonly used to connect to digital PDM microphones. Up to two microphones can be connected to the same PDM Data line. Measurement of VDDA against an internal reference without the use of GPIO or external components CapSense Subsystem The CSD block has two programmable current sources, which offer the following features: CapSense is supported in PSoC 6 MCU through a CapSense sigma-delta (CSD) hardware block. It is designed for high-sensitivity self-capacitance and mutual-capacitance measurements, and is specifically built for user interface solutions. In addition to CapSense, the CSD hardware block supports three general-purpose functions. These are available when CapSense is not being used. Alternatively, two or more functions can be time-multiplexed in an application under firmware control. The four functions supported by the CSD hardware block are: CapSense 10-bit ADC Programmable current sources (IDAC) Comparator Document Number: 002-18449 Rev. *J IDAC 7-bit resolution Sink and source current modes A current source programmable from 37.5 nA to 609 A Two IDACs that can be used in parallel to form one 8-bit IDAC Comparator The CapSense subsystem comparator operates in the system Low Power and Ultra-Low Power modes. The inverting input is connected to an internal programmable reference voltage and the non-inverting input can be connected to any GPIO via the AMUXBUS. Page 17 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet CapSense Hardware Subsystem Figure 7 shows the high-level hardware overview of the CapSense subsystem, which includes a delta sigma converter, internal clock dividers, a shield driver, and two programmable current sources. The inputs are managed through analog multiplexed buses (AMUXBUS A/B). The input and output of all functions offered by the CSD block can be provided on any GPIO or on a group of GPIOs under software control, with the exception of the comparator output and external capacitors that use dedicated GPIOs. Self-capacitance is supported by the CSD block using AMUXBUS A, an external modulator capacitor, and a GPIO for each sensor. There is a shield electrode (optional) for self-capacitance sensing. This is supported using AMUXBUS B and an optional external shield tank capacitor (to increase the drive capability of the shield driver) should this be required. Mutual-capacitance is supported by the CSD block using AMUXBUS A, two external integrated capacitors, and a GPIO for transmit and receive electrodes. The ADC does not require an external component. Any GPIO that can be connected to AMUXBUS A can be an input to the ADC under software control. The ADC can accept VDDA as an input without needing GPIOs (for applications such as battery voltage measurement). The two programmable current sources (IDACs) in general-purpose mode can be connected to AMUXBUS A or B. They can therefore connect to any GPIO pin. The comparator resides in the delta-sigma converter. The comparator inverting input can be connected to the reference. Both comparator inputs can be connected to any GPIO using AMUXBUS B; see Figure 6. The reference has a direct connection to a dedicated GPIO; see Table 7. The CSD block can operate in active and sleep CPU power modes, and seamlessly transition between system LP and ULP modes. It can be powered down in system Deep Sleep and Hibernate modes. Upon wakeup from Hibernate mode, the CSD block requires re-initialization. However, operation can be resumed without re-initialization upon exit from Deep Sleep mode, under firmware control. Figure 7. CapSense Hardware Subsystem AMUXBUS A B GPIO Pin CSD Sensor 1 GPIO Cell Clock Input CS1 I / O Configured for CSD Mode GPIO Pin GPIO Cell CSD Sensor 2 CS2 CSD Hardware Block C MOD Pin CMO D C SH_TANK Sense clock Clock Generator GPIO Pin ( optional ) Modulator Clock Shield Drive Circuit GPIO Pin GPIO Cell Compensation IDAC CSHIELD Shield Electrode Modulator IDAC GPIO Pin Tx I / O Configured for CSX Mode CSX Sensor 3 CS3 Rx GPIO Pin C INTA Pin CINT A I / O for General Purpose Mode CINT B Document Number: 002-18449 Rev. *J C INTB Pin IDAC control GPIO Cell GPIO Cell Sigma Delta Converter Raw Count VREF GPIO Cell GPIO Cell ADC Input IDAC Outputs Comp Input Page 18 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Figure 8 shows the high-level software overview. Cypress provides a middleware library for each function to enable quick integration. User applications interact only with middleware to implement functions of the CSD block. The middleware interacts with underlying drivers to access hardware as necessary. The CSD driver facilitates time-multiplexing of the CSD hardware if more than one piece of CSD-related middleware is present in a project. It prevents access conflicts in this case. CapSense and ADC middleware use the CSD interrupt to implement non-blocking sensing and A-to-D conversion. Therefore, interrupt service routines are a defined part of the middleware, which must be initialized by the application. Middleware and drivers can operate on either CPU. Cypress recommends using the middleware only in one CPU. If both CPUs must access the CSD driver, memory access should be managed in the application. CapSense middleware has configurator software to enable fast configuration and incorporating it into middleware. It also has a tuner for performance evaluation and real-time tuning of the system. Both can be launched from the ModusToolbox IDE or in standalone mode. The tuner requires the EZI2C communication interface in the application to enable real-time tuning capability. The tuner can update configuration parameters directly in the device as well as in the configurator. Refer to AN85951: PSoC 4 and PSoC 6 MCU CapSense Design Guide for more details on CSX sensing, CSD sensing, shield electrode usage and its benefits, and capacitive system design guidelines. Refer to the middleware API reference guide available in the PSoC 6 SDK for more detail on middleware. Figure 8. CapSense Software/Firmware Subsystem Application Program Software Middleware Comp IDAC ADC CapSense Configurator Tuner SCB Driver (EZI2C) CSD Driver GPIO / Clock Drivers SCB CSD Block GPIOs / Clock Hardware and Drivers Document Number: 002-18449 Rev. *J Page 19 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Pinouts Note: The CY8C62x6/CY8C62x7 datasheet web page contains a spreadsheet with a consolidated list of pinouts and pin alternate functions with HSIOM mapping. GPIO ports are powered by VDDx pins as follows: P0: VBACKUP P1: VDDD. Port 1 pins are overvoltage tolerant (OVT). P2, P3, P4: VDDIO2 P5, P6, P7, P8: VDDIO1 P9, P10: VDDIOA, VDDA (VDDIOA, when present, and VDDA must be connected together on the PCB) P11, P12, P13: VDDIO0 P14: VDDUSB Table 5. Packages and Pin Information Pin VDDD VCCD VDDA VDDIOA VDDIO0 VDDIO1 VDDIO2 VBACKUP VDDUSB VSS VDD_NS VIND1 VIND2 VBUCK1 VRF XRES VREF P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P2.0 Packages Pin Packages 124-BGA A1 A2 A12 A13 C4 K12 L4 D1 M1 B12, C3, D4, D10, K4, K10 80-WLCSP B11 A10 F1 A6 M1 D11 P11 A8, D1, P5, R8 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 124-BGA N2 L3 M3 N3 N1 M4 N4 L5 M5 N5 80-WLCSP - J1 J2 K2 K3 K1 F1 B13 E3 E2 E1 F3 F2 G3 G2 G1 H3 H2 H1 J3 M2 K11 L10 M11 N10 G10 C10 D9 E10 F9 G8 F11 H11 H9 K9 J10 - P3.3 P3.4 P3.5 P4.0 P4.1 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 L6 M6 N6 L7 M7 N7 L8 M8 N8 L9 M9 N9 N10 M10 L10 L11 M11 N11 M12 N12 M9 N8 R6 P7 L8 M7 R4 N6 J8 K7 L6 R2 P3 N4 M5 Document Number: 002-18449 Rev. *J Page 20 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 5. Packages and Pin Information (continued) Pin Packages P6.7 P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7 P8.0 P8.1 P8.2 P8.3 124-BGA M13 L13 L12 K13 N13 K11 J13 J12 J11 H13 H12 H11 G13 80-WLCSP J6 N2 M3 L4 K5 L2 H3 K1 K3 J4 P8.4 P8.5 P8.6 P8.7 P9.0 P9.1 P9.2 P9.3 P9.4 P9.5 P9.6 P9.7 P10.0 P10.1 P10.2 P10.3 P10.4 G12 G11 F13 F12 E11 E12 E13 F11 D13 D12 D11 C13 C12 A11 B11 C11 A10 J2 H1 G2 E2 C2 F3 A2 G4 H5 B3 Document Number: 002-18449 Rev. *J Pin Packages P10.5 P10.6 P10.7 P11.0 P11.1 P11.2 P11.3 P11.4 P11.5 P11.6 P11.7 P12.0 124-BGA B10 C10 A9 B9 C9 A8 B8 C8 A7 B7 C7 A6 80-WLCSP D3 E4 F5 G6 A4 C4 B5 D5 C6 B7 P12.1 P12.2 P12.3 P12.4 P12.5 P12.6 P12.7 P13.0 P13.1 P13.2 P13.3 P13.4 P13.5 P13.6 P13.7 P14.0 / USBDP P14.1 / USBDM B6 C6 A5 B5 C5 A4 B4 B1 A3 B3 B2 C2 C1 D3 D2 L2 L1 D7 C8 B9 E6 E8 F7 H7 R10 P9 Page 21 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Each Port Pin has multiple alternate functions. These are defined in Table 6. Table 6. Multiple Alternate Functions[1] Port/ Pin ACT #0 ACT #1 P0.0 tcpwm[0].li tcpwm[1].lin ne[0]:0 e[0]:0 P0.1 DS #2 ACT #4 ACT #5 ACT #6 srss.ext_ clk:0 ACT #7 ACT #8 ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15 DS #4 scb[0].spi_ select1:0 peri.tr_io_in put[0]:0 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[0]: 0]:0 0 scb[0].spi_ select2:0 peri.tr_io_in put[1]:0 P0.2 tcpwm[0].li tcpwm[1].lin ne[1]:0 e[1]:0 scb[0].uart scb[0].i2c scb[0].spi_ _rx:0 _scl:0 mosi:0 P0.3 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[1]: 1]:0 0 scb[0].uart scb[0].i2c scb[0].spi_ _tx:0 _sda:0 miso:0 P0.4 tcpwm[0].li tcpwm[1].lin ne[2]:0 e[2]:0 scb[0].uart _rts:0 scb[0].spi_ clk:0 peri.tr_io_ output[0]:2 P0.5 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[2]: 2]:0 0 scb[0].uart _cts:0 scb[0].spi_ select0:0 peri.tr_io_ output[1]:2 P1.0 tcpwm[0].li tcpwm[1].lin ne[3]:0 e[3]:0 scb[7].uart scb[7].i2c scb[7].spi_ _rx:0 _scl:0 mosi:0 peri.tr_io_in put[2]:0 P1.1 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[3]: 3]:0 0 scb[7].uart scb[7].i2c scb[7].spi_ _tx:0 _sda:0 miso:0 peri.tr_io_in put[3]:0 P1.2 tcpwm[0].li tcpwm[1].lin ne[4]:4 e[12]:1 scb[7].uart _rts:0 scb[7].spi_ clk:0 P1.3 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[12 4]:4 ]:1 scb[7].uart _cts:0 scb[7].spi_ select0:0 P1.4 tcpwm[0].li tcpwm[1].lin ne[5]:4 e[13]:1 scb[7].spi_ select1:0 P1.5 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[14 5]:4 ]:1 scb[7].spi_ select2:0 P2.0 tcpwm[0].li tcpwm[1].lin ne[6]:4 e[15]:1 scb[1].uart scb[1].i2c scb[1].spi_ _rx:0 _scl:0 mosi:0 peri.tr_io_in put[4]:0 bless.mxd_ dpslp_ret_s witch_hv P2.1 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[15 6]:4 ]:1 scb[1].uart scb[1].i2c scb[1].spi_ _tx:0 _sda:0 miso:0 peri.tr_io_in put[5]:0 bless.mxd_ dpslp_ret_l do_ol_hv P2.2 tcpwm[0].li tcpwm[1].lin ne[7]:4 e[16]:1 scb[1].uart _rts:0 srss.ext_ clk:1 scb[1].spi_ clk:0 DS #5 DS #6 cpuss.swj_ trstn bless.mxd_ dpslp_buck_en Note 1. The notation for a signal is of the form IPName[x].signal_name[u]:y. IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name. For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources. Document Number: 002-18449 Rev. *J Page 22 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 6. Multiple Alternate Functions[1] (continued) Port/ Pin ACT #0 ACT #1 P2.3 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[16 7]:4 ]:1 P2.4 DS #2 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15 DS #4 scb[1].spi_ select0:0 bless.mxd_ dpslp_reset_n tcpwm[0].li tcpwm[1].lin ne[0]:5 e[17]:1 scb[1].spi_ select1:0 bless.mxd_ dpslp_clk_en P2.5 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[17 0]:5 ]:1 scb[1].spi_ select2:0 bless.mxd_ dpslp_isolate_n P2.6 tcpwm[0].li tcpwm[1].lin ne[1]:5 e[18]:1 scb[1].spi_ select3:0 bless.mxd_ dpslp_act_l do_en P2.7 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[18 1]:5 ]:1 P3.0 tcpwm[0].li tcpwm[1].lin ne[2]:5 e[19]:1 scb[2].uart scb[2].i2c scb[2].spi_ _rx:1 _scl:1 mosi:1 peri.tr_io_in put[6]:0 P3.1 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[19 2]:5 ]:1 scb[2].uart scb[2].i2c scb[2].spi_ _tx:1 _sda:1 miso:1 peri.tr_io_in put[7]:0 P3.2 tcpwm[0].li tcpwm[1].lin ne[3]:5 e[20]:1 scb[2].uart _rts:1 scb[2].spi_ clk:1 bless.mxd_ act_dbus_tx_en P3.3 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[20 3]:5 ]:1 scb[2].uart _cts:1 scb[2].spi_ select0:1 bless.mxd_ act_bpktctl P3.4 tcpwm[0].li tcpwm[1].lin ne[4]:5 e[21]:1 scb[2].spi_ select1:1 bless.mxd_ act_txd_rxd P3.5 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[21 4]:5 ]:1 scb[2].spi_ select2:1 bless.mxd_ dpslp_rcb_data P4.0 tcpwm[0].li tcpwm[1].lin ne[5]:5 e[22]:1 scb[7].uart scb[7].i2c scb[7].spi_ _rx:1 _scl:1 mosi:1 peri.tr_io_in put[8]:0 bless.mxd_ dpslp_rcb_clk P4.1 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[22 5]:5 ]:1 scb[7].uart scb[7].i2c scb[7].spi_ _tx:1 _sda:1 miso:1 peri.tr_io_in put[9]:0 bless.mxd_ dpslp_rcb_ le P5.0 tcpwm[0].li tcpwm[1].lin ne[4]:0 e[4]:0 scb[5].uart scb[5].i2c scb[5].spi_ _rx:0 _scl:0 mosi:0 audioss.clk peri.tr_io_in _i2s_if put[10]:0 scb[1].uart _cts:0 DS #5 DS #6 bless.mxd_ dpslp_xtal_en bless.mxd_ dpslp_dig_l do_en bless.mxd_ act_dbus_rx_en Note 1. The notation for a signal is of the form IPName[x].signal_name[u]:y. IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name. For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources. Document Number: 002-18449 Rev. *J Page 23 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 6. Multiple Alternate Functions[1] (continued) Port/ Pin ACT #0 ACT #1 DS #2 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15 DS #4 DS #5 DS #6 P5.1 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[4]: 4]:0 0 scb[5].uart scb[5].i2c scb[5].spi_ _tx:0 _sda:0 miso:0 audioss.tx peri.tr_io_in _sck put[11]:0 P5.2 tcpwm[0].li tcpwm[1].lin ne[5]:0 e[5]:0 scb[5].uart _rts:0 scb[5].spi_ clk:0 audioss.tx _ws P5.3 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[5]: 5]:0 0 scb[5].uart _cts:0 scb[5].spi_ select0:0 audioss.tx _sdo P5.4 tcpwm[0].li tcpwm[1].lin ne[6]:0 e[6]:0 scb[5].spi_ select1:0 audioss.rx _sck P5.5 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[6]: 6]:0 0 scb[5].spi_ select2:0 audioss.rx _ws P5.6 tcpwm[0].li tcpwm[1].lin ne[7]:0 e[7]:0 scb[5].spi_ select3:0 audioss.rx _sdi P5.7 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[7]: 7]:0 0 scb[3].spi_ select3:0 P6.0 tcpwm[0].li tcpwm[1].lin scb[8].i2 ne[0]:1 e[8]:0 c_scl:0 scb[3].uart scb[3].i2c scb[3].spi_ _rx:0 _scl:0 mosi:0 cpuss.fault _out[0] scb[8].spi _mosi:0 P6.1 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[8]: scb[8].i2 c_sda:0 0]:1 0 scb[3].uart scb[3].i2c scb[3].spi_ _tx:0 _sda:0 miso:0 cpuss.fault _out[1] scb[8].spi _miso:0 P6.2 tcpwm[0].li tcpwm[1].lin ne[1]:1 e[9]:0 scb[3].uart _rts:0 scb[3].spi_ clk:0 scb[8].spi _clk:0 P6.3 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[9]: 1]:1 0 scb[3].uart _cts:0 scb[3].spi_ select0:0 scb[8].spi _select0:0 P6.4 tcpwm[0].li tcpwm[1].lin scb[8].i2 ne[2]:1 e[10]:0 c_scl:1 scb[6].uart scb[6].i2c scb[6].spi_ _rx:2 _scl:2 mosi:2 peri.tr_io_in peri.tr_io_ put[12]:0 output[0]:1 cpuss.swj_ scb[8].spi swo_tdo _mosi:1 P6.5 tcpwm[0].li tcpwm[1].lin scb[8].i2 ne_compl[ e_compl[10 c_sda:1 2]:1 ]:0 scb[6].uart scb[6].i2c scb[6].spi_ _tx:2 _sda:2 miso:2 peri.tr_io_in peri.tr_io_ put[13]:0 output[1]:1 cpuss.swj_ scb[8].spi swdoe_tdi _miso:1 P6.6 tcpwm[0].li tcpwm[1].lin ne[3]:1 e[11]:0 scb[6].uart _rts:2 scb[6].spi_ clk:2 cpuss.swj_ scb[8].spi swdio_tms _clk:1 P6.7 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[11] 3]:1 :0 scb[6].uart _cts:2 scb[6].spi_ select0:2 cpuss.swj_ scb[8].spi swclk_tclk _select0:1 P7.0 tcpwm[0].li tcpwm[1].lin ne[4]:1 e[12]:0 scb[4].uart scb[4].i2c scb[4].spi_ _rx:1 _scl:1 mosi:1 peri.tr_io_in put[14]:0 cpuss.trac e_clock Note 1. The notation for a signal is of the form IPName[x].signal_name[u]:y. IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name. For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources. Document Number: 002-18449 Rev. *J Page 24 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 6. Multiple Alternate Functions[1] (continued) Port/ Pin ACT #0 ACT #1 DS #2 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15 P7.1 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[12 4]:1 ]:0 scb[4].uart scb[4].i2c scb[4].spi_ _tx:1 _sda:1 miso:1 P7.2 tcpwm[0].li tcpwm[1].lin ne[5]:1 e[13]:0 scb[4].uart _rts:1 scb[4].spi_ clk:1 P7.3 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[13 5]:1 ]:0 scb[4].uart _cts:1 scb[4].spi_ select0:1 P7.4 tcpwm[0].li tcpwm[1].lin ne[6]:1 e[14]:0 scb[4].spi_ select1:1 bless.ext_l- cpuss.trace_ na_rx_ctdata[3]:2 l_out P7.5 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[14 6]:1 ]:0 scb[4].spi_ select2:1 bless.ext_p cpuss.trace_ a_tx_ctdata[2]:2 l_out P7.6 tcpwm[0].li tcpwm[1].lin ne[7]:1 e[15]:0 scb[4].spi_ select3:1 bless.ext_p a_lna_cpuss.trace_ chip_en_o data[1]:2 ut P7.7 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[15 7]:1 ]:0 scb[3].spi_ cpuss.clk_ select1:0 fm_pump P8.0 tcpwm[0].li tcpwm[1].lin ne[0]:2 e[16]:0 scb[4].uart scb[4].i2c scb[4].spi_ _rx:0 _scl:0 mosi:0 peri.tr_io_in put[16]:0 P8.1 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[16 0]:2 ]:0 scb[4].uart scb[4].i2c scb[4].spi_ _tx:0 _sda:0 miso:0 peri.tr_io_in put[17]:0 P8.2 tcpwm[0].li tcpwm[1].lin ne[1]:2 e[17]:0 scb[4].uart _rts:0 scb[4].spi_ clk:0 P8.3 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[17 1]:2 ]:0 scb[4].uart _cts:0 scb[4].spi_ select0:0 P8.4 tcpwm[0].li tcpwm[1].lin ne[2]:2 e[18]:0 scb[4].spi_ select1:0 P8.5 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[18 2]:2 ]:0 scb[4].spi_ select2:0 P8.6 tcpwm[0].li tcpwm[1].lin ne[3]:2 e[19]:0 scb[4].spi_ select3:0 P8.7 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[19 3]:2 ]:0 scb[3].spi_ select2:0 DS #4 DS #5 DS #6 peri.tr_io_in put[15]:0 cpuss.trace_ data[0]:2 Note 1. The notation for a signal is of the form IPName[x].signal_name[u]:y. IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name. For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources. Document Number: 002-18449 Rev. *J Page 25 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 6. Multiple Alternate Functions[1] (continued) Port/ Pin ACT #0 ACT #1 DS #2 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15 P9.0 tcpwm[0].li tcpwm[1].lin ne[4]:2 e[20]:0 scb[2].uart scb[2].i2c scb[2].spi_ _rx:0 _scl:0 mosi:0 peri.tr_io_in put[18]:0 cpuss.trace_ data[3]:0 P9.1 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[20 4]:2 ]:0 scb[2].uart scb[2].i2c scb[2].spi_ _tx:0 _sda:0 miso:0 peri.tr_io_in put[19]:0 cpuss.trace_ data[2]:0 P9.2 tcpwm[0].li tcpwm[1].lin ne[5]:2 e[21]:0 scb[2].uart _rts:0 scb[2].spi_ clk:0 pass.dsi_c tb_cmp0:1 cpuss.trace_ data[1]:0 P9.3 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[21 5]:2 ]:0 scb[2].uart _cts:0 scb[2].spi_ select0:0 pass.dsi_c tb_cmp1:1 cpuss.trace_ data[0]:0 P9.4 tcpwm[0].li tcpwm[1].lin ne[7]:5 e[0]:2 scb[2].spi_ select1:0 P9.5 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[0]: 7]:5 2 scb[2].spi_ select2:0 P9.6 tcpwm[0].li tcpwm[1].lin ne[0]:6 e[1]:2 scb[2].spi_ select3:0 P9.7 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[1]: 0]:6 2 P10.0 tcpwm[0].li tcpwm[1].lin ne[6]:2 e[22]:0 scb[1].uart scb[1].i2c scb[1].spi_ _rx:1 _scl:1 mosi:1 peri.tr_io_in put[20]:0 cpuss.trace_ data[3]:1 P10.1 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[22 6]:2 ]:0 scb[1].uart scb[1].i2c scb[1].spi_ _tx:1 _sda:1 miso:1 peri.tr_io_in put[21]:0 cpuss.trace_ data[2]:1 P10.2 tcpwm[0].li tcpwm[1].lin ne[7]:2 e[23]:0 scb[1].uart _rts:1 scb[1].spi_ clk:1 cpuss.trace_ data[1]:1 P10.3 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[23 7]:2 ]:0 scb[1].uart _cts:1 scb[1].spi_ select0:1 cpuss.trace_ data[0]:1 P10.4 tcpwm[0].li tcpwm[1].lin ne[0]:3 e[0]:1 scb[1].spi_ audioss.p select1:1 dm_clk P10.5 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[0]: 0]:3 1 scb[1].spi_ audioss.p select2:1 dm_data P10.6 tcpwm[0].li tcpwm[1].lin ne[1]:6 e[2]:2 scb[1].spi_ select3:1 P10.7 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[2]: 1]:6 2 DS #4 DS #5 DS #6 Note 1. The notation for a signal is of the form IPName[x].signal_name[u]:y. IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name. For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources. Document Number: 002-18449 Rev. *J Page 26 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 6. Multiple Alternate Functions[1] (continued) Port/ Pin ACT #0 ACT #1 DS #2 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 P11.0 tcpwm[0].li tcpwm[1].lin ne[1]:3 e[1]:1 smif.spi_ scb[5].uart scb[5].i2c scb[5].spi_ select2 _rx:1 _scl:1 mosi:1 peri.tr_io_in put[22]:0 P11.1 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[1]: 1]:3 1 smif.spi_ scb[5].uart scb[5].i2c scb[5].spi_ select1 _tx:1 _sda:1 miso:1 peri.tr_io_in put[23]:0 P11.2 tcpwm[0].li tcpwm[1].lin ne[2]:3 e[2]:1 smif.spi_ scb[5].uart select0 _rts:1 scb[5].spi_ clk:1 P11.3 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[2]: 2]:3 1 smif.spi_ scb[5].uart data3 _cts:1 scb[5].spi_ select0:1 peri.tr_io_ output[0]:0 P11.4 tcpwm[0].li tcpwm[1].lin ne[3]:3 e[3]:1 smif.spi_ data2 scb[5].spi_ select1:1 peri.tr_io_ output[1]:0 P11.5 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[3]: 3]:3 1 smif.spi_ data1 scb[5].spi_ select2:1 P11.6 smif.spi_ data0 scb[5].spi_ select3:1 P11.7 smif.spi_ clk P12.0 tcpwm[0].li tcpwm[1].lin ne[4]:3 e[4]:1 smif.spi_ scb[6].uart scb[6].i2c scb[6].spi_ data4 _rx:0 _scl:0 mosi:0 peri.tr_io_in put[24]:0 P12.1 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[4]: 4]:3 1 smif.spi_ scb[6].uart scb[6].i2c scb[6].spi_ data5 _tx:0 _sda:0 miso:0 peri.tr_io_in put[25]:0 P12.2 tcpwm[0].li tcpwm[1].lin ne[5]:3 e[5]:1 smif.spi_ scb[6].uart data6 _rts:0 scb[6].spi_ clk:0 P12.3 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[5]: 5]:3 1 smif.spi_ scb[6].uart data7 _cts:0 scb[6].spi_ select0:0 P12.4 tcpwm[0].li tcpwm[1].lin ne[6]:3 e[6]:1 smif.spi_ select3 scb[6].spi_ select1:0 audioss.p dm_clk P12.5 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[6]: 6]:3 1 scb[6].spi_ select2:0 audioss.p dm_data P12.6 tcpwm[0].li tcpwm[1].lin ne[7]:3 e[7]:1 scb[6].spi_ select3:0 P12.7 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[7]: 7]:3 1 ACT #15 DS #4 DS #5 DS #6 Note 1. The notation for a signal is of the form IPName[x].signal_name[u]:y. IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name. For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources. Document Number: 002-18449 Rev. *J Page 27 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 6. Multiple Alternate Functions[1] (continued) Port/ Pin ACT #0 ACT #1 DS #2 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #12 P13.0 tcpwm[0].li tcpwm[1].lin ne[0]:4 e[8]:1 scb[6].uart scb[6].i2c scb[6].spi_ _rx:1 _scl:1 mosi:1 peri.tr_io_in put[26]:0 P13.1 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[8]: 0]:4 1 scb[6].uart scb[6].i2c scb[6].spi_ _tx:1 _sda:1 miso:1 peri.tr_io_in put[27]:0 P13.2 tcpwm[0].li tcpwm[1].lin ne[1]:4 e[9]:1 scb[6].uart _rts:1 scb[6].spi_ clk:1 P13.3 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[9]: 1]:4 1 scb[6].uart _cts:1 scb[6].spi_ select0:1 P13.4 tcpwm[0].li tcpwm[1].lin ne[2]:4 e[10]:1 scb[6].spi_ select1:1 P13.5 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[10 2]:4 ]:1 scb[6].spi_ select2:1 P13.6 tcpwm[0].li tcpwm[1].lin ne[3]:4 e[11]:1 scb[6].spi_ select3:1 P13.7 tcpwm[0].li tcpwm[1].lin ne_compl[ e_compl[11] 3]:4 :1 ACT #13 ACT #14 ACT #15 DS #4 DS #5 DS #6 Note 1. The notation for a signal is of the form IPName[x].signal_name[u]:y. IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name. For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources. Document Number: 002-18449 Rev. *J Page 28 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Analog, Smart I/O, and DSI alternate Port Pin functionality is provided in Table 10. Table 7. Port Pin Analog, Smart I/O, and DSI Functions Port/Pin Name Analog Digital HV DSI P0.0 P0.0 wco_in dsi[0].port_if[0] P0.1 P0.1 wco_out dsi[0].port_if[1] P0.2 P0.2 dsi[0].port_if[2] P0.3 P0.3 dsi[0].port_if[3] P0.4 P0.4 pmic_wakeup_in hibernate_wakeup[1] pmic_wakeup_out P0.5 P0.5 P1.0 dsi[1].port_if[0] P1.1 P1.1 dsi[1].port_if[1] P1.2 P1.2 dsi[1].port_if[2] P1.3 P1.4 P1.4 USB dsi[0].port_if[4] P1.0 P1.3 SMARTIO dsi[0].port_if[5] dsi[1].port_if[3] hibernate_wakeup[0] dsi[1].port_if[4] P1.5 P1.5 P14.0 USBDP dsi[1].port_if[5] P14.1 USBDM P2.0 P2.0 dsi[2].port_if[0] P2.1 P2.1 dsi[2].port_if[1] P2.2 P2.2 dsi[2].port_if[2] P2.3 P2.3 dsi[2].port_if[3] P2.4 P2.4 dsi[2].port_if[4] P2.5 P2.5 dsi[2].port_if[5] P2.6 P2.6 dsi[2].port_if[6] P2.7 P2.7 dsi[2].port_if[7] P3.0 P3.0 P3.1 P3.1 P3.2 P3.2 P3.3 P3.3 P3.4 P3.4 usb.usb_dp_pad usb.usb_dm_pad P3.5 P3.5 P4.0 P4.0 dsi[0].port_if[6] P4.1 P4.1 dsi[0].port_if[7] P4.2 P4.2 dsi[1].port_if[6] P4.3 P4.3 dsi[1].port_if[7] P5.0 P5.0 dsi[3].port_if[0] P5.1 P5.1 dsi[3].port_if[1] P5.2 P5.2 dsi[3].port_if[2] P5.3 P5.3 dsi[3].port_if[3] P5.4 P5.4 dsi[3].port_if[4] P5.5 P5.5 P5.6 P5.6 lpcomp.inp_comp0 dsi[3].port_if[5] P5.7 P5.7 lpcomp.inn_comp0 P6.0 P6.0 Document Number: 002-18449 Rev. *J dsi[3].port_if[6] dsi[3].port_if[7] dsi[4].port_if[0] Page 29 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 7. Port Pin Analog, Smart I/O, and DSI Functions (continued) Port/Pin Name P6.1 P6.1 Analog Digital HV DSI P6.2 P6.2 lpcomp.inp_comp1 dsi[4].port_if[2] P6.3 P6.3 lpcomp.inn_comp1 dsi[4].port_if[3] P6.4 P6.4 dsi[4].port_if[4] P6.5 P6.5 dsi[4].port_if[5] SMARTIO USB dsi[4].port_if[1] P6.6 P6.6 swd_data dsi[4].port_if[6] P6.7 P6.7 swd_clk dsi[4].port_if[7] P7.0 P7.0 P7.1 P7.1 csd.cmodpadd csd.cmodpads dsi[5].port_if[1] P7.2 P7.2 csd.csh_tankpadd csd.csh_tankpads dsi[5].port_if[2] P7.3 P7.3 csd.vref_ext dsi[5].port_if[3] P7.4 P7.4 dsi[5].port_if[4] P7.5 P7.5 dsi[5].port_if[5] P7.6 P7.6 P7.7 P7.7 P8.0 P8.0 dsi[11].port_if[0] smartio[8].io[0] P8.1 P8.1 dsi[11].port_if[1] smartio[8].io[1] P8.2 P8.2 dsi[11].port_if[2] smartio[8].io[2] P8.3 P8.3 dsi[11].port_if[3] smartio[8].io[3] P8.4 P8.4 dsi[11].port_if[4] smartio[8].io[4] P8.5 P8.5 dsi[11].port_if[5] smartio[8].io[5] P8.6 P8.6 dsi[11].port_if[6] smartio[8].io[6] P8.7 P8.7 dsi[11].port_if[7] smartio[8].io[7] P9.0 P9.0 ctb_oa0+ dsi[10].port_if[0] smartio[9].io[0] P9.1 P9.1 ctb_oa0- dsi[10].port_if[1] smartio[9].io[1] P9.2 P9.2 ctb_oa0_out dsi[10].port_if[2] smartio[9].io[2] P9.3 P9.3 ctb_oa1_out dsi[10].port_if[3] smartio[9].io[3] P9.4 P9.4 ctb_oa1- dsi[10].port_if[4] smartio[9].io[4] P9.5 P9.5 ctb_oa1+ dsi[10].port_if[5] smartio[9].io[5] P9.6 P9.6 ctb_oa0+ dsi[10].port_if[6] smartio[9].io[6] P9.7 P9.7 ctb_oa1+ or ext_vref dsi[10].port_if[7] smartio[9].io[7] P10.0 P10.0 sarmux[0] dsi[9].port_if[0] P10.1 P10.1 sarmux[1] dsi[9].port_if[1] P10.2 P10.2 sarmux[2] dsi[9].port_if[2] P10.3 P10.3 sarmux[3] dsi[9].port_if[3] P10.4 P10.4 sarmux[4] dsi[9].port_if[4] P10.5 P10.5 sarmux[5] dsi[9].port_if[5] P10.6 P10.6 sarmux[6] dsi[9].port_if[6] P10.7 P10.7 sarmux[7] dsi[9].port_if[7] dsi[5].port_if[0] dsi[5].port_if[6] csd.cshieldpads Document Number: 002-18449 Rev. *J dsi[5].port_if[7] Page 30 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 7. Port Pin Analog, Smart I/O, and DSI Functions (continued) Port/Pin Name P11.0 P11.0 Analog Digital HV dsi[8].port_if[0] DSI P11.1 P11.1 dsi[8].port_if[1] P11.2 P11.2 dsi[8].port_if[2] P11.3 P11.3 dsi[8].port_if[3] P11.4 P11.4 dsi[8].port_if[4] P11.5 P11.5 dsi[8].port_if[5] P11.6 P11.6 dsi[8].port_if[6] P11.7 P11.7 dsi[8].port_if[7] P12.0 P12.0 dsi[7].port_if[0] P12.1 P12.1 dsi[7].port_if[1] P12.2 P12.2 dsi[7].port_if[2] P12.3 P12.3 dsi[7].port_if[3] P12.4 P12.4 dsi[7].port_if[4] P12.5 P12.5 P12.6 P12.6 eco_in P12.7 P12.7 eco_out P13.0 P13.0 dsi[6].port_if[0] P13.1 P13.1 dsi[6].port_if[1] P13.2 P13.2 dsi[6].port_if[2] P13.3 P13.3 dsi[6].port_if[3] P13.4 P13.4 dsi[6].port_if[4] P13.5 P13.5 dsi[6].port_if[5] P13.6 P13.6 dsi[6].port_if[6] P13.7 P13.7 dsi[6].port_if[7] SMARTIO USB dsi[7].port_if[5] Document Number: 002-18449 Rev. *J dsi[7].port_if[6] dsi[7].port_if[7] Page 31 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Power Supply Considerations The following power system diagrams show typical connections for power pins for all supported packages, and with and without usage of the buck regulator. In these diagrams, the package pin is shown with the pin name, for example "VDDA, A12". For VDDx pins, the I/O port that is powered by that pin is also shown, for example "VDDD, A1; I/O port P1". Figure 9. 124-BGA Power Connection Diagram 1.7 to 3.6 V CY8C62x6/7, 124-BGA package 1 K at 100 MHz 1 K at 100 MHz 1 K at 100 MHz 10 F 0.1 F 1 F 0.1 F 1 F 0.1 F 1 F 0.1 F 1 F 0.1 F 1 F 0.1 F 10 F 0.1 F VDDD, A1; I/O port P1 VDD_NS, J1 VBACKUP, D1; I/O port P0 V BUCK1, K3 0.1 F 10 F 4.7 F VDDIO0, C4; I/O ports P11, P12, P13 V CCD, A2 VDDIO1, K12; I/O ports P5, P6, P7, P8 VDDIO2 , L4; I/O ports P2, P3, P4 VIND1, J2 2.2 H VDDUSB , M1; I/O port P14 VIND2 , K2 VDDA, A12 V RF, K1 0.1 F 10 F VDDIOA, A13; I/O ports P9, P10 B12,C3,D4,D10,K4,K10 V SS Document Number: 002-18449 Rev. *J Page 32 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Figure 10. 124-BGA (No Buck) Power Connection Diagram 1.7 to 3.6 V CY8C62x6/7, 124-BGA package 1 K at 100 MHz 1 K at 100 MHz 10 F 0.1 F 1 F 0.1 F 1 F 0.1 F 1 F 0.1 F 1 F 0.1 F 1 F 0.1 F 10 F 0.1 F V DDD , A1; I/O port P1 V DD_NS, J1 V BACKUP, D1; I/O port P0 VBUCK1 , K3 V DDIO0, C4; I/O ports P11, P12, P13 VCCD , A2 V DDIO1, K12; I/O ports P5, P6, P7, P8 VDDIO2, L4; I/O ports P2, P3, P4 V IND1, J2 V DDUSB, M1; I/O port P14 VIND2, K2 4.7 V VRF, K1 VDDA , A12 VDDIOA , A13; I/O ports P9, P10 B12,C3,D4,D10,K4,K10 VSS Document Number: 002-18449 Rev. *J Page 33 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Figure 11. 80-WLCSP Power Connection Diagram 1.7 to 3.6 V CY8C62x6/7, 80-WLCSP package 1 K at 100 MHz 10 F 0.1 F 1 F 0.1 F 1 F 1 K at 100 MHz 1 K at 100 MHz 0.1 F 1 F 0.1 F 1 F 0.1 F VDDD , B11; I/O port P1 VDD_NS, K11 VBACKUP, D11; I/O port P0 V BUCK1, N10 0.1 F 10 F 4.7 F VDDIO0, A6; I/O ports P11, P12 V CCD, A10 VDDIO1, M1; I/O ports P5, P6, P7, P8 VDDUSB , P11; I/O port P14 VIND1, L10 2.2 H 10 F 0.1 F VDDA, F1; I/O ports P9, P10 V IND2, M11 0.1 F A8, D1, P5, R8 VSS Figure 12. 80-WLCSP (No Buck) Power Connection Diagram 1.7 to 3.6 V CY8C62x6/7, 80-WLCSP package 1 K at 100 MHz 1 K at 100 MHz 10 F 0.1 F 1 F 0.1 F 1 F 0.1 F 1 F 0.1 F 1 F 0.1 F 10 F 0.1 F VDDD, B11; I/O port P1 V DD_NS, K11 VBACKUP, D11; I/O port P0 V BUCK1, N10 VDDIO0, A6; I/O ports P11, P12 VCCD, A10 VDDIO1, M1; I/O ports P5, P6, P7, P8 4.7 V VIND1 , L10 VDDUSB , P11; I/O port P14 V DDA, F1; I/O ports P9, P10 VIND2, M11 A8, D1, P5, R8 V SS Document Number: 002-18449 Rev. *J Page 34 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet There are as many as eight VDDx supply pins, depending on the package, and multiple VSS ground pins. The power pins are: VDDD: the main digital supply. It powers the low dropout (LDO) regulators and I/O port 1 VCCD: the main LDO output. It requires a 4.7-F capacitor for regulation. The LDO can be turned off when VCCD is driven from the switching regulator (see VBUCK1 below). For more information, see the power system block diagram in the device technical reference manual (TRM). VDDA: the supply for the analog peripherals. It is also the supply for I/O ports 9 and 10 when VDDIOA is not present. VDDIOA: the supply for I/O ports 9 and 10. If it is present in the device package, it must be connected to VDDA. VDDIO0: the supply for I/O ports 11, 12, and 13. VDDIO1: the supply for I/O ports 5, 6, 7, and 8. VDDIO2: the supply for I/O ports 2, 3, and 4. VBACKUP: the supply for the backup domain, which includes the 32-kHz WCO and the RTC. It can be a separate supply as low as 1.4 V, for battery or supercapacitor backup, as Figure 13 shows. Otherwise it is connected to VDDD. It powers I/O port 0. Figure 13. Separate Battery Connection to VBACKUP 1.7 to 3.6 V VSS: ground pins for the above supplies. All ground pins should be connected together to a common ground. In addition to the LDO regulator, a single input multiple output (SIMO) switching regulator is included. It provides two regulated outputs using a single inductor. The regulator pins are: VDD_NS: the regulator supply. VIND1 and VIND2: the inductor and capacitor connections. VBUCK1: the first regulator output. It is typically used to drive VCCD, see above. VRF: the second regulator output. It is typically not used; the pin may not be available in some packages. The various VDD power pins are not connected together on chip. They can be connected off chip, in one or more separate nets. If separate power nets are used, they can be isolated from noise from the other nets using optional ferrite beads, as indicated in the diagrams. No external load should be placed on VCCD, VRF, or any of the switching regulator power pins; whether or not the switching regulator is used. There are no power pin sequencing requirements; power supplies may be brought up in any order. The power management system holds the device in reset until all power pins are at the voltage levels required for proper operation. Note: If a battery is installed on the PCB first, VDDD must be cycled for at least 50 s. This prevents premature drain of the battery during product manufacture and storage. 10 F 0.1 F 1 F 0.1 F 1.4 to 3.6 V VDDD VBACKUP VDDUSB: the supply for the USB peripheral and the USBDP and USBDM pins. It must be 2.85 V to 3.6 V for USB operation. If USB is not used, it can be 1.7 V to 3.6 V, and the USB pins can be used as limited-capability GPIOs on I/O port 14. Table 8 shows a summary of the I/O port supplies: Table 8. I/O Port Supplies Port Supply Alternate Supply 0 VBACKUP VDDD 1 VDDD - 2, 3, 4 VDDIO2 - 5, 6, 7, 8 VDDIO1 - 9, 10 VDDIOA VDDA 11, 12, 13 VDDIO0 - 14 VDDUSB - Document Number: 002-18449 Rev. *J Bypass capacitors must be connected to a common ground from the VDDx and other pins, as indicated in the diagrams. Typical practice for systems in this frequency range is to use a 10-F or 1-F capacitor in parallel with a smaller capacitor (0.1 F, for example). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated for optimal bypassing. All capacitors and inductors should be 20% or better. The capacitor connected to VIND2 should be 100 nF. The recommended inductor value is 2.2 H 20% (for example, TDK MLP2012H2R2MT0S1). It is good practice to check the datasheets for your bypass capacitors, specifically the working voltage and the DC bias specifications. With some capacitors, the actual capacitance can decrease considerably when the applied voltage is a significant percentage of the rated working voltage. For more information on pad layout, refer to PSoC 6 CAD libraries. Page 35 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Electrical Specifications All specifications are valid for -40 C TA 85 C and for 1.71 V to 3.6 V except where noted. Absolute Maximum Ratings Table 9. Absolute Maximum Ratings[2] Description Min Typ Max Unit SID1 Spec ID# VDD_ABS Parameter Analog or digital supply relative to VSS (VSSD = VSSA) -0.5 - 4 V SID2 VCCD_ABS Direct digital core voltage input relative to VSSD -0.5 - 1.2 V SID3 VGPIO_ABS GPIO voltage; VDDD or VDDA -0.5 - VDD + 0.5 V SID4 IGPIO_ABS Current per GPIO -25 - 25 mA SID5 IGPIO_injection GPIO injection current per pin -0.5 - 0.5 mA SID3A ESD_HBM Electrostatic discharge Human Body Model 2200 - - V SID4A ESD_CDM Electrostatic discharge Charged Device Model 500 - - V SID5A LU Pin current for latchup-free operation -100 - 100 mA Details / Conditions Note 2. Usage above the absolute maximum conditions listed in Table 9 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150 C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Document Number: 002-18449 Rev. *J Page 36 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Device-Level Specifications Table 10. Power Supply Range, CPU Current, and Transition Time Specifications Spec ID# Parameter Description Min Typ Max Unit Details / Conditions DC Specifications SID6 VDDD Internal regulator and Port 1 GPIO supply 1.7 - 3.6 V - SID7 VDDA Analog power supply voltage. Shorted to VDDIOA on PCB. 1.7 - 3.6 V Internally unregulated supply SID7A VDDIO1 GPIO supply for ports 5 to 8 when present 1.7 - 3.6 V VDDIO_1 must be VDDA. - SID7B VDDIO0 GPIO supply for ports 11 to 13 when present 1.7 - 3.6 V SID7E VDDIO0 Supply for eFuse programming 2.38 2.5 2.62 V SID7C VDDIO2 GPIO supply for ports 2 to 4 on BGA 124 only 1.7 - 3.6 V - SID7D VDDIOA GPIO supply for ports 9 to 10. Must be connected to VDDA on PCB. 1.7 - 3.6 V - SID7F VDDUSB Supply for port 14 (USB or GPIO) when present 1.7 - 3.6 V Min. supply is 2.85 V for USB SID6B VBACKUP Backup power and GPIO Port 0 supply when present 1.7 - 3.6 V Min. is 1.4 V when VDDD is removed. SID8 VCCD1 Output voltage (for core logic bypass) - 1.1 - V High-speed mode SID9 VCCD2 Output voltage (for core logic bypass) - 0.9 - V ULP mode. Valid for -20 to 85 C. SID10 CEFC External regulator voltage (VCCD) bypass SID11 CEXC Power supply decoupling capacitor 3.8 4.7 5.6 F X5R ceramic or better; Value for 0.8 to 1.2 V. - 10 - F X5R ceramic or better - 2.3 3.2 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 3.1 3.6 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 5.7 6.5 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 0.9 1.5 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 1.2 1.6 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 2.8 3.5 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 6.3 7 mA VDDD = 3.3 V, Buck ON, Max at 60 C LP RANGE POWER SPECIFICATIONS (for VCCD = 1.1 V with Buck and LDO) Cortex M4. Active Mode Execute with Cache Disabled (Flash) SIDF1 SIDF2 IDD1 IDD2 Execute from Flash; CM4 Active 50 MHz, CM0+ Sleep 25 MHz. With IMO & FLL. While(1). Execute from Flash; CM4 Active 8 MHz, CM0+ Sleep 8 MHz. With IMO. While(1). Execute with Cache Enabled SIDC1 SIDC2 IDD3 IDD4 Execute from Cache; CM4 Active 150 MHz, CM0+ Sleep 75 MHz. IMO & FLL. Dhrystone. Execute from Cache; CM4 Active 100 MHz, CM0+ Sleep 100 MHz. IMO & FLL. Dhrystone. Document Number: 002-18449 Rev. *J - 9.7 11.2 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 14.4 15.1 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 4.8 5.8 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 7.4 8.4 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 11.3 12 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C Page 37 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 10. Power Supply Range, CPU Current, and Transition Time Specifications (continued) Spec ID# SIDC3 SIDC4 Parameter IDD5 IDD6 Description Execute from Cache; CM4 Active 50 MHz, CM0+ Sleep 25 MHz. IMO & FLL. Dhrystone Execute from Cache; CM4 Active 8 MHz, CM0+ Sleep 8 MHz. IMO. Dhrystone. Min Typ Max Unit Details / Conditions - 2.4 3.4 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 3.7 4.1 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 6.3 7.2 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 0.9 1.5 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 1.3 1.8 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 3 3.8 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 2.4 3.3 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 3.2 3.7 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 5.6 6.3 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 0.8 1.5 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 1.1 1.6 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 2.60 3.4 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 3.8 4.5 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 5.9 6.5 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 9 9.7 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 0.8 1.3 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 1.20 1.7 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 2.60 3.4 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 1.5 2.2 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 2.2 2.7 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 4 4.6 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 1.2 1.9 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 1.7 2.2 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 3.4 4.3 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 0.7 1.3 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 1 1.5 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 2.4 3.3 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 1.3 2 mA VDDD = 3.3 V, Buck ON, Max at 60 C Cortex M0+. Active Mode Execute with Cache Disabled (Flash) SIDF3 SIDF4 IDD7 IDD8 Execute from Flash; CM4 Off, CM0+ Active 50 MHz. With IMO & FLL. While (1). Execute from Flash; CM4 Off, CM0+ Active 8 MHz. With IMO. While (1). Execute with Cache Enabled SIDC5 SIDC6 IDD9 IDD10 Execute from Cache; CM4 Off, CM0+ Active 100 MHz. With IMO & FLL. Dhrystone. Execute from Cache; CM4 Off, CM0+ Active 8 MHz. With IMO. Dhrystone. Cortex M4. Sleep Mode SIDS1 SIDS2 SIDS3 IDD11 IDD12 IDD13 CM4 Sleep 100 MHz; CM0+ Sleep 25 MHz. With IMO & FLL. CM4 Sleep 50 MHz; CM0+ Sleep 25 MHz. With IMO & FLL. CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With IMO. Cortex M0+. Sleep Mode SIDS4 IDD14 CM4 Off, CM0+ Sleep 50 MHz. With IMO & FLL. Document Number: 002-18449 Rev. *J - 1.9 2.4 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 3.80 4.6 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C Page 38 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 10. Power Supply Range, CPU Current, and Transition Time Specifications (continued) Spec ID# SIDS5 Parameter IDD15 Description CM4 Off, CM0+ Sleep 8 MHz. With IMO. Min Typ Max Unit Details / Conditions - 0.7 1.3 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 1 1.5 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 2.4 3.3 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 0.9 1.5 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 1.2 1.7 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 2.8 3.5 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 0.9 1.5 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 1.3 1.8 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 2.9 3.7 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 0.8 1.4 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 1.1 1.6 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 2.7 3.6 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 0.8 1.4 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 1.2 1.7 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 2.7 3.6 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 0.7 1.1 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 1 1.5 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 2.4 3.3 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C - 0.6 1.1 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 0.9 1.5 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 2.4 3.3 mA VDDD = 1.8 to 3.3 V, LDO, Max at 85 C Cortex M4. Minimum Regulator Current Mode SIDLPA1 SIDLPA2 IDD16 IDD17 Execute from Flash; CM4 LPA 8 MHz, CM0+ Sleep 8 MHz. With IMO. While (1). Execute from Cache; CM4 LPA 8 MHz, CM0+ Sleep 8 MHz. With IMO. Dhrystone. Cortex M0+. Minimum Regulator Current Mode SIDLPA3 SIDLPA4 IDD18 IDD19 Execute from Flash; CM4 Off, CM0+ Active 8 MHz. With IMO. While (1). Execute from Cache; CM4 Off, CM0+ Active 8 MHz. With IMO. Dhrystone. Cortex M4. Minimum Regulator Current Mode SIDLPS1 IDD20 CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With IMO. Cortex M0+. Minimum Regulator Current Mode SIDLPS3 IDD22 CM4 Off, CM0+ Sleep 8 MHz. With IMO. ULP RANGE POWER SPECIFICATIONS (for VCCD = 0.9 V using the Buck). ULP mode is valid from -20 to +85 C. Cortex M4. Active Mode Execute with Cache Disabled (Flash) SIDF5 SIDF6 IDD3 IDD4 Execute from Flash; CM4 Active 50 MHz, CM0+ Sleep 25 MHz. With IMO & FLL. While(1). - 1.7 2.2 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 2.1 2.4 mA VDDD = 1.8 V, Buck ON, Max at 60 C Execute from Flash; CM4 Active 8 MHz, CM0+ Sleep 8 MHz. With IMO. While (1) - 0.56 0.8 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 0.75 1 mA VDDD = 1.8 V, Buck ON, Max at 60 C Execute from Cache; CM4 Active 50 MHz, CM0+ Sleep 25 MHz. With IMO & FLL. Dhrystone. - 1.6 2.2 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 2.4 2.7 mA VDDD = 1.8 V, Buck ON, Max at 60 C Execute from Cache; CM4 Active 8 MHz, CM0+ Sleep 8 MHz. With IMO. Dhrystone. - 0.65 0.8 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 0.8 1.1 mA VDDD = 1.8 V, Buck ON, Max at 60 C Execute with Cache Enabled SIDC8 SIDC9 IDD10 IDD11 Document Number: 002-18449 Rev. *J Page 39 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 10. Power Supply Range, CPU Current, and Transition Time Specifications (continued) Spec ID# Parameter Description Min Typ Max Unit Details / Conditions IDD16 Execute from Flash; CM4 Off, CM0+ Active 25 MHz. With IMO & FLL. Write(1). - 1 1.4 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 1.34 1.6 mA VDDD = 1.8 V, Buck ON, Max at 60 C IDD17 Execute from Flash; CM4 Off, CM0+ Active 8 MHz. With IMO. While(1). - 0.54 0.75 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 0.73 1 mA VDDD = 1.8 V, Buck ON, Max at 60 C Execute from Cache; CM4 Off, CM0+ Active 25 MHz. With IMO & FLL. Dhrystone. - 0.91 1.25 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 1.34 1.6 mA VDDD = 1.8 V, Buck ON, Max at 60 C Execute from Cache; CM4 Off, CM0+ Active 8 MHz. With IMO. Dhrystone. - 0.51 0.72 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 0.73 0.95 mA VDDD = 1.8 V, Buck ON, Max at 60 C IDD21 CM4 Sleep 50 MHz, CM0+ Sleep 25 MHz. With IMO & FLL. - 0.76 1.1 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 1.1 1.4 mA VDDD = 1.8 V, Buck ON, Max at 60 C IDD22 CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With IMO. - 0.42 0.65 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 0.59 0.8 mA VDDD = 1.8 V, Buck ON, Max at 60 C CM4 Off, CM0+ Sleep 25 MHz. With IMO & FLL. - 0.62 0.9 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 0.88 1.1 mA VDDD = 1.8 V, Buck ON, Max at 60 C CM4 Off, CM0+ Sleep 8 MHz. With IMO. - 0.41 0.6 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 0.58 0.8 mA VDDD = 1.8 V, Buck ON, Max at 60 C Cortex M0+. Active Mode Execute with Cache Disabled (Flash) SIDF7 SIDF8 Execute with Cache Enabled SIDC10 SIDC11 IDD18 IDD19 Cortex M4. Sleep Mode SIDS7 SIDS8 Cortex M0+. Sleep Mode SIDS9 SIDS10 IDD23 IDD24 Cortex M4. Minimum Regulator Current Mode SIDLPA5 SIDLPA6 IDD25 Execute from Flash. CM4 Active 8 MHz, CM0+ Sleep 8 MHz. With IMO. While(1). - 0.52 0.75 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 0.76 1 mA VDDD = 1.8 V, Buck ON, Max at 60 C IDD26 Execute from Cache. CM4 Active 8 MHz, CM0+ Sleep 8 MHz. With IMO. Dhrystone. - 0.54 0.76 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 0.78 1 mA VDDD = 1.8 V, Buck ON, Max at 60 C Execute from Flash. CM4 Off, CM0+ Active 8 MHz. With IMO. While (1). - 0.51 0.75 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 0.75 1 mA VDDD = 1.8 V, Buck ON, Max at 60 C Execute from Cache. CM4 Off, CM0+ Active 8 MHz. With IMO. Dhrystone. - 0.48 0.7 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 0.7 0.95 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 0.4 0.6 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 0.57 0.8 mA VDDD = 1.8 V, Buck ON, Max at 60 C - 0.39 0.6 mA VDDD = 3.3 V, Buck ON, Max at 60 C - 0.56 0.8 mA VDDD = 1.8 V, Buck ON, Max at 60 C Cortex M0+. Minimum Regulator Current Mode SIDLPA7 SIDLPA8 IDD27 IDD28 Cortex M4. Minimum Regulator Current Mode SIDLPS5 IDD29 CM4 Sleep 8 MHz, CM0 Sleep 8 MHz. With IMO. Cortex M0+. Minimum Regulator Current Mode SIDLPS7 IDD31 CM4 Off, CM0+ Sleep 8 MHz. With IMO. Document Number: 002-18449 Rev. *J Page 40 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 10. Power Supply Range, CPU Current, and Transition Time Specifications (continued) Spec ID# Parameter Description Min Typ Max Unit Details / Conditions With internal Buck enabled and 64K SRAM retention - 7 - A Max value is at 85 C SIDDS1_B IDD33A_B With internal Buck enabled and 64K SRAM retention - 7 - A Max value is at 60 C SIDDS2 With internal Buck enabled and 256K SRAM retention - 9 - A Max value is at 85 C With internal Buck enabled and 256K SRAM retention - 9 - A Max value is at 60 C Deep Sleep Mode SIDDS1 IDD33A IDD33B SIDDS2_B IDD33B_B Hibernate Mode SIDHIB1 IDD34 VDDD = 1.8 V - 300 - nA No clocks running SIDHIB2 IDD34A VDDD = 3.3 V - 800 - nA No clocks running Power Mode Transition Times SID12 TLPACT_ACT Minimum regulator current to LP transition time - - 35 s Including PLL lock time SID13 TDS_LPACT Deep Sleep to LP transition time - - 25 s Guaranteed by design SID14 THIB_ACT Hibernate to LP transition time - 500 - s Including PLL lock time Min Typ Max Unit XRES Table 11. XRES DC Specifications Spec ID# Parameter Description Details / Conditions SID17 TXRES_IDD IDD when XRES asserted - 300 - nA VDDD = 1.8 V SID17A TXRES_IDD_1 IDD when XRES asserted - 800 - nA VDDD = 3.3 V SID77 VIH Input voltage high threshold 0.7 x VDD - - V CMOS Input SID78 VIL Input voltage low threshold - - 0.3 x VDD V CMOS Input SID80 CIN Input capacitance - 3 - pF - SID81 VHYSXRES Input voltage hysteresis - 100 - mV - SID82 IDIODE Current through protection diode to VDD/VSS - - 100 A - Min Typ Max Unit Table 12. XRES AC Specifications Spec ID# Parameter Description Details / Conditions SID15 TXRES_ACT POR or XRES release to Active transition time - 750 - s Normal mode, 50 MHz M0+. SID16 TXRES_PW XRES Pulse width 5 - - s - Document Number: 002-18449 Rev. *J Page 41 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet GPIO Table 13. GPIO DC Specifications Spec ID# Parameter Description Min Typ Max Unit 0.7 x VDD - - V CMOS Input Input current when Pad > VDDIO for OVT inputs - - 10 A Per I2C Spec VIL Input voltage low threshold - - 0.3 x VDD V CMOS Input SID241 VIH LVTTL input, VDD < 2.7 V 0.7 x VDD - - V - SID242 VIL LVTTL input, VDD < 2.7 V - - 0.3* VDD V - SID243 VIH LVTTL input, VDD 2.7 V 2.0 - - V - SID244 VIL LVTTL input, VDD 2.7 V - - 0.8 V - SID59 VOH Output voltage high level VDD - 0.5 - - V IOH = 8 mA SID62A VOL Output voltage low level - - 0.4 V IOL = 8 mA SID63 RPULLUP Pull-up resistor 3.5 5.6 8.5 k - SID64 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 k - SID65 IIL Input leakage current (absolute value) - - 2 nA 25 C, VDD = 3.0 V SID65A IIL_CTBM Input leakage on CTBm input pins - - 4 nA - SID66 CIN Input Capacitance - - 5 pF - SID67 VHYSTTL Input hysteresis LVTTL VDD > 2.7 V 100 0 - mV - SID68 VHYSCMOS Input hysteresis CMOS 0.05 x VDD - - mV - SID69 IDIODE Current through protection diode to VDD/VSS - - 100 A - SID69A ITOT_GPIO Maximum total source or sink Chip Current - - 200 mA - Min Typ Max Unit SID57 VIH Input voltage high threshold SID57A IIHS SID58 Details / Conditions Table 14. GPIO AC Specifications Spec ID# Parameter Description Details / Conditions SID70 TRISEF Rise time in Fast Strong Mode. 10% to 90% of VDD - - 2.5 ns Cload = 15 pF, 8 mA drive strength SID71 TFALLF Fall time in Fast Strong Mode. 10% to 90% of VDD - - 2.5 ns Cload = 15 pF, 8 mA drive strength SID72 TRISES_1 Rise time in Slow Strong Mode. 10% to 90% of VDD 52 - 142 ns Cload = 15 pF, 8 mA drive strength, VDD 2.7 V SID72A TRISES_2 Rise time in Slow Strong Mode. 10% to 90% of VDD 48 - 102 ns Cload = 15 pF, 8 mA drive strength, 2.7 V < VDD 3.6 V SID73 TFALLS_1 Fall time in Slow Strong Mode. 10% to 90% of VDD 44 - 211 ns Cload = 15 pF, 8 mA drive strength, VDD 2.7 V SID73A TFALLS_2 Fall time in Slow Strong Mode. 10% to 90% of VDD 42 - 93 ns Cload = 15 pF, 8 mA drive strength, 2.7 V < VDD 3.6 V Document Number: 002-18449 Rev. *J Page 42 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 14. GPIO AC Specifications (continued) Spec ID# Parameter Description Min Typ Max Unit Details / Conditions Cload = 10 pF to 400 pF, 8-mA drive strength SID73G TFALL_I2C Fall time (30% to 70% of VDD) in 20 x VDDIO/ Slow Strong mode 5.5 - 250 ns SID74 FGPIOUT1 GPIO Fout. Fast Strong mode. - - 100 MHz 90/10%, 15-pF load, 60/40 duty cycle SID75 FGPIOUT2 GPIO Fout; Slow Strong mode. - - 16.7 MHz 90/10%, 15-pF load, 60/40 duty cycle SID76 FGPIOUT3 GPIO Fout; Fast Strong mode. - - 7 MHz 90/10%, 25-pF load, 60/40 duty cycle SID245 FGPIOUT4 GPIO Fout; Slow Strong mode. - - 3.5 MHz 90/10%, 25-pF load, 60/40 duty cycle SID246 FGPIOIN GPIO input operating frequency;1.71 V VDD 3.6 V - - 100 MHz 90/10% VIO Unit Analog Peripherals Opamp Table 15. Opamp Specifications Spec ID# Min Typ Max IDD Parameter Opamp block current. No load. Description - - - SID269 IDD_HI Power = Hi - 1300 1500 A - SID270 IDD_MED Power = Med - 450 600 A - SID271 IDD_LOW Power = Lo - 250 350 A - GBW Load = 50 pF, 0.1 mA. VDDA 2.7 V - - - SID272 GBW_HI Power = Hi 6 - - SID273 GBW_MED Power = Med 3 - - MHz - SID274 GBW_LO Power = Lo 1 - - MHz - IOUT_MAX VDDA 2.7 V, 500 mV from rail - - - SID275 IOUT_MAX_HI Power = Hi 10 - - mA - SID276 IOUT_MAX_MID Power = Mid 10 - - mA - SID277 IOUT_MAX_LO Power = Lo - 5 - mA - IOUT VDDA = 1.71 V, 500 mV from rail - - - SID278 IOUT_MAX_HI Power = Hi 4 - - SID279 IOUT_MAX_MID Power = Mid 4 - - mA - SID280 IOUT_MAX_LO Power = Lo - 2 - mA - SID281 VIN Input voltage range 0 - VDDA - 0.2 V SID282 VCM Input common mode voltage 0 - VDDA - 1.5 V VOUT VDDA 2.7 V - - - - V - - MHz - - - mA SID283 VOUT_1 Power = Hi, Iload = 10 mA 0.5 - VDDA - 0.5 SID284 VOUT_2 Power = Hi, Iload = 1 mA 0.2 - VDDA - 0.2 V SID285 VOUT_3 Power = Med, Iload = 1 mA 0.2 - VDDA - 0.2 V Document Number: 002-18449 Rev. *J Details / Conditions - - Charge pump ON Charge pump OFF, VDDA 2.7 V - - Page 43 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 15. Opamp Specifications (continued) Spec ID# Parameter Description Min Typ Max Unit V Details / Conditions SID286 VOUT_4 Power = Lo, Iload = 0.1 mA 0.2 - VDDA - 0.2 SID288 VOS_TR Offset voltage -1 0.5 1 mV Power = Hi, 0.2 V < VOUT < (VDDA - 0.2 V) SID288A VOS_TR Offset voltage - 1 - mV Power = Med SID288B VOS_TR Offset voltage - 2 - mV Power = Lo SID290 VOS_DR_TR Offset voltage drift -10 3 10 V/C SID290A VOS_DR_TR Offset voltage drift - 10 - V/C Power = Med SID290B VOS_DR_TR Offset voltage drift - 10 - V/C Power = Lo SID291 CMRR DC common mode rejection ratio 67 80 - dB VDDA 2.7 V SID292 PSRR Power supply rejection ratio at 1 kHz, 10-mV ripple 70 85 - dB VDDA 2.7 V SID65A IIL_CTBM Input leakage on CTBm input pins nA Noise - - 4 - - - - Power = Hi, 0.2 V < VOUT < (VDDA - 0.2 V) - - SID293 VN1 Input-referred, 1 Hz - 1 GHz, power = Hi - 100 - Vrms SID294 VN2 Input-referred, 1 kHz, power = Hi - 180 - nV/rtHz SID295 VN3 Input-referred, 10 kHz, power = Hi - 70 - nV/rtHz SID296 VN4 Input-referred, 100 kHz, power = Hi - 38 - nV/rtHz SID297 CLOAD Stable up to max. load. Performance specs at 50 pF. - - 125 pF SID298 SLEW_RATE Output slew rate 4 - - V/s SID299 T_OP_WAKE From disable to enable, no external RC dominating - 25 - s COMP_MODE Comparator mode; 50-mV overdrive, Trise = Tfall (approx.) - SID300 TPD1 Response time; power = Hi - SID301 TPD2 Response time; power = Med - 400 - ns - SID302 TPD3 Response time; power = Lo - 2000 - ns - SID303 VHYST_OP Hysteresis - 10 - mV - Deep Sleep Mode Mode 1 - Full reference current (Higher GBW) Mode 2 - Approximately 1/10th reference current (Lower Power Consumption)[3] - - - - - Cload = 50 pF, Power = Hi, VDDA 2.7 V - - - 150 - ns - Deep Sleep mode operation: VDDA 2.7 V. VIN is 0.2 to VDDA -1.5 V SID_DS_1 IDD_HI_M1 Mode 1, High current - 1300 1500 A Typ at 25 C SID_DS_2 IDD_MED_M1 Mode 1, Medium current - 460 600 A Typ at 25 C SID_DS_3 IDD_LOW_M1 Mode 1, Low current - 230 350 A Typ at 25 C SID_DS_4 IDD_HI_M2 Mode 2, High current - 120 - A 25 C Note 3. Reference current is supplied by AREF (analog reference) block. Document Number: 002-18449 Rev. *J Page 44 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 15. Opamp Specifications (continued) Spec ID# Parameter SID_DS_5 IDD_MED_M2 SID_DS_6 IDD_LOW_M2 SID_DS_7 GBW_HI_M1 Description Min Typ Max Unit - 60 - A Mode 2, Low current - 15 - A 25 C Mode 1, High current - 4 - MHz 25 C Mode 2, Medium current Details / Conditions 25 C SID_DS_8 GBW_MED_M1 Mode 1, Medium current - 2 - MHz 25 C SID_DS_9 GBW_LOW_M1 Mode 1, Low current - 0.5 - MHz 25 C SID_DS_10 GBW_HI_M2 - 0.5 - MHz 20-pF load, no DC load 0.2 V to VDDA - 1.5 V SID_DS_11 GBW_MED_M2 Mode 2, Medium current - 0.2 - MHz 20-pF load, no DC load 0.2 V to VDDA - 1.5 V SID_DS_12 GBW_LOW_M2 Mode 2, Low current - 0.1 - MHz 20-pF load, no DC load 0.2 V to VDDA - 1.5 V SID_DS_13 VOS_HI_M1 Mode 1, High current - 5 - mV 25 C, 0.2 V to VDDA - 1.5 V SID_DS_14 VOS_MED_M1 Mode 1, Medium current - 5 - mV 25 C, 0.2 V to VDDA - 1.5 V SID_DS_15 VOS_LOW_M1 Mode 1, Low current - 5 - mV 25 C, 0.2 V to VDDA - 1.5 V SID_DS_16 VOS_HI_M2 Mode 2, High current - 5 - mV 25 C, 0.2 V to VDDA - 1.5 V SID_DS_17 VOS_MED_M2 Mode 2, Medium current - 5 - mV 25 C, 0.2 V to VDDA - 1.5 V SID_DS_18 VOS_LOW_M2 Mode 2, Low current - 5 - mV 25 C, 0.2 V to VDDA - 1.5 V SID_DS_19 IOUT_HI_M1 Mode 1, High current - 10 - mA Output is 0.5 V to VDDA - 0.5 V SID_DS_20 IOUT_MED_M1 Mode 1, Medium current - 10 - mA Output is 0.5 V to VDDA - 0.5 V SID_DS_21 IOUT_LOW_M1 Mode 1, Low current - 4 - mA Output is 0.5 V to VDDA - 0.5 V SID_DS_22 IOUT_HI_M2 Mode 2, High current - 1 - mA Output is 0.5 V to VDDA - 0.5 V SID_DS_23 IOUT_MED_M2 Mode 2, Medium current - 1 - mA Output is 0.5 V to VDDA - 0.5 V SID_DS_24 IOUT_LOW_M2 Mode 2, Low current - 0.5 - mA Output is 0.5 V to VDDA - 0.5 V Mode 2, High current Low-Power (LP) Comparator Table 16. LP Comparator DC Specifications Spec ID# Parameter Description Min Typ Max Unit Details / Conditions COMP0 offset is 25 mV SID84 VOFFSET1 Input offset voltage for COMP1. Normal power mode. -10 - 10 mV SID85A VOFFSET2 Input offset voltage. Low-power mode. -25 12 25 mV SID85B VOFFSET3 Input offset voltage. Ultra low-power mode. -25 12 25 mV SID86 VHYST1 Hysteresis when enabled in Normal mode - - 60 mV Document Number: 002-18449 Rev. *J - - - Page 45 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 16. LP Comparator DC Specifications (continued) Spec ID# Parameter Description Min Typ Max Unit Details / Conditions SID86A VHYST2 Hysteresis when enabled in Low-power mode - - 80 mV SID87 VICM1 Input common mode voltage in Normal mode 0 - VDDIO1 - 0.1 V SID247 VICM2 Input common mode voltage in Low power mode 0 - VDDIO1 - 0.1 V SID247A VICM3 Input common mode voltage in Ultra low power mode 0 - VDDIO1 - 0.1 V SID88 CMRR Common mode rejection ratio in Normal power mode 50 - - dB SID89 ICMP1 Block Current, Normal mode - - 150 A - SID248 ICMP2 Block Current, Low power mode - - 10 A - SID259 ICMP3 Block Current in Ultra low-power mode - 0.3 0.85 A SID90 ZCMP DC Input impedance of comparator 35 - - M Min Typ Max Unit - - - - - - - Table 17. LP Comparator AC Specifications Spec ID# Parameter Description Details / Conditions SID91 TRESP1 Response time, Normal mode, 100 mV overdrive - - 100 ns - SID258 TRESP2 Response time, Low power mode, 100 mV overdrive - - 1000 ns SID92 TRESP3 Response time, Ultra-low power mode, 100 mV overdrive - - 20 s SID92E T_CMP_EN1 Time from Enabling to operation - - 10 s Normal and Low-power modes SID92F T_CMP_EN2 Time from Enabling to operation - - 50 s Ultra low-power mode Min Typ Max Unit -5 1 5 C Description Min Typ Max Unit - 1.188 1.2 1.212 V - - Table 18. Temperature Sensor Specifications Spec ID# SID93 Parameter TSENSACC Description Temperature sensor accuracy Details / Conditions -40 to +85 C Table 19. Internal Reference Specification Spec ID# SID93R Parameter VREFBG Document Number: 002-18449 Rev. *J Details / Conditions - Page 46 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet SAR ADC Table 20. 12-bit SAR ADC DC Specifications Spec ID# Min Typ Max Unit SID94 A_RES Parameter SAR ADC Resolution Description - - 12 bits Details / Conditions SID95 A_CHNLS_S Number of channels single-ended - - 16 - 8 full speed. SID96 A-CHNKS_D Number of channels - differential - - 8 - Diff inputs use neighboring I/O SID97 A-MONO Monotonicity - - - - Yes SID98 A_GAINERR Gain error - - 0.2 % With external reference. SID99 A_OFFSET Input offset voltage - - 2 mV Measured with 1-V reference SID100 A_ISAR_1 Current consumption at 1 Msps - - 1 mA At 1 Msps. External Bypass Cap. SID100A A_ISAR_2 Current consumption at 1 Msps. Reference = VDD - - 1.25 mA At 1 Msps. External Bypass Cap. SID101 A_VINS Input voltage range - single-ended VSS - VDDA V - SID102 A_VIND Input voltage range - differential VSS - VDDA V - SID103 A_INRES Input resistance - - 2.2 k - SID104 A_INCAP Input capacitance - - 10 pF - Min Typ Max Unit - Table 21. 12-bit SAR ADC AC Specifications Spec ID# Parameter Description Details / Conditions 12-bit SAR ADC AC Specifications SID106 A_PSRR Power supply rejection ratio 70 - - dB - SID107 A_CMRR Common mode rejection ratio 66 - - dB Measured at 1 V. One Megasample per second mode: SID108 A_SAMP_1 Sample rate with external reference bypass cap. - - 1 Msps - SID108A A_SAMP_2 Sample rate with no bypass cap; Reference = VDD - - 250 ksps - SID108B A_SAMP_3 Sample rate with no bypass cap. Internal reference. - - 100 ksps - SID109 A_SINAD Signal-to-noise and Distortion ratio (SINAD). VDDA = 2.7 to 3.6 V, 1 Msps. 64 - - dB SID111A A_INL Integral Non Linearity. VDDA = 2.7 to 3.6 V, 1 Msps -2 - 2 LSB Measured with internal VREF = 1.2 V and bypass cap. SID111B A_INL Integral Non Linearity. VDDA = 2.7 to 3.6 V, 1 Msps -4 - 4 LSB Measured with external VREF 1 V and VIN common mode < 2 * Vref. SID112A A_DNL Differential Non Linearity. VDDA = 2.7 to 3.6 V, 1 Msps -1 - 1.4 LSB Measured with internal VREF = 1.2 V and bypass cap. SID112B A_DNL Differential Non Linearity. VDDA = 2.7 to 3.6 V, 1 Msps -1 - 1.7 LSB Measured with external VREF 1 V and VIN common mode < 2 * Vref. SID113 A_THD Total harmonic distortion. VDDA = 2.7 to 3.6 V, 1 Msps. - - -65 dB Document Number: 002-18449 Rev. *J Fin = 10 kHz Fin = 10 kHz Page 47 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet DAC Table 22. 12-bit DAC DC Specifications Min Typ Max Unit SID108D DAC_RES Spec ID# Parameter DAC resolution - - 12 bits - SID111D Integral non-linearity -4 - 4 LSB - SID112D DAC_DNL Differential non-linearity -2 - 2 LSB Monotonic to 11 bits. SID99D Output Voltage zero offset error DAC_INL DAC_OFFSET Description Details / Conditions -2 - 1 mV For 000 (hex) SID103D DAC_OUT_RES DAC Output Resistance - 15 - k - SID100D DAC_IDD DAC Current - - 125 A - SID101D DAC_QIDD DAC Current when DAC stopped - - 1 A - Min Typ Max Unit Details / Conditions Table 23. 12-bit DAC AC Specifications Spec ID# Parameter Description SID109D DAC_CONV DAC Settling time - - 2 s Driving through CTBm buffer; 25-pF load SID110D DAC_Wakeup Time from Enabling to ready for conversion - - 10 s - CSD Table 24. CapSense Sigma-Delta (CSD) Specifications Spec ID# Parameter Description Min Typ Max Unit Details / Conditions CSD V2 Specifications SYS.PER#3 VDD_RIPPLE Max allowed ripple on power supply, DC to 10 MHz - - 50 mV VDDA > 2 V (with ripple), 25 C TA, Sensitivity = 0.1 pF SYS.PER#16 VDD_RIPPLE_1.8 Max allowed ripple on power supply, DC to 10 MHz - - 25 mV VDDA > 1.75 V (with ripple), 25 C TA, Parasitic Capacitance (CP) < 20 pF, Sensitivity 0.4 pF 4500 A - 1.2 VDDA - 0.6 V VDDA - VREF 0.6 V VDDA - 0.6 V VDDA - VREF 0.6 V SID.CSD.BLK ICSD Maximum block current SID.CSD#15 Voltage reference for CSD and Comparator 0.6 SID.CSD#15A VREF_EXT External Voltage reference for CSD and Comparator 0.6 SID.CSD#16 IDAC1IDD IDAC1 (7-bits) block current SID.CSD#17 IDAC2IDD IDAC2 (7-bits) block current SID308 VCSD Voltage range of operation SID308A VCOMPIDAC Voltage compliance range of IDAC SID309 IDAC1DNL SID310 VREF - - 1900 A - - - 1900 A - 1.7 - 3.6 V 1.71 to 3.6 V 0.6 - VDDA - 0.6 V VDDA - VREF 0.6 V DNL -1 - 1 LSB - IDAC1INL INL -3 - 3 LSB If VDDA < 2 V then for LSB of 2.4 A or less SID311 IDAC2DNL DNL -1 - 1 LSB - SID312 IDAC2INL INL -3 - 3 LSB If VDDA < 2 V then for LSB of 2.4 A or less Document Number: 002-18449 Rev. *J Page 48 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 24. CapSense Sigma-Delta (CSD) Specifications (continued) Spec ID# Parameter Description Min Typ Max Unit Details / Conditions SNRC of the following is Ratio of counts of finger to noise. Guaranteed by characterization SID313_1A SNRC_1 SRSS Reference. IMO + FLL Clock Source. 0.1-pF sensitivity 5 - - Ratio 9.5-pF max. capacitance SID313_1B SNRC_2 SRSS Reference. IMO + FLL Clock Source. 0.3-pF sensitivity 5 - - Ratio 31-pF max. capacitance SID313_1C SNRC_3 SRSS Reference. IMO + FLL Clock Source. 0.6-pF sensitivity 5 - - Ratio 61-pF max. capacitance SID313_2A SNRC_4 PASS Reference. IMO + FLL Clock Source. 0.1-pF sensitivity 5 - - Ratio 12-pF max. capacitance SID313_2B SNRC_5 PASS Reference. IMO + FLL Clock Source. 0.3-pF sensitivity 5 - - Ratio 47-pF max. capacitance SID313_2C SNRC_6 PASS Reference. IMO + FLL Clock Source. 0.6-pF sensitivity 5 - - Ratio 86-pF max. capacitance SID313_3A SNRC_7 PASS Reference. IMO + PLL Clock Source. 0.1-pF sensitivity 5 - - Ratio 27-pF max. capacitance SID313_3B SNRC_8 PASS Reference. IMO + PLL Clock Source. 0.3-pF sensitivity 5 - - Ratio 86-pF max. capacitance SID313_3C SNRC_9 PASS Reference. IMO + PLL Clock Source. 0.6-pF sensitivity 5 - - Ratio 168-pF max. capacitance SID314 IDAC1CRT1 Output current of IDAC1 (7 bits) in low range 4.2 5.7 A LSB = 37.5-nA typ SID314A IDAC1CRT2 Output current of IDAC1(7 bits) in medium range 33.7 45.6 A LSB = 300-nA typ. SID314B IDAC1CRT3 Output current of IDAC1(7 bits) in high range 270 365 A LSB = 2.4-A typ. SID314C IDAC1CRT12 Output current of IDAC1 (7 bits) in low range, 2X mode 8 11.4 A LSB = 37.5-nA typ. 2X output stage SID314D IDAC1CRT22 Output current of IDAC1(7 bits) in medium range, 2X mode 67 91 A LSB = 300-nA typ. 2X output stage SID314E IDAC1CRT32 Output current of IDAC1(7 bits) in high range, 2X mode. VDDA > 2V 540 730 A LSB = 2.4-A typ. 2X output stage SID315 IDAC2CRT1 Output current of IDAC2 (7 bits) in low range 4.2 5.7 A LSB = 37.5-nA typ. SID315A IDAC2CRT2 Output current of IDAC2 (7 bits) in medium range 33.7 45.6 A LSB = 300-nA typ. SID315B IDAC2CRT3 Output current of IDAC2 (7 bits) in high range 270 365 A LSB = 2.4-A typ. SID315C IDAC2CRT12 Output current of IDAC2 (7 bits) in low range, 2X mode 8 11.4 A LSB = 37.5-nA typ. 2X output stage SID315D IDAC2CRT22 Output current of IDAC2(7 bits) in medium range, 2X mode 67 91 A LSB = 300-nA typ. 2X output stage SID315E IDAC2CRT32 Output current of IDAC2(7 bits) in high range, 2X mode. VDDA > 2V 540 730 A LSB = 2.4-A typ. 2X output stage SID315F IDAC3CRT13 Output current of IDAC in 8-bit mode in low range 8 11.4 A LSB = 37.5-nA typ. Document Number: 002-18449 Rev. *J Page 49 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 24. CapSense Sigma-Delta (CSD) Specifications (continued) Spec ID# Parameter Description Min Typ Max Unit Details / Conditions SID315G IDAC3CRT23 Output current of IDAC in 8-bit mode in medium range 67 91 A LSB = 300-nA typ. SID315H IDAC3CRT33 Output current of IDAC in 8-bit mode in high range. VDDA > 2V 540 730 A LSB = 2.4-A typ. SID320 IDACOFFSET All zeroes input - - 1 SID321 IDACGAIN Full-scale error less offset - - 15 SID322 IDACMISMATCH1 Mismatch between IDAC1 and IDAC2 in Low mode - - 9.2 LSB LSB = 37.5-nA typ. SID322A IDACMISMATCH2 Mismatch between IDAC1 and IDAC2 in Medium mode - - 6 LSB LSB = 300-nA typ. SID322B IDACMISMATCH3 Mismatch between IDAC1 and IDAC2 in High mode - - 5.8 LSB LSB = 2.4-A typ. SID323 IDACSET8 Settling time to 0.5 LSB for 8-bit IDAC - - 10 s Full-scale transition. No external load. SID324 IDACSET7 Settling time to 0.5 LSB for 7-bit IDAC - - 10 s Full-scale transition. No external load. SID325 CMOD External modulator capacitor. - 2.2 - nF 5-V rating, X7R or NP0 cap. LSB Polarity set by Source or Sink % LSB = 2.4-A typ. Table 25. CSD ADC Specifications Spec ID# Parameter Description Min Typ Max Unit Details / Conditions CSDv2 ADC Specifications SIDA94 A_RES Resolution - - 10 bits Auto-zeroing is required every millisecond SID95 A_CHNLS_S Number of channels - single ended - - - 16 - SIDA97 A-MONO Monotonicity - - Yes - VREF mode SIDA98 A_GAINERR_VREF Gain error - 0.6 - % Reference Source: SRSS (VREF = 1.20 V, VDDA < 2.2 V), (VREF = 1.6 V, 2.2 V < VDDA<2.7 V), (VREF = 2.13 V, VDDA>2.7 V) SIDA98A A_GAINERR_VDDA Gain error - 0.2 - % Reference Source: SRSS (VREF = 1.20 V, VDDA< 2.2V), (VREF = 1.6 V, 2.2 V < VDDA < 2.7 V), (VREF = 2.13 V, VDDA > 2.7 V) SIDA99 A_OFFSET_VREF Input offset voltage - 0.5 - LSB After ADC calibration, Ref. Src = SRSS, (VREF = 1.20 V, VDDA < 2.2 V), (VREF = 1.6 V, 2.2 V<VDDA < 2.7 V), (VREF = 2.13 V, VDDA > 2.7 V) SIDA99A A_OFFSET_VDDA Input offset voltage - 0.5 - LSB After ADC calibration, Ref. Src = SRSS, (VREF = 1.20 V, VDDA < 2.2 V), (VREF = 1.6 V, 2.2 V<VDDA < 2.7 V), (VREF = 2.13 V, VDDA > 2.7 V) Document Number: 002-18449 Rev. *J Page 50 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 25. CSD ADC Specifications (continued) Spec ID# Parameter Description Min Typ Max Unit Details / Conditions SIDA100 A_ISAR_VREF Current consumption - 0.3 - mA CSD ADC Block current SIDA100A A_ISAR_VDDA Current consumption - 0.3 - mA CSD ADC Block current SIDA101 A_VINS_VREF Input voltage range - single ended VSSA - VREF V (VREF = 1.20 V, VDDA < 2.2 V), (VREF =1.6 V, 2.2 V<VDDA < 2.7 V), (VREF = 2.13 V, VDDA > 2.7 V) SIDA101A A_VINS_VDDA Input voltage range - single ended VSSA - VDDA V (VREF = 1.20 V, VDDA < 2.2 V), (VREF = 1.6 V, 2.2 V<VDDA < 2.7 V), (VREF = 2.13 V, VDDA > 2.7 V) SIDA103 A_INRES Input charging resistance - 15 - k - SIDA104 A_INCAP Input capacitance - 41 - pF - SIDA106 A_PSRR Power supply rejection ratio (DC) - 60 - dB - SIDA107 A_TACQ Sample acquisition time - 10 - s Measured with 50- source impedance. 10 s is default software driver acquisition time setting. Settling to within 0.05%. SIDA108 A_CONV8 Conversion time for 8-bit resolution at conversion rate = Fhclk/(2"(N+2)). Clock frequency = 50 MHz. - 25 - s Does not include acquisition time. SIDA108A A_CONV10 Conversion time for 10-bit resolution at conversion rate = Fhclk/(2"(N+2)). Clock frequency = 50 MHz. - 60 - s Does not include acquisition time. SIDA109 A_SND_VRE Signal-to-noise and Distortion ratio (SINAD) - 57 - dB Measured with 50- source impedance SIDA109A A_SND_VDDA Signal-to-noise and Distortion ratio (SINAD) - 52 - dB Measured with 50- source impedance SIDA111 A_INL_VREF Integral non-linearity. 11.6 ksps - - 2 LSB Measured with 50- source impedance SIDA111A A_INL_VDDA Integral non-linearity. 11.6 ksps - - 2 LSB Measured with 50- source impedance SIDA112 A_DNL_VREF Differential non-linearity. 11.6 ksps - - 1 LSB Measured with 50- source impedance SIDA112A A_DNL_VDDA Differential non- linearity. 11.6 ksps - - 1 LSB Measured with 50- source impedance Document Number: 002-18449 Rev. *J Page 51 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Digital Peripherals Table 26. Timer/Counter/PWM (TCPWM) Specifications Spec ID# Parameter Description Min Typ Max Unit Details / Conditions SID.TCPWM.1 ITCPWM1 Block current consumption at 8 MHz - - 70 A All modes (TCPWM) SID.TCPWM.2 ITCPWM2 Block current consumption at 24 MHz - - 180 A All modes (TCPWM) SID.TCPWM.2A ITCPWM3 Block current consumption at 50 MHz - - 270 A All modes (TCPWM) SID.TCPWM.2B ITCPWM4 Block current consumption at 100 MHz - - 540 A All modes (TCPWM) - - 100 MHz Fc max = Fcpu Maximum = 100 MHz SID.TCPWM.3 TCPWMFREQ Operating frequency SID.TCPWM.4 TPWMENEXT Input Trigger Pulse Width for all Trigger Events 2 / Fc - - ns Trigger Events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected. Fc is counter operating frequency. SID.TCPWM.5 TPWMEXT Output Trigger Pulse widths 1.5 / Fc - - ns Minimum possible width of Overflow, Underflow, and CC (Counter equals Compare value) trigger outputs SID.TCPWM.5A TCRES Resolution of Counter 1 / Fc - - ns Minimum time between successive counts SID.TCPWM.5B PWMRES PWM Resolution 1 / Fc - - ns Minimum pulse width of PWM Output SID.TCPWM.5C QRES Quadrature inputs resolution 2 / Fc - - ns Minimum pulse width between Quadrature phase inputs. Delays from pins should be similar. Table 27. Serial Communication Block (SCB) Specifications Spec ID# Parameter Description Min Typ Max Unit Details / Conditions 2 Fixed I C DC Specifications SID149 II2C1 Block current consumption at 100 kHz - - 30 A - SID150 II2C2 Block current consumption at 400 kHz - - 80 A - SID151 II2C3 Block current consumption at 1 Mbps - - 180 A - - - 1.7 A At 60 C - - 1 SID152 Fixed II2C4 I2C enabled 2 I C AC Specifications SID153 FI2C1 in Deep Sleep mode Bit Rate Mbps - Fixed UART DC Specifications SID160 IUART1 Block current consumption at 100 kbps - - 30 A - SID161 IUART2 Block current consumption at 1000 kbps - - 180 A - - - 3 - - 8 - - 220 Fixed UART AC Specifications SID162A FUART1 SID162B FUART2 Bit Rate Mbps ULP Mode LP Mode Fixed SPI DC Specifications SID163 ISPI1 Block current consumption at 1 Mbps Document Number: 002-18449 Rev. *J A - Page 52 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 27. Serial Communication Block (SCB) Specifications (continued) Spec ID# Parameter Description Min Typ Max Unit Details / Conditions SID164 ISPI2 Block current consumption at 4 Mbps - - 340 A - SID165 ISPI3 Block current consumption at 8 Mbps - - 360 A - SID165A ISP14 Block current consumption at 25 Mbps - - Fixed SPI AC Specifications for LP Mode (1.1 V) unless noted otherwise. 800 A - SID166 FSPI SID166A FSPI_IC SID166B FSPI_EXT SPI Operating Frequency Master and Externally Clocked Slave - - 25 MHz 14-MHz max for ULP (0.9 V) mode SPI Slave Internally Clocked - - 15 MHz 5-MHz max for ULP (0.9 V) mode SPI Operating Frequency Master (FSCB is SPI Clock) - - FSCB/4 MHz FSCB max is 100 MHz in LP mode, 25 MHz max in ULP mode Fixed SPI Master mode AC Specifications for LP Mode (1.1 V) unless noted otherwise. SID167 TDMO MOSI Valid after SClock driving edge - - 12 ns 20-ns max for ULP (0.9 V) mode SID168 TDSI MISO Valid before SClock capturing edge 5 - - ns Full clock, late MISO sampling SID169 THMO MOSI data hold time 0 - - ns Referred to Slave capturing edge SID169A TSSELMSCK1 SSEL Valid to first SCK Valid edge 18 - - ns Referred to Master clock edge SID169B TSSELMSCK2 SSEL Hold after last SCK Valid edge 18 - - ns Referred to Master clock edge Fixed SPI Slave mode AC Specifications for LP Mode (1.1 V) unless noted otherwise. SID170 TDMI MOSI Valid before Sclock Capturing edge 5 - - ns - SID171A TDSO_EXT MISO Valid after Sclock driving edge in Ext. Clk. mode - - 20 ns 35-ns max. for ULP (0.9 V) mode SID171 TDSO MISO Valid after Sclock driving edge in Internally Clk. Mode - - TDSO_EXT + 3 x Tscb ns Tscb is Serial Comm. Block clock period. SID171B TDSO MISO Valid after Sclock driving edge in Internally Clk. Mode with Median filter enabled. - - TDSO_EXT + 4 x Tscb ns Tscb is Serial Comm. Block clock period. SID172 Previous MISO data hold time 5 - - ns - SID172A TSSELSCK1 THSO SSEL Valid to first SCK Valid edge 65 - - ns - SID172B TSSELSCK2 SSEL Hold after Last SCK Valid edge 65 - - ns LCD Specifications Table 28. LCD Direct Drive DC Specifications Min Typ Max SID154 Spec ID# Parameter ILCDLOW Operating current in low-power mode Description - 5 - SID155 CLCDCAP LCD capacitance per segment/common driver - 500 5000 pF SID156 LCDOFFSET Long-term segment offset - 20 - mV SID157 ILCDOP1 PWM Mode current. 3.3-V bias. 8-MHz IMO. 25 C. - 0.6 - mA 32 x 4 segments 50 Hz SID158 ILCDOP2 PWM Mode current. 3.3-V bias. 8-MHz IMO. 25 C. - 0.5 - mA 32 x 4 segments 50 Hz Document Number: 002-18449 Rev. *J Unit Details / Conditions A 16 x 4 small segment display at 50 Hz - - Page 53 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 29. LCD Direct Drive AC Specifications Spec ID# Parameter SID159 FLCD Description LCD frame rate Min Typ Max Unit 10 50 150 Hz Min Typ Max Unit - - 6 mA Details / Conditions - Memory Flash Table 30. Flash DC Specifications[4] Spec ID# Parameter SID173A IPE Description Erase and program current Details / Conditions - Table 31. Flash AC Specifications Spec ID# SID174 Min Typ Max Unit TROWWRITE Parameter Row write time (erase & program) Description - - 16 ms Row = 512 bytes Row erase time - - 11 ms - - - 5 ms - SID175 TROWERASE SID176 TROWPROGRAM Row program time after erase SID178 TBULKERASE SID179 TSECTORERASE Sector erase time (256 KB) Bulk erase time (1024 KB) Details / Conditions - - 11 ms - - - 11 ms 512 rows per sector SID178S TSSERIAE Subsector erase time - - 11 ms 8 rows per subsector SID179S TSSWRITE Subsector write time; 1 erase plus 8 program times - - 51 ms - SID180S TSWRITE Sector write time; 1 erase plus 512 program times - - 2.6 seconds - SID180 TDEVPROG Total device write time - - 15 seconds - SID181 FEND Flash Endurance 100 k - - cycles - FRET1 Flash Retention. TA 25 C, 100 k P/E cycles 10 - - years - SID182A FRET2 Flash Retention. TA 85 C, 10 k P/E cycles 10 - - years - SID182B FRET3 Flash Retention. TA 55 C, 20 k P/E cycles 20 - - years - SID256 TWS100 Number of Wait states at 100 MHz 3 - - - SID257 TWS50 Number of Wait states at 50 MHz 2 - - - SID182 Note 4. It can take as much as 16 milliseconds to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Document Number: 002-18449 Rev. *J Page 54 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet System Resources Power-on-Reset Table 32. Power-On-Reset with Brown-out DC Specifications Spec ID# Parameter Description Min Typ Max Unit Details / Conditions Precise POR (PPOR) Specifications SID190 VFALLPPOR BOD trip voltage in Active and Sleep modes. VDDD. 1.54 - - V BOD Reset guaranteed for levels below 1.54 V SID192 VFALLDPSLP BOD trip voltage in Deep Sleep. VDDD 1.54 - - V - - - 100 Min Typ Max - - 10 Min Typ Max Unit SID192A VDDRAMP Maximum power supply ramp rate (any supply) mV/s Active mode Table 33. POR with Brown-out AC Specification Spec ID# Parameter SID194A VDDRAMP_DS Description Maximum power supply ramp rate (any supply) in Deep Sleep Unit Details / Conditions mV/s BOD operation guaranteed Voltage Monitors Table 34. Voltage Monitors DC Specifications Spec ID# Parameter Description Details / Conditions SID195R VHVD0 1.18 1.23 1.27 V - SID195 VHVDI1 1.38 1.43 1.47 V - SID196 VHVDI2 1.57 1.63 1.68 V - SID197 VHVDI3 1.76 1.83 1.89 V - SID198 VHVDI4 1.95 2.03 2.1 V - SID199 VHVDI5 2.05 2.13 2.2 V - SID200 VHVDI6 2.15 2.23 2.3 V - SID201 VHVDI7 2.24 2.33 2.41 V - SID202 VHVDI8 2.34 2.43 2.51 V - SID203 VHVDI9 2.44 2.53 2.61 V - SID204 VHVDI10 2.53 2.63 2.72 V - SID205 VHVDI11 2.63 2.73 2.82 V - SID206 VHVDI12 2.73 2.83 2.92 V - SID207 VHVDI13 2.82 2.93 3.03 V - SID208 VHVDI14 2.92 3.03 3.13 V - SID209 VHVDI15 3.02 3.13 3.23 V - SID211 LVI_IDD - 5 15 A - Min Typ Max Unit - - 170 ns Block current Table 35. Voltage Monitors AC Specification Spec ID# SID212 Parameter TMONTRIP Description Voltage monitor trip time Document Number: 002-18449 Rev. *J Details / Conditions - Page 55 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet SWD and Trace Interface Table 36. SWD and Trace Specifications Spec ID# Parameter Description Min Typ Max Unit Details / Conditions SID214 F_SWDCLK2 1.7 V VDDD 3.6 V - - 25 MHz LP mode. VCCD = 1.1 V SID214L F_SWDCLK2L 1.7 V VDDD 3.6 V - - 12 MHz ULP mode. VCCD = 0.9 V. T_SWDI_SETUP T = 1/f SWDCLK 0.25 * T - - ns - SID216 T_SWDI_HOLD T = 1/f SWDCLK 0.25 * T - - ns - SID217 T_SWDO_VALID T = 1/f SWDCLK - - 0.5 * T ns - SID217A T_SWDO_HOLD T = 1/f SWDCLK 1 - - ns - SID215 SID214T F_TRCLK_LP1 With Trace Data setup/hold times of 2/1 ns respectively - - 75 MHz LP Mode. VDD = 1.1 V SID215T F_TRCLK_LP2 With Trace Data setup/hold times of 3/2 ns respectively - - 70 MHz LP Mode. VDD = 1.1 V SID216T F_TRCLK_ULP With Trace Data setup/hold times of 3/2 ns respectively - - 25 MHz ULP Mode. VDD = 0.9 V Min Typ Max Unit - 9 15 A Min Typ Max Unit Internal Main Oscillator Table 37. IMO DC Specifications Spec ID# SID218 Parameter IIMO1 Description IMO operating current at 8 MHz Details / Conditions - Table 38. IMO AC Specifications Spec ID# Parameter Description SID223 FIMOTOL1 Frequency variation centered on 8 MHz - - 2 % SID227 TJITR Cycle-to-Cycle and Period jitter - 250 - ps Min Typ Max Unit - 0.3 0.7 A Min Typ Max Unit Details / Conditions - - Internal Low-Speed Oscillator Table 39. ILO DC Specification Spec ID# SID231 Parameter IILO2 Description ILO operating current at 32 kHz Details / Conditions - Table 40. ILO AC Specifications Spec ID# Parameter Description Details / Conditions SID234 TSTARTILO1 ILO startup time - - 7 s Startup time to 95% of final frequency SID236 TLIODUTY ILO Duty cycle 45 50 55 % - SID237 FILOTRIM1 32-kHz trimmed frequency 28.8 32 36.1 kHz Document Number: 002-18449 Rev. *J Page 56 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Crystal Oscillator Table 41. ECO Specifications Spec ID# Parameter Description Min Typ Max Unit Details / Conditions Block operating current with Cload up to 18 pF - 800 1600 A Crystal frequency range 16 - 35 MHz Block operating current with 32-kHz crystal - 0.38 1 A SID321E ESR32K Equivalent Series Resistance - 80 - k - SID322E PD32K Drive level - - 1 W - MHz ECO DC Specifications SID316 IDD_MHz Max = 33 MHz, Type = 16 MHz MHz ECO AC Specifications SID317 F_MHz - kHz ECO DC Specification SID318 IDD_kHz - kHz ECO AC Specification SID319 F_kHz 32-kHz trimmed frequency - 32.768 - kHz - SID320 Ton_kHz Startup time - - 500 ms - Frequency tolerance - 50 250 ppm - Min Typ Max Unit SID320E FTOL32K External Clock Table 42. External Clock Specifications Spec ID# Parameter Description Details / Conditions SID305 EXTCLKFREQ External Clock input Frequency 0 - 100 MHz - SID306 EXTCLKDUTY Duty cycle; Measured at VDD/2 45 - 55 % - PLL Table 43. PLL Specifications Min Typ Max Unit SID305P PLL_LOCK Spec ID# Parameter Time to achieve PLL Lock Description - 16 35 s - Details / Conditions SID306P PLL_OUT Output frequency from PLL Block - - 150 MHz - SID307P PLL_IDD PLL Current - 0.55 1.1 mA Typ at 100 MHz out. SID308P PLL_JTR Period Jitter - - 150 ps 100-MHz output frequency Description Min Typ Max Unit Clock switching from clk1 to clk2 in clock periods[5] - - Clock Source Switching Time Table 44. Clock Source Switching Time Specifications Spec ID# SID262 Parameter TCLKSWITCH Details / Conditions 4 clk1 + - periods 3 clk2 Note 5. As an example, if the clk_path[1] source is changed from the IMO to the FLL (see Figure 4) then clk1 is the IMO and clk2 is the FLL. Document Number: 002-18449 Rev. *J Page 57 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet FLL Table 45. Frequency Locked Loop (FLL) Specifications Min Typ Max Unit SID450 Spec ID# FLL_RANGE Parameter Input frequency range. Description 0.001 - 100 MHz Lower limit allows lock to USB SOF signal (1 kHz). Upper limit is for External input. Details / Conditions SID451 FLL_OUT_DIV2 Output frequency range. VCCD = 1.1 V 24.00 - 100.00 MHz Output range of FLL divided-by-2 output SID451A FLL_OUT_DIV2 Output frequency range. VCCD = 0.9 V 24.00 - 50.00 MHz Output range of FLL divided-by-2 output SID452 FLL_DUTY_DIV2 Divided-by-2 output; High or Low 47.00 - 53.00 % - SID454 FLL_WAKEUP Time from stable input clock to 1% of final value on deep sleep wakeup - - 7.50 s With IMO input, less than 10 C change in temperature while in Deep Sleep, and Fout 50 MHz. SID455 FLL_JITTER Period jitter (1 sigma at 100 MHz) - - 35.00 ps 50 ps at 48 MHz, 35 ps at 100 MHz SID456 FLL_CURRENT CCO + Logic current - - 5.50 Min Typ Max Unit A/MHz - UDB Table 46. UDB AC Specifications Spec ID# Parameter Description Details / Conditions Data Path Performance SID249 FMAX-TIMER Max frequency of 16-bit timer in a UDB pair - - 100 MHz SID250 FMAX-ADDER Max frequency of 16-bit adder in a UDB pair - - 100 MHz SID251 FMAX_CRC Max frequency of 16-bit CRC/PRS in a UDB pair - - 100 MHz Max frequency of 2-pass PLD function in a UDB pair - - 100 MHz Prop. delay for clock in to data out - 5 - ns - - - - PLD Performance in UDB SID252 FMAX_PLD - Clock to Output Performance SID253 TCLK_OUT_UDB1 UDB Port Adaptor Specifications Conditions: 10-pF load, 3-V VDDIO and VDDD SID263 TLCLKDO LCLK to Output delay - - 11 ns - SID264 TDINLCLK Input setup time to LCLCK rising edge - - 7 ns - SID265 TDINLCLKHLD Input hold time from LCLK rising edge 5 - - ns - SID266 TLCLKHIZ LCLK to Output tristated - - 28 ns - SID267 TFLCLK LCLK frequency SID268 TLCLKDUTY LCLK duty cycle (percentage high) Document Number: 002-18449 Rev. *J - - 33 MHz - 40% - 60% % - Page 58 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet USB Table 47. USB Specifications (USB requires LP Mode 1.1-V Internal Supply) Spec ID# Parameter Description Min Typ Max Unit Details / Conditions USB Block Specifications SID322U Vusb_3.3 Device supply for USB operation 3.15 - 3.6 V USB Configured SID323U Vusb_3 Device supply for USB operation (functional operation only) 2.85 - 3.6 V USB Configured SID325U Iusb_config Device supply current in Active mode - 8 - mA VDDD = 3.3 V SID328 Isub_suspend Device supply current in Sleep mode - 0.5 - mA VDDD = 3.3 V, Device connected SID329 Isub_suspend Device supply current in Sleep mode - 0.3 - mA VDDD = 3.3 V, Device disconnected SID330U USB_Drive_Res USB driver impedance 28 - 44 Series resistors are on chip SID331U USB_Pulldown USB pull-down resistors in Host mode 14.25 - 24.8 k - SID332U USB_Pullup_Idle Idle mode range 900 - 1575 Bus idle SID333U USB_Pullup Active mode 1425 - 3090 Upstream device transmitting QSPI Table 48. QSPI Specifications Spec ID# Parameter Description Min Typ Max Unit Details / Conditions SMIF QSPI Specifications. All specs with 15-pF load. SID390Q Fsmifclock SMIF QSPI output clock frequency - - 80 MHz LP mode (1.1 V) SID390QU Fsmifclocku SMIF QSPI output clock frequency - - 50 MHz ULP mode (0.9 V). Guaranteed by Char. SID397Q Idd_qspi Block current in LP mode (1.1 V) - - 1900 A LP mode (1.1 V) SID398Q Idd_qspi_u Block current in ULP mode (0.9 V) - - 590 A ULP mode (0.9 V) SID391Q Tsetup Input data set-up time with respect to clock capturing edge 4.5 - - ns - SID392Q Tdatahold Input data hold time with respect to clock capturing edge 0 - - ns - SID393Q Tdataoutvalid Output data valid time with respect to clock falling edge - - 3.7 ns 7.5-ns max for ULP mode (0.9 V) SID394Q Tholdtime Output data hold time with respect to clock rising edge 3 - - ns - SID395Q Tseloutvalid Output Select valid time with respect to clock rising edge - - 7.5 ns 15-ns max for ULP mode (0.9 V) SID396Q Tselouthold Output Select hold time with respect to 0.5*Tsc clock rising edge lk - - ns Tsclk = Fsmifclk cycle time Document Number: 002-18449 Rev. *J Page 59 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Audio Subsystem Table 49. Audio Subsystem Specifications Spec ID# Parameter Description Min Typ Max Unit Details / Conditions PDM Specifications SID400P PDM_IDD1 PDM Active current, Stereo operation, 1-MHz clock - 175 - A 16-bit audio at 16 ksps SID401 PDM_IDD2 PDM Active current, Stereo operation, 3-MHz clock - 600 - A 24-bit audio at 48 ksps SID402 PDM_JITTER RMS Jitter in PDM clock -200 - 200 ps - SID403 PDM_CLK PDM Clock speed 0.384 - 3.072 MHz - SID403A PDM_BLK_CLK PDM Block input clock 1.024 - 49.152 MHz - SID403B PDM_SETUP Data input set-up time to PDM_CLK edge 10 - - ns - SID403C PDM_HOLD Data input hold time to PDM_CLK edge 10 - - ns - SID404 PDM_OUT Audio sample rate 8 - 48 ksps - SID405 PDM_WL Word Length 16 - 24 bits - SID406 PDM_SNR Signal-to-Noise Ratio (A-weighted) - 100 - dB PDM input, 20 Hz to 20 kHz BW SID407 PDM_DR Dynamic Range (A-weighted) - 100 - dB 20 Hz to 20 kHz BW, - 60 dB FS SID408 PDM_FR Frequency Response -0.2 - 0.2 dB DC to 0.45. DC Blocking filter off. SID409 PDM_SB Stop Band - 0.566 - f - SID410 PDM_SBA Stop Band Attenuation - 60 - dB - SID411 PDM_GAIN Adjustable Gain -12 - 10.5 dB PDM to PCM, 1.5 dB/step SID412 PDM_ST Startup time - 48 - WS (Word Select) cycles I2S Specifications. The same for LP and ULP modes unless stated otherwise. SID413 I2S_WORD Length of I2S Word 8 - 32 bits - SID414 I2S_WS Word Clock frequency in LP mode - - 192 kHz 12.288-MHz bit clock with 32-bit word SID414M I2S_WS_U Word Clock frequency in ULP mode - - 48 kHz 3.072-MHz bit clock with 32-bit word SID414A I2S_WS_TDM Word Clock frequency in TDM mode for LP - - 48 kHz Eight 32-bit channels SID414X I2S_WS_TDM_U Word Clock frequency in TDM mode for ULP - - 12 kHz Eight 32-bit channels I2S Slave Mode SID430 TS_WS WS Setup Time to the Following Rising Edge of SCK for LP Mode 5 - - ns - SID430U TS_WS WS Setup Time to the Following Rising Edge of SCK for ULP Mode 11 - - ns - SID430A TH_WS WS Hold Time to the Following Edge of SCK TMCLK_SOC + 5 - - ns - SID432 TD_SDO - Delay Time of TX_SDO Transition (TMCLK_SOC + from Edge of TX_SCK for LP mode 25) - TMCLK_SOC + 25 ns Associated clock edge depends on selected polarity SID432U TD_SDO Delay Time of TX_SDO Transition from Edge of TX_SCK for ULP mode - TMCLK_SOC + 70 ns Associated clock edge depends on selected polarity Document Number: 002-18449 Rev. *J - (TMCLK_SOC + 70) Page 60 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Table 49. Audio Subsystem Specifications (continued) Spec ID# Parameter Description Min Typ Max Unit Details / Conditions 5 - - ns - 11 - - ns - TMCLK_SOC + 5 - - ns - SID433 TS_SDI RX_SDI Setup Time to the Following Edge of RX_SCK in Lp Mode SID433U TS_SDI RX_SDI Setup Time to the Following Edge of RX_SCK in ULP mode SID434 TH_SDI RX_SDI Hold Time to the Rising Edge of RX_SCK SID435 TSCKCY TX/RX_SCK Bit Clock Duty Cycle 45 - 55 % - I2S Master Mode SID437 TD_WS WS Transition Delay from Falling Edge of SCK in LP mode -10 - 20 ns - SID437U TD_WS_U WS Transition Delay from Falling Edge of SCK in ULP mode -10 - 40 ns - SID438 TD_SDO SDO Transition Delay from Falling Edge of SCK in LP mode -10 - 20 ns - SID438U TD_SDO SDO Transition Delay from Falling Edge of SCK in ULP mode -10 - 40 ns - SID439 TS_SDI SDI Setup Time to the Associated Edge of SCK 5 - - ns Associated clock edge depends on selected polarity SID440 TH_SDI SDI Hold Time to the Associated Edge of SCK TMCLK_SOC + 5 - - ns T is TX/RX_SCK Bit Clock period. Associated clock edge depends on selected polarity. SID443 TSCKCY SCK Bit Clock Duty Cycle 45 - 55 % - SID445 FMCLK_SOC MCLK_SOC Frequency in LP mode 1.024 - 98.304 MHz FMCLK_SOC = 8 * Bit-clock SID445U FMCLK_SOC_U MCLK_SOC Frequency in ULP mode 1.024 - 24.576 MHz FMCLK_SOC_U = 8 * Bit-clock SID446 TMCLKCY MCLK_SOC Duty Cycle 45 - 55 % - SID447 TJITTER MCLK_SOC Input Jitter -100 - 100 ps - Document Number: 002-18449 Rev. *J Page 61 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Smart I/O Table 50. Smart I/O Specifications Min Typ Max Unit SID420 Spec ID# SMIO_BYP Parameter Smart I/O Bypass delay Description - - 2 ns - Details / Conditions SID421 SMIO_LUT Smart I/O LUT prop delay - 8 - ns - Min Typ Max Unit Precision ILO (PILO) Table 51. PILO Specifications Spec ID# Parameter Description Details / Conditions SID 430R IPILO Operating current - 1.2 4 A - SID431 F_PILO PILO nominal frequency - 32768 - Hz T = 25 C with 20-ppm crystal SID432R ACC_PILO PILO accuracy with periodic calibration -500 - 500 ppm Document Number: 002-18449 Rev. *J - Page 62 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Ordering Information Table 52 lists the CY8C62x6 and CY8C62x7 part numbers and features. All devices include DC-DC converter, QSPI SMIF, ADC, DAC, 9 SCBs, USB-FS, 32 TCPWMs, 2 PDM, and I2S. See also the product selector guide. 62 MPN CPU Speed (CM4) CPU Speed (CM0+) Single CPU/Dual CPU ULP/LP Flash (KB) SRAM (KB) No. of CTBMs No. of UDBs CapSense GPIOs CRYPTO Secure Boot Package Family Table 52. Marketing Part Numbers CY8C6246BZI-D04 150/50 100/25 Dual FLEX 512 128 0 0 No 100 No No 124-BGA CY8C6247BZI-D44 150/50 100/25 Dual FLEX 1024 288 0 0 Yes 100 Yes Yes 124-BGA CY8C6247BZI-D34 150/50 100/25 Dual FLEX 1024 288 1 12 Yes 100 No No 124-BGA CY8C6247BZI-D54 150/50 100/25 Dual FLEX 1024 288 1 12 Yes 100 Yes Yes CY8C6247FDI-D02 150/50 100/25 Dual FLEX 1024 288 0 0 No 62 No No 80-WLCSP CY8C6247FDI-D32 150/50 100/25 Dual FLEX 1024 288 1 12 Yes 62 No No 80-WLCSP CY8C6247FTI-D52 150/50 100/25 Dual FLEX 1024 288 1 12 Yes 62 Yes Yes Thin 80-WLCSP CY8C6247FDI-D52 150/50 100/25 Dual FLEX 1024 288 1 12 Yes 62 Yes Yes 80-WLCSP Document Number: 002-18449 Rev. *J 124-BGA Page 63 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet PSoC 6 MPN Decoder CY XX 6 A B C DD E - FF G H I JJ K L Field CY XX 6 A B Description Cypress Firmware Architecture Line Speed Values CY Cypress 8C Standard B0 Secure Boot v1 S0 Std. Secure - AWS 6 Memory Size (Flash/SRAM) PSoC 6 0 Value 1 Programmable 2 Performance 3 Connectivity 4 Security 2 100 MHz 3 150 MHz 4 150/50 MHz 0-3 C Meaning Reserved 4 256K/128K 5 512K/256K 6 512K/128K 7 1024K/288K 8 1024K/512K 9 Reserved A 2048K/1024K Field Description E Temperature Range FF Feature Code Values C Consumer I Industrial Q Extended Industrial S2-S6 BL G CPU Core H Attributes Code I GPIO count JJ Engineering sample (optional) K Die Revision (optional) L Tape/Reel Shipment (optional) Meaning Cypress internal Integrated BLE F Single Core D Dual Core 0-9 Feature set 1 31-50 2 51-70 3 71-90 4 91-110 ES Engineering samples or not Base A1-A9 T Die revision Tape and Reel shipment AZ, AX TQFP DD Package LQ QFN BZ BGA FM M-CSP FN, FD, WLCSP FT Document Number: 002-18449 Rev. *J Page 64 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Packaging This product line is offered in 124-BGA[6] and 80-ball WLCSP packages in 0.43 mm and 0.33 mm[6] heights. The 124-BGA package qualification is in process. Table 53. Package Dimensions Spec ID# Package PKG_1 124-BGA PKG_2 80-WLCSP PKG_3 Description Package Drawing Number 124-BGA, 9 mm 9 mm 1 mm height with 0.65-mm pitch 001-97718 80-WLCSP, 3.7 mm 3.2 mm 0.43 mm height with 0.35-mm pitch 002-20310 Thin 80-WLCSP Thin 80 -WLCSP, 3.7 mm 3.3 mm 0.33mm height with 0.35-mm pitch 002-23411 Table 54. Package Characteristics Conditions Min Typ Max Unit TA Parameter Operating ambient temperature Description - -40 25 85 C TJ Operating junction temperature - -40 - 100 C TJA Package JA (124-BGA) - - 36.2 - C/watt TJC Package JC (124-BGA) - - 15 - C/watt TJA Package JA (80-WLCSP) - - 20.4 - C/watt TJC Package JC (80-WLCSP) - - 0.2 - C/watt TJA Package JA (Thin 80-WLCSP) - - 20.4 - C/watt TJC Package JC (Thin 80-WLCSP) - - 0.2 - C/watt Table 55. Solder Reflow Peak Temperature Package Maximum Peak Temperature Maximum Time at Peak Temperature All 260 C 30 seconds Table 56. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package MSL 124-BGA MSL 3 80-WLCSP Packages MSL 1 Note 6. The 124-BGA and Thin 80-WLCSP packages are in the process of qualification. Document Number: 002-18449 Rev. *J Page 65 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Figure 14. 124-BGA 9.0 x 9.0 x1.0 mm 001-97718 *B Document Number: 002-18449 Rev. *J Page 66 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Figure 15. 80-Ball WLCSP 3.676 x 3.190 x 0.467 mm DIMENSIONS NOTES SYMBOL MIN. NOM. MAX. A 0.387 0.427 0.467 A1 0.122 0.182 3.676 BSC D E 3.190 BSC D1 3.031 BSC E1 2.450 BSC n Ob 1. ALL DIMENSIONS ARE IN MILLIMETERS. 80 0.188 0.218 eD 0.303 BSC eE 0.350 BSC 0.248 002-20310 *A Document Number: 002-18449 Rev. *J Page 67 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Figure 16. Thin 80-Ball WLCSP 3.676 x 3.190 x 0.33 mm 6 6 7 5 NOTES: DIMENSIONS SYMBOL 1. ALL DIMENSIONS ARE IN MILLIMETERS. MIN NOM MAX A - - 0.33 A1 0.081 - - 2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. 3. "e" REPRESENTS THE SOLDER BALL GRID PITCH. 4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. D 3.676 BSC E 3.190 BSC D1 3.031 BSC E1 2.450 BSC MD 11 ME 15 DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. N 80 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0. Ob 0.1035 0.1150 eD 0.303 BSC eE 0.350 BSC SD 0.00 BSC SE 0.00 BSC N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND 0.1265 WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2. 7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALIZED MARK, INDENTATION OR OTHER MEANS. 8. JEDEC SPECIFICATION NO. REF. : N/A 002-23411 ** Document Number: 002-18449 Rev. *J Page 68 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Acronyms Acronym Description 3DES triple DES (data encryption standard) ADC analog-to-digital converter AES Acronym FS Description full-speed GND Ground advanced encryption standard GPIO general-purpose input/output, applies to a PSoC pin AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm data transfer bus HMAC Hash-based message authentication code HSIOM high-speed I/O matrix AMUX analog multiplexer I/O input/output, see also GPIO, DIO, SIO, USBIO AMUXBUS analog multiplexer bus I2C, or IIC Inter-Integrated Circuit, a communications protocol API application programming interface I2S inter-IC sound Arm(R) advanced RISC machine, a CPU architecture IC integrated circuit BGA ball grid array IDAC current DAC, see also DAC, VDAC BOD brown-out detect IDE integrated development environment CAD computer aided design ILO internal low-speed oscillator, see also IMO CCO current controlled oscillator IMO internal main oscillator, see also ILO CM0+ Cortex-M0+, an Arm CPU INL integral nonlinearity, see also DNL CM4 Cortex-M4, an Arm CPU IoT internet of things CMAC cipher-based message authentication code IPC inter-processor communication CMOS complementary metal-oxide-semiconductor, a process technology for IC fabrication IRQ interrupt request ISR interrupt service routine CMRR common-mode rejection ratio JTAG Joint Test Action Group CPU central processing unit LCD liquid crystal display CRC cyclic redundancy check, an error-checking protocol LIN Local Interconnect Network, a communications protocol CSD CapSense Sigma-Delta LP low power CSX Cypress mutual capacitance sensing method. See also CSD LS low-speed DAC digital-to-analog converter, see also IDAC, VDAC LUT lookup table DAP debug access port LVD low-voltage detect, see also LVI DES data encryption standard LVTTL low-voltage transistor-transistor logic DMA direct memory access, see also TD MAC multiply-accumulate DNL differential nonlinearity, see also INL MCU microcontroller unit DSI digital system interconnect MCWDT multi-counter watchdog timer DU data unit MISO master-in slave-out ECC elliptic curve cryptography MMIO memory-mapped input output ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory MOSI master-out slave-in MPU memory protection unit MSL moisture sensitivity level million samples per second EMI electromagnetic interference Msps ESD electrostatic discharge MTB micro trace buffer ETM embedded trace macrocell MUL multiplier FIFO first-in, first-out NC no connect FLL frequency locked loop NMI nonmaskable interrupt floating-point unit NVIC nested vectored interrupt controller FPU Document Number: 002-18449 Rev. *J Page 69 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Acronym OTP Description Acronym Description one-time programmable SWV OVT overvoltage tolerant TCPWM timer, counter, pulse-width modulator PASS programmable analog subsystem TDM time division multiplexed PCB printed circuit board TQFP thin quad flat package PCM pulse code modulation TRM technical reference manual PDM pulse density modulation TRNG true random number generator PHY physical layer TX transmit PICU port interrupt control unit UART PLL phase-locked loop Universal Asynchronous Transmitter Receiver, a communications protocol PMIC power management integrated circuit UDB universal digital block POR power-on reset PPU peripheral protection unit PRNG pseudo random number generator PSoC(R) Programmable System-on-ChipTM PSRR power supply rejection ratio PWM pulse-width modulator QD quadrature decoder QSPI quad serial peripheral interface RAM random-access memory RISC reduced-instruction-set computing RMS root-mean-square ROM read-only memory RSA Rivest-Shamir-Adleman, a public-key cryptography algorithm RTC real-time clock RX receive S/H sample and hold SAR successive approximation register SARMUX SAR ADC multiplexer bus SCB serial communication block SFlash supervisory flash SHA secure hash algorithm SINAD signal to noise and distortion ratio SNR signal-to-noise ration SOF start of frame SPI Serial Peripheral Interface, a communications protocol SRAM static random access memory SROM supervisory read-only memory SRSS system resources subsystem SWD serial wire debug, a test protocol SWJ serial wire JTAG SWO single wire output Document Number: 002-18449 Rev. *J serial-wire viewer ULP ultra-low power USB Universal Serial Bus WCO watch crystal oscillator WDT watchdog timer WIC wakeup interrupt controller WLCSP wafer level chip scale package XIP execute-in-place XRES external reset input pin Page 70 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Document Conventions Unit of Measure Table 57. Unit of Measure (continued) Table 57. Unit of Measure Symbol Symbol Unit of Measure H Unit of Measure microhenry degrees Celsius s microsecond dB decibel V microvolt fF femto farad W microwatt Hz hertz mA milliampere KB 1024 bytes ms millisecond kbps kilobits per second mV millivolt khr kilohour nA nanoampere kHz kilohertz ns nanosecond k kilo ohm nV nanovolt ksps kilosamples per second ohm LSB least significant bit pF picofarad Mbps megabits per second ppm parts per million MHz megahertz ps picosecond M mega-ohm s second Msps megasamples per second sps samples per second A microampere sqrtHz square root of hertz F microfarad V volt C Document Number: 002-18449 Rev. *J Page 71 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Errata This section describes the errata for the PSoC 62 Product Family. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this document to the device's datasheet for a complete functional description. Contact your local Cypress Sales Representative if you have questions. Part Numbers Affected Part Number Device Characteristics CY8C6xx PSoC 62 Product Family PSoC 62 Qualification Status Production PSoC 62 Errata Summary Noise is caused in supply and ground traces when multiple outputs switch. The amount of noise is dependent on the number of outputs, the drive strength of the output drivers, the frequency of the switching, and the impact on specific ports. The noise is worse at higher voltages (VDD = 2.7 V and higher) and should not be an issue with 1.8 V externally regulated (that is, VDD = 1.8 V 5%) designs. For cases where there are large numbers of GPIOs switching simultaneously, the following errata conditions are applicable. Note that the exact number cannot be specified as there are too many system-dependent conditions. This table defines the errata applicability to available PSoC 62 family devices. Items CY8C6XX Silicon Revision Fix Status All *C silicon Investigation underway. Fix planned by Q3'20 [2] CapSense use is restricted to Ports 6 and 7 with switching restrictions on other ports. All *C silicon Investigation underway. Fix planned by Q3'20 [3] Switching noise can cause ADC errors due to voltage reference noise. All *C silicon Investigation underway. Fix planned by Q3'20 All *C silicon Investigation underway. Fix planned by Q3'20 All *C silicon Investigation underway. Fix planned by Q3'20 [1] Drive mode strength must be limited. [4] Port Usage restrictions must be applied. [5] MHz ECO usage requires Ports 11, 12, and 13 be restricted to slow slew rate (2.5-MHz max frequency). 1. Drive mode strength must be limited. Problem Definition There are four Drive mode strengths: DM0, DM1, DM2, and DM3, DM0 being the strongest and DM3 the weakest in order. Usage of DM0 can cause noise in supply and ground lines for simultaneous outputs switching. Drive mode strength must be limited to DM2 for all GPIOs except for the 80 MHz QSPI clock which may use DM1. The VOL and VOH specs are affected as follows (also applies to VDDIO, VDDIOA, and VDDA pins): VDD < 2.7 V: VOL = 0.5 V @ IOL = 6 mA. VOH = VDD - 0.5 V, IOH = 6 mA. VDD 2.7 V: VOL = 0.4 @ IOL = 6 mA. VOH = VDD - 0.5 V, IOH = 6 mA. Parameters Affected Drive mode settings. Trigger Condition(s) Simultaneous outputs switching with high drive strength Scope of Impact Causes supply and ground noise, which can affect ADC and CapSense operation Workaround Follow drive mode strength restrictions. Drive Mode 2 (DM2) should be used for all ports except for the 80-MHz QSPI clock, which should be DM1 Fix Status Investigation underway. Fix planned by Q3'20. Document Number: 002-18449 Rev. *J Page 72 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet 2. CapSense use is restricted to Ports 6 and 7 with switching restrictions on other ports. Problem Definition GPIO simultaneous switching creates noise which can affect CapSense accuracy in unrestricted use Parameters Affected CapSense sensitivity and accuracy Trigger Condition(s) Noise caused by GPIO simultaneous output switching during CapSense operation Scope of Impact CapSense may produce erroneous results due to noise coupling from switching GPIOs. Workaround For CapSense usage, the following restrictions apply: a. Limit switching on Port 1 to 1 MHz (no more than 2 outputs) with slow slew rate. b. CapSense pins are restricted to Ports 6 and 7. No other GPIO output activity is allowed on Ports 6 and 7. c. Switching in Ports 5 and 8 is restricted to 1 MHz (no more than 2 outputs) with slow slew rate setting. CapSense must use the SRSS reference. Fix Status Investigation underway. Fix planned by Q3'20. 3. Switching noise can cause ADC errors due to voltage reference noise. Problem Definition 12-bit SAR ADC Counts are affected by switching noise Parameters Affected ADC accuracy Trigger Condition(s) Switching noise caused by GPIO simultaneous switching Scope of Impact ADC accuracy will be impacted Workaround Restrict switching on Ports 9 and 10 (analog input ports). The Programmable Analog Sub-System (PASS), including the SAR ADC, is connected to Ports 9 and 10. With no switching on Ports 9 and 10, the ADC error may be up to 4 LSB counts. Switching in Ports 9 and 10 is restricted to 1 MHz (no more than 2 outputs) with slow slew rate setting and, in this case, the ADC error may be up to 12 counts. Fix Status Investigation underway; Fix planned by Q3'20. 4. Port Usage restrictions must be applied. Problem Definition GPIO simultaneous switching causes supply and ground noise that adversely affects other on-chip subsystems). Parameters Affected CapSense and ADC results Trigger Condition(s) GPIO simultaneous switching with unrestricted strengths and frequency. Scope of Impact Incorrect results may cause false sensing or failure to sense for CapSense and inaccurate results for the SAR ADC (may not deliver 12-bit accuracy). Follow Port Usage restrictions: Workaround Fix Status a. Switching on Port 0 must be restricted to less than 8 MHz. b. Switching on Port 1 must be restricted to less than 1 MHz with slow rate and no more than 2 outputs. c. Ports 9 and 10 must be restricted to 8 MHz when not using the ADC and the restrictions stated earlier used when the ADC is used. d. Use VREF from System Resource Subsystem (SRSS) for CapSense Investigation underway. Fix planned by Q3'20. Document Number: 002-18449 Rev. *J Page 73 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet 5. MHz ECO usage requires Ports 11, 12, and 13 be restricted to slow slew rate (2.5-MHz max frequency). Problem Definition MHz ECO is sensitive to GPIO switching noise on adjacent I/O ports and requires edge rates be restricted when the MHz ECO is used. Parameters Affected Slew rate is restricted to slow switching and this affects switching frequency which is restricted to 2.5 MHz. Trigger Condition(s) Usage of fast slew rates on ECO Port and adjacent port (Ports 11 and 12). Scope of Impact Slew rates must be restricted to slow mode for reliable ECO operation. Note this includes the QSPI interface port (Port 11). Workaround None Fix Status Investigation underway. Resolution planned by Q3 20. Document Number: 002-18449 Rev. *J Page 74 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Revision History Description Title: PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Document Number: 002-18449 Submission Revision ECN Description of Change Date External posting: Publish to web *B 5896512 09/27/2017 Internal posting: Released to web for PSoC 62 *C 5956122 11/03/2017 Corrected typo in Development Support. Updated Table 5. Updated SID84 description and conditions. Updated Table 13. *D 5974156 11/29/2017 Updated max value for SID223. Updated min and max values of SID432R. Updated Table 39. Updated Units of Measure. Updated Active CPU power consumption in 32-bit Dual Core CPU Subsystem. Updated Table 5, Table 6, Table 16, Table 21, Table 32, and Table 35. Updated min value for SID4B and SID291. Updated Fixed UART AC specifications. *E 6065337 02/10/2018 Updated SID190 and removed SID194. Removed SID226. Updated max value for SID234. Updated Units of Measure. Removed Preliminary document status. Corrected units usage throughout the document. Added note explaining Fc for the SID.TCPWM.4 parameter. Updated Features, CPU, Flash, One-Time-Programmable (OTP) eFuse, ILO Clock Source, Watchdog Timer (WDT), Serial Communication Blocks (SCB), Ordering Information, and Packaging. *F 6221434 09/08/2018 Added Resource Protection. Removed Errata section. Updated package diagram (spec 001-97718 *A to *B) in Packaging. Updated Figure 2. Added a note in Table 2. Updated Table 5 through Table 8, Table 12, Table 15, Table 18, Table 28, Table 30, Table 36, and Table 38. Updated the title. *G 6663442 09/20/2019 Updated Ordering Information and Packaging. Added UDB in Acronyms. Updated Features. *H 6757930 12/20/2019 Updated Blocks and Functionality and Functional Description. Updated Pinouts and Power Supply Considerations. Updated Features. Updated Functional Description. *I 6842918 03/31/2020 Updated Pinouts. Updated PSoC 6 MPN Decoder. Updated Development Ecosystem, GPIO, and LCD sections. *J 6898008 06/22/2020 Added External Crystal Oscillators. Updated Errata. Document Number: 002-18449 Rev. *J Page 75 of 76 PSoC 6 MCU: CY8C62x6, CY8C62x7 Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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