M69KM048AA 32 Mbit (2 Mb x16), 83MHz Clock Rate, 1.8V Supply, Multiplexed I/O, Bare Die, Burst PSRAM Preliminary Data Feature summary Supply Voltage - VCC = 1.7 to 1.95V core supply voltage - VCCQ = 1.7 to 1.95V for I/O buffers Multiplexed Address/Data bus Asynchronous Operating Modes - Random Read: 70ns access time - Asynchronous Write Synchronous modes - Synchronous Read: Fixed length (4, 8, and 16 Words) or continuous burst Clock Frequency: 83MHz (max.) - Synchronous Write: continuous burst Low Power Consumption - Active Current: < 35mA - Standby Current: < 110A - Deep Power-Down Current: 10A (typical) Low Power Features - Partial Array Self-Refresh (PASR) - Deep Power-Down (DPD) Mode - Automatic Temperature-compensated SelfRefresh Operating Temperature - -30C to +85C Wafer The M69KM048AA is only available as part of a multi-chip package Product. May 2006 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/61 www.st.com 1 Contents M69KM048AA Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Address Inputs (A16-A20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Address Inputs or Data Input/Outputs (ADQ0-ADQ15) . . . . . . . . . . . . . . . 9 2.3 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 Upper Byte Enable (UB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 Lower Byte Enable (LB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 Configuration Register Enable (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.10 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.11 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.12 VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.13 VCCQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.14 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.15 VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 6 2/61 4.1 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Automatic Temperature Compensated Self Refresh . . . . . . . . . . . . . . . . 13 Standard Asynchronous operating modes . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Asynchronous Read and Write modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 Configuration Registers Asynchronous Read and Write . . . . . . . . . . . . . 14 Synchronous Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 M69KM048AA 7 Contents 6.1 NOR-Flash Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 Full Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 Synchronous Burst Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3.1 Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.2 Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.3 Row Boundary Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 Synchronous Burst Read Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5 Synchronous Burst Write Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.6 Synchronous Burst Read and Write Suspend . . . . . . . . . . . . . . . . . . . . . 19 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 Programming the Registers using the CR controlled method . . . . . . . . . 25 7.2 Reading and programming the registers using the software method . . . . 26 7.3 Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4 7.3.1 Operating Mode Bit (BCR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3.2 Latency Type (BCR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3.3 Latency Counter Bits (BCR13-BCR11) . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3.4 WAIT Polarity Bit (BCR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3.5 WAIT Configuration Bit (BCR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3.6 Driver Strength Bits (BCR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3.7 Burst Wrap Bit (BCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3.8 Burst Length Bits (BCR2-BCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.4.1 Deep Power-Down Bit (RCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.4.2 Partial Array Refresh Bits (RCR2-RCR0) . . . . . . . . . . . . . . . . . . . . . . . 34 8 Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3/61 List of tables M69KM048AA List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. 4/61 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Standard Asynchronous Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Asynchronous Write Operations (NOR-Flash Synchronous Mode) . . . . . . . . . . . . . . . . . . 20 Synchronous Read Operations (NOR-Flash Synchronous mode) . . . . . . . . . . . . . . . . . . . 21 Full Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Register Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Variable Latency Counter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Fixed Latency Counter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Refresh Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Address patterns for Partial Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Asynchronous Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Asynchronous Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Clock Related AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Synchronous Burst Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Power-Up and Deep Power-Down AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 M69KM048AA List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Variable Latency Mode, No Refresh Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Fixed Latency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Refresh Collision during Synchronous Burst Read in Variable Latency Mode . . . . . . . . . . 24 Set Configuration Register (software method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Read Configuration Register (software method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 WAIT Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 WAIT Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 AC Input Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Asynchronous Random Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Asynchronous Write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Asynchronous Write followed by Read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 CR Controlled Configuration Register Program, Asynchronous Mode . . . . . . . . . . . . . . . . 45 Clock input AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Single Synchronous Burst Read AC waveforms (Fixed Latency mode). . . . . . . . . . . . . . . 47 4-Word Synchronous Burst Read AC waveforms (Variable Latency mode). . . . . . . . . . . . 48 Synchronous Burst Read Suspend and Resume AC waveforms . . . . . . . . . . . . . . . . . . . . 49 Burst Read Showing End-of-Row Condition AC waveforms (No Wrap) . . . . . . . . . . . . . . . 50 Asynchronous Write followed by Burst Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . 51 Burst Read followed by Asynchronous Write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . 52 4-Word Synchronous Burst Write AC waveforms (Fixed Latency mode) . . . . . . . . . . . . . . 54 Burst Write Showing End-of-Row Condition AC waveforms (No Wrap) . . . . . . . . . . . . . . . 55 Synchronous Burst Write Followed by Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . 56 CR Controlled Configuration Register Program, Synchronous Mode. . . . . . . . . . . . . . . . . 57 Power-Up AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Deep Power-Down Entry and Exit AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5/61 Summary description 1 M69KM048AA Summary description The M69KM048AA is a 32 Mbit (33,554,432 bit) PSRAM, organized as 2,097,152 Words by 16 bits. It uses a high-speed CMOS DRAM technology implemented using a one transistorper-cell topology that achieves bigger array sizes. It provides a high-density solution for lowpower handheld applications. The device operates from a 1.7 to 1.95V supply voltage. It has a 16-bit data bus. To reduce the number of pins. the first sixteen address lines are multiplexed with the Data Input/Output signals on the multiplexed address/data bus ADQ0-ADQ15. The remaining address lines A16-A20 are the MSB addresses. The PSRAM interface supports various operating modes: Asynchronous Random Read and Write - when operating in one of these modes, the M69KM048AA is compatible with low power SRAMs. Synchronous modes that increase read and write speeds. Two types of Synchronous modes are available: - Flash-NOR: the device operates in Synchronous mode for read operations and Asynchronous mode for write operations. - Full Synchronous: the device supports Synchronous transfers for both read and write operations. The M69KM048AA features two user-programmable configuration registers, which are used to define the device operation: The Bus Configuration Register (BCR) The Refresh Configuration Register (RCR) The Bus Configuration Register (BCR) indicates how the device interacts with the system memory bus. The Refresh Configuration Register (RCR) is used to control how the memory array refresh is performed. At Power-Up, the registers are automatically loaded with default settings and can be updated any time during normal operation. PSRAMs are based on the DRAM technology, but have a transparent internal self-refresh mechanism that requires no additional support from the system memory microcontroller. To minimize the value of the Standby current during self-refresh operations, the M69KM048AA includes three system-accessible mechanisms configured via the Refresh Configuration Register (RCR): 6/61 Partial Array Self Refresh (PASR) performs a limited refresh of the part of the PSRAM array that contains essential data. Deep Power-Down (DPD) mode completely halts the refresh operation. It is used when no essential data is being held in the device. Automatic Temperature Compensated Self Refresh (TCSR) adjusts the refresh rate according to the operating temperature. M69KM048AA Figure 1. Summary description Logic Diagram VCC VCCQ 5 16 A16-A20 ADDQ0-DQ15 W WAIT E CR G M69KM048AA UB LB K L VSS Table 1. VSSQ AI12174 Signal Names A16-A20 Address Inputs ADQ0-ADQ15 Address Inputs or Data Input/Outputs E Chip Enable Input CR Configuration Register Enable Input G Output Enable Input W Write Enable Input UB Upper Byte Enable Input LB Lower Byte Enable Input K Clock Input L Latch Enable Input WAIT Wait Output VCC Core Supply Voltage VCCQ Input/Output Buffers Supply Voltage VSS Ground VSSQ Input/Output Buffers Ground 7/61 Summary description Figure 2. M69KM048AA Block Diagram Address Decoder A16-A20 ADQ0ADQ15 2,048K x 16 Memory Array Refresh Configuration Register (RCR) I/O MUX and Buffers Bus Configuration Register (BCR) E W G K L CR Control Logic WAIT LB UB AI12175b 1. This functional block diagram illustrates simplified device operation. 8/61 M69KM048AA 2 Signal descriptions Signal descriptions The signals are summarized in Figure 1: Logic Diagram, and Table 1: Signal Names. 2.1 Address Inputs (A16-A20) The Address Inputs A16-A20 are used in conjunction with ADQ0 to ADQ15, to select the cells in the memory array that are accessed during read and write operations. 2.2 Address Inputs or Data Input/Outputs (ADQ0-ADQ15) ADQ0-ADQ15 support multiplexed address/data sequencing. They are used to input addresses to the memory array, or to program data in the memory array. Addresses are internally latched during Read and Write operations. ADQO-ADQ15 are also used to define the value to be loaded into the BCR or the RCR, along with A16- A20 address Inputs. 2.3 Chip Enable (E) Chip Enable, E, activates the device when driven Low (asserted). When de-asserted (VIH), the device is disabled and goes automatically in low-power Standby mode or Deep PowerDown mode, according to the RCR settings. 2.4 Output Enable (G) When held Low, VIL, the Output Enable, G, enables the Bus Read operations of the memory. 2.5 Write Enable (W) Write Enable, W, controls the Bus Write operation of the memory. When asserted (VIL), the device is in write mode and write operations can be performed either to the configuration registers or to the memory array. 2.6 Upper Byte Enable (UB) The Upper Byte Enable, UB, gates the data on the Upper Byte of the Address Inputs/ Data Inputs/Outputs (ADQ8-ADQ15) to or from the upper part of the selected address during a write or read operation. 9/61 Signal descriptions 2.7 M69KM048AA Lower Byte Enable (LB) The Lower Byte Enable, LB, gates the data on the Lower Byte of the Address Inputs/Data Input/Outputs (ADQ0-ADQ7) to or from the lower part of the selected address during a write or read operation. If both LB and UB are disabled (High), the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as E remains Low. 2.8 Clock Input (K) The Clock, K, is an input signal to synchronize the memory to the microcontroller or system bus frequency during Synchronous Burst Read and Write operations. The Clock input signal increments the device internal address counter. The addresses are latched on the rising edge of the Clock K, when L is Low during Synchronous Bus operations. Latency counts are defined from the first Clock rising edge after L falling edge to the first data input latched or the first data output valid. The Clock input is required during all synchronous operations and must be kept Low during asynchronous operations. 2.9 Configuration Register Enable (CR) When this signal is driven High, VIH, bus read or write operations access either the value of the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR) according to the value of A19. 2.10 Latch Enable (L) In Synchronous mode, addresses are latched on the rising edge of the Clock K when the Latch Enable input, L is Low. In Asynchronous mode, addresses are latched on L rising edge. 2.11 Wait (WAIT) The WAIT output signal provides data-valid feedback during Synchronous Burst Read and Write operations. The signal is gated by E. Driving E High while WAIT is asserted may cause data corruption. Once a read or write operation has been initiated, the WAIT signal goes active to indicate that the M69KM048AA device requires additional time before data can be transferred. The WAIT signal also is used for arbitration when a Read or Write operation is launched while an on-chip refresh is in progress (see Figure 5: Refresh Collision during Synchronous Burst Read in Variable Latency Mode). Typically, the WAIT pin of the M69KM048AA can be connected to a shared WAIT signal used by the processor to coordinate transactions with multiple memories on the synchronous bus. See Section 3: Power-up for details on the WAIT signal operation. 10/61 M69KM048AA 2.12 Signal descriptions VCC Supply Voltage The VCC Supply Voltage is the core supply voltage. 2.13 VCCQ Supply Voltage VCCQ provides the power supply for the I/O pins. This allows all Outputs to be powered independently from the core power supply, VCC. 2.14 VSS Ground. The VSS Ground is the reference for all voltage measurements. 2.15 VSSQ Ground VSSQ ground is the reference for the input/output circuitry driven by VCCQ. VSSQ must be connected to VSS. 11/61 Power-up 3 M69KM048AA Power-up To guarantee correct operation, a specific Power-Up sequence must be followed to initialize the M69KM048AA. Power must be applied simultaneously to VCC and VCCQ. Once VCC and VCCQ have reached a stable level (see Figure 29: Deep Power-Down Entry and Exit AC waveforms and Figure 28: Power-Up AC waveforms), the device will require tVCHEL to complete its self-initialization process. During the initialization period, the E signal must remain High. Once initialization has completed, the device is ready for normal operation. Initialization will load the Bus Configuration Register (BCR) and the Refresh Configuration Register (RCR) with their default settings (see Table 7: Bus Configuration Register Definition, and Table 11: Refresh Configuration Register Definition). 4 Low-power modes 4.1 Standby When the device is in Standby, the current consumption is reduced to the level necessary to perform the memory array refresh operation. The device will enter Standby when a read or write operation is completed, depending on the operating mode (asynchronous, synchronous). For details on how to enter Standby, refer to Table 2: Standard Asynchronous Operating Modes, Table 3: Asynchronous Write Operations (NOR-Flash Synchronous Mode) and Table 4: Synchronous Read Operations (NOR-Flash Synchronous mode). 4.2 Deep Power-Down Deep Power-Down (DPD) is used by the system memory microcontroller to disable the PSRAM device when its storage capabilities are not needed. All refresh operations are then disabled. For the device to enter Deep Power-Down mode, bit 4 of the RCR must be set to `0' and Chip Enable, E, must go High, VIH. When the Deep Power-Down is enabled, the data stored in the device may be corrupted and the BCR, and the RCR contents are saved. The device exits from Deep Power-Down mode when the Chip Enable signal, E, has been Low again for a minimum time of tELEH(DP) (see Table 22: Power-Up and Deep Power-Down AC Characteristics and Figure 28: Power-Up AC waveforms). Bit 4 of the RCR will be automatically set to `1'. Once the Deep Power-Down is exited, the device will be available for normal operations after tVCHEL (time to perform an initialization sequence) During this delay, the current consumption will be higher than the specified Standby levels, but considerably lower than the active current. The content of the registers will be restored after Deep Power-Down. For details on how to enter Deep Power-Down, refer to Table 2: Standard Asynchronous Operating Modes, Table 3: Asynchronous Write Operations (NOR-Flash Synchronous Mode) and Table 4: Synchronous Read Operations (NOR-Flash Synchronous mode). 12/61 M69KM048AA 4.3 Low-power modes Partial Array Self Refresh The Partial Array Self Refresh (PASR) performs a limited refresh of part of the PSRAM array. This mechanism enables the device to reduce the Standby current by refreshing only the part of the memory array that contains essential data. Different refresh options can be defined by setting the RCR0 to RCR2 bits of the RCR: Full array One eighth of the array One half of the array One quarter of the array None of the array. These memory areas can be located either at the top or bottom of the memory array. The WAIT signal is used for arbitration when a read/write operation is launched while an onchip refresh is in progress. If locations are addressed while they are undergoing refresh, the WAIT signal will be asserted for additional clock cycles, until the refresh has completed (see Figure 5: Refresh Collision during Synchronous Burst Read in Variable Latency Mode). When the refresh operation is completed, the read or write operation will be allowed to continue normally. 4.4 Automatic Temperature Compensated Self Refresh The leakage current of DRAM capacitive storage elements increases with the temperature. At lower temperatures, the refresh rate can be decreased to minimize the Standby current. The M69KM048AA is based on DRAM architecture, consequently it requires increasingly frequent refresh operations to maintain data integrity as the temperature increases. The Automatic Temperature Compensated Self Refresh mechanism (TCSR) that the devices feature, automatically adjusts the refresh rate depending on the operating temperature. 13/61 Standard Asynchronous operating modes 5 M69KM048AA Standard Asynchronous operating modes The M69KM048AA supports Asynchronous Read and Write modes (Random Read, Asynchronous Write). The device is put in Asynchronous mode by setting bit 15 (BCR15) of the BCR to `1'. During asynchronous operations, the WAIT signal should be ignored and the Clock input signal K should be held Low, VIL. Refer to Table 2: Standard Asynchronous Operating Modes for a detailed description of asynchronous operating modes. 5.1 Asynchronous Read and Write modes At Power-Up, the device defaults to Asynchronous Random Read mode (bit BCR15 set to `1'). This mode uses the industry standard control bus (E, G, W, LB, UB). Read operations are initiated by bringing E, G and L Low, VIL, while keeping W High, VIH, and driving the address onto the multiplexed address/data bus. L is then taken High, VIH, to capture the address, and G is taken Low, VIL. Valid data will be gated through the output buffers after the specific access time tELQV has elapsed. Write operations occur when E, W and L are driven Low, VIL with the address on the multiplexed address/data bus. L is then taken High, VIH, to capture the address, and the write data is driven onto the bus. During Asynchronous Random Write operations, the G signal is `don't care' and W will override G. The data to be written is latched on the rising edge of E, W, LB or UB (whichever occurs first). The write operation is terminated by deasserting E, W, LB or UB. See Figure 13, and Table 17 for details on Asynchronous Read AC waveforms and characteristics and Figure 14, and Table 18 for details of Asynchronous Write AC waveforms and characteristics. 5.2 Configuration Registers Asynchronous Read and Write The BCR and RCR can be programmed using the CR controlled method in standard Asynchronous mode (see Figure 16 and Figure 27). The CR controlled method cannot be used to read the BCR and RCR contents. 14/61 M69KM048AA Table 2. Standard Asynchronous operating modes Standard Asynchronous Operating Modes Asynchronous Modes(1) Power E L W G UB LB CR A19 A16 A18 A20 ADQ0ADQ7 ADQ8ADQ15 Word Read VIL VIL VIL VIL Address In Valid Address In/ Data Out Valid Lower Byte Read VIL VIH VIL VIL Address In Valid Address In/ Data Out Valid High-Z VIL VIL VIH VIL Address In Valid High-Z Address In/ Data Out Valid VIL VIL VIL Address In Valid Address In/ Data In Valid VIH VIL VIL Address In Valid Address In/ Data In Data In Invalid Valid VIL VIH VIL Address InValid VIH Upper Byte Read \_/ Word Write Lower Byte Write Active (ICC) VIL VIL VIH Upper Byte Write Program Configuration Register (CR Controlled)(2) VIL Output Disable/No Operation Idle Deep Power-Down(4) Deep PowerDown (ICCPD) Standby VIH Standby VIH (IPASR) X VIL VIH X X X VIH 0(RCR) 1(BCR) (3) Data In Invalid Address In/ Data In Valid BCR/ RCR Data Address In Valid X X X VIL X X X X X X X X X High-Z X X X X X X High-Z 1. The Clock signal, K, must remain Low in asynchronous operating mode. 2. BCR and RCR only. 3. A19 is used to select between the BCR and the RCR. 4. The device enters Deep Power-Down mode by driving the Chip Enable signal, E, from Low to High, with bit 4 of the RCR set to `0'. The device remains in Deep Power-Down mode until E goes Low again and is held Low for tELEH(DP). 15/61 Synchronous Operating modes 6 M69KM048AA Synchronous Operating modes The synchronous modes allow high-speed read and write operations synchronized with the clock. The M69KM048AA supports two types of synchronous modes: NOR-Flash:- this mode greatly simplifies the interfacing with traditional burst-mode Flash memory microcontrollers. Full Synchronous: both read and write are performed in Synchronous mode. All the options related to the synchronous modes can be configured through the Bus Configuration Register, BCR. In particular, the device is put in Synchronous mode, either NOR-Flash or Full Synchronous, by setting bit BCR15 of the Bus Configuration Register to `0'. The device will automatically detect whether the NOR-Flash or the Full Synchronous mode is being used by monitoring the Clock, K, and the Latch Enable, L, signals. If a rising edge of the Clock K is detected while L is held Low, VIL (active), the device operates in Full Synchronous mode. 6.1 NOR-Flash Synchronous mode In this mode, the device operates in synchronous mode for read operations, and in asynchronous mode for write operations. Asynchronous write operations are performed at Word level, with LB and UB Low. The data is latched on E, W, LB, UB, whichever occurs first. RCR and BCR registers can be programmed in NOR-Flash Asynchronous Write mode, using the CR controlled method (see Section 7.1: Programming the Registers using the CR controlled method). A Program Configuration Register operation can only be issued if the device is in idle state and no burst operations are in progress. NOR-Flash Asynchronous Write operations are described in Table 3: Asynchronous Write Operations (NOR-Flash Synchronous Mode). Synchronous read operations are also performed at Word level. They are controlled by the state of E, L, G, W, LB and UB signals when a rising edge of the clock signal, K, occurs. The initial Burst Read access latches the Burst start address. The number of Words to be output is controlled by bits 0 to 2 of the BCR. The first data will be output after a number of clock cycles, also called Latency. NOR-Flash Synchronous Burst Read operations are described in Table 4: Synchronous Read Operations (NOR-Flash Synchronous mode). When a Burst Write operation is initiated or when switching from NOR-Flash mode to Full Synchronous mode, the delay from E Low to Clock High, tELKH, should not exceed 20ns. However, when it is not possible to meet these specifications, special care must be taken to keep addresses stable after driving the Write Enable signal, W, Low. Write operations are considered as Asynchronous operations until the device detects a valid clock edge and hence the address setup time of tAVWL must be satisfied (see Figure 5: Refresh Collision during Synchronous Burst Read in Variable Latency Mode). 16/61 M69KM048AA 6.2 Synchronous Operating modes Full Synchronous mode In Full Synchronous mode, the device performs read and write operations synchronously. Synchronous Read and Write operations are performed at Word level. The initial Burst Read and Write access latches the Burst start address. The number of Words to be output or input during Synchronous Read and Write operations is controlled by bits 0 to 2 of the BCR. During Burst Read and Write operations, the first data will be output after a number of clock cycles defined by the Latency value. The BCR and RCR can be programmed using the CR controlled method in Full Synchronous mode. The CR controlled method cannot be used to read BCR and RCR content. Full Synchronous operations are described in Table 5: Full Synchronous Mode. 6.3 Synchronous Burst Read and Write During Synchronous Burst Read or Write operations, addresses are latched on the rising edge of the Clock K when L is Low and data are latched on the rising edge of K. The Write Enable, W, signal indicates whether the operation is going to be a read (W=VIH) or a write (W=VIL). The WAIT output will be asserted as soon as a Synchronous Burst operation is initiated and will be de-asserted to indicate when data are to be transferred to (or from) the memory array. The Burst Length is the number of Words to be output or input during a Synchronous Burst Read or Write operation. It can be configured as 4, 8, or 16 Words or continuous through bit BCR0 to BCR2 or the Burst Configuration Register. The Latency defines the number of clock cycles between the beginning of a Burst Read operation and the first data output (counting from the first Clock edge where L was detected Low) or between the beginning of a Burst Write operation and the first data input. The Latency can be set through bits BCR13 to BCR11 of the Bus Configuration Register. The latency can also be configured to fixed or variable by programming bit BCR14. By default, the Latency Type is set to variable. Synchronous Read operations are performed in both fixed and variable latency mode while Synchronous Write operations are only performed with fixed latency. See Figure 18, Figure 19, Figure 21, Figure 25, Figure 26, for details on Synchronous Read and Write AC waveforms, respectively. 17/61 Synchronous Operating modes 6.3.1 M69KM048AA Variable Latency In Variable Latency mode, the latency programmed in the BCR is not guaranteed and is maintained only if there is no conflict with a refresh operation. The Latency set in the BCR is applicable only for an initial burst read access, when no refresh request is pending. For a given latency value, the Variable Latency mode allows higher operating frequencies than the Fixed Latency mode (see Table 9: Variable Latency Counter Configuration and Figure 3: Variable Latency Mode, No Refresh Collision). Burst Write operations are always performed at fixed latency, even if BCR14 is configured to Variable Latency (see Section 6.3.2: Fixed Latency). Monitoring of the WAIT signal is recommended for reliable operation in this mode. See Figure 19. and Figure 26 for details on Synchronous Burst Read and Write AC waveforms in Variable Latency mode. 6.3.2 Fixed Latency The latency programmed in the BCR is the real latency. The number of clock cycles is calculated by taking into account the time necessary for a refresh operation and the time necessary for an initial Burst access. This limits the operating frequency for a given latency value (see Table 10: Fixed Latency Counter Configuration and Figure 4: Fixed Latency Mode). It is recommended to use the Fixed Latency mode if the microcontroller cannot monitor the WAIT signal. See Figure 18 for details on Synchronous Burst Read AC waveforms in fixed Latency mode. 6.3.3 Row Boundary Crossing The M69KM048AA features 128-Word rows. Row boundary crossings between adjacent rows may occur during Burst Read and Write operations. Row boundary crossings are not handled automatically by the PSRAM. The microcontroller must stop the Burst operation at the row boundary and restart it at the beginning of the next row. Burst operations must be stopped by driving the Chip Enable signal, E, High, after the WAIT signal falling edge. E must transition: before the third Clock cycle after the WAIT signal goes Low if BCR[8] = 0, before the fourth Clock cycle after WAIT signal goes Low if BCR[8] = 1. Refer to Figure 21 and Figure 25 for details on how to manage row boundary crossings during burst operations. 18/61 M69KM048AA 6.4 Synchronous Operating modes Synchronous Burst Read Interrupt Ongoing Burst Read operations can be interrupted to start a new Burst cycle by either of the following means: Driving E High, VIH, and then Low, VIL on the next clock cycle (recommended). If necessary, refresh cycles will be added during the new Burst operation to schedule any outstanding refresh. If Variable Latency mode is set, additional wait cycles will be added if a refresh operation is scheduled during the Synchronous Burst Read Interrupt. WAIT monitoring is mandatory for proper system operation. Starting a new Synchronous Burst Read operation without toggling E. An ongoing Burst Read operation can be interrupted only after the first valid data is output. When a new Burst access starts, I/O signals immediately become high impedance. 6.5 Synchronous Burst Write Interrupt Ongoing Burst Write operations can be interrupted to start a new Burst cycle by either of the following means: Driving E High, VIH, and then Low, VIL on the next clock cycle (recommended), Starting a new Synchronous Burst Write without toggling E. Considering that Burst Writes are always performed in Fixed Latency mode, refresh is never scheduled. A maximum Chip Enable, E, low time (tELEH) must be respected for proper device operation. An ongoing Burst Write can be interrupted only after the first data is input. When a new Burst access starts, I/O signals immediately become high impedance. 6.6 Synchronous Burst Read and Write Suspend Synchronous Burst Read and Write operations can be suspended by halting the Clock K holding it Low, VIL. The status of the I/O signals will depend on the status of Output enable input, G. The device internal address counter is suspended and data outputs become high impedance tGHQZ after the rising edge of the Output Enable signal, G. It is prohibited to suspend the first data output at the beginning of a Synchronous Burst Read. See Figure 20 for details on the Synchronous Burst Read and Write Suspend mechanisms. During Synchronous Burst Read and Synchronous Burst Write Suspend operations, the WAIT output will be asserted. Bit BCR8 of the Bus Configuration Register is used to configure when the transition of the WAIT output signal between the asserted and the deasserted state occurs with respect to valid data available on the data bus. 19/61 Synchronous Operating modes Table 3. M69KM048AA Asynchronous Write Operations (NOR-Flash Synchronous Mode) Asynchronous Operations Power K Word Write(1) Program Configuration Register (CR Controlled)(3) E L W G UB, CR LB A19 A16- A18, A20 ADQ0ADQ15 VIL VIL VIL VIH VIL VIL Address In Valid Address In /Data In Valid VIL VIL VIL X X VIH 0(RCR) RCR/BCR 1(BCR) Data X Active (ICC) VIL (2) Output Disable/No Operation(1)(4) Idle VIL X X X X X VIL X Standby(5)(4) Standby (IPASR) VIH X X X X VIL X High-Z Deep Power-Down(6) Deep PowerDown (ICCPD) VIH X X X X X X High-Z 1. The device will consume active power in this mode whenever addresses are changed. 2. K must be held Low during Asynchronous Read And Write operations. It must also be kept Low for the device to consume Standby current during Standby and Deep Power-Down modes, and during Burst Suspend operations. 3. BCR and RCR only. 4. VIN = 0V or VCCQ; all signals must be stable in order to achieve standby current. 5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 6. The device enters Deep Power-Down mode by driving the Chip Enable signal, E, from Low to High, with bit 4 of the RCR set to `0'. The device remains in Deep Power-Down mode until E goes Low again and is held Low for tELEH(DP). 20/61 M69KM048AA Table 4. Synchronous Operating modes ) Synchronous Read Operations (NOR-Flash Synchronous mode) Synchronous Operations Power K (1) Initial Burst Read(3)(4) Subsequent Burst Read(3)(4)(5) E L W G LB, UB WAIT (2) CR A19 A16-A18, A20 VIL VIL VIH VIH VIL VIL Address In Valid X VIL VIH VIL VIL X Address In/Data Out Valid Active (ICC) X X Low-Z Burst Read Suspend(3)(4) Active (ICC) Output Disable/No Operation(4)(6) Idle Standby(6)(7) Standby (IPASR) Deep Power-Down(8) Deep PowerDown (ICCPD) X ADQ15ADQ0 VIL X X VIH X X X High-Z VIL X X X X VIL X X VIL VIH X X X X VIL X High-Z X X High-Z High-Z VIL VIH X X X X 1. K must be held Low for the device to consume Standby current during Standby and Deep Power-Down modes, and during Burst Suspend operations. 2. The WAIT polarity is configured through bit 10 (BCR10) of the Bus Configuration Register. 3. The Burst mode is configured through bit 15 (BCR15) of the Bus Configuration Register. 4. The device will consume active power in this mode whenever addresses are changed. 5. Burst Read Interrupt and Suspend are described in dedicated paragraph of the Section 6: Synchronous Operating modes. 6. VIN = 0V or VCCQ; all signals must be stable in order to achieve standby current. 7. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 8. The device enters Deep Power-Down mode by driving the Chip Enable signal, E, from Low to High, with bit 4 of the RCR set to `0'. The device remains in Deep Power-Down mode until E goes Low again and is held Low for tELEH(DP). 21/61 Synchronous Operating modes Table 5. M69KM048AA Full Synchronous Mode Synchronous Mode E L W G LB, UB Initial Burst Read(3)(6) VIL VIL VIH VIH Subsequent Burst Read(3)(4)(6) VIL VIH X Initial Burst Write(3)(6) VIL VIL VIL VIH Subsequent Burst Write(3)(6) Power K (1) Active (ICC) WAIT A16-A18, A20 A19 VIL VIL Address In Valid X X VIL X X Address In/Data Out Valid VIL VIH X VIL Address In Valid Address In/Data In Valid X VIH VIL X X Address In/Data In Valid Low-Z Burst Read Suspend(3)(6) X ADQ15ADQ0 CR (2) VIL X X VIH X X X High-Z VIL VIL VIL VIH X VIH 0(RCR) RCR/BCR Data 1(BCR) X VIL VIL X X X X VIL X X Standby(7)(8) Standby VIL VIH (IPASR) X X X X VIL X High-Z Deep PowerDown(9) Deep PowerDown (ICCPD) X X High-Z Program Configuration Register (CR Controlled)(3)(5) Output Disable/No Operation(6)(8) Idle High-Z VIL VIH X X X X 1. K must be held Low for the device to consume Standby current during Standby and Deep Power-Down modes, and during Burst Suspend operations. 2. The WAIT polarity is configured through bit 10 (BCR10) of the Bus Configuration Register. 3. The Burst mode is configured through bit 15 (BCR15) of the Bus Configuration Register. 4. Burst Read Interrupt, Suspend, Terminate and Burst Write Interrupt, Suspend and Terminate are described in dedicated paragraph of the Section 6: Synchronous Operating modes. 5. The Configuration Register is output during the initial burst operation (read or write). The following read or write operations are similar to subsequent burst operations. E must be held Low for the equivalent of a single-word burst operation (as indicated by the WAIT signal). 6. The device will consume active power in this mode whenever addresses are changed. 7. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 8. VIN = 0V or VCCQ; all signals must be stable in order to achieve standby current. 9. The device enters Deep Power-Down mode by driving the Chip Enable signal, E, from Low to High, with bit 4 of the RCR set to `0'. The device remains in Deep Power-Down mode until E goes Low again and is held Low for tELEH(DP). 22/61 M69KM048AA Figure 3. Synchronous Operating modes Variable Latency Mode, No Refresh Collision K 0 1 2 3 4 5 6 7 Address Valid A16-A20 L Latency = 3 Clock Cycles ADQ0-ADQ15 Hi Z Address Valid Q1 Q2 Q3 Q4 Q5 Q1 Q2 Q3 Q4 Latency = 4 Clock Cycles ADQ0-ADQ15 Hi Z Address Valid AI12176 Figure 4. Fixed Latency Mode N-1 Cycle N Cycle K tAVQV Address Valid A16-A20 tLLQV L tELQV E tKHQV2 ADQ0-ADQ15 OUT Hi Z Address Valid Q1 Q2 Q3 Q4 Q5 AI12177 1. See Table 20: Synchronous Burst Read AC Characteristics for details on the synchronous read AC Characteristics shown in the above waveforms. 23/61 Synchronous Operating modes Figure 5. M69KM048AA Refresh Collision during Synchronous Burst Read in Variable Latency Mode K A16-A20 Address Valid L E G W LB/UB WAIT ADQ0-ADQ15 Hi Z Address Valid Additional WAIT states inserted to allow Refresh completion Hi Z Q0 Q1 Q2 Q3 AI12178b= 1. Additional Wait states are inserted to allow Refresh completion. The latency is set to 3 clock cycles (BCR13-BCR11 = 010). The WAIT must be active Low, VIL, (BCR10 = 0) and asserted during delay (BCR8= 0). 24/61 M69KM048AA 7 Configuration Registers Configuration Registers The M69KM048AA features two registers: The Bus Configuration Register (BCR) The Refresh Configuration Register (RCR) BCR and RCR are user-programmable registers that define the device operating mode. They are automatically loaded with default settings during Power-Up, and selected by address bit A19 (see Table 6: Register Selection). The configuration registers can be programmed using two methods: The CR controlled method (or hardware method) The software method. They can only be read by using the software method. 7.1 Programming the Registers using the CR controlled method BCR and RCR registers can be programmed by issuing a bus write operation, in asynchronous or synchronous mode (NOR-Flash or Full Synchronous), with Configuration Register Enable signal, CR, High, VIH. Address bit A19 allows to select between BCR and RCR (see Table 6: Register Selection). In synchronous mode, the values placed on address lines ADQ0 to ADQ15 are latched on the rising edge of L, E, or W, whichever occurs first. In asynchronous mode, a register is programmed by toggling L signal. LB and UB are `don't care'. The CR pin has to be driven high prior to any access. Refer to Table 3 and Table 5 for a detailed description of Configuration Register Program by the CR Controlled method and to Figure 16 and Figure 27, showing CR controlled Configuration Register Program waveforms in asynchronous and synchronous mode. Table 6. Register Selection Register Read or Write Operation A19 RCR Read/Write 0 BCR Read/Write 1 25/61 Configuration Registers 7.2 M69KM048AA Reading and programming the registers using the software method The BCR and the RCR can be read and programmed by issuing a Read Configuration Register and Set Configuration Register sequence, respectively (see Figure 7: Read Configuration Register (software method) and Figure 6: Set Configuration Register (software method)). The timings will be identical to those described in Table 17: Asynchronous Read AC Characteristics and Table 3: Asynchronous Write Operations (NOR-Flash Synchronous Mode). The Configuration Register Enable input, CR, is `don't care'. Read Configuration Register and Set Configuration Register sequences both require 4 read and write cycles. These cycles are performed in asynchronous mode, whatever the device operating mode: 2 bus read and one bus write cycles to a unique address location, 1FFFFFh, indicate that the next operation will read or write to a configuration register. The data written during the third cycle must be `0000h' to access the RCR, `0001h' to access the BCR, during the next cycle. The fourth cycle reads from or writes to the configuration register. The timings for programming and reading the registers by the software method are identical to the asynchronous write and read timings. The software method should not be used to disable or enable the Deep Power-Down mode (bit 4 of the Refresh Configuration Register). 26/61 M69KM048AA Figure 6. Configuration Registers Set Configuration Register (software method) A16-A20 1FFFFFh 1FFFFFh 1FFFFFh 1FFFFFh E tEHEL2 tEHEL2 tEHEL2 G W LB, UB L ADQ0-ADQ15 1FFFFFh Read cycle 1FFFFFh Read cycle 1FFFFFh (2) Write cycle 1FFFFFh CR Data In Write cycle AI12179 1. Only the Bus Configuration Register (BCR) and the Refresh Configuration Register (RCR) can be modified. 2. To program the BCR or the RCR on last bus write cycle, ADQ0-ADQ15 must be set to `0001h' and `0000h' respectively. 3. The control signals E, G, W, LB and UB, must be toggled as shown in the above figure. Figure 7. Read Configuration Register (software method) A16-A20 1FFFFFh 1FFFFFh 1FFFFFh 1FFFFFh E tEHEL2 tEHEL2 tEHEL2 G W LB, UB L ADQ0-ADQ15 1FFFFFh Read cycle 1FFFFFh Read cycle 1FFFFFh (2) Write cycle CR 1FFFFFh Data Out Read cycle AI12180 1. The highest order address location is not modified during this operation. 2. To read the BCR or the RCR on last bus read cycle, ADQ0-ADQ15 must be set to `0001h' and `0000h', respectively. 3. The control signals E, G, W, LB and UB, must be toggled as shown in the above figure. 27/61 Configuration Registers 7.3 M69KM048AA Bus Configuration Register The Bus Configuration Register (BCR) defines how the PSRAM interacts with the system memory bus. All the device operating modes are configured through the BCR. Refer to Table 7 for the description of the Bus Configuration Register Bits. 7.3.1 Operating Mode Bit (BCR15) The Operating Mode bit allows the Synchronous mode or the Asynchronous mode (default setting) to be selected. Selecting the Synchronous mode will allow the device to operate either in NOR Flash mode or in full Synchronous Burst mode. The device will automatically detect that the NOR Flash mode is being used by monitoring a rising edge of the Clock signal, K, when L is Low. If this should not be the case, the device operates in full Synchronous mode. 7.3.2 Latency Type (BCR14) The Latency Type bit is used to configure the latency type. When the Latency Type bit is set to `0', the device operates in variable latency mode (only available for Synchronous Read mode). When it is `1', the fixed latency mode is selected and the latency is defined by the values of bits BCR13 to BCR11. Refer to Figure 3 and Figure 4 for examples of fixed and variable latency configuration. 7.3.3 Latency Counter Bits (BCR13-BCR11) The Latency Counter bits are used to set the number of clock cycles between the beginning of a synchronous read or write operation and the first data output or input. The Latency Counter bits can only assume the values shown in Table 7: Bus Configuration Register Definition (see also Figure 3 and Figure 4). 7.3.4 WAIT Polarity Bit (BCR10) The WAIT Polarity bit indicates whether the WAIT output signal is active High or Low. As a consequence, it also determines whether the WAIT signal requires a pull-up or pull-down resistor to maintain the de-asserted state (see Figure 9: WAIT Polarity). By default, the WAIT output signal is active High. 28/61 M69KM048AA 7.3.5 Configuration Registers WAIT Configuration Bit (BCR8) The system memory microcontroller uses the WAIT signal to control data transfer during Synchronous Burst Read and Write operations. The WAIT Configuration bit is used to determine when the transition of the WAIT output signal between the asserted and the de-asserted state occurs with respect to valid data available on the data bus. When the Wait Configuration bit is set to `0', data is valid or invalid on the first Clock rising edge immediately after the WAIT signal transition to the de-asserted or asserted state. When the Wait Configuration bit is set to `1' (default settings), the WAIT signal transition occurs one clock cycle prior to the data bus going valid or invalid. See Figure 8: WAIT Configuration Example for an example of WAIT configuration. 7.3.6 Driver Strength Bits (BCR5) The Driver Strength bits allow to set the output drive strength to adjust to different data bus loading. Full driver strength and reduced driver strength (a quarter of drive) are available. By default, outputs are configured to `full driver" strength. 7.3.7 Burst Wrap Bit (BCR3) Burst Read operations can be confined inside the 4, 8, or 16 boundary (wrap mode). If the wrap mode is not enabled, the device outputs data sequentially up to the end of the row, regardless of burst boundaries. The Burst Wrap bit is used to select between `wrap' and `no wrap' mode. 7.3.8 Burst Length Bits (BCR2-BCR0) The Burst Length bits set the number of Words to be output or input during a Synchronous Burst Read or Write operation. They can be set for 4 Words, 8 Words, 16 Words or Continuous Burst (default settings), where all the Words are output or input sequentially regardless of address boundaries (see also Table 8: Burst Type Definition). 29/61 Configuration Registers Table 7. Address Bits ADQ15 ADQ14 M69KM048AA Bus Configuration Register Definition(1) Bus Configuration Register Bits Name BCR15 Operating Mode Bit BCR14 Value Description 0 Synchronous Mode (NOR Flash or Full Synchronous Mode) 1 Asynchronous Mode (Default) 0 Variable Latency (Default) 1 Fixed Latency Latency Type ADQ13ADQ11 BCR13BCR11 010 3 Clock Cycles Latency Counter 011 4 Clock Cycles (Default) Bits Other Configurations Reserved(2) ADQ10 BCR10 WAIT Polarity Bit ADQ9 ADQ8 - BCR8 - - - ADQ5 BCR5 Driver Strength Bits ADQ4 - - ADQ3 BCR3 Burst Wrap Bit BCR2-BCR0 WAIT Active Low 1 WAIT Active High (default).See Figure 9: WAIT Polarity. Must be set to `0' Reserved(2) 0 WAIT Asserted During Delay (see Figure 8: WAIT Configuration Example). 1 WAIT Asserted One Clock Cycle Before Delay (Default) Wait Configuration Bit ADQ7ADQ6 ADQ2ADQ0 0 Burst Length Bit Must be set to `0' Reserved(2) 0 Full Drive (default) 1 1/4 Drive Must be set to `0' Reserved(2) 0 Wrap (within the Burst Length) 1 No Wrap (default) 001 4 Words 010 8 Words 011 16 Words 111 Continuous Burst (default) Other Configurations Reserved(2) 1. Address bits A16 to A18 and A20 are reserved and must be set to `0'. 2. Programming the BCR with reserved value will force the device to use the default register settings. 30/61 M69KM048AA Wrap (BCR3='0') Mode Table 8. Burst Type Definition Start Add 4 Words (Sequential) BCR2-BCR0 = 001b 8 Words (Sequential) BCR2-BCR0=010b 16 Words (Sequential) BCR2-BCR0=011b Continuous Burst BCR2-BCR0=111b 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-...-14-15 0-1-2-3-..-511-. 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-...-14-15-0 1-2-3-4-...-510-511- 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-...-15-0-1 2-3-4-5-6-...-511- 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-...-15-0-1-2 3-4-5-...-511- 4 4-5-6-7-0-1-2-3 4-5-...-15-0-1-2-3 4-5-...-511- 5 5-6-7-0-1-2-3-4 5-6-7-...-15-0-1-...-4 5-6-7-...-511- 6 6-7-0-1-2-3-4-5 6-7-8-...-15-0-1-...-5 6-7-8-...-511- 7 7-0-1-2-3-4-5-6 7-8-9-...15-0-1-...-6 7-8-9-...-511- ... ... ... 14 14-15-0-1-2-...-13 14-...511- 15 15-0-1-2-...-14 15-...511- ... ... ... ... No Wrap (BCR3='1') Configuration Registers ... ... ... 30 30-...-511- 31 31-...-511- 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-...-14-15 0-1-2-3-..-511-. 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-..-15-16 1-2-3-4-...-512- 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-...-17 2-3-4-5-...-513- 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-...-18 3-4-5-...-514- 4 4-5-6-7-8-9-10-11 4-5-6-...-19 4-5-6-...-515- 5 5-6-7-8-9-10-11-12 5-6-7-...-20 5-6-7-...-516- 6 6-7-8-9-10-11-12-13 6-7-8-...-21 6-7-8-...-517- 7 7-8-9-10-11-12-13-14 7-8-9-...-22 7-8-9-...-518- ... ... ... 14 14-15-...-29 14-...-525- 15 15-16-17-...-30 15-...-526- ... ... ... 30 30-...-541- 31 31-...-542- 31/61 Configuration Registers Table 9. M69KM048AA Variable Latency Counter Configuration Maximum Clock Rate in Burst Mode Latency Latency Configuration Code BCR13- BCR11 Normal Refresh Collision 83MHz 010 2 (3 clocks cycles) 2 4 53 (18.75ns) 011 3 (4 clocks cycles) - default 3 6 83 (12ns) Others Reserved - - - Table 10. Fixed Latency Counter Configuration BCR13- BCR11 Latency Configuration Code Latency Max Input Clock Frequency 83MHz 010 2 (3 clocks cycles) 2 33 (30ns) 011 3 (4 clocks cycles)-default 3 52 (19.2ns) Others Reserved - - Figure 8. WAIT Configuration Example K WAIT DQ0-DQ15 BCR8='0', BCR10='1' Data Valid During Current Cycle Hi-Z DQ0-DQ15 BCR8='1', BCR10='1' Data Valid During Next Cycle Hi-Z Data[0] Data[1] Data[0] AI06795b 32/61 M69KM048AA Configuration Registers Figure 9. WAIT Polarity BCR8='0' BCR10='0' BCR8='0' BCR10='1' K WAIT DQ0-DQ15 Hi-Z Data[0] Data[1] WAIT DQ0-DQ15 Hi-Z Data[0] Data[1] AI09963 33/61 Configuration Registers 7.4 M69KM048AA Refresh Configuration Register The role of the Refresh Configuration Register (RCR) is: to define how the self refresh of the PSRAM array is performed to select the Deep Power-Down mode Refer to Table 11 for the description of the Refresh Configuration Register Bits. 7.4.1 Deep Power-Down Bit (RCR4) The Deep Power-Down bit enables or disables all refresh-related operations. Deep PowerDown mode is enabled when the RCR4 bit is set to `0', and remains enabled until this bit is set to `1'. When E goes high, the device enters Deep-Power Down mode and remains in this mode until the E mean time goes low and stays low for at least 10s. At power-up, the Deep Power-Down mode is disabled. See the Section 4.2: Deep Power-Down for more details. 7.4.2 Partial Array Refresh Bits (RCR2-RCR0) The Partial Array Refresh bits allow refresh operations to be restricted to a portion of the total PSRAM array. The refresh options can be full array, one half, one quarter, one eighth or none of the array. These memory areas can be located either at the top or bottom of the memory array. By default, the full memory array is refreshed. Table 11. Refresh Configuration Register Definition(1) Address Bits Refresh Configuration Register Bits Name ADQ15ADQ5 - - ADQ4 RCR4(2) Deep PowerDown Bit ADQ3 ADQ2ADQ0 - RCR2-RCR0 - Partial Array Refresh Bits Value Must be set to `0' Reserved 0 Deep Power-Down Enabled 1 Deep Power-Down Disabled (Default) Must be set to `0' Reserved 000 Full Array Refresh (Default) 001 Refresh of the bottom half of the array 010 Refresh of the bottom quarter of the array 011 Refresh of the bottom eighth of the array 100 None of the array 101 Refresh of the top half of the array 110 Refresh of the top quarter of the array 111 Refresh of the top eighth of the array 1. Address bits A16 to A18 and A20 are reserved and must be set to `0'. 2. The software method should not be used to program this bit. 34/61 Description M69KM048AA Configuration Registers Address patterns for Partial Array Refresh(1) Table 12. RCR2 RCR1 RCR0 Refreshed Area Address Space Size of Refreshed Density Area 0 0 0 Full array (Default) 000000h-1FFFFFh 2Mbx16 32Mb 0 0 1 Bottom half of the array 000000h-0FFFFFh 1Mbx16 16Mb 0 1 0 Bottom quarter of the array 000000h-07FFFFh 512Kbx16 8Mb 0 1 1 Bottom eight of the array 000000h-03FFFFh 256Kbx16 4Mb 1 0 0 None of the array 0 0Mb 0Mb 1 0 1 Top half of the array 100000h-1FFFFFh 1Mbx16 16Mb 1 1 0 Top quarter of the array 180000h-1FFFFFh 526Kbx16 8Mb 1 1 1 Top eight of the array 1C0000h-1FFFFFh 256Kbx16 4Mb 1. RCR4 is set to `1'. 35/61 Maximum Rating 8 M69KM048AA Maximum Rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 13. Absolute Maximum Ratings Symbol Parameter Min Max Unit Ambient Operating Temperature -30 +85 C TSTG Storage Temperature -55 150 C VCC Core Supply Voltage -0.2 2.45 V Input/Output Buffer Supply Voltage -0.2 2.45 V Input or Output Voltage -0.5 VCCQ+ 0.3 V TA VCCQ VIO 36/61 M69KM048AA 9 DC and AC parameters DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 14: Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 14. Operating and AC Measurement Conditions M69KM048AA Parameter(1) Unit Min Max VCC Supply Voltage 1.7 1.95 V VCCQ Input/Output Buffer Supply Voltage 1.7 1.95 V Load Capacitance (CL) 30 pF Output Circuit Protection Resistance (R) 50 Input Pulse Voltages(2)(3) 0 Input and Output Timing Ref. VCC Voltages(2)(3) Input Rise Time tr and Fall Time tf VCC/2 (2)(3) V V 1 V/ns 1. All voltages are referenced to VSS. 2. Referenced to VSS. 3. VCC=VCCQ Figure 10. AC Measurement I/O Waveform I/O Timing Reference Voltage VCCQ VCCQ/2 VSSQ AI09484c 1. Logic states `1' and `0' correspond to AC test inputs driven at VCCQ and VSS respectively. Input timings begin at VCCQ/2 and output timings end at VCCQ/2. Figure 11. AC Input Transitions VCCTyp VSS 90% 90% 10% tr 10% tf ai10122 37/61 DC and AC parameters M69KM048AA Figure 12. AC Measurement Load Circuit VCCQ/2 R DEVICE UNDER TEST OUT CL AI11289 Table 15. Symbol 38/61 Capacitance Parameter CIN Input Capacitance CIO Data Input/Output Capacitance Test Condition Min Max Unit TA = 25C, f = 1MHz, VIN = 0V 2 6.5 pF 3 6.5 pF M69KM048AA Table 16. DC Characteristics Symbol Parameter VOH(1) (1) VOL Refreshed Array Test Conditions Min. Output High Voltage IOH = -0.2mA 0.8VCCQ Output Low Voltage IOL = 0.2mA VIH(2) Input High Voltage (3) Input Low Voltage VIL DC and AC parameters ILI Input Leakage Current ILO Output Leakage Current Typ Max. Unit V 0.2VCCQ V 1.4 VCCQ + 0.2 V -0.2 0.4 V VIN = 0 to VCCQ 1 A G = VIH or E = VIH 1 A ICC1(4) Asynchronous Read/Write Random at tRC min VIN = 0V or VCCQ, IOUT = 0mA, E = VIL 25 mA ICC2(4) Burst, Initial Read/Write Access VIN = 0V or VCCQ IOUT = 0mA, E = VIL 40 mA ICC3R(4) Continuous Burst Read VIN = 0V or VCCQ IOUT = 0mA, E = VIL 35 mA ICC3W(4) Continuous Burst Write VIN = 0V or VCCQ IOUT = 0mA, E = VIL 35 mA 110 A 105 A 95 A 95 A 70 A 110 A 70 A Full Array 1/2 Array Partial Array Refresh 1/4 Array IPASR(4) Standby Current 1/8 Array VIN = 0V or VCCQ E = VCCQ None ISB(5) Standby Current ICCPD Deep-Power Down Current VIN = 0V or VCCQ E = VCCQ VIN = 0V or VCCQ, VCC, VCCQ = 1.95V; TA= +85C 10 1. BCR5-BCR4 = 01 (default settings). 2. Input signals may overshoot to VCCQ+ 1.0V for periods of less than 2ns during transitions. 3. Output signals may undershoot to VSS - 1.0V for periods of less than 2ns during transitions. 4. This parameter is specified with all outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected for the actual system. 5. ISB maximum value is measured at +85C with PAR set to Full Array. In order to achieve low standby current, all inputs must be driven either to VCCQ or VSSQ. ISB might be slightly higher for up to 500ms after Power-up, or when entering Standby mode. 39/61 DC and AC parameters Table 17. M69KM048AA Asynchronous Read AC Characteristics(1) Symbol Alt. Parameter Min Max Unit tAVQV tAA Address Valid to Output Valid 70 ns tAVAX tRC Read Cycle Time 70 ns tAVLH tRHLH tAVS Address Valid to L High Configuration Register High to L High 10 ns tBLQV tBA Upper/Lower Byte Enable Low to Output Valid 70 ns (2) tBHZ Upper/Lower Byte Enable High to Output Hi-Z 8 ns tBLQX(3) tBLZ Upper/Lower Byte Enable Low to Output transition 10 tELTV tCEW Chip Enable Low to WAIT Valid 1 tELQV tCO Chip Enable Low to Output Valid tELLH tCVS Chip Enable Low to L High tEHQZ(2) tHZ Output Enable High to Output Hi-Z Chip Enable High to Output Hi-Z tELQX(3) tLZ Chip Enable Low to Output transition tGLQV tOE Output Enable Low to Output Valid 20 ns tGHQZ(2) tOHZ Output Enable Low to Output Hi-Z 8 ns tGLQX(3) tOLZ Output Enable Low to Output transition tLLQV tAADV Latch Enable Low to Output Valid tLHAX tLHRL tAVH Latch Enable High to Address transition Latch Enable High to Configuration Register Low 2 ns tLLQZ tAHZ Latch Enable Low to Output Hi-Z 7 ns tLHQX tALZ Latch Enable High to Output transition 15 ns tLLLH tVP Latch Enable Low Pulse Width 5 ns tBHQZ ns 7.5 ns 70 ns 10 ns 8 10 ns ns 3 ns 70 ns 1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement Conditions and Figure 12: AC Measurement Load Circuit. 2. The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2. 3. The transition timings measure a 100mV transition from the Hi-Z (VCCQ/2) level to either VOH or VOL. 40/61 M69KM048AA DC and AC parameters Figure 13. Asynchronous Random Read AC waveforms tAVAX A16-A20 VALID ADDRESS tLHQX tLLQZ tAVLH tLHAX L tLLLH tELLH tEHTZ tEHQZ tAVQV E tELQV tLLQV tBHQZ LB/UB tBLQV tGHQZ G tGLQV W tGLQX tBLQX VALID ADDRESS ADQ0-ADQ15 VALID OUTPUT Hi-Z tELQX tELTV WAIT Hi-Z AI12181b 41/61 DC and AC parameters Table 18. M69KM048AA Asynchronous Write AC Characteristics(1) Symbol Alt. Parameter Min Max Unit tAVBL, tAVEL tAVWL, tLLWL tAS Address Set-up to Beginning of Write Operation 0 ns tAVLH, tRHLH tAVS Address Valid to Latch Enable High Configuration Register High to Latch Enable High 10 ns tAVWH, tAVEH tAVBH tAW Address Set-up to End of Write Operation 70 ns tAVAX tWC Write Cycle Time 70 ns tBLBH, tBLEH tBLWH tBW Upper/Lower Byte Enable Low to End of Write Operation 70 ns tELTV tCEW Chip Enable Low to WAIT Valid 1 tEHEL tCBPH Chip Enable High between Subsequent Asynchronous Operations 6 ns tELLH tCVS Chip Enable Low to L High 10 ns tELWH, tELEH tELBH tCW Chip Enable Low to End of Write Operation 70 ns tEHDX tWHDX tBHDX tDH Input Hold from Write 0 ns tELWH, tDVBH tDVEH, tDVWH tDW Input Valid to Write Setup Time 20 ns tEHTZ, tBHTZ, tWHTZ(2) tHZ Chip Enable High to WAIT Hi-Z LB/UB High to WAIT Hi-Z Write Enable High to WAIT Hi-Z tLLWH, tLLEH, tLLBH tVS Latch Enable Low to Write Enable High 70 ns tLHAX, tLHRL tAVH Latch Enable High to Address Transition or Latch Enable High to Configuration Register Low 2 ns tLLLH tVP Latch Enable Low Pulse Width 5 ns tWLBH, tWLEH tWLWH(3) tWP Write Pulse Width 45 ns 10 ns tWHWL tWPH Write Enable Pulse Width High 7.5 8 ns ns 1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement Conditions and Figure 12: AC Measurement Load Circuit. 2. The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2. 3. W Low time must be limited to tEHEL. 42/61 M69KM048AA DC and AC parameters Figure 14. Asynchronous Write AC waveforms tAVAX A16-A20 VALID ADDRESS tAVLH tLHAX tLLLH tAVEH, tAVBH, tAVWH L tLLWH, tLLEH, tLLBH tELWH, tELEH, tELBH E tBLWH, tBLEH, tBLWH LB/UB tLLWL tWLWH, tWLBH, tWLEH(2) tAVWL W tEHDX tDVEH ADQ0-ADQ15 Hi-Z VALID ADDRESS tEHTZ, tBHTZ, tWHTZ tELTV WAIT VALID INPUT Hi-Z Hi-Z AI12182b 1. Data Inputs are Hi-Z if E is High, VIH. 2. When E is Low, VIL (device selected), W must not remain Low, for longer than tEHEL. 3. The end of the Write operation is controlled by E, LB, UB, or W, whichever is de-asserted first. 43/61 DC and AC parameters M69KM048AA Figure 15. Asynchronous Write followed by Read AC waveforms tAVAX A16-A20 VALID ADDRESS VALID ADDRESS tAVLH tAVLH tLHAX tLHAX tLHQX tLLLH tAVWH tLLQZ tAVQV L tELQX tLLWH tEHEL(1) tELWH tEHQZ E tELLH tBLQX tBHQZ tGLQX tBHQZ LB/UB tBLWH G tAVWL tWLWH tGLQV W tWHDX tDVWH ADQ0ADQ15 WAIT Hi-Z VALID ADDRESS VALID INPUT VALID ADDRESS VALID OUTPUT Hi-Z AI12183b 1. When configured to operate in Synchronous mode (BCR[15] = 0), E must remain High, VIH, for at least tEHEL to schedule the appropriate refresh interval. Otherwise, tELEH is only required after E controlled write operations. 44/61 M69KM048AA DC and AC parameters Figure 16. CR Controlled Configuration Register Program, Asynchronous Mode A16 - A18, A20 OPCODE(2) tAVLH A19 ADDRESS Data Valid ADDRESS Data Valid tLHAX 0(RCR), 1(BCR) L tELWH E tEHEL First access to Configuration Register G Write Add. Value to Configuration Register W tWLWH CR tRHLH tLHRL LB, UB AI12184 1. Only the content of the Bus Configuration Register (BCR) and Refresh Configuration Register (RCR) can be modified. 2. The Opcode is the value to be written the configuration register. 3. CR is latched on the rising edge of L. There is no setup requirement of CR with respect to E. 45/61 DC and AC parameters Table 19. M69KM048AA Clock Related AC Timings M69KM048AA Symbol Alt. Parameter Unit Min Max fCLK fCLK Clock frequency tKHKH tCLK Clock Period 12 ns tKHKL, tKLKH tKP Clock High to Clock Low, Clock Low to Clock High 4 ns tR, tF tKHKL Table 20. 83 Clock Rise Time, Clock Fall Time 1.8 MHz ns Synchronous Burst Read AC Characteristics(1) M69KM048AA Symbol Alt. Parameter Unit Min Max tAVQV tAA Address Valid to Output valid (Fixed Latency) tAVKH, tRHKH tQVKH, tLLKH tBLKH, tWHKH tSP Set-up Time to Active Clock Edge 3 ns tEHEL(2) tCBPH Chip Enable High between Subsequent Operations in FullSynchronous or NOR-Flash mode. 6 ns tELEH(2) tCEM Chip Enable Pulse Width tELTV, tLLTV tCEW Chip Enable Low to WAIT Valid Latch Enable Low to WAIT Valid tELQV tCO Chip Enable Low to Output Valid tELKH tCSP Chip Enable Low to Clock High tEHQZ, tEHTZ(3) tHZ Chip Enable High to Output Hi-Z or WAIT Hi-Z 8 ns tGLQV tBOE Output Enable Low to Output Valid in Burst mode 20 ns tGHQZ(3) tOHZ Output Enable High to Output Hi-Z 8 ns tGLQX(4) tOLZ Output Enable Low to output transition 3 ns tGHQV tOHZS Output Enable high to address valid 8 ns tKHQV1 tABA Burst to Read Access Time (Variable Latency) 46 ns tKHQV2 tACLK Clock High to Output Delay 9 ns tKHAX, tKHBH, tKHWL, tKHEH, tKHLH, tKHQX tHD tLLQV tAADV Latch Enable Low to Output Valid (Fixed Latency) 70 ns tKHTX, tKHTV tKHTL Clock High to WAIT Valid 9 ns Hold Time From Active Clock Edge 70 1 ns 8 s 7.5 ns 70 ns 4.5 ns 2 ns 1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement Conditions and Figure 12: AC Measurement Load Circuit. 2. A refresh opportunity must be offered every tELEH. A refresh opportunity is possible either if E is High during the rising edge of K; or if E is High for longer than 15ns. 3. The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2. 4. The transition timings measure a 100mV transition from the Hi-Z (VCCQ/2) level to either VOH or VOL. 46/61 M69KM048AA DC and AC parameters Figure 17. Clock input AC Waveform tKHKL tKHKH tr tf tKLKH AI06981 Figure 18. Single Synchronous Burst Read AC waveforms (Fixed Latency mode) tKHKH tKHKL tF K tKHAX tAVKH ADDRESS VALID A16-A19 tKHLH tLLKH L tKHQV1 tELKH tEHQZ tKHEH E tELEH tGLQV tGHQV tGHQZ G tWHKH tKHWL tGLQX W tBLKH tKHBH LB/UB tELTV WAIT tKHAX tKHQV2 tAVKH ADQ0-ADQ15 tKHTX Hi-Z ADDRESS VALID tKHQX OUTPUT VALID AI12721 1. The latency Type (BCR14) is set to fixed (BCR14 = 1). The Latency is set to 3 clock cycles (BCR13-BCR11 = 010), and The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). 47/61 DC and AC parameters M69KM048AA Figure 19. 4-Word Synchronous Burst Read AC waveforms (Variable Latency mode) tKHKL tKHKH K tKHAX tAVKH VALID ADDRESS A16-A20 tKHLH tLLKH L tELEH tELKH tEHEL tKHEH tKHQV1 E tGHQV tEHQZ tGLQV G tWHKH tKHWL tGLQX tGHQZ W LB/UB tKHTX tELTV Hi-Z WAIT Hi-Z tKHQV2 ADQ0-ADQ15 Hi-Z VALID ADDRESS READ Burst Identified (W = High) tKHQX VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT AI12185b 1. The latency Type (BCR14) is set to variable (BCR14 = 0). The Latency is set to 3 clock cycles (BCR13-BCR11 = 010). The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). 48/61 M69KM048AA DC and AC parameters Valid Output Hi-Z DON'T CARE tKHQV1 Valid Address Hi-Z ADQ0-ADQ15 WAIT Hi-Z LB/UB W tBLKH tWHKH G tGHQV tELKH E L A16-A20 tAVLH tLLKH Valid Address tAVKH K tKHQX Valid Output Valid Output Valid Output tKHTX tKHWL tKHAX tKHLH tGLQX tGLQV tKHKL DON'T CARE tGHQZ Valid Output tGLQV Valid Output tGHQZ tEHEL tEHQZ Valid Address AI12186b Figure 20. Synchronous Burst Read Suspend and Resume AC waveforms 1. The latency Type (BCR14) can be set to fixed or variable during Burst Read Suspend operations.The Latency is set to 3 clock cycles (BCR13-BCR11 = 010). The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). 2. During Burst Read Suspend operations, the Clock signal must be stopped (Low). 3. G can be held Low, VIL, during Burst Suspend operations. If so, data output remain valid. 49/61 DC and AC parameters M69KM048AA Figure 21. Burst Read Showing End-of-Row Condition AC waveforms (No Wrap) tKLKH, tKHKL K tKHKH tF A16-A20 DON'T CARE High L LB/UB E Low G Low Note 2 W DON'T CARE tKHTV tEHTZ tEHTZ High-Z WAIT ADQ0-ADQ15 VALID OUTPUT VALID OUTPUT End of Row AI12187b 1. The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). 2. The Chip Enable signal, E, must go High before the third Clock cycle after the WAIT signal goes Low. If BCR8 were set to 1, E would have to go Low before the fourth Clock cycle after WAIT signal goes Low. 50/61 M69KM048AA DC and AC parameters ai12722 tGLQV tKHWX tELTV tELWH tWHWL (2) tEHEL tWLWH tWHKH tELKH tKHBH WAIT W G E LB/UB L tAVLH tAVWL tBLWH tAVWH tLHAX tLLLH, tELLH tLLKH tBLKH VALID ADDRESS tDVWH VALID ADDRESS ADQ0-ADQ15 A19-A16 K VALID ADDRESS VALID DATA tAVKH tWHDX VALID ADDRESS tKHLH tKHAX tKHQV2 tKHKH VALID OUTPUT VALID OUTPUT VALID OUTPUT tGHQZ VALID OUTPUT Hi-Z Figure 22. Asynchronous Write followed by Burst Read AC waveforms 1. The latency Type (BCR14) can be set to fixed or variable.The Latency is set to 3 clock cycles (BCR13-BCR11 = 010). The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). 2. When transitioning from an asynchronous Write operation to a synchronous Read operation in variable latency mode, E must go High, VIH. When transitioning to a synchronous Read operation in fixed latency mode, E can stay Low, VIL. A refresh opportunity must be provided every tELEH. A refresh opportunity is possible either if E is High during the rising edge of K; or if E is High for longer than 15ns. 51/61 DC and AC parameters M69KM048AA AI12723 tEHDX VALID INPUT tAVLH VALID ADDRESS tDVEH tLHAX tWHTZ tBLBH tWLWH VALID OUTPUT ADQ0-ADQ15 tQVKH Burst Read Identified (W = High) tKHQX WAIT Hi Z LB/UB Hi-Z VALID ADDRESS tELTV tKHBH W G tBLKH tWHKH tGHQZ E tELKH tLLKH L A19-A16 K tKHWX tKHLH ADDRESS VALID tKHAX tAVKH tGLQX tKHQV2 tKHTV tKHBX tGHQZ tELTV tEHQZ tGLQV tKHKH tKHEH (2) tEHEL tAVLH tAVWL tELWL tELEH, tELWH tAVEH tLLLH tLLWH VALID ADDRESS tLHAX Hi-Z tWHWL Figure 23. Burst Read followed by Asynchronous Write AC waveforms 1. The latency Type (BCR14) can be set to fixed or variable.The Latency is set to 3 clock cycles (BCR13-BCR11 = 010). The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). 2. When transitioning from a synchronous Read operation in variable latency mode to an asynchronous Write operation, E must go High, VIH. When transitioning from a synchronous Read operation in fixed latency mode, E can stay Low, VIL. Asynchronous operations begin at the falling edge of L. A refresh opportunity must be offered every tELEH. A refresh opportunity is possible either if E is High during the rising edge of K; or if E is High for longer than 15ns. 52/61 M69KM048AA Table 21. DC and AC parameters Synchronous Burst Write AC Characteristics(1) M69KM048AA Symbol Alt. Parameter Unit Min Max tAVWL tLLWL(2) tAS Address Set-up to Beginning of Write Operation 0 ns tAVKH tDVKH tWLKH tLLKH tBLKH tWHKH tWHWL tSP Set-up Time to Active Clock Edge 3 ns tLHAX tAVH Latch Enable High to Address Transition (Fixed Latency) 2 ns tEHEL(3) tCBPH Chip Enable High between Subsequent Operations in FullSynchronous or NOR-Flash mode. 6 ns tELEH(3) tCEM Maximum Chip Enable Low Pulse tELTV tLLTV tCEW Chip Enable Low to WAIT Valid 1 tELKH tCSP Chip Enable Low to Clock High 4.5 tEHDZ tEHTZ(4) tHZ Chip Enable High to Input Hi-Z or WAIT Hi-Z tKHAX tKHRL tKHLH tKHDX tKHEH tKHBH tKHWH tHD Hold Time From Active Clock Edge tKHLL tKHTV tKHTX tKADV Last Clock Rising Edge to Latch Enable Low (Fixed Latency) tKHTL Clock High to WAIT Valid or Low 8 s 7.5 ns ns 8 ns 2 ns 6 ns 9 ns 1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement Conditions and Figure 12: AC Measurement Load Circuit. 2. tAVWL and tLLWL, are required if tELKH> 20ns. 3. A refresh opportunity must be offered every tELEH. A refresh opportunity is possible either if E is High during the rising edge of K; or if E is High for longer than 15ns. 4. The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2. 53/61 DC and AC parameters M69KM048AA Figure 24. 4-Word Synchronous Burst Write AC waveforms (Fixed Latency mode) tKHKH K VALID ADDRESS A16-A20 tAVKH tKHAX tAVWL tLLWL tKHLL L tLLKH tKHLH tKHBH tBLKH LB/UB tELEH tELKH tEHEL E tKHEH High G tWLKH tKHWH W tKHTX tEHTZ tELTV Hi-Z WAIT Note 2 Hi-Z tKHDX tDVKH ADQ0-ADQ15 Hi-Z VALID ADDRESS VALID INPUT VALID INPUT VALID INPUT VALID INPUT WRITE Burst Identified (W = Low) ai12188 1. The Latency type is set to fixed (BCR14 = 1).The Latency is set to 3 clock cycles (BCR13-BCR11 = 010). The WAIT signal is active Low (BCR10=0), and asserted during delay (BCR8=0). 2. The WAIT signal must remain asserted for LC clock cycles (LC Latency code), whatever the Latency mode (fixed or variable). 3. tAVLL and tLLWL, are required if tELKH> 20ns. 54/61 M69KM048AA DC and AC parameters Figure 25. Burst Write Showing End-of-Row Condition AC waveforms (No Wrap) tKLKH K tKHKH A16-A20 tF DON'T CARE L LB/UB Note 2 E High G DON'T CARE W tKHTV tEHTZ tEHTZ High-Z WAIT tDVKH ADQ0-ADQ15 tKHDX VALID INPUT D[n] VALID INPUT D[n+1] End of Row (A6-A0 = 7Fh) ai12189 1. The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). 2. The Chip Enable signal, E, must go High before the third Clock cycle after the WAIT signal goes Low. If BCR8 were set to 1, E would have to go Low before the fourth Clock cycle after WAIT signal goes Low. 55/61 DC and AC parameters M69KM048AA DO3 DO0 tKHTX tKHWL tGLQX DIN3 DIN1 DIN2 tDVKH WAIT UB, LB ADQ0ADQ15 VALID ADD. tBLKH tKHWH W tWLKH G E L tLLKH tELKH VALID ADD. tAVKH A16-A20 K tKHAX tKHLH tKHKH DIN0 tKHTX tKHBH tKHKL tKHEH tKHLL tKHDX (2) tELKH tWHKH tEHEL tKHLH VALID ADD. tAVKH tKHAX tKLKH DO1 DO2 tKHQX tKHEH ai12190b tGHQZ Figure 26. Synchronous Burst Write Followed by Read AC waveforms 1. The Latency type can set to fixed or variable mode. The Latency is set to 3 clock cycles (BCR13-BCR11 = 010). The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). 2. E can remain Low between the Burst Read and Burst Write operation, but it must not be held Low for longer than tELEH. 56/61 M69KM048AA DC and AC parameters Figure 27. CR Controlled Configuration Register Program, Synchronous Mode K A16-A18, A20(3) Opcode tAVKH tKHAX 0 (RCR) 1 (BCR) A19(4) tRHKH tKHRL tLLKH tKHLH CR(5) L tELEH E G tWLKH tKHWH W UB, LB ADQ0-ADQ15(2) tELTV WAIT Hi-Z AI12191 1. Only the Configuration Register (BCR) and the Refresh Configuration Register (RCR) can be modified. 2. Data Inputs/Outputs are not used. 3. The Opcode is the value to be written in the Configuration Register. 4. A19 gives the Configuration Register address. 5. CR initiates the Configuration Register Access. 57/61 DC and AC parameters Table 22. M69KM048AA Power-Up and Deep Power-Down AC Characteristics Symbol Alt. Parameter Min Max Unit tVCHEL tPU Initialization delay after Power-Up or Deep Power-Down Exit 150 s tEHEL(DP) tDPD Deep Power-Down Entry to Deep Power-Down Exit 10 s tELEH(DP) tDPDX Chip Enable Low to Deep Power-Down Exit 10 s Figure 28. Power-Up AC waveforms E tVCHEL VCC, VCCQ 1.7V Device Ready for Normal Operation Device Initialization AI09465e 1. Power must be applied to VCC prior to or at the same time as VCCQ. Figure 29. Deep Power-Down Entry and Exit AC waveforms E tEHEL(DP) Deep Power-Down Entry (RCR4= 0) Deep Power-Down Mode tELEH (DP) tVCHEL Deep Power-Down Device Initialization Device Ready Exit for Normal Operation AI11306b 58/61 M69KM048AA 10 Part numbering Table 23. Ordering Information Scheme Example: Part numbering M69KM048AA CW8 Device Type M69 = PSRAM Mode K = Bare Die Operating Voltage M= VCC = 1.7 to 1.95V, x16, Multiplexed I/O, PSRAM Array Organization 048 = 32 Mbit (2 Mbit x16) Option 1 A = 1 Chip Enable Silicon Revision A = A Die Maximum Clock Frequency C = 83MHz Package W = Unsawn Wafer Operating Temperature 8 = -30 to 85 C The notation used for the device number is as shown in Table 23. Not all combinations are necessarily available. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest STMicroelectronics Sales Office. 59/61 Revision history 11 Revision history Table 24. Document Revision History Date Rev. 22-Dec-2005 0.1 29-May-2006 60/61 M69KM048AA 1 Revision Details First Issue. Maximum clock frequency changed to 83MHz. Output Disable/No Operation updated in Table 2, Table 3, Table 4, and Table 5. CR status for subsequent Burst Read and Write operations modified in Table 5. LB/UB status modified in Figure 5. Table 9 updated. Table 12 added. VIO updated in Table 13. Table 15 updated. VIH minimum value, IPASR maximum values, ICC1, ICC2 and ICC3R maximum values modified in Table 16. tAVLH, tRHLH, tELLH updated, tEHEL removed, and tLHQX added in Table 17. Figure 13 and Figure 15 updated. tAVLH, tRHLH, tELLH updated, and tWHQZ removed in Table 18. tLLWL added in Figure 14. tGHQV added in Table 20. G, LB/UB status modified in Figure 19 and Figure 20. LB/UB status modified in Figure 21, Figure 24, and Figure 26. Figure 18, Figure 22, and Figure 23 added. tPU changed to tVCHEL in Table 22, Figure 28 and Figure 29. Wafer and die specifications removed. M69KM048AA Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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