Preliminary Data
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
May 2006 Rev 1 1/61
1
M69KM048AA
32 Mbit (2 Mb x16), 83MHz Clock Rate,
1.8V Supply, Multiplexed I/O, Bare Die, Burst PSRAM
Feature summary
■Supply Voltage
–V
CC = 1.7 to 1.95V core supply voltage
–V
CCQ = 1.7 to 1.95V for I/O buffers
■Multiplexed Address/Data bus
■Asynchronous Operating Modes
– Random Read: 70ns access time
– Asynchronous Write
■Synchronous modes
– Synchronous Read:
Fixed length (4, 8, and 16 Words) or
continuous burst
Clock Frequency: 83MHz (max.)
– Synchronous Write: continuous burst
■Low Power Consumption
– Active Current: < 35mA
– Standby Current: < 110µA
– Deep Power-Down Current: 10µA (typical)
■Low Power Features
– Partial Array Self-Refresh (PASR)
– Deep Power-Down (DPD) Mode
– Automatic Temperature-compensated Self-
Refresh
■Operating Temperature
– –30°C to +85°C
The M69KM048AA is only available as part of a multi-chip package Product.
Wafer
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Contents M69KM048AA
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Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Address Inputs (A16-A20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Address Inputs or Data Input/Outputs (ADQ0-ADQ15) . . . . . . . . . . . . . . . 9
2.3 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Upper Byte Enable (UB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7 Lower Byte Enable (LB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8 Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9 Configuration Register Enable (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.11 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.12 VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.13 VCCQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.14 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.15 VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Automatic Temperature Compensated Self Refresh . . . . . . . . . . . . . . . . 13
5 Standard Asynchronous operating modes . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Asynchronous Read and Write modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Configuration Registers Asynchronous Read and Write . . . . . . . . . . . . . 14
6 Synchronous Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
M69KM048AA Contents
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6.1 NOR-Flash Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Full Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 Synchronous Burst Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3.1 Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.2 Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.3 Row Boundary Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Synchronous Burst Read Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.5 Synchronous Burst Write Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.6 Synchronous Burst Read and Write Suspend . . . . . . . . . . . . . . . . . . . . . 19
7 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 Programming the Registers using the CR controlled method . . . . . . . . . 25
7.2 Reading and programming the registers using the software method . . . . 26
7.3 Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.3.1 Operating Mode Bit (BCR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.3.2 Latency Type (BCR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.3.3 Latency Counter Bits (BCR13-BCR11) . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.3.4 WAIT Polarity Bit (BCR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.3.5 WAIT Configuration Bit (BCR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3.6 Driver Strength Bits (BCR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3.7 Burst Wrap Bit (BCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3.8 Burst Length Bits (BCR2-BCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.4 Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.4.1 Deep Power-Down Bit (RCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.4.2 Partial Array Refresh Bits (RCR2-RCR0) . . . . . . . . . . . . . . . . . . . . . . . 34
8 Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
List of tables M69KM048AA
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List of tables
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Standard Asynchronous Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Asynchronous Write Operations (NOR-Flash Synchronous Mode) . . . . . . . . . . . . . . . . . . 20
Table 4. Synchronous Read Operations (NOR-Flash Synchronous mode) . . . . . . . . . . . . . . . . . . . 21
Table 5. Full Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Register Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. Bus Configuration Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. Variable Latency Counter Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Fixed Latency Counter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 11. Refresh Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 12. Address patterns for Partial Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 13. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 14. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 15. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 16. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 17. Asynchronous Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 18. Asynchronous Write AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 19. Clock Related AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 20. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 21. Synchronous Burst Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 22. Power-Up and Deep Power-Down AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 23. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 24. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
M69KM048AA List of figures
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List of figures
Figure 1. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Variable Latency Mode, No Refresh Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. Fixed Latency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 5. Refresh Collision during Synchronous Burst Read in Variable Latency Mode . . . . . . . . . . 24
Figure 6. Set Configuration Register (software method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 7. Read Configuration Register (software method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8. WAIT Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 9. WAIT Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 10. AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11. AC Input Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13. Asynchronous Random Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 14. Asynchronous Write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 15. Asynchronous Write followed by Read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16. CR Controlled Configuration Register Program, Asynchronous Mode. . . . . . . . . . . . . . . . 45
Figure 17. Clock input AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 18. Single Synchronous Burst Read AC waveforms (Fixed Latency mode). . . . . . . . . . . . . . . 47
Figure 19. 4-Word Synchronous Burst Read AC waveforms (Variable Latency mode). . . . . . . . . . . . 48
Figure 20. Synchronous Burst Read Suspend and Resume AC waveforms . . . . . . . . . . . . . . . . . . . . 49
Figure 21. Burst Read Showing End-of-Row Condition AC waveforms (No Wrap) . . . . . . . . . . . . . . . 50
Figure 22. Asynchronous Write followed by Burst Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 23. Burst Read followed by Asynchronous Write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 24. 4-Word Synchronous Burst Write AC waveforms (Fixed Latency mode) . . . . . . . . . . . . . . 54
Figure 25. Burst Write Showing End-of-Row Condition AC waveforms (No Wrap) . . . . . . . . . . . . . . . 55
Figure 26. Synchronous Burst Write Followed by Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 27. CR Controlled Configuration Register Program, Synchronous Mode. . . . . . . . . . . . . . . . . 57
Figure 28. Power-Up AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 29. Deep Power-Down Entry and Exit AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Summary description M69KM048AA
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1 Summary description
The M69KM048AA is a 32 Mbit (33,554,432 bit) PSRAM, organized as 2,097,152 Words by
16 bits. It uses a high-speed CMOS DRAM technology implemented using a one transistor-
per-cell topology that achieves bigger array sizes. It provides a high-density solution for low-
power handheld applications.
The device operates from a 1.7 to 1.95V supply voltage. It has a 16-bit data bus. To reduce
the number of pins. the first sixteen address lines are multiplexed with the Data Input/Output
signals on the multiplexed address/data bus ADQ0-ADQ15. The remaining address lines
A16-A20 are the MSB addresses.
The PSRAM interface supports various operating modes:
●Asynchronous Random Read and Write - when operating in one of these modes, the
M69KM048AA is compatible with low power SRAMs.
●Synchronous modes that increase read and write speeds. Two types of Synchronous
modes are available:
– Flash-NOR: the device operates in Synchronous mode for read operations and
Asynchronous mode for write operations.
– Full Synchronous: the device supports Synchronous transfers for both read and
write operations.
The M69KM048AA features two user-programmable configuration registers, which are used
to define the device operation:
●The Bus Configuration Register (BCR)
●The Refresh Configuration Register (RCR)
The Bus Configuration Register (BCR) indicates how the device interacts with the system
memory bus. The Refresh Configuration Register (RCR) is used to control how the memory
array refresh is performed. At Power-Up, the registers are automatically loaded with default
settings and can be updated any time during normal operation.
PSRAMs are based on the DRAM technology, but have a transparent internal self-refresh
mechanism that requires no additional support from the system memory microcontroller. To
minimize the value of the Standby current during self-refresh operations, the M69KM048AA
includes three system-accessible mechanisms configured via the Refresh Configuration
Register (RCR):
●Partial Array Self Refresh (PASR) performs a limited refresh of the part of the PSRAM
array that contains essential data.
●Deep Power-Down (DPD) mode completely halts the refresh operation. It is used when
no essential data is being held in the device.
●Automatic Temperature Compensated Self Refresh (TCSR) adjusts the refresh rate
according to the operating temperature.
M69KM048AA Summary description
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Figure 1. Logic Diagram
Table 1. Signal Names
A16-A20 Address Inputs
ADQ0-ADQ15 Address Inputs or Data Input/Outputs
EChip Enable Input
CR Configuration Register Enable Input
GOutput Enable Input
WWrite Enable Input
UB Upper Byte Enable Input
LB Lower Byte Enable Input
K Clock Input
LLatch Enable Input
WAIT Wait Output
VCC Core Supply Voltage
VCCQ Input/Output Buffers Supply Voltage
VSS Ground
VSSQ Input/Output Buffers Ground
AI12174
5
A16-A20
W
ADDQ0-DQ15
VCC
M69KM048AA
G
16
E
UB
LB
VSS
CR
K
L
VCCQ
VSSQ
WAIT
Summary description M69KM048AA
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Figure 2. Block Diagram
1. This functional block diagram illustrates simplified device operation.
AI12175b
K
WAIT
Control
Logic
CR
L
UB
LB
W
E
G
Bus Configuration
Register (BCR)
Bus Configuration
Register (BCR)
Refresh Configuration
Register (RCR)
A16-A20 Address Decoder
I/O MUX
and Buffers
2,048K x 16
Memory Array ADQ0-
ADQ15
M69KM048AA Signal descriptions
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2 Signal descriptions
The signals are summarized in Figure 1: Logic Diagram, and Table 1: Signal Names.
2.1 Address Inputs (A16-A20)
The Address Inputs A16-A20 are used in conjunction with ADQ0 to ADQ15, to select the
cells in the memory array that are accessed during read and write operations.
2.2 Address Inputs or Data Input/Outputs (ADQ0-ADQ15)
ADQ0-ADQ15 support multiplexed address/data sequencing. They are used to input
addresses to the memory array, or to program data in the memory array. Addresses are
internally latched during Read and Write operations.
ADQO-ADQ15 are also used to define the value to be loaded into the BCR or the RCR,
along with A16- A20 address Inputs.
2.3 Chip Enable (E)
Chip Enable, E, activates the device when driven Low (asserted). When de-asserted (VIH),
the device is disabled and goes automatically in low-power Standby mode or Deep Power-
Down mode, according to the RCR settings.
2.4 Output Enable (G)
When held Low, VIL, the Output Enable, G, enables the Bus Read operations of the memory.
2.5 Write Enable (W)
Write Enable, W, controls the Bus Write operation of the memory. When asserted (VIL), the
device is in write mode and write operations can be performed either to the configuration
registers or to the memory array.
2.6 Upper Byte Enable (UB)
The Upper Byte Enable, UB, gates the data on the Upper Byte of the Address Inputs/ Data
Inputs/Outputs (ADQ8-ADQ15) to or from the upper part of the selected address during a
write or read operation.
Signal descriptions M69KM048AA
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2.7 Lower Byte Enable (LB)
The Lower Byte Enable, LB, gates the data on the Lower Byte of the Address Inputs/Data
Input/Outputs (ADQ0-ADQ7) to or from the lower part of the selected address during a write
or read operation.
If both LB and UB are disabled (High), the device will disable the data bus from receiving or
transmitting data. Although the device will seem to be deselected, it remains in an active
mode as long as E remains Low.
2.8 Clock Input (K)
The Clock, K, is an input signal to synchronize the memory to the microcontroller or system
bus frequency during Synchronous Burst Read and Write operations. The Clock input signal
increments the device internal address counter.
The addresses are latched on the rising edge of the Clock K, when L is Low during
Synchronous Bus operations. Latency counts are defined from the first Clock rising edge
after L falling edge to the first data input latched or the first data output valid.
The Clock input is required during all synchronous operations and must be kept Low during
asynchronous operations.
2.9 Configuration Register Enable (CR)
When this signal is driven High, VIH, bus read or write operations access either the value of
the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR)
according to the value of A19.
2.10 Latch Enable (L)
In Synchronous mode, addresses are latched on the rising edge of the Clock K when the
Latch Enable input, L is Low. In Asynchronous mode, addresses are latched on L rising
edge.
2.11 Wait (WAIT)
The WAIT output signal provides data-valid feedback during Synchronous Burst Read and
Write operations. The signal is gated by E. Driving E High while WAIT is asserted may
cause data corruption.
Once a read or write operation has been initiated, the WAIT signal goes active to indicate
that the M69KM048AA device requires additional time before data can be transferred.
The WAIT signal also is used for arbitration when a Read or Write operation is launched
while an on-chip refresh is in progress (see Figure 5: Refresh Collision during Synchronous
Burst Read in Variable Latency Mode). Typically, the WAIT pin of the M69KM048AA can be
connected to a shared WAIT signal used by the processor to coordinate transactions with
multiple memories on the synchronous bus.
See Section 3: Power-up for details on the WAIT signal operation.
M69KM048AA Signal descriptions
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2.12 VCC Supply Voltage
The VCC Supply Voltage is the core supply voltage.
2.13 VCCQ Supply Voltage
VCCQ provides the power supply for the I/O pins. This allows all Outputs to be powered
independently from the core power supply, VCC.
2.14 VSS Ground.
The VSS Ground is the reference for all voltage measurements.
2.15 VSSQ Ground
VSSQ ground is the reference for the input/output circuitry driven by VCCQ. VSSQ must be
connected to VSS.
Power-up M69KM048AA
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3 Power-up
To guarantee correct operation, a specific Power-Up sequence must be followed to initialize
the M69KM048AA. Power must be applied simultaneously to VCC and VCCQ. Once VCC and
VCCQ have reached a stable level (see Figure 29: Deep Power-Down Entry and Exit AC
waveforms and Figure 28: Power-Up AC waveforms), the device will require tVCHEL to
complete its self-initialization process. During the initialization period, the E signal must
remain High. Once initialization has completed, the device is ready for normal operation.
Initialization will load the Bus Configuration Register (BCR) and the Refresh Configuration
Register (RCR) with their default settings (see Table 7: Bus Configuration Register
Definition, and Table 11: Refresh Configuration Register Definition).
4 Low-power modes
4.1 Standby
When the device is in Standby, the current consumption is reduced to the level necessary to
perform the memory array refresh operation. The device will enter Standby when a read or
write operation is completed, depending on the operating mode (asynchronous,
synchronous).
For details on how to enter Standby, refer to Table 2: Standard Asynchronous Operating
Modes, Table 3: Asynchronous Write Operations (NOR-Flash Synchronous Mode) and
Table 4: Synchronous Read Operations (NOR-Flash Synchronous mode).
4.2 Deep Power-Down
Deep Power-Down (DPD) is used by the system memory microcontroller to disable the
PSRAM device when its storage capabilities are not needed. All refresh operations are then
disabled.
For the device to enter Deep Power-Down mode, bit 4 of the RCR must be set to ‘0’ and
Chip Enable, E, must go High, VIH. When the Deep Power-Down is enabled, the data stored
in the device may be corrupted and the BCR, and the RCR contents are saved.
The device exits from Deep Power-Down mode when the Chip Enable signal, E, has been
Low again for a minimum time of tELEH(DP) (see Table 22: Power-Up and Deep Power-Down
AC Characteristics and Figure 28: Power-Up AC waveforms).
Bit 4 of the RCR will be automatically set to ‘1’. Once the Deep Power-Down is exited, the
device will be available for normal operations after tVCHEL (time to perform an initialization
sequence) During this delay, the current consumption will be higher than the specified
Standby levels, but considerably lower than the active current. The content of the registers
will be restored after Deep Power-Down.
For details on how to enter Deep Power-Down, refer to Table 2: Standard Asynchronous
Operating Modes, Table 3: Asynchronous Write Operations (NOR-Flash Synchronous
Mode) and Table 4: Synchronous Read Operations (NOR-Flash Synchronous mode).
M69KM048AA Low-power modes
13/61
4.3 Partial Array Self Refresh
The Partial Array Self Refresh (PASR) performs a limited refresh of part of the PSRAM
array. This mechanism enables the device to reduce the Standby current by refreshing only
the part of the memory array that contains essential data. Different refresh options can be
defined by setting the RCR0 to RCR2 bits of the RCR:
●Full array
●One eighth of the array
●One half of the array
●One quarter of the array
●None of the array.
These memory areas can be located either at the top or bottom of the memory array.
The WAIT signal is used for arbitration when a read/write operation is launched while an on-
chip refresh is in progress. If locations are addressed while they are undergoing refresh, the
WAIT signal will be asserted for additional clock cycles, until the refresh has completed (see
Figure 5: Refresh Collision during Synchronous Burst Read in Variable Latency Mode).
When the refresh operation is completed, the read or write operation will be allowed to
continue normally.
4.4 Automatic Temperature Compensated Self Refresh
The leakage current of DRAM capacitive storage elements increases with the temperature.
At lower temperatures, the refresh rate can be decreased to minimize the Standby current.
The M69KM048AA is based on DRAM architecture, consequently it requires increasingly
frequent refresh operations to maintain data integrity as the temperature increases. The
Automatic Temperature Compensated Self Refresh mechanism (TCSR) that the devices
feature, automatically adjusts the refresh rate depending on the operating temperature.
Standard Asynchronous operating modes M69KM048AA
14/61
5 Standard Asynchronous operating modes
The M69KM048AA supports Asynchronous Read and Write modes (Random Read,
Asynchronous Write).
The device is put in Asynchronous mode by setting bit 15 (BCR15) of the BCR to ‘1’.
During asynchronous operations, the WAIT signal should be ignored and the Clock input
signal K should be held Low, VIL.
Refer to Table 2: Standard Asynchronous Operating Modes for a detailed description of
asynchronous operating modes.
5.1 Asynchronous Read and Write modes
At Power-Up, the device defaults to Asynchronous Random Read mode (bit BCR15 set to
‘1’). This mode uses the industry standard control bus (E, G, W, LB, UB). Read operations
are initiated by bringing E, G and L Low, VIL, while keeping W High, VIH, and driving the
address onto the multiplexed address/data bus. L is then taken High, VIH, to capture the
address, and G is taken Low, VIL. Valid data will be gated through the output buffers after the
specific access time tELQV has elapsed.
Write operations occur when E, W and L are driven Low, VIL with the address on the
multiplexed address/data bus. L is then taken High, VIH, to capture the address, and the
write data is driven onto the bus. During Asynchronous Random Write operations, the G
signal is ‘don't care’ and W will override G. The data to be written is latched on the rising
edge of E, W, LB or UB (whichever occurs first). The write operation is terminated by de-
asserting E, W, LB or UB.
See Figure 13, and Ta b l e 1 7 for details on Asynchronous Read AC waveforms and
characteristics and Figure 14, and Ta b l e 1 8 for details of Asynchronous Write AC waveforms
and characteristics.
5.2 Configuration Registers Asynchronous Read and Write
The BCR and RCR can be programmed using the CR controlled method in standard
Asynchronous mode (see Figure 16 and Figure 27).
The CR controlled method cannot be used to read the BCR and RCR contents.
M69KM048AA Standard Asynchronous operating modes
15/61
Table 2. Standard Asynchronous Operating Modes
Asynchronous
Modes(1) Power E L W G UB LB CR A19
A16 -
A18
A20
ADQ0-
ADQ7
ADQ8-
ADQ15
Word Read
Active
(ICC)
VIL
\_/
VIH
VIL VIL VIL VIL Address In Valid Address In/ Data Out Valid
Lower Byte
Read VIL VIH VIL VIL Address In Valid
Address In/
Data Out
Valid
High-Z
Upper Byte
Read VIL VIL VIH VIL Address In Valid High-Z
Address In/
Data Out
Valid
Word Write
VIL VIH
VIL VIL VIL Address In Valid Address In/ Data In Valid
Lower Byte
Write VIH VIL VIL Address In Valid
Address In/
Data In
Valid
Data In Invalid
Upper Byte
Write VIL VIH VIL Address InValid Data In
Invalid
Address In/
Data In Valid
Program
Configuration
Register (CR
Controlled)(2)
VIL VIL VIH XXV
IH
0(RCR)
1(BCR)
(3)
BCR/
RCR
Data
Address In Valid
Output
Disable/No
Operation
Idle
XX
XXXV
IL XX X
Deep
Power-Down(4)
Deep
Power-
Down
(ICCPD)
VIH X X X X X X High-Z
Standby Standby
(IPASR)VIH X X X X X X High-Z
1. The Clock signal, K, must remain Low in asynchronous operating mode.
2. BCR and RCR only.
3. A19 is used to select between the BCR and the RCR.
4. The device enters Deep Power-Down mode by driving the Chip Enable signal, E, from Low to High, with bit 4 of the RCR set
to ‘0’. The device remains in Deep Power-Down mode until E goes Low again and is held Low for tELEH(DP).
Synchronous Operating modes M69KM048AA
16/61
6 Synchronous Operating modes
The synchronous modes allow high-speed read and write operations synchronized with the
clock.
The M69KM048AA supports two types of synchronous modes:
●NOR-Flash:- this mode greatly simplifies the interfacing with traditional burst-mode
Flash memory microcontrollers.
●Full Synchronous: both read and write are performed in Synchronous mode.
All the options related to the synchronous modes can be configured through the Bus
Configuration Register, BCR. In particular, the device is put in Synchronous mode, either
NOR-Flash or Full Synchronous, by setting bit BCR15 of the Bus Configuration Register to
‘0’.
The device will automatically detect whether the NOR-Flash or the Full Synchronous mode
is being used by monitoring the Clock, K, and the Latch Enable, L, signals. If a rising edge of
the Clock K is detected while L is held Low, VIL (active), the device operates in Full
Synchronous mode.
6.1 NOR-Flash Synchronous mode
In this mode, the device operates in synchronous mode for read operations, and in
asynchronous mode for write operations.
Asynchronous write operations are performed at Word level, with LB and UB Low. The data
is latched on E, W, LB, UB, whichever occurs first.
RCR and BCR registers can be programmed in NOR-Flash Asynchronous Write mode,
using the CR controlled method (see Section 7.1: Programming the Registers using the CR
controlled method). A Program Configuration Register operation can only be issued if the
device is in idle state and no burst operations are in progress. NOR-Flash Asynchronous
Write operations are described in Table 3: Asynchronous Write Operations (NOR-Flash
Synchronous Mode).
Synchronous read operations are also performed at Word level. They are controlled by the
state of E, L, G, W, LB and UB signals when a rising edge of the clock signal, K, occurs. The
initial Burst Read access latches the Burst start address. The number of Words to be output
is controlled by bits 0 to 2 of the BCR. The first data will be output after a number of clock
cycles, also called Latency. NOR-Flash Synchronous Burst Read operations are described
in Table 4: Synchronous Read Operations (NOR-Flash Synchronous mode).
When a Burst Write operation is initiated or when switching from NOR-Flash mode to Full
Synchronous mode, the delay from E Low to Clock High, tELKH, should not exceed 20ns.
However, when it is not possible to meet these specifications, special care must be taken to
keep addresses stable after driving the Write Enable signal, W, Low.
Write operations are considered as Asynchronous operations until the device detects a valid
clock edge and hence the address setup time of tAVWL must be satisfied (see Figure 5:
Refresh Collision during Synchronous Burst Read in Variable Latency Mode).
M69KM048AA Synchronous Operating modes
17/61
6.2 Full Synchronous mode
In Full Synchronous mode, the device performs read and write operations synchronously.
Synchronous Read and Write operations are performed at Word level. The initial Burst Read
and Write access latches the Burst start address. The number of Words to be output or input
during Synchronous Read and Write operations is controlled by bits 0 to 2 of the BCR.
During Burst Read and Write operations, the first data will be output after a number of clock
cycles defined by the Latency value.
The BCR and RCR can be programmed using the CR controlled method in Full
Synchronous mode. The CR controlled method cannot be used to read BCR and RCR
content.
Full Synchronous operations are described in Table 5: Full Synchronous Mode.
6.3 Synchronous Burst Read and Write
During Synchronous Burst Read or Write operations, addresses are latched on the rising
edge of the Clock K when L is Low and data are latched on the rising edge of K. The Write
Enable, W, signal indicates whether the operation is going to be a read (W=VIH) or a write
(W=VIL).
The WAIT output will be asserted as soon as a Synchronous Burst operation is initiated and
will be de-asserted to indicate when data are to be transferred to (or from) the memory
array.
The Burst Length is the number of Words to be output or input during a Synchronous Burst
Read or Write operation. It can be configured as 4, 8, or 16 Words or continuous through bit
BCR0 to BCR2 or the Burst Configuration Register.
The Latency defines the number of clock cycles between the beginning of a Burst Read
operation and the first data output (counting from the first Clock edge where L was detected
Low) or between the beginning of a Burst Write operation and the first data input. The
Latency can be set through bits BCR13 to BCR11 of the Bus Configuration Register.
The latency can also be configured to fixed or variable by programming bit BCR14. By
default, the Latency Type is set to variable. Synchronous Read operations are performed in
both fixed and variable latency mode while Synchronous Write operations are only
performed with fixed latency.
See Figure 18, Figure 19, Figure 21, Figure 25, Figure 26, for details on Synchronous Read
and Write AC waveforms, respectively.
Synchronous Operating modes M69KM048AA
18/61
6.3.1 Variable Latency
In Variable Latency mode, the latency programmed in the BCR is not guaranteed and is
maintained only if there is no conflict with a refresh operation. The Latency set in the BCR is
applicable only for an initial burst read access, when no refresh request is pending. For a
given latency value, the Variable Latency mode allows higher operating frequencies than the
Fixed Latency mode (see Table 9: Variable Latency Counter Configuration and Figure 3:
Variable Latency Mode, No Refresh Collision).
Burst Write operations are always performed at fixed latency, even if BCR14 is configured to
Variable Latency (see Section 6.3.2: Fixed Latency).
Monitoring of the WAIT signal is recommended for reliable operation in this mode. See
Figure 19. and Figure 26 for details on Synchronous Burst Read and Write AC waveforms in
Variable Latency mode.
6.3.2 Fixed Latency
The latency programmed in the BCR is the real latency. The number of clock cycles is
calculated by taking into account the time necessary for a refresh operation and the time
necessary for an initial Burst access. This limits the operating frequency for a given latency
value (see Table 10: Fixed Latency Counter Configuration and Figure 4: Fixed Latency
Mode).
It is recommended to use the Fixed Latency mode if the microcontroller cannot monitor the
WAIT signal.
See Figure 18 for details on Synchronous Burst Read AC waveforms in fixed Latency mode.
6.3.3 Row Boundary Crossing
The M69KM048AA features 128-Word rows. Row boundary crossings between adjacent
rows may occur during Burst Read and Write operations. Row boundary crossings are not
handled automatically by the PSRAM.
The microcontroller must stop the Burst operation at the row boundary and restart it at the
beginning of the next row. Burst operations must be stopped by driving the Chip Enable
signal, E, High, after the WAIT signal falling edge. E must transition:
●before the third Clock cycle after the WAIT signal goes Low if BCR[8] = 0,
●before the fourth Clock cycle after WAIT signal goes Low if BCR[8] = 1.
Refer to Figure 21 and Figure 25 for details on how to manage row boundary crossings
during burst operations.
M69KM048AA Synchronous Operating modes
19/61
6.4 Synchronous Burst Read Interrupt
Ongoing Burst Read operations can be interrupted to start a new Burst cycle by either of the
following means:
●Driving E High, VIH, and then Low, VIL on the next clock cycle (recommended). If
necessary, refresh cycles will be added during the new Burst operation to schedule any
outstanding refresh. If Variable Latency mode is set, additional wait cycles will be
added if a refresh operation is scheduled during the Synchronous Burst Read Interrupt.
WAIT monitoring is mandatory for proper system operation.
●Starting a new Synchronous Burst Read operation without toggling E.
An ongoing Burst Read operation can be interrupted only after the first valid data is output.
When a new Burst access starts, I/O signals immediately become high impedance.
6.5 Synchronous Burst Write Interrupt
Ongoing Burst Write operations can be interrupted to start a new Burst cycle by either of the
following means:
●Driving E High, VIH, and then Low, VIL on the next clock cycle (recommended),
●Starting a new Synchronous Burst Write without toggling E. Considering that Burst
Writes are always performed in Fixed Latency mode, refresh is never scheduled. A
maximum Chip Enable, E, low time (tELEH) must be respected for proper device
operation.
An ongoing Burst Write can be interrupted only after the first data is input. When a new
Burst access starts, I/O signals immediately become high impedance.
6.6 Synchronous Burst Read and Write Suspend
Synchronous Burst Read and Write operations can be suspended by halting the Clock K
holding it Low, VIL. The status of the I/O signals will depend on the status of Output enable
input, G. The device internal address counter is suspended and data outputs become high
impedance tGHQZ after the rising edge of the Output Enable signal, G. It is prohibited to
suspend the first data output at the beginning of a Synchronous Burst Read.
See Figure 20 for details on the Synchronous Burst Read and Write Suspend mechanisms.
During Synchronous Burst Read and Synchronous Burst Write Suspend operations, the
WAIT output will be asserted. Bit BCR8 of the Bus Configuration Register is used to
configure when the transition of the WAIT output signal between the asserted and the de-
asserted state occurs with respect to valid data available on the data bus.
Synchronous Operating modes M69KM048AA
20/61
Table 3. Asynchronous Write Operations (NOR-Flash Synchronous Mode)
Asynchronous
Operations Power K E L W G UB,
LB CR A19 A16- A18,
A20
ADQ0-
ADQ15
Word Write(1)
Active (ICC)
VIL
(2)
VIL VIL VIL VIH VIL VIL Address In Valid Address In
/Data In Valid
Program Configuration
Register
(CR Controlled)(3)
VIL VIL VIL XXV
IH
0(RCR)
1(BCR)
RCR/BCR
Data X
Output Disable/No
Operation(1)(4) Idle VIL XXXXX V
IL X
Standby(5)(4) Standby (IPAS R )V
IH XXX XV
IL XHigh-Z
Deep Power-Down(6) Deep Power-
Down (ICCPD)
VIH XXXXX X High-Z
1. The device will consume active power in this mode whenever addresses are changed.
2. K must be held Low during Asynchronous Read And Write operations. It must also be kept Low for the device to consume
Standby current during Standby and Deep Power-Down modes, and during Burst Suspend operations.
3. BCR and RCR only.
4. VIN = 0V or VCCQ; all signals must be stable in order to achieve standby current.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external
influence.
6. The device enters Deep Power-Down mode by driving the Chip Enable signal, E, from Low to High, with bit 4 of the RCR
set to ‘0’. The device remains in Deep Power-Down mode until E goes Low again and is held Low for tELEH(DP).
M69KM048AA Synchronous Operating modes
21/61
)
Table 4. Synchronous Read Operations (NOR-Flash Synchronous mode)
Synchronous
Operations Power K
(1) E L W G LB,
UB
WAIT
(2) CR A19 A16-A18,
A20
ADQ15-
ADQ0
Initial Burst
Read(3)(4)
Active (ICC)
VIL VIL VIH VIH VIL
Low-Z
VIL Address In Valid X
Subsequent Burst
Read(3)(4)(5) VIL VIH XXV
IL VIL X
Address
In/Data Out
Valid
Burst Read
Suspend(3)(4) Active (ICC)XV
IL XXV
IH XXXHigh-Z
Output Disable/No
Operation(4)(6) Idle VIL XXX X V
IL XX
Standby(6)(7) Standby
(IPASR)VIL VIH XXX X
High-Z
VIL XHigh-Z
Deep Power-Down(8)
Deep
Power-
Down
(ICCPD)
VIL VIH XXX X X X High-Z
1. K must be held Low for the device to consume Standby current during Standby and Deep Power-Down modes, and during
Burst Suspend operations.
2. The WAIT polarity is configured through bit 10 (BCR10) of the Bus Configuration Register.
3. The Burst mode is configured through bit 15 (BCR15) of the Bus Configuration Register.
4. The device will consume active power in this mode whenever addresses are changed.
5. Burst Read Interrupt and Suspend are described in dedicated paragraph of the Section 6: Synchronous Operating modes.
6. VIN = 0V or VCCQ; all signals must be stable in order to achieve standby current.
7. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external
influence.
8. The device enters Deep Power-Down mode by driving the Chip Enable signal, E, from Low to High, with bit 4 of the RCR
set to ‘0’. The device remains in Deep Power-Down mode until E goes Low again and is held Low for tELEH(DP).
Synchronous Operating modes M69KM048AA
22/61
Table 5. Full Synchronous Mode
Synchronous
Mode Power K
(1) E L W G LB,
UB
WAIT
(2) CR A19 A16-A18,
A20
ADQ15-
ADQ0
Initial Burst
Read(3)(6)
Active
(ICC)
VIL VIL VIH VIH VIL
Low-Z
VIL Address In Valid X
Subsequent
Burst
Read(3)(4)(6)
VIL VIH XXV
IL XX
Address
In/Data Out
Valid
Initial Burst
Write(3)(6) VIL VIL VIL VIH XV
IL Address In Valid
Address
In/Data In
Valid
Subsequent
Burst Write(3)(6) VIL VIH XV
IH VIL XX
Address
In/Data In
Valid
Burst Read
Suspend(3)(6) XV
IL XXV
IH XXXHigh-Z
Program
Configuration
Register
(CR
Controlled)(3)(5)
VIL VIL VIL VIH XV
IH
0(RCR)
1(BCR)
RCR/BCR
Data X
Output
Disable/No
Operation(6)(8)
Idle VIL VIL XXX X V
IL XX
Standby(7)(8) Standby
(IPASR)VIL VIH XXX X
High-Z
VIL XHigh-Z
Deep Power-
Down(9)
Deep
Power-
Down
(ICCPD)
VIL VIH XXX X X X High-Z
1. K must be held Low for the device to consume Standby current during Standby and Deep Power-Down modes, and during
Burst Suspend operations.
2. The WAIT polarity is configured through bit 10 (BCR10) of the Bus Configuration Register.
3. The Burst mode is configured through bit 15 (BCR15) of the Bus Configuration Register.
4. Burst Read Interrupt, Suspend, Terminate and Burst Write Interrupt, Suspend and Terminate are described in dedicated
paragraph of the Section 6: Synchronous Operating modes.
5. The Configuration Register is output during the initial burst operation (read or write). The following read or write operations
are similar to subsequent burst operations. E must be held Low for the equivalent of a single-word burst operation (as
indicated by the WAIT signal).
6. The device will consume active power in this mode whenever addresses are changed.
7. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external
influence.
8. VIN = 0V or VCCQ; all signals must be stable in order to achieve standby current.
9. The device enters Deep Power-Down mode by driving the Chip Enable signal, E, from Low to High, with bit 4 of the RCR
set to ‘0’. The device remains in Deep Power-Down mode until E goes Low again and is held Low for tELEH(DP).
M69KM048AA Synchronous Operating modes
23/61
Figure 3. Variable Latency Mode, No Refresh Collision
Figure 4. Fixed Latency Mode
1. See Table 20: Synchronous Burst Read AC Characteristics for details on the synchronous read AC Characteristics shown
in the above waveforms.
A16-A20
ADQ0-ADQ15
K
Address
Valid
Q1
Hi Z
012345
Q4
Q3
Q2
Latency = 3 Clock Cycles
AI12176
L
Hi Z Q1Q3
Q2
Q5
Q4
67
Latency = 4 Clock Cycles
ADQ0-ADQ15
Address
Valid
Address
Valid
A16-A20
ADQ0-ADQ15
OUT
K
Address
Valid
Q1
Hi Z
N-1
Cycle
N
Cycle
Q4
Q3
Q2
tAVQV
AI12177
Q5
tLLQV
E
tELQV
tKHQV2
L
Address
Valid
Synchronous Operating modes M69KM048AA
24/61
Figure 5. Refresh Collision during Synchronous Burst Read in Variable Latency Mode
1. Additional Wait states are inserted to allow Refresh completion. The latency is set to 3 clock cycles (BCR13-BCR11 = 010).
The WAIT must be active Low, VIL, (BCR10 = 0) and asserted during delay (BCR8= 0).
A16-A20
WAIT
ADQ0-ADQ15
K
Additional WAIT states inserted
to allow Refresh completion
Address
Valid
AI12178b=
L
E
G
W
Hi Z Hi Z
LB/UB
Q0 Q1 Q2 Q3
Address
Valid
M69KM048AA Configuration Registers
25/61
7 Configuration Registers
The M69KM048AA features two registers:
●The Bus Configuration Register (BCR)
●The Refresh Configuration Register (RCR)
BCR and RCR are user-programmable registers that define the device operating mode.
They are automatically loaded with default settings during Power-Up, and selected by
address bit A19 (see Table 6: Register Selection).
The configuration registers can be programmed using two methods:
●The CR controlled method (or hardware method)
●The software method.
They can only be read by using the software method.
7.1 Programming the Registers using the CR controlled method
BCR and RCR registers can be programmed by issuing a bus write operation, in
asynchronous or synchronous mode (NOR-Flash or Full Synchronous), with Configuration
Register Enable signal, CR, High, VIH. Address bit A19 allows to select between BCR and
RCR (see Table 6: Register Selection).
In synchronous mode, the values placed on address lines ADQ0 to ADQ15 are latched on
the rising edge of L, E, or W, whichever occurs first.
In asynchronous mode, a register is programmed by toggling L signal.
LB and UB are ‘don’t care’. The CR pin has to be driven high prior to any access.
Refer to Table 3 and Ta b l e 5 for a detailed description of Configuration Register Program by
the CR Controlled method and to Figure 16 and Figure 27, showing CR controlled
Configuration Register Program waveforms in asynchronous and synchronous mode.
Table 6. Register Selection
Register Read or Write Operation A19
RCR Read/Write 0
BCR Read/Write 1
Configuration Registers M69KM048AA
26/61
7.2 Reading and programming the registers using the software
method
The BCR and the RCR can be read and programmed by issuing a Read Configuration
Register and Set Configuration Register sequence, respectively (see Figure 7: Read
Configuration Register (software method) and Figure 6: Set Configuration Register
(software method)).
The timings will be identical to those described in Table 17: Asynchronous Read AC
Characteristics and Table 3: Asynchronous Write Operations (NOR-Flash Synchronous
Mode). The Configuration Register Enable input, CR, is ‘don’t care’.
Read Configuration Register and Set Configuration Register sequences both require 4 read
and write cycles. These cycles are performed in asynchronous mode, whatever the device
operating mode:
●2 bus read and one bus write cycles to a unique address location, 1FFFFFh, indicate
that the next operation will read or write to a configuration register. The data written
during the third cycle must be ‘0000h’ to access the RCR, ‘0001h’ to access the BCR,
during the next cycle.
●The fourth cycle reads from or writes to the configuration register.
The timings for programming and reading the registers by the software method are identical
to the asynchronous write and read timings.
The software method should not be used to disable or enable the Deep Power-Down mode
(bit 4 of the Refresh Configuration Register).
M69KM048AA Configuration Registers
27/61
Figure 6. Set Configuration Register (software method)
1. Only the Bus Configuration Register (BCR) and the Refresh Configuration Register (RCR) can be modified.
2. To program the BCR or the RCR on last bus write cycle, ADQ0-ADQ15 must be set to ‘0001h’ and ‘0000h’ respectively.
3. The control signals E, G, W, LB and UB, must be toggled as shown in the above figure.
Figure 7. Read Configuration Register (software method)
1. The highest order address location is not modified during this operation.
2. To read the BCR or the RCR on last bus read cycle, ADQ0-ADQ15 must be set to ‘0001h’ and ‘0000h’, respectively.
3. The control signals E, G, W, LB and UB, must be toggled as shown in the above figure.
1FFFFFh
A16-A20 1FFFFFh
G
W
E
LB, UB
AI12179
1FFFFFh 1FFFFFh 1FFFFFh
ADQ0-ADQ15 CR
Data In
tEHEL2 tEHEL2 tEHEL2
Read cycle Read cycle Write cycle Write cycle
L
1FFFFFh 1FFFFFh (2) 1FFFFFh
1FFFFFh
A16-A20 1FFFFFh
G
W
E
LB, UB
AI12180
1FFFFFh 1FFFFFh 1FFFFFh
ADQ0-ADQ15 CR
Data Out
tEHEL2 tEHEL2 tEHEL2
Read cycle Read cycle Write cycle Read cycle
L
1FFFFFh 1FFFFFh (2) 1FFFFFh
Configuration Registers M69KM048AA
28/61
7.3 Bus Configuration Register
The Bus Configuration Register (BCR) defines how the PSRAM interacts with the system
memory bus. All the device operating modes are configured through the BCR.
Refer to Ta bl e 7 for the description of the Bus Configuration Register Bits.
7.3.1 Operating Mode Bit (BCR15)
The Operating Mode bit allows the Synchronous mode or the Asynchronous mode (default
setting) to be selected. Selecting the Synchronous mode will allow the device to operate
either in NOR Flash mode or in full Synchronous Burst mode.
The device will automatically detect that the NOR Flash mode is being used by monitoring a
rising edge of the Clock signal, K, when L is Low. If this should not be the case, the device
operates in full Synchronous mode.
7.3.2 Latency Type (BCR14)
The Latency Type bit is used to configure the latency type. When the Latency Type bit is set
to ‘0’, the device operates in variable latency mode (only available for Synchronous Read
mode). When it is ‘1’, the fixed latency mode is selected and the latency is defined by the
values of bits BCR13 to BCR11.
Refer to Figure 3 and Figure 4 for examples of fixed and variable latency configuration.
7.3.3 Latency Counter Bits (BCR13-BCR11)
The Latency Counter bits are used to set the number of clock cycles between the beginning
of a synchronous read or write operation and the first data output or input.
The Latency Counter bits can only assume the values shown in Table 7: Bus Configuration
Register Definition (see also Figure 3 and Figure 4).
7.3.4 WAIT Polarity Bit (BCR10)
The WAIT Polarity bit indicates whether the WAIT output signal is active High or Low. As a
consequence, it also determines whether the WAIT signal requires a pull-up or pull-down
resistor to maintain the de-asserted state (see Figure 9: WAIT Polarity).
By default, the WAIT output signal is active High.
M69KM048AA Configuration Registers
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7.3.5 WAIT Configuration Bit (BCR8)
The system memory microcontroller uses the WAIT signal to control data transfer during
Synchronous Burst Read and Write operations.
The WAIT Configuration bit is used to determine when the transition of the WAIT output
signal between the asserted and the de-asserted state occurs with respect to valid data
available on the data bus.
When the Wait Configuration bit is set to ‘0’, data is valid or invalid on the first Clock rising
edge immediately after the WAIT signal transition to the de-asserted or asserted state.
When the Wait Configuration bit is set to ‘1’ (default settings), the WAIT signal transition
occurs one clock cycle prior to the data bus going valid or invalid.
See Figure 8: WAIT Configuration Example for an example of WAIT configuration.
7.3.6 Driver Strength Bits (BCR5)
The Driver Strength bits allow to set the output drive strength to adjust to different data bus
loading. Full driver strength and reduced driver strength (a quarter of drive) are available.
By default, outputs are configured to ‘full driver” strength.
7.3.7 Burst Wrap Bit (BCR3)
Burst Read operations can be confined inside the 4, 8, or 16 boundary (wrap mode). If the
wrap mode is not enabled, the device outputs data sequentially up to the end of the row,
regardless of burst boundaries.
The Burst Wrap bit is used to select between ‘wrap’ and ‘no wrap’ mode.
7.3.8 Burst Length Bits (BCR2-BCR0)
The Burst Length bits set the number of Words to be output or input during a Synchronous
Burst Read or Write operation. They can be set for 4 Words, 8 Words, 16 Words or
Continuous Burst (default settings), where all the Words are output or input sequentially
regardless of address boundaries (see also Table 8: Burst Type Definition).
Configuration Registers M69KM048AA
30/61
Table 7. Bus Configuration Register Definition(1)
Address
Bits
Bus
Configuration
Register Bits
Name Value Description
ADQ15 BCR15 Operating Mode
Bit
0Synchronous Mode (NOR Flash or Full
Synchronous Mode)
1 Asynchronous Mode (Default)
ADQ14 BCR14 Latency Type 0 Variable Latency (Default)
1 Fixed Latency
ADQ13-
ADQ11
BCR13-
BCR11
Latency Counter
Bits
010 3 Clock Cycles
011 4 Clock Cycles (Default)
Other Configurations Reserved(2)
ADQ10 BCR10 WAIT Polarity Bit
0 WAIT Active Low
1WAIT Active High (default).See Figure 9:
WAIT Polarity.
ADQ9 - - Must be set to ‘0’ Reserved(2)
ADQ8 BCR8 Wait
Configuration Bit
0WAIT Asserted During Delay (see Figure 8:
WAIT Configuration Example).
1WAIT Asserted One Clock Cycle Before Delay
(Default)
ADQ7-
ADQ6 - - Must be set to ‘0’ Reserved(2)
ADQ5 BCR5 Driver Strength
Bits
0 Full Drive (default)
11/4 Drive
ADQ4 - - Must be set to ‘0’ Reserved(2)
ADQ3 BCR3 Burst Wrap Bit 0 Wrap (within the Burst Length)
1 No Wrap (default)
ADQ2-
ADQ0 BCR2-BCR0 Burst Length Bit
001 4 Words
010 8 Words
011 16 Words
111 Continuous Burst (default)
Other Configurations Reserved(2)
1. Address bits A16 to A18 and A20 are reserved and must be set to ‘0’.
2. Programming the BCR with reserved value will force the device to use the default register settings.
M69KM048AA Configuration Registers
31/61
Table 8. Burst Type Definition
Mode
Start
Add
4 Words
(Sequential)
BCR2-BCR0 =
001b
8 Words (Sequential)
BCR2-BCR0=010b
16 Words (Sequential)
BCR2-BCR0=011b
Continuous Burst
BCR2-BCR0=111b
Wrap (BCR3=’0’)
0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-...-14-15 0-1-2-3-..-511-.
1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-...-14-15-0 1-2-3-4-...-510-511-
2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-...-15-0-1 2-3-4-5-6-...-511-
3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-...-15-0-1-2 3-4-5-...-511-
4 4-5-6-7-0-1-2-3 4-5-...-15-0-1-2-3 4-5-...-511-
5 5-6-7-0-1-2-3-4 5-6-7-...-15-0-1-...-4 5-6-7-...-511-
6 6-7-0-1-2-3-4-5 6-7-8-...-15-0-1-...-5 6-7-8-...-511-
7 7-0-1-2-3-4-5-6 7-8-9-...15-0-1-...-6 7-8-9-...-511-
... ... ... ... ...
14 14-15-0-1-2-...-13 14-...511-
15 15-0-1-2-...-14 15-...511-
... ... ... ... ...
30 30-...-511-
31 31-...-511-
No Wrap (BCR3=’1’)
0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-...-14-15 0-1-2-3-..-511-.
1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-..-15-16 1-2-3-4-...-512-
2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-...-17 2-3-4-5-...-513-
3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-...-18 3-4-5-...-514-
4 4-5-6-7-8-9-10-11 4-5-6-...-19 4-5-6-...-515-
5 5-6-7-8-9-10-11-12 5-6-7-...-20 5-6-7-...-516-
6 6-7-8-9-10-11-12-13 6-7-8-...-21 6-7-8-...-517-
7 7-8-9-10-11-12-13-14 7-8-9-...-22 7-8-9-...-518-
... ... ...
14 14-15-...-29 14-...-525-
15 15-16-17-...-30 15-...-526-
... ... ...
30 30-...-541-
31 31-...-542-
Configuration Registers M69KM048AA
32/61
Figure 8. WAIT Configuration Example
Table 9. Variable Latency Counter Configuration
BCR13- BCR11 Latency Configuration
Code
Latency Maximum Clock
Rate in Burst Mode
Normal Refresh
Collision 83MHz
010 2 (3 clocks cycles) 2 4 53 (18.75ns)
011 3 (4 clocks cycles) - default 3 6 83 (12ns)
Others Reserved - - -
Table 10. Fixed Latency Counter Configuration
BCR13- BCR11 Latency Configuration Code Latency
Max Input Clock
Frequency
83MHz
010 2 (3 clocks cycles) 2 33 (30ns)
011 3 (4 clocks cycles)-default 3 52 (19.2ns)
Others Reserved - -
AI06795b
DQ0-DQ15
BCR8='0', BCR10='1'
Data Valid During Current Cycle
K
WAIT
Data[0] Data[1]
Hi-Z
Data[0]
Hi-Z
DQ0-DQ15
BCR8='1', BCR10='1'
Data Valid During Next Cycle
M69KM048AA Configuration Registers
33/61
Figure 9. WAIT Polarity
AI09963
DQ0-DQ15
K
BCR8='0'
BCR10='1'
Data[0] Data[1]
Hi-Z
DQ0-DQ15 Data[0] Data[1]
Hi-Z
WAIT
WAIT
BCR8='0'
BCR10='0'
Configuration Registers M69KM048AA
34/61
7.4 Refresh Configuration Register
The role of the Refresh Configuration Register (RCR) is:
●to define how the self refresh of the PSRAM array is performed
●to select the Deep Power-Down mode
Refer to Ta bl e 1 1 for the description of the Refresh Configuration Register Bits.
7.4.1 Deep Power-Down Bit (RCR4)
The Deep Power-Down bit enables or disables all refresh-related operations. Deep Power-
Down mode is enabled when the RCR4 bit is set to ‘0’, and remains enabled until this bit is
set to ‘1’. When E goes high, the device enters Deep-Power Down mode and remains in this
mode until the E mean time goes low and stays low for at least 10µs. At power-up, the Deep
Power-Down mode is disabled.
See the Section 4.2: Deep Power-Down for more details.
7.4.2 Partial Array Refresh Bits (RCR2-RCR0)
The Partial Array Refresh bits allow refresh operations to be restricted to a portion of the
total PSRAM array. The refresh options can be full array, one half, one quarter, one eighth or
none of the array. These memory areas can be located either at the top or bottom of the
memory array. By default, the full memory array is refreshed.
Table 11. Refresh Configuration Register Definition(1)
Address
Bits
Refresh
Configuration
Register Bits
Name Value Description
ADQ15-
ADQ5 - - Must be set to ‘0’ Reserved
ADQ4 RCR4(2) Deep Power-
Down Bit
0 Deep Power-Down Enabled
1 Deep Power-Down Disabled (Default)
ADQ3 - - Must be set to ‘0’ Reserved
ADQ2-
ADQ0 RCR2-RCR0 Partial Array
Refresh Bits
000 Full Array Refresh (Default)
001 Refresh of the bottom half of the array
010 Refresh of the bottom quarter of the array
011 Refresh of the bottom eighth of the array
100 None of the array
101 Refresh of the top half of the array
110 Refresh of the top quarter of the array
111 Refresh of the top eighth of the array
1. Address bits A16 to A18 and A20 are reserved and must be set to ‘0’.
2. The software method should not be used to program this bit.
M69KM048AA Configuration Registers
35/61
Table 12. Address patterns for Partial Array Refresh(1)
RCR2 RCR1 RCR0 Refreshed Area Address Space
Size of
Refreshed
Area
Density
0 0 0 Full array (Default) 000000h-1FFFFFh 2Mbx16 32Mb
0 0 1 Bottom half of the array 000000h-0FFFFFh 1Mbx16 16Mb
0 1 0 Bottom quarter of the array 000000h-07FFFFh 512Kbx16 8Mb
0 1 1 Bottom eight of the array 000000h-03FFFFh 256Kbx16 4Mb
1 0 0 None of the array 0 0Mb 0Mb
1 0 1 Top half of the array 100000h-1FFFFFh 1Mbx16 16Mb
1 1 0 Top quarter of the array 180000h-1FFFFFh 526Kbx16 8Mb
1 1 1 Top eight of the array 1C0000h-1FFFFFh 256Kbx16 4Mb
1. RCR4 is set to ‘1’.
Maximum Rating M69KM048AA
36/61
8 Maximum Rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
Operating sections of this specification is not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 13. Absolute Maximum Ratings
Symbol Parameter Min Max Unit
TAAmbient Operating Temperature –30 +85 °C
TSTG Storage Temperature –55 150 °C
VCC Core Supply Voltage –0.2 2.45 V
VCCQ Input/Output Buffer Supply Voltage –0.2 2.45 V
VIO Input or Output Voltage –0.5 VCCQ+ 0.3 V
M69KM048AA DC and AC parameters
37/61
9 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 14: Operating and AC Measurement Conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Figure 10. AC Measurement I/O Waveform
1. Logic states ‘1’ and ‘0’ correspond to AC test inputs driven at VCCQ and VSS respectively. Input timings
begin at VCCQ/2 and output timings end at VCCQ/2.
Figure 11. AC Input Transitions
Table 14. Operating and AC Measurement Conditions
Parameter(1)
1. All voltages are referenced to VSS.
M69KM048AA
Unit
Min Max
VCC Supply Voltage 1.7 1.95 V
VCCQ Input/Output Buffer Supply Voltage 1.7 1.95 V
Load Capacitance (CL)30pF
Output Circuit Protection Resistance (R) 50 Ω
Input Pulse Voltages(2)(3)
2. Referenced to VSS.
3. VCC=VCCQ
0V
CC V
Input and Output Timing Ref. Voltages(2)(3) VCC/2 V
Input Rise Time tr and Fall Time tf(2)(3) 1V/ns
AI09484c
VCCQ
I/O Timing Reference Voltage
VSSQ
VCCQ/2
90%
10%
90%
10%
V
CC
Typ
V
SS
t
r
t
f
ai10122
DC and AC parameters M69KM048AA
38/61
Figure 12. AC Measurement Load Circuit
Table 15. Capacitance
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance TA = 25°C, f =
1MHz, VIN = 0V
26.5pF
CIO Data Input/Output Capacitance 3 6.5 pF
AI11289
VCCQ/2
OUT
DEVICE
UNDER
TEST
CL
R
M69KM048AA DC and AC parameters
39/61
Table 16. DC Characteristics
Symbol Parameter Refreshed
Array Test Conditions Min. Typ Max. Unit
VOH(1) Output High Voltage IOH = –0.2mA 0.8VCCQ V
VOL(1) Output Low Voltage IOL = 0.2mA 0.2VCCQ V
VIH(2) Input High Voltage 1.4 VCCQ + 0.2 V
VIL(3) Input Low Voltage –0.2 0.4 V
ILI Input Leakage Current VIN = 0 to VCCQ 1µA
ILO Output Leakage Current G = VIH or E = VIH 1µA
ICC1(4) Asynchronous Read/Write Random
at tRC min
VIN = 0V or VCCQ,
IOUT = 0mA, E = VIL
25 mA
ICC2(4) Burst, Initial Read/Write Access VIN = 0V or VCCQ
IOUT = 0mA, E = VIL
40 mA
ICC3R(4) Continuous Burst Read VIN = 0V or VCCQ
IOUT = 0mA, E = VIL
35 mA
ICC3W(4) Continuous Burst Write VIN = 0V or VCCQ
IOUT = 0mA, E = VIL
35 mA
IPASR(4) Partial Array Refresh
Standby Current
Full Array
VIN = 0V or VCCQ
E = VCCQ
110 µA
1/2 Array 105 µA
1/4 Array 95 µA
1/8 Array 95 µA
None 70 µA
ISB(5) Standby Current VIN = 0V or VCCQ
E = VCCQ
110 µA
ICCPD Deep-Power Down Current
VIN = 0V or VCCQ,
VCC, VCCQ = 1.95V; TA=
+85°C
10 70 µA
1. BCR5-BCR4 = 01 (default settings).
2. Input signals may overshoot to VCCQ+ 1.0V for periods of less than 2ns during transitions.
3. Output signals may undershoot to VSS – 1.0V for periods of less than 2ns during transitions.
4. This parameter is specified with all outputs disabled to avoid external loading effects. The user must add the current
required to drive output capacitance expected for the actual system.
5. ISB maximum value is measured at +85°C with PAR set to Full Array. In order to achieve low standby current, all inputs
must be driven either to VCCQ or VSSQ. ISB might be slightly higher for up to 500ms after Power-up, or when entering
Standby mode.
DC and AC parameters M69KM048AA
40/61
Table 17. Asynchronous Read AC Characteristics(1)
Symbol Alt. Parameter Min Max Unit
tAVQV tAA Address Valid to Output Valid 70 ns
tAVAX tRC Read Cycle Time 70 ns
tAVLH
tRHLH
tAVS
Address Valid to L High
Configuration Register High to L High 10 ns
tBLQV tBA Upper/Lower Byte Enable Low to Output Valid 70 ns
tBHQZ(2) tBHZ Upper/Lower Byte Enable High to Output Hi-Z 8 ns
tBLQX(3) tBLZ Upper/Lower Byte Enable Low to Output transition 10 ns
tELTV tCEW Chip Enable Low to WAIT Valid 1 7.5 ns
tELQV tCO Chip Enable Low to Output Valid 70 ns
tELLH tCVS Chip Enable Low to L High 10 ns
tEHQZ(2) tHZ
Output Enable High to Output Hi-Z
Chip Enable High to Output Hi-Z 8ns
tELQX(3) tLZ Chip Enable Low to Output transition 10 ns
tGLQV tOE Output Enable Low to Output Valid 20 ns
tGHQZ(2) tOHZ Output Enable Low to Output Hi-Z 8 ns
tGLQX(3) tOLZ Output Enable Low to Output transition 3 ns
tLLQV tAADV Latch Enable Low to Output Valid 70 ns
tLHAX
tLHRL
tAVH
Latch Enable High to Address transition
Latch Enable High to Configuration Register Low 2ns
tLLQZ tAHZ Latch Enable Low to Output Hi-Z 7 ns
tLHQX tALZ Latch Enable High to Output transition 15 ns
tLLLH tVP Latch Enable Low Pulse Width 5 ns
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement
Conditions and Figure 12: AC Measurement Load Circuit.
2. The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2.
3. The transition timings measure a 100mV transition from the Hi-Z (VCCQ/2) level to either VOH or VOL.
M69KM048AA DC and AC parameters
41/61
Figure 13. Asynchronous Random Read AC waveforms
AI12181b
A16-A20
WAIT
VALID ADDRESS
tEHQZ
tBLQV
Hi-Z
tAVAX
tELQV
tLLQV tBHQZ
tGHQZ
tGLQV
tELTV
VALID
OUTPUT
tELQX
tGLQX
E
LB/UB
G
W
ADQ0-ADQ15
tAVQV
Hi-Z
tBLQX
L
VALID ADDRESS
tAVLH tLHAX
tLLLH
tELLH tEHTZ
tLHQX
tLLQZ
DC and AC parameters M69KM048AA
42/61
Table 18. Asynchronous Write AC Characteristics(1)
Symbol Alt. Parameter Min Max Unit
tAVBL, tAVEL
tAVWL, tLLWL
tAS Address Set-up to Beginning of Write Operation 0 ns
tAVLH, tRHLH tAVS
Address Valid to Latch Enable High
Configuration Register High to Latch Enable High 10 ns
tAVWH, tAVEH
tAVBH
tAW Address Set-up to End of Write Operation 70 ns
tAVAX tWC Write Cycle Time 70 ns
tBLBH, tBLEH
tBLWH
tBW Upper/Lower Byte Enable Low to End of Write Operation 70 ns
tELTV tCEW Chip Enable Low to WAIT Valid 1 7.5 ns
tEHEL tCBPH Chip Enable High between Subsequent Asynchronous Operations 6 ns
tELLH tCVS Chip Enable Low to L High 10 ns
tELWH, tELEH
tELBH
tCW Chip Enable Low to End of Write Operation 70 ns
tEHDX
tWHDX
tBHDX
tDH Input Hold from Write 0 ns
tELWH, tDVBH
tDVEH, tDVWH
tDW Input Valid to Write Setup Time 20 ns
tEHTZ, tBHTZ,
tWHTZ(2) tHZ
Chip Enable High to WAIT Hi-Z
LB/UB High to WAIT Hi-Z
Write Enable High to WAIT Hi-Z
8ns
tLLWH, tLLEH,
tLLBH
tVS Latch Enable Low to Write Enable High 70 ns
tLHAX, tLHRL tAVH
Latch Enable High to Address Transition or
Latch Enable High to Configuration Register Low 2ns
tLLLH tVP Latch Enable Low Pulse Width 5 ns
tWLBH, tWLEH
tWLWH(3) tWP Write Pulse Width 45 ns
tWHWL tWPH Write Enable Pulse Width High 10 ns
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement
Conditions and Figure 12: AC Measurement Load Circuit.
2. The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2.
3. W Low time must be limited to tEHEL.
M69KM048AA DC and AC parameters
43/61
Figure 14. Asynchronous Write AC waveforms
1. Data Inputs are Hi-Z if E is High, VIH.
2. When E is Low, VIL (device selected), W must not remain Low, for longer than tEHEL.
3. The end of the Write operation is controlled by E, LB, UB, or W, whichever is de-asserted first.
ADQ0-ADQ15
VALID ADDRESS
Hi-Z Hi-Z
tAVAX
tELTV
VALID INPUT
tAVEH, tAVBH, tAVWH
tELWH, tELEH, tELBH
tDVEH
tBLWH, tBLEH, tBLWH
Hi-Z
tEHDX
tWLWH, tWLBH, tWLEH(2)
AI12182b
A16-A20
WAIT
LB/UB
W
L
tAVWL
tEHTZ, tBHTZ, tWHTZ
VALID ADDRESS
E
tAVLH tLHAX
tLLWH, tLLEH, tLLBH
tLLLH
tLLWL
DC and AC parameters M69KM048AA
44/61
Figure 15. Asynchronous Write followed by Read AC waveforms
1. When configured to operate in Synchronous mode (BCR[15] = 0), E must remain High, VIH, for at least tEHEL to schedule
the appropriate refresh interval. Otherwise, tELEH is only required after E controlled write operations.
ADQ0-
ADQ15
VALID ADDRESS
Hi-Z
tAVAX
VALID INPUT
tAVWH
tELWH
tDVWH
tBLWH
Hi-Z
tWHDX
tWLWH
AI12183b
A16-A20
WAIT
LB/UB
W
L
tAVWL
VALID ADDRESS
E
tAVLH tLHAX
tLLWH
VALID
ADDRESS
VALID
ADDRESS
VALID
OUTPUT
G
tAVLH tLHAX
tAVQV
tELLH
tEHEL(1) tEHQZ
tBHQZ
tBHQZ
tELQX
tBLQX
tGLQX
tGLQV
tLLLH
tLLQZ
tLHQX
M69KM048AA DC and AC parameters
45/61
Figure 16. CR Controlled Configuration Register Program, Asynchronous Mode
1. Only the content of the Bus Configuration Register (BCR) and Refresh Configuration Register (RCR) can be modified.
2. The Opcode is the value to be written the configuration register.
3. CR is latched on the rising edge of L. There is no setup requirement of CR with respect to E.
AI12184
A16 - A18,
A20 OPCODE(2)
L
E
G
W
A19 0(RCR), 1(BCR)
tWLWH
CR
Write Add. Value
to Configuration Register
tRHLH tLHRL
LB, UB
First access to Configuration Register
tLHAXtAVLH
Data
Valid
ADDRESS
Data
Valid
ADDRESS
tEHEL
tELWH
DC and AC parameters M69KM048AA
46/61
Table 19. Clock Related AC Timings
Symbol Alt. Parameter
M69KM048AA
Unit
Min Max
fCLK fCLK Clock frequency 83 MHz
tKHKH tCLK Clock Period 12 ns
tKHKL, tKLKH tKP Clock High to Clock Low, Clock Low to Clock High 4 ns
tR, tFtKHKL Clock Rise Time, Clock Fall Time 1.8 ns
Table 20. Synchronous Burst Read AC Characteristics(1)
Symbol Alt. Parameter
M69KM048AA
Unit
Min Max
tAVQV tAA Address Valid to Output valid (Fixed Latency) 70 ns
tAVKH, tRHKH
tQVKH, tLLKH
tBLKH, tWHKH
tSP Set-up Time to Active Clock Edge 3 ns
tEHEL(2) tCBPH
Chip Enable High between Subsequent Operations in Full-
Synchronous or NOR-Flash mode. 6ns
tELEH(2) tCEM Chip Enable Pulse Width 8 µs
tELTV
, tLLTV tCEW
Chip Enable Low to WAIT Valid
Latch Enable Low to WAIT Valid 17.5ns
tELQV tCO Chip Enable Low to Output Valid 70 ns
tELKH tCSP Chip Enable Low to Clock High 4.5 ns
tEHQZ, tEHTZ(3) tHZ Chip Enable High to Output Hi-Z or WAIT Hi-Z 8 ns
tGLQV tBOE Output Enable Low to Output Valid in Burst mode 20 ns
tGHQZ(3) tOHZ Output Enable High to Output Hi-Z 8 ns
tGLQX(4) tOLZ Output Enable Low to output transition 3 ns
tGHQV tOHZS Output Enable high to address valid 8 ns
tKHQV1 tABA Burst to Read Access Time (Variable Latency) 46 ns
tKHQV2 tACLK Clock High to Output Delay 9 ns
tKHAX, tKHBH,
tKHWL, tKHEH,
tKHLH, tKHQX
tHD Hold Time From Active Clock Edge 2 ns
tLLQV tAADV Latch Enable Low to Output Valid (Fixed Latency) 70 ns
tKHTX, tKHTV tKHTL Clock High to WAIT Valid 9 ns
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement
Conditions and Figure 12: AC Measurement Load Circuit.
2. A refresh opportunity must be offered every tELEH. A refresh opportunity is possible either if E is High during the rising edge
of K; or if E is High for longer than 15ns.
3. The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2.
4. The transition timings measure a 100mV transition from the Hi-Z (VCCQ/2) level to either VOH or VOL.
M69KM048AA DC and AC parameters
47/61
Figure 17. Clock input AC Waveform
Figure 18. Single Synchronous Burst Read AC waveforms (Fixed Latency mode)
1. The latency Type (BCR14) is set to fixed (BCR14 = 1). The Latency is set to 3 clock cycles (BCR13-BCR11 = 010), and
The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
AI06981
tKHKH
tf tr
tKHKL
tKLKH
A16-A19
WAIT
ADQ0-ADQ15
K
E
G
W
LB/UB
L
ADDRESS
VALID
ADDRESS
VALID
OUTPUT
VALID
AI12721
tKHKH tKHKL
tAVKH
tF
tLLKH
tKHLH
tKHEH
tEHQZ
tELKH
tELEH
tGHQV tGLQV tGHQZ
tWHKH tKHWL tGLQX
tKHTX
tELTV
tKHQX
tKHQV2
tAVKH
Hi-Z
tKHAX
tKHQV1
tBLKH tKHBH
tKHAX
DC and AC parameters M69KM048AA
48/61
Figure 19. 4-Word Synchronous Burst Read AC waveforms (Variable Latency mode)
1. The latency Type (BCR14) is set to variable (BCR14 = 0). The Latency is set to 3 clock cycles (BCR13-BCR11 = 010). The
WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
A16-A20
WAIT
ADQ0-ADQ15
K
tAVKH
tKHKH
tKHAX
tKHQV1
VALID
ADDRESS
tKHQX
tEHQZ
tKHEH
tLLKH
tGLQX
tEHEL
tELKH
tWHKH tKHWL
tGHQZ
tKHKL
READ Burst Identified
tKHTX
Hi-Z
Hi-Z
Hi-Z
tGLQV
AI12185b
E
G
W
LB/UB
(W = High)
tELTV
tKHQV2
L
tKHLH
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tELEH
VALID
ADDRESS
tGHQV
M69KM048AA DC and AC parameters
49/61
Figure 20. Synchronous Burst Read Suspend and Resume AC waveforms
1. The latency Type (BCR14) can be set to fixed or variable during Burst Read Suspend operations.The Latency is set to 3
clock cycles (BCR13-BCR11 = 010). The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
2. During Burst Read Suspend operations, the Clock signal must be stopped (Low).
3. G can be held Low, VIL, during Burst Suspend operations. If so, data output remain valid.
DON'T CARE
DON'T CARE
A16-A20
WAIT
ADQ0-ADQ15
K
tAVKH tKHAX
tKHQX
tEHQZ
tLLKH
tGLQX
tEHELtELKH
tWHKH tKHWL
tBLKH
tGHQZ
tAVLH
tKHKL
Hi-Z
Valid
Output
Hi-Z
Hi-Z
AI12186b
E
G
W
LB/UB
tKHQV1
L
Valid
Output
Valid
Address Valid
Address
tGLQV
tGHQZ
Valid
Output Valid
Output Valid
Output Valid
Output
tKHLH
tGLQV
tKHTX
Valid
Address
tGHQV
DC and AC parameters M69KM048AA
50/61
Figure 21. Burst Read Showing End-of-Row Condition AC waveforms (No Wrap)
1. The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
2. The Chip Enable signal, E, must go High before the third Clock cycle after the WAIT signal goes Low. If BCR8 were set to
1, E would have to go Low before the fourth Clock cycle after WAIT signal goes Low.
A16-A20
ADQ0-ADQ15
K
tKHTV
tKHKH
tKLKH, tKHKL
tF
WAIT
AI12187b
E
G
LB/UB
W
DON'T CARE
DON'T CARE
tEHTZ
L
VALID
OUTPUT VALID
OUTPUT
Low
Low
High
Note 2
tEHTZ
High-Z
End of Row
M69KM048AA DC and AC parameters
51/61
Figure 22. Asynchronous Write followed by Burst Read AC waveforms
1. The latency Type (BCR14) can be set to fixed or variable.The Latency is set to 3 clock cycles (BCR13-BCR11 = 010). The
WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
2. When transitioning from an asynchronous Write operation to a synchronous Read operation in variable latency mode, E
must go High, VIH. When transitioning to a synchronous Read operation in fixed latency mode, E can stay Low, VIL. A
refresh opportunity must be provided every tELEH. A refresh opportunity is possible either if E is High during the rising edge
of K; or if E is High for longer than 15ns.
A19-A16
WAIT
ADQ0-ADQ15
K
tAVKH
tKHKH
tKHAX
VALID
ADDRESS
tLLKH
tWHKH tKHWX
tGLQV
Hi-Z
E
G
W
LB/UB
tELTV
L
tKHLH
tAVWL
VALID
ADDRESS
tLHAX
tAVLH
tAVWH
tLLLH, tELLH
tBLWH
tEHEL(2)
tWLWH
tWHWL
VALID
ADDRESS
VALID
ADDRESS VALID DATA VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tKHQV2
tWHDX
tDVWH
tELWH tELKH
tGHQZ
ai12722
tBLKH
tKHBH
DC and AC parameters M69KM048AA
52/61
Figure 23. Burst Read followed by Asynchronous Write AC waveforms
1. The latency Type (BCR14) can be set to fixed or variable.The Latency is set to 3 clock cycles (BCR13-BCR11 = 010). The
WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
2. When transitioning from a synchronous Read operation in variable latency mode to an asynchronous Write operation, E
must go High, VIH. When transitioning from a synchronous Read operation in fixed latency mode, E can stay Low, VIL.
Asynchronous operations begin at the falling edge of L. A refresh opportunity must be offered every tELEH. A refresh
opportunity is possible either if E is High during the rising edge of K; or if E is High for longer than 15ns.
A19-A16
ADQ0-ADQ15
K
ADDRESS
VALID
AI12723
L
E
G
WAIT Hi Z
LB/UB
VALID OUTPUT
Hi-Z
Burst Read Identified
tKHKH
tAVKH
tKHAX
tLLKH
tELKH tKHEH tEHQZ
tGLQV
tGHQZ
W
tWHKH tKHWX tGLQX
tBLKH tKHBX
tELTV tKHTV
tKHQV2
(W = High)
tKHLH
VALID ADDRESS
Hi-Z
tELTV
VALID INPUT
tAVLH tLHAX
tELEH, tELWH
tDVEH
tBLBH
tEHDX
tWLWH
tAVWL
tLLLH
tLLWH
tELWL
tEHEL(2)
tWHWL
tWHTZ
tGHQZ
VALID
ADDRESS VALID
ADDRESS
tAVEH
tQVKH tKHQX tAVLH tLHAX
tKHBH
M69KM048AA DC and AC parameters
53/61
Table 21. Synchronous Burst Write AC Characteristics(1)
Symbol Alt. Parameter
M69KM048AA
Unit
Min Max
tAVWL
tLLWL(2) tAS Address Set-up to Beginning of Write Operation 0 ns
tAVKH
tDVKH
tWLKH
tLLKH
tBLKH
tWHKH
tWHWL
tSP Set-up Time to Active Clock Edge 3 ns
tLHAX tAVH Latch Enable High to Address Transition (Fixed Latency) 2 ns
tEHEL(3) tCBPH
Chip Enable High between Subsequent Operations in Full-
Synchronous or NOR-Flash mode. 6ns
tELEH(3) tCEM Maximum Chip Enable Low Pulse 8 µs
tELTV
tLLTV
tCEW Chip Enable Low to WAIT Valid 1 7.5 ns
tELKH tCSP Chip Enable Low to Clock High 4.5 ns
tEHDZ
tEHTZ(4) tHZ Chip Enable High to Input Hi-Z or WAIT Hi-Z 8 ns
tKHAX
tKHRL
tKHLH
tKHDX
tKHEH
tKHBH
tKHWH
tHD Hold Time From Active Clock Edge 2 ns
tKHLL tKADV Last Clock Rising Edge to Latch Enable Low (Fixed Latency) 6 ns
tKHTV
tKHTX
tKHTL Clock High to WAIT Valid or Low 9 ns
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement
Conditions and Figure 12: AC Measurement Load Circuit.
2. tAVWL and tLLWL, are required if tELKH> 20ns.
3. A refresh opportunity must be offered every tELEH. A refresh opportunity is possible either if E is High during the rising edge
of K; or if E is High for longer than 15ns.
4. The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2.
DC and AC parameters M69KM048AA
54/61
Figure 24. 4-Word Synchronous Burst Write AC waveforms (Fixed Latency mode)
1. The Latency type is set to fixed (BCR14 = 1).The Latency is set to 3 clock cycles (BCR13-BCR11 = 010). The WAIT signal
is active Low (BCR10=0), and asserted during delay (BCR8=0).
2. The WAIT signal must remain asserted for LC clock cycles (LC Latency code), whatever the Latency mode (fixed or
variable).
3. tAVLL and tLLWL, are required if tELKH> 20ns.
A16-A20
WAIT
ADQ0-ADQ15
K
tKHKH
VALID
ADDRESS
tKHDX
tELKH
tWLKH tKHWH
tAVKH
WRITE Burst Identified
tKHTX
Hi-Z
VALID
INPUT
Hi-Z
Hi-Z
ai12188
E
G
W
(W = Low)
tKHEH
tEHEL
tBLKH tKHBH
LB/UB
tELTV
tDVKH
L
VALID
INPUT
VALID
INPUT
VALID
INPUT
tELEH
tKHAX
tAVWL
tLLWL
tLLKH tKHLH
tKHLL
High
tEHTZ
Note 2
VALID
ADDRESS
M69KM048AA DC and AC parameters
55/61
Figure 25. Burst Write Showing End-of-Row Condition AC waveforms (No Wrap)
1. The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
2. The Chip Enable signal, E, must go High before the third Clock cycle after the WAIT signal goes Low. If BCR8 were set to
1, E would have to go Low before the fourth Clock cycle after WAIT signal goes Low.
DON'T CARE
A16-A20
ADQ0-ADQ15
K
tKHKH
tKLKH
tF
WAIT
ai12189
E
G
LB/UB
WDON'T CARE
L
tKHDX
tDVKH
VALID
INPUT D[n]
VALID
INPUT D[n+1]
End of Row
(A6-A0 = 7Fh)
Note 2
High
tKHTV tEHTZ
tEHTZ
High-Z
DC and AC parameters M69KM048AA
56/61
Figure 26. Synchronous Burst Write Followed by Read AC waveforms
1. The Latency type can set to fixed or variable mode. The Latency is set to 3 clock cycles (BCR13-BCR11 = 010). The WAIT
signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
2. E can remain Low between the Burst Read and Burst Write operation, but it must not be held Low for longer than tELEH.
A16-A20
WAIT
ADQ0-
ADQ15
K
tKHAX
ai12190b
E
G
W
L
tKHKH
DIN0 DIN1 DIN2 DIN3
UB, LB
tKLKH
tKHKL
tAVKH
tKHLH
tLLKH
tELKH
tWLKH
tKHWH
tDVKH
tKHLL
tEHEL
tGHQZtGLQX
tKHQX
DO0 DO1 DO2 DO3
tKHDX
tKHAX
tAVKH
(2)
tKHEH
tELKH
tKHLH
tKHEH
tKHTX tKHTX
tWHKH tKHWL
VALID
ADD.
VALID
ADD.
VALID
ADD.
tBLKH tKHBH
M69KM048AA DC and AC parameters
57/61
Figure 27. CR Controlled Configuration Register Program, Synchronous Mode
1. Only the Configuration Register (BCR) and the Refresh Configuration Register (RCR) can be modified.
2. Data Inputs/Outputs are not used.
3. The Opcode is the value to be written in the Configuration Register.
4. A19 gives the Configuration Register address.
5. CR initiates the Configuration Register Access.
A16-A18,
A20(3)
K
tELEH
Hi-Z
AI12191
L
E
W
CR
(5)
Opcode
A19(4)
0 (RCR)
1 (BCR)
G
UB, LB
ADQ0-ADQ15
(2)
WAIT
tAVKH
tKHRL
tRHKH
tLLKH tKHLH
tKHAX
tWLKH tKHWH
tELTV
DC and AC parameters M69KM048AA
58/61
Figure 28. Power-Up AC waveforms
1. Power must be applied to VCC prior to or at the same time as VCCQ.
Figure 29. Deep Power-Down Entry and Exit AC waveforms
Table 22. Power-Up and Deep Power-Down AC Characteristics
Symbol Alt. Parameter Min Max Unit
tVCHEL tPU Initialization delay after Power-Up or Deep Power-Down Exit 150 µs
tEHEL(DP) tDPD Deep Power-Down Entry to Deep Power-Down Exit 10 µs
tELEH(DP) tDPDX Chip Enable Low to Deep Power-Down Exit 10 µs
AI09465e
VCC, VCCQ
tVCHEL
1.7V
Device Ready
for Normal Operation
Device Initialization
E
AI11306b
tEHEL(DP)
Device Ready
for Normal Operation
E
tELEH (DP)
Deep Power-Down
Mode
Deep Power-Down
Entry (RCR4= 0)
Deep Power-Down
Exit
tVCHEL
Device Initialization
M69KM048AA Part numbering
59/61
10 Part numbering
The notation used for the device number is as shown in Table 23. Not all combinations are
necessarily available. For a list of available options (speed, package, etc.) or for further
information on any aspect of this device, please contact your nearest STMicroelectronics
Sales Office.
Table 23. Ordering Information Scheme
Example: M69KM048AA C W 8
Device Type
M69 = PSRAM
Mode
K = Bare Die
Operating Voltage
M= VCC = 1.7 to 1.95V, x16, Multiplexed I/O, PSRAM
Array Organization
048 = 32 Mbit (2 Mbit x16)
Option 1
A = 1 Chip Enable
Silicon Revision
A = A Die
Maximum Clock Frequency
C = 83MHz
Package
W = Unsawn Wafer
Operating Temperature
8 = –30 to 85 °C
Revision history M69KM048AA
60/61
11 Revision history
Table 24. Document Revision History
Date Rev. Revision Details
22-Dec-2005 0.1 First Issue.
29-May-2006 1
Maximum clock frequency changed to 83MHz.
Output Disable/No Operation updated in Ta b l e 2 , Ta b l e 3 , Ta bl e 4 , and
Ta bl e 5 . CR status for subsequent Burst Read and Write operations modified
in Table 5.
LB/UB status modified in Figure 5.
Ta bl e 9 updated. Ta bl e 1 2 added.
VIO updated in Ta bl e 1 3 . Ta b le 1 5 updated. VIH minimum value, IPASR
maximum values, ICC1, ICC2 and ICC3R maximum values modified in Ta b l e 1 6 .
tAVL H, tRHLH, tELLH updated, tEHEL removed, and tLHQX added in Ta bl e 1 7 .
Figure 13 and Figure 15 updated. tAVLH, tRHLH, tELLH updated, and tWHQZ
removed in Ta b le 1 8 . tLLWL added in Figure 14. tGHQV added in Ta bl e 2 0 . G,
LB/UB status modified in Figure 19 and Figure 20. LB/UB status modified in
Figure 21, Figure 24, and Figure 26.
Figure 18, Figure 22, and Figure 23 added.
tPU changed to tVCHEL in Ta b l e 2 2 , Figure 28 and Figure 29.
Wafer and die specifications removed.
M69KM048AA
61/61
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