S-8204A Series www.sii-ic.com BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK Rev.3.3_00 (c) Seiko Instruments Inc., 2007-2013 The S-8204A Series includes high-accuracy voltage detection circuits and delay circuits, in single use, makes it possible for users to monitor the status of 3-series or 4-series cell lithium-ion rechargeable battery. By switching the voltage level which is applied to the SEL pin, users are able to use the S-8204A Series either for 3-series or 4-series cell pack. By cascade connection using the S-8204A Series, it is also possible to protect 6-series or more cells*1 lithium-ion rechargeable battery pack. *1. Refer to the application note for connection examples of protection circuit for 6-series or more cells. In case of protecting 5-series cell lithium-ion rechargeable battery pack, contact our sales office. Features * High-accuracy voltage detection function for each cell Overcharge detection voltage n (n = 1 to 4) 3.8 V to 4.6 V (50 mV step) Overcharge release voltage n (n = 1 to 4) 3.6 V to 4.6 V*1 Overdischarge detection voltage n (n = 1 to 4) 2.0 V to 3.0 V (100 mV step) Overdischarge release voltage n (n = 1 to 4) 2.0 V to 3.4 V*2 * Discharge overcurrent detection function in 3-step Discharge overcurrent detection voltage 1 0.05 V to 0.30 V (50 mV step) Discharge overcurrent detection voltage 2 0.5 V (fixed) Load short-circuit detection voltage 1.0 V (fixed) * Charge overcurrent detection function Charge overcurrent detection voltage -0.25 V to -0.05 V (50 mV step) * Settable by external capacitor; overcharge detection delay time, overdischarge discharge overcurrent detection delay time 1, discharge overcurrent detection overcurrent detection delay time (Load short-circuit detection delay time is internally fixed.) * Switchable between 3-series and 4-series cell by using the SEL pin * Independent charge and discharge control by the control pins * High-withstand voltage element Absolute maximum rating: 24 V * Wide operation voltage range 2 V to 22 V * Wide operation temperature range Ta = -40C to +85C * Low current consumption During operation 33 A max. (Ta = +25C) During power-down 0.1 A max. (Ta = +25C) *3 * Lead-free, Sn 100%, halogen-free Accuracy 25 mV Accuracy 50 mV Accuracy 80 mV Accuracy 100 mV Accuracy 15 mV Accuracy 100 mV Accuracy 300 mV Accuracy 30 mV detection delay time, delay time 2, charge *1. Overcharge hysteresis voltage n (n = 1 to 4) is selectable in 0 V, or in 0.1 V to 0.4 V in 50 mV step. (Overcharge hysteresis voltage = Overcharge detection voltage - Overcharge release voltage) *2. Overdischarge hysteresis voltage n (n = 1 to 4) is selectable in 0 V, or in 0.2 V to 0.7 V in 100 mV step. (Overdischarge hysteresis voltage = Overdischarge release voltage - Overdischarge detection voltage) *3. Refer to " Product Name Structure" for details. Application * Rechargeable lithium-ion battery pack Package * 16-Pin TSSOP Seiko Instruments Inc. 1 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 Block Diagram COP Control circuit Delay circuit CTLC Delay circuit Delay circuit RVMD CTLD Delay circuit VMP RVMS Delay circuit Delay circuit Overcharge 1 VDD - Over- + discharge + 1 DOP - VINI + - + - + - + - Overcharge 2 VC1 - Over- + discharge + 2 Discharge overcurrent 1 - Discharge overcurrent 2 Short circuit Overcharge 3 - VC2 + Overdischarge 3 Charge overcurrent + - CDT Overcharge 4 - VC3 + Overdischarge 4 CCT + - VC4 CIT VSS SEL Remark Diodes in the figure are parasitic diodes. Figure 1 2 Seiko Instruments Inc. BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 Product Name Structure 1. Product name S-8204A xx - xxxx x Environmental code U: Lead-free (Sn 100%), halogen-free S: Lead-free, halogen-free Package name (abbreviation) and packing specifications*1 TCT1: 16-Pin TSSOP, Tape Serial code*2 Sequentially set from AA to ZZ *1. Refer to the tape drawing. *2. Refer to "3. Product name list". 2. Package Table 1 Package Drawing Codes Package Name Environmental code = S 16-Pin TSSOP Environmental code = U Dimension FT016-A-P-SD FT016-A-P-SD Tape FT016-A-C-SD FT016-A-C-SD Reel FT016-A-R-SD FT016-A-R-S1 3. Product name list Table 2 Product Name Charge Discharge Overcharge Overdischarge Overdischarge Overcharge Overcurrent 0 V Battery Overcurrent Detection Voltage Release Voltage Detection Voltage Release Voltage Detection Voltage 1 Detection Voltage Charge Function [VCL] [VDL] [VDU] [VCU] [VCIOV] [VDIOV1] S-8204AAB-TCT1y 4.350 0.025 V 4.150 0.050 V 2.00 0.080 V 2.70 0.100 V 0.25 0.015 V -0.10 0.030 V Available S-8204AAC-TCT1y 4.200 0.025 V 4.100 0.050 V S-8204AAD-TCT1y 3.800 0.025 V 3.600 0.050 V S-8204AAE-TCT1y 4.250 0.025 V 4.050 0.050 V 2.70 0.080 V 2.00 0.080 V 2.40 0.080 V 2.90 0.100 V 2.30 0.100 V 2.70 0.100 V 0.25 0.015 V 0.30 0.015 V 0.20 0.015 V -0.25 0.030 V -0.25 0.030 V -0.15 0.030 V Available Available Unavailable 2.70 0.080 V 2.20 0.080 V 2.00 0.080 V 2.00 0.080 V 2.50 0.080 V 2.30 0.080 V 2.90 0.100 V 2.50 0.100 V 2.30 0.100 V 2.30 0.100 V 3.00 0.100 V 2.60 0.100 V 0.10 0.015 V 0.10 0.015 V 0.10 0.015 V 0.05 0.015 V 0.30 0.015 V 0.15 0.015 V -0.10 0.030 V -0.10 0.030 V -0.05 0.030 V -0.05 0.030 V -0.20 0.030 V -0.15 0.030 V Available Available Available Available Unavailable Unavailable S-8204AAF-TCT1y S-8204AAG-TCT1y S-8204AAH-TCT1y S-8204AAI-TCT1y S-8204AAJ-TCT1U S-8204AAK-TCT1U 4.200 0.025 V 3.800 0.025 V 3.800 0.025 V 3.800 0.025 V 4.350 0.025 V 4.300 0.025 V 4.100 0.050 V 3.650 0.050 V 3.600 0.050 V 3.600 0.050 V 4.150 0.050 V 4.100 0.050 V Remark 1. Please contact our sales office for products with detection voltage values other than those specified above. 2. y: S or U 3. Please select products of environmental code = U for Sn 100%, halogen-free products. Seiko Instruments Inc. 3 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 Pin Configuration 1. 16-Pin TSSOP Top view 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Figure 2 Table 3 Pin No. 1 2 3 4 Symbol COP VMP DOP 4 VINI 5 6 CDT CCT 7 CIT 8 SEL 9 VSS 10 VC4 11 VC3 12 VC2 13 VC1 14 VDD 15 16 CTLD CTLC Description Connection pin of charge control FET gate (Nch open-drain output) Voltage detection pin between VDD pin and VMP pin Connection pin of discharge control FET gate (CMOS output) Voltage detection pin between VSS pin and VINI pin * Discharge overcurrent 1 / 2 detection pin, load short-circuit detection pin * Charge overcurrent detection pin Capacitor connection pin for delay for overdischarge detection Capacitor connection pin for delay for overcharge detection Capacitor connection pin for delay for discharge overcurrent 1 / 2, capacitor connection pin for delay for charge overcurrent detection Pin for switching 3-series or 4-series cell * VSS level: 3-series cell * VDD level: 4-series cell Input pin for negative power supply, Connection pin for negative voltage of battery 4 Connection pin for negative voltage of battery 4 Connection pin for negative voltage of battery 3, Connection pin for positive voltage of battery 4 Connection pin for negative voltage of battery 2, Connection pin for positive voltage of battery 3 Connection pin for negative voltage of battery 1, Connection pin for positive voltage of battery 2 Input pin for positive power supply, Connection pin for positive voltage of battery 1 Discharge FET control pin Charge FET control pin Seiko Instruments Inc. Rev.3.3_00 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Absolute Maximum Ratings Table 4 Item Input voltage between VDD pin and VSS pin Symbol Applied Pin VIN VMP pin input voltage DOP pin output voltage COP pin output voltage VVMP VDOP VCOP Power dissipation PD VSS - 0.3 to VSS + 24 V VSS - 0.3 to VDD + 0.3 V VSS - 0.3 to VSS + 24 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VSS + 24 400 (When not mounted on board) 1100*1 -40 to +85 -40 to +125 V V V mW mW C C - VDS Input pin voltage (Ta = +25C unless otherwise specified) Absolute Maximum Rating Unit VC1, VC2, VC3, VC4, CTLC, CTLD, SEL, CCT, CDT, CIT, VINI VMP DOP COP - - Operation ambient temperature Topr - Storage temperature Tstg *1. When mounted on board [Mounted board] (1) Board size: 114.3 mm x 76.2 mm x t1.6 mm (2) Board name: JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation (PD) [mW] 1200 1000 800 600 400 200 0 0 50 100 150 Ambient Temperature (Ta) [C] Figure 3 Power Dissipation of Package (When Mounted on Board) Seiko Instruments Inc. 5 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 Electrical Characteristics Table 5 (1 / 2) Item Detection Voltage Overcharge detection voltage n (n = 1, 2, 3, 4) Overcharge release voltage n (n = 1, 2, 3, 4) Symbol Condition VCUn 3.8 V to 4.6 V, adjustable, 50 mV step VCLn 3.6 V to 4.6 V, adjustable, 50 mV step VCL VCU VCL = VCU Overdischarge detection voltage n VDLn (n = 1, 2, 3, 4) 2.0 V to 3.0 V, adjustable, 100 mV step Overdischarge release voltage n (n = 1, 2, 3, 4) 2.0 V to 3.4 V, adjustable, 100 mV step VDUn Discharge overcurrent detection voltage 1 Discharge overcurrent detection voltage 2 Load short-circuit detection voltage Charge overcurrent detection voltage Temperature coefficient 1*1 Temperature coefficient 2*2 Delay Time Function*4 CCT pin internal resistance CDT pin internal resistance CIT pin internal resistance 1 CIT pin internal resistance 2 CCT pin detection voltage VCCT CDT pin detection voltage VCDT CIT pin detection voltage VCIT Load short-circuit detection delay time 0 V Battery Charge Function 0 V battery charge starting charger voltage 0 V battery charge inhibition battery voltage Internal Resistance Resistance between VMP pin and VDD pin Resistance between VMP pin and VSS pin 6 VDIOV1 VDL VDU VDL = VDU 0.05 V to 0.30 V, adjustable (Ta = +25C unless otherwise specified) Test Min. Typ. Max. Unit Circuit VCUn - 0.025 VCLn - 0.05 VCLn - 0.025 VDLn - 0.08 VDUn - 0.10 VDUn - 0.08 VDIOV1 - 0.015 VCUn VCLn VCLn VDLn VDUn VDUn VDIOV1 VCUn + 0.025 VCLn + 0.05 VCLn + 0.025 VDLn + 0.08 VDUn + 0.10 VDUn + 0.08 VDIOV1 + 0.015 V 2 V 2 V 2 V 2 V 2 V 2 V 2 VDIOV2 - 0.4 0.5 0.6 V 2 VSHORT - 1.0 2 -0.25 V to -0.05 V, adjustable V 2 TCOE1 TCOE2 Ta = 0C to 50C*3 Ta = 0C to 50C*3 0 0 1.3 VCIOV +0.03 1.0 0.5 V VCIOV 0.7 VCIOV - 0.03 -1.0 -0.5 mV/C mV/C 2 2 RINC RIND RINI1 RINI2 V1 = 4.7 V, V2 = V3 = V4 = 3.5 V V1 = 1.5 V, V2 = V3 = V4 = 3.5 V V1 = V2 = V3 = V4 = 3.5 V V1 = V2 = V3 = V4 = 3.5 V VDS = 15.2 V, V1 = 4.7 V, V2 = V3 = V4 = 3.5 V VDS = 12.0 V, V1 = 1.5 V, V2 = V3 = V4 = 3.5 V VDS = 14.0 V, V1 = V2 = V3 = V4 = 3.5 V 6.15 615 123 12.3 VDS x 0.68 VDS x 0.68 VDS x 0.68 8.31 831 166 16.6 VDS x 0.70 VDS x 0.70 VDS x 0.70 10.2 1020 204 20.4 VDS x 0.72 VDS x 0.72 VDS x 0.72 M k k k 3 3 3 3 V 3 V 3 V 3 FET gate capacitance = 2000 pF 100 300 600 s 3 - 0.8 1.5 V 4 0.4 0.7 1.1 V 4 tSHORT V0CHA V0INH 0 V battery charge function "available" 0 V battery charge function "inhibition" VCIOV RVMD - 0.5 1 1.5 M 5 RVMS - 450 900 1800 k 5 Seiko Instruments Inc. Rev.3.3_00 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Table 5 (2 / 2) Item Input Voltage Operation voltage between VDD pin and VSS pin CTLC pin input voltage "H" CTLC pin input voltage "L" CTLD pin input voltage "H" CTLD pin input voltage "L" Symbol VDSOP VCTLCH VCTLCL VCTLDH VCTLDL SEL pin input voltage "H" VSELH SEL pin input voltage "L" VSELL Input Current Current consumption during operation Current consumption during power-down VC1 pin current VC2 pin current VC3 pin current VC4 pin current Condition Fixed output voltage of DOP pin and COP pin V1 = V2 = V3 = V4 = 3.5 V V1 = V2 = V3 = V4 = 3.5 V V1 = V2 = V3 = V4 = 3.5 V V1 = V2 = V3 = V4 = 3.5 V VDS = 14.0 V, V1 = V2 = V3 = V4 = 3.5 V VDS = 14.0 V, V1 = V2 = V3 = V4 = 3.5 V (Ta = +25C unless otherwise specified) Test Min. Typ. Max. Unit Circuit 2 - 22 V 2 - 0.59 - 0.59 VDS x 0.8 - - - - 0.91 - 0.91 - V V V V 2 2 2 2 - - V 2 - - VDS x 0.2 V 2 IOPE V1 = V2 = V3 = V4 = 3.5 V - 15 33 A 1 IPDN V1 = V2 = V3 = V4 = 1.5 V - - 0.1 A 1 IVC1 IVC2 IVC3 IVC4 V1 = V2 = V3 = V4 = 3.5 V V1 = V2 = V3 = V4 = 3.5 V V1 = V2 = V3 = V4 = 3.5 V V1 = V2 = V3 = V4 = 3.5 V V1 = V2 = V3 = V4 = 3.5 V, maximum current flowing into CTLC pin V1 = V2 = V3 = V4 = 3.5 V, VCTLC = VSS V1 = V2 = V3 = V4 = 3.5 V, maximum current flowing into CTLD pin V1 = V2 = V3 = V4 = 3.5 V, VCTLD = VSS V1 = V2 = V3 = V4 = 3.5 V, VSEL = VDD V1 = V2 = V3 = V4 = 3.5 V, VSEL = VSS -0.3 -0.3 -0.3 -6.0 0 0 0 -3.0 0.3 0.3 0.3 -0.5 A A A A 5 5 5 5 3.0 10.0 20.0 A 5 -0.8 -0.6 -0.4 A 5 3.0 10.0 20.0 A 5 -0.8 -0.6 -0.4 A 5 - - 0.1 A 5 -0.1 - - A 5 CTLC pin current "H" ICTLCH CTLC pin current "L" ICTLCL CTLD pin current "H" ICTLDH CTLD pin current "L" ICTLDL SEL pin current "H" ISELH SEL pin current "L" ISELL Output Current 0.1 COP pin leakage current ICOH VCOP = 22 V 5 A - - 10 COP pin sink current ICOL 5 A VCOP = VSS + 0.5 V - - 10 DOP pin source current IDOH 5 A VDOP = VDD - 0.5 V - - 10 DOP pin sink current IDOL 5 A VDOP = VSS + 0.5 V - - *1. Voltage temperature coefficient 1: Overcharge detection voltage *2. Voltage temperature coefficient 2: Discharge overcurrent detection voltage 1 *3. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production. *4. Delay time function is described in " Operation" in detail. Seiko Instruments Inc. 7 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 Test Circuit This chapter describes how to test the S-8204A Series. In case of selecting to use it for 4-series cell battery, set SEL pin = VDD. For 3-series cell battery, set SEL pin = VSS and short between VC3 pin and VC4 pin. 1. Current consumption during operation and power-down (Test circuit 1) 1. 1 Current consumption during operation (IOPE) The current at the VSS pin when V1 = V2 = V3 = V4 = 3.5 V and VVMP = VDD is the current consumption during operation (IOPE). 1. 2 Current consumption during power-down (IPDN) The current at the VSS pin when V1 = V2 = V3 = V4 = 1.5 V and VVMP = VSS is the current consumption during power-down (IPDN). 2. Overcharge detection voltage, overcharge release voltage, overdischarge detection voltage, overdischarge release voltage, discharge overcurrent detection voltage 1, discharge overcurrent detection voltage 2, load short-circuit detection voltage, charge overcurrent detection voltage, CTLC pin input voltage "H", CTLC pin input voltage "L", CTLD pin input voltage "H", CTLD pin input voltage "L", SEL pin input voltage "H", SEL pin input voltage "L" (Test circuit 2) Confirm both COP pin and DOP pin are in "L" (its voltage level is VDS x 0.1 V or less) after setting VVMP = VSEL = VDD, VVINI = VCTLC = VCTLD = VSS, CCT pin = Open, CDT pin = Open, CIT pin = Open, V1 = V2 = V3 = V4 = 3.5 V. (This status is referred to as initial status.) 2. 1 Overcharge detection voltage (VCU1), overcharge release voltage (VCL1) The overcharge detection voltage (VCU1) is a voltage at V1; when the COP pin's voltage is set to "H" (its voltage level is VDS x 0.9 V or more) after increasing a voltage at V1 gradually from the initial status. After that, decreasing a voltage at V1 gradually, a voltage at V1 when the COP pin's voltage is set to "L"; is the overcharge release voltage (VCL1). 2. 2 Overdischarge detection voltage (VDL1), overdischarge release voltage (VDU1) The overdischarge detection voltage (VDL1) is a voltage at V1; when the DOP pin's voltage is set to "H" after decreasing a voltage at V1 gradually from the initial status. After that, increasing a voltage at V1 gradually, a voltage at V1 when the DOP pin's voltage is set to "L"; is the overdischarge release voltage (VDU1). By changing the voltage at Vn (n = 2 to 4), users can define the overcharge detection voltage (VCUn), the overcharge release voltage (VCLn), the overdischarge detection voltage (VDLn), the overdischarge release voltage (VDUn) as well when n = 1. 2. 3 Discharge overcurrent detection voltage 1 (VDIOV1) The discharge overcurrent detection voltage 1 (VDIOV1) is the VINI pin's voltage; when the DOP pin's voltage is set to "H" after increasing the VINI pin's voltage gradually from the initial status. 2. 4 Discharge overcurrent detection voltage 2 (VDIOV2) The discharge overcurrent detection voltage 2 (VDIOV2) is a voltage at the VINI pin; when a flowing current from the CIT pin reaches 500 A or more after increasing the VINI pin's voltage gradually from the initial status. 2. 5 Load short-circuit detection voltage (VSHORT) The load short-circuit detection voltage (VSHORT) is the VINI pin's voltage; when the DOP pin's voltage is set to "H" after increasing the VINI pin's voltage gradually from the initial status after setting the CIT pin's voltage to the VSS level. 8 Seiko Instruments Inc. Rev.3.3_00 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series 2. 6 Charge overcurrent detection voltage (VCIOV) The charge overcurrent detection voltage (VCIOV) is the VINI pin's voltage; when the COP pin's voltage is set to "H" after decreasing the VINI pin's voltage gradually from the initial status. 2. 7 CTLC pin input voltage "H" (VCTLCH), CTLC pin input voltage "L" (VCTLCL) The CTLC pin input voltage "H" (VCTLCH) is the CTLC pin's voltage; when the COP pin's voltage is set to "H" after increasing the CTLC pin's voltage gradually from the initial status. After that, decreasing the CTLC pin's voltage gradually, the CTLC pin's voltage when the COP pin's voltage is set to "L"; is the CTLC pin input voltage "L" (VCTLCL). 2. 8 CTLD pin input voltage "H" (VCTLDH), CTLD pin input voltage "L" (VCTLDL) The CTLD pin input voltage "H" (VCTLDH) is the CTLD pin's voltage; when the DOP pin's voltage is set to "H" after increasing the CTLD pin's voltage gradually from the initial status. After that, decreasing the CTLD pin's voltage gradually, the CTLD pin's voltage when the DOP pin's voltage is set to "L"; is the CTLD pin input voltage "L" (VCTLDL). 2. 9 SEL pin input voltage "H" (VSELH), SEL pin input voltage "L" (VSELL) Start from the initial status, set V4 = 0 V. Confirm the DOP pin is in "H". After that, decreasing the SEL pin's voltage gradually, the SEL pin's voltage when the DOP pin's voltage is set to "L"; is the SEL pin input voltage "L" (VSELL). After that, increasing the SEL pin's voltage gradually, the SEL pin's voltage when the DOP pin's voltage is set to "H"; is the SEL pin input voltage "H" (VSELH). 3. CCT pin internal resistance, CDT pin internal resistance, CIT pin internal resistance 1, CIT pin internal resistance 2, CCT pin detection voltage, CDT pin detection voltage, CIT pin detection voltage, short circuit detection voltage delay time (Test circuit 3) Confirm both COP pin and DOP pin are in "L" after setting VVMP = VSEL = VDD, VVINI = VCTLC = VCTLD = CCT = CDT = CIT = VSS, V1 = V2 = V3 = V4 = 3.5 V. (This status is referred to as initial status.) 3. 1 CCT pin internal resistance (RINC) The CCT pin internal resistance (RINC) is RINC = VDS / ICCT, ICCT is the current which flows from the CCT pin when setting V1 = 4.7 V from the initial status. 3. 2 CDT pin internal resistance (RIND) The CDT pin internal resistance (RIND) is RIND = VDS / ICDT, ICDT is the current which flows from the CDT pin when setting V1 = 1.5 V from the initial status. 3. 3 CIT pin internal resistance 1 (RINI1) The CIT pin internal resistance 1 (RINI1) is RINI1 = VDS / ICIT1, ICIT1 is the current which flows from the CIT pin when setting VVINI = VDIOV1 max. + 0.05 V from the initial status. 3. 4 CIT pin internal resistance 2 (RINI2) The CIT pin internal resistance 2 (RINI2) is RINI2 = VDS / ICIT2, ICIT2 is the current which flows from the CIT pin when setting VVINI = VDIOV2 max. + 0.05 V from the initial status. 3. 5 CCT pin detection voltage (VCCT) The CCT pin detection voltage (VCCT) is the voltage at the CCT pin when the COP pin's voltage is set to "H" (voltage VDS x 0.9 V or more) after increasing the CCT pin's voltage gradually, after setting V1 = 4.7 V from the initial status. Seiko Instruments Inc. 9 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 3. 6 CDT pin detection voltage (VCDT) The CDT pin detection voltage (VCDT) is the voltage at the CDT pin when the DOP pin's voltage is set to "H" (voltage VDS x 0.9 V or more) after increasing the CDT pin's voltage gradually, after setting V1 = 1.5 V from the initial status. 3. 7 CIT pin detection voltage (VCIT) The CIT pin detection voltage (VCIT) is the voltage at the CIT pin when the DOP pin's voltage is set to "H" (voltage VDS x 0.9 V or more) after increasing the CIT pin's voltage gradually, after setting VVINI = VDIOV1 max. + 0.05 V from the initial status. 3. 8 Load short-circuit detection delay time (tSHORT) Load short-circuit detection delay time (tSHORT) is a period in which the DOP pin's voltage changes from "L" to "H" by changing the VINI pin's voltage instantaneously from the initial status to VSHORT max.+ 0.05 V. 4. 0 V battery charge starting charger voltage (0 V battery charge function "available"), 0 V Battery charge inhibition battery voltage (0 V battery charge function "inhibition") (Test circuit 4) According to user's selection of the function to charge 0 V battery, either function of 0 V battery charge starting charger voltage or 0 V battery charge inhibition battery voltage is applied to each product. 4. 1 0 V battery charge starting charger voltage (V0CHA) (0V battery charge function "available") In this 0 V battery charge starting charger voltage, when V1 = V2 = V3 = V4 = 0 V, VVMP = V0CHA max., the COP pin's voltage is V0CHA max. - 1 V or less. 4. 2 0 V battery charge inhibition battery voltage (V0CHA) (0V battery charge function "inhibition") In this 0 V battery charge inhibition battery voltage, when V1 = V2 = V3 = V4 = V0INH min., VVMP = 22 V, the COP pin's voltage is VVMP - 1 V or more. 5. Resistance between VMP pin and VDD pin, resistance between VMP pin and VSS pin, VC1 pin current, VC2 pin current, VC3 pin current, VC4 pin current, CTLC pin current "H", CTLC pin current "L", CTLD pin current "H", CTLD pin current "L", SEL pin current "H", SEL pin current "L", COP pin leakage current, COP pin sink current, DOP pin source current, DOP pin sink current (Test circuit 5) Set VVMP = VSEL = VDD, VVINI = VCTLC = VCTLD = VSS, V1 = V2 = V3 = V4 = 3.5 V, set other pins open. (This status is referred to as initial status.) 5. 1 Resistance between VMP pin and VDD pin (RVMD) The value of resistance between VMP pin and VDD pin (RVMD) can be defined by RVMD = VDS / IVMD by using the VMP pin's current (IVMD) when VVINI = 1.5 V and VVMP = VSS after the initial status. 5. 2 Resistance between VMP pin and VSS pin (RVMS) The value of resistance between VMP pin and VSS pin (RVMS) can be defined by RVMS = VDS / IVMS by using the VMP pin's current (IVMS) when V1 = V2 = V3 = V4 = 1.8 V after the initial status. 10 Seiko Instruments Inc. Rev.3.3_00 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series 5. 3 VC1 pin current (IVC1), VC2 pin current (IVC2), VC3 pin current (IVC3), VC4 pin current (IVC4) In the initial status, each current flows in the VC1 pin, VC2 pin, VC3 pin, VC4 pin is the VC1 pin current (IVC1), the VC2 pin current (IVC2), the VC3 pin current (IVC3), the VC4 pin current (IVC4), respectively. 5. 4 CTLC pin current "H" (ICTLCH), CTLC pin current "L" (ICTLCL) In the initial status, the current which flows in the CTLC pin is the CTLC pin current "L" (ICTLCL). After that, increasing the CTLC pin's voltage gradually, the maximum current which flows in the CTLC pin is the CTLC pin current "H" (ICTLCH). 5. 5 CTLD pin current "H" (ICTLDH), CTLD pin current "L" (ICTLDL) In the initial status, a current which flows in the CTLD pin is the CTLD pin current "L" (ICTLDL). After that, increasing the CTLD pin's voltage gradually, the maximum current which flows in the CTLD pin is the CTLD pin current "H" (ICTLDH). 5. 6 SEL pin current "H" (ISELH), SEL pin current "L" (ISELL) In the initial status, a current which flows in the SEL pin is the SEL pin current "H" (ISELH). After that, a current which flows in the SEL pin when setting VSEL = VSS is the SEL pin current "L" (ISELL). 5. 7 COP pin Leakage current (ICOH), COP pin sink current (ICOL) Start from the initial status, set VCOP = VSS + 0.5 V, a current which flows in the COP pin is the COP pin sink current (ICOL). After that, a current which flows in the COP pin when setting V1 = V2 = V3 = V4 = 5.5 V, VCOP = VDD is the COP pin leakage current (ICOH). 5. 8 DOP pin source current (IDOH), DOP pin sink current (IDOL) Start from the initial status, set VDOP = VSS + 0.5 V, a current which flows in the DOP pin is the DOP pin sink current (IDOL). After that, a current which flows in the DOP pin when setting V1 = V2 = V3 = V4 = 1.8 V, VDOP = VDD - 0.5 V is the DOP pin source current (IDOH). Seiko Instruments Inc. 11 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 S-8204A 1 2 3 4 5 6 7 8 COP VMP DOP VINI CDT CCT CIT SEL CTLC CTLD VDD VC1 VC2 VC3 VC4 VSS 16 15 14 13 12 11 10 9 V1 V2 V3 V4 A C1 = 0.1 F Figure 4 Test Circuit 1 S-8204A V 1 2 3 4 5 6 7 8 V COP VMP DOP VINI CDT CCT CIT SEL CTLC CTLD VDD VC1 VC2 VC3 VC4 VSS 16 15 14 13 12 11 10 9 V1 V2 V3 V4 C1 = 0.1 F A Figure 5 Test Circuit 2 S-8204A 1 2 3 4 5 6 A V V A A COP VMP DOP VINI CDT CCT 7 CIT 8 SEL CTLC CTLD VDD VC1 VC2 VC3 VC4 VSS 16 15 14 13 12 11 10 V1 V2 V3 V4 9 C1 = 0.1 F Figure 6 Test Circuit 3 12 Seiko Instruments Inc. Rev.3.3_00 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series S-8204A 1 2 3 4 5 6 7 8 V COP VMP DOP VINI CDT CCT CIT SEL CTLC CTLD VDD VC1 VC2 VC3 VC4 VSS 16 15 14 13 12 11 10 9 V1 V2 V3 V4 C1 = 0.1 F Figure 7 Test Circuit 4 S-8204A A A A A 1 2 3 4 5 6 7 8 COP VMP DOP VINI CDT CCT CIT SEL CTLC CTLD VDD VC1 VC2 VC3 VC4 VSS 16 15 14 13 12 11 10 9 A A V1 V2 V3 V4 A A A A C1 = 0.1 F Figure 8 Test Circuit 5 Seiko Instruments Inc. 13 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 Operation Remark Refer to " Connection Example of Battery Protection IC". 1. Normal status In the S-8204A Series, both of COP pin and DOP pin get the VSS level; when all values of battery voltage are in the range of overdischarge detection voltage (VDLn) to overcharge detection voltage (VCUn), and due to the discharge or charge current, the VINI pin's voltage is in the range of charge overcurrent detection voltage (VCIOV) to discharge overcurrent detection voltage 1 (VDIOV1). This is the normal status. At this time, the charge FET and the discharge FET are on. 2. Overcharge status In the S-8204A Series, when any voltage of the batteries increases to the level of more than VCUn, the COP pin is set in high impedance. This is the overcharge status. The COP pin is pulled up to EB+ by an external resistor so that the charge FET is turned off and it stops charging. This overcharge status is released if either condition mentioned below is satisfied; (1) In case that the VMP pin voltage is set 39 / 40 x VDS or more; all voltages of the batteries are in the level of overcharge release voltage (VCLn) or less. (2) In case that the VMP pin voltage is set 39 / 40 x VDS or less; all voltages of the batteries are in the level of VCUn or less. 3. Overdischarge status In the S-8204A Series, when any voltage of the batteries decreases to the level of VDLn or less, the DOP pin voltage gets the VDD level. This is the overdischarge status. At this time, the discharge FET is turned off and it stops discharging. This overdischarge status is released / maintained if either condition mentioned below is satisfied; (1) To release; the VMP pin voltage is in the VDD level or more, all voltages of the batteries are in the VDLn level or more. (2) To release; the VMP pin voltage is VDS / 2 or more and the VMP pin voltage is in the VDD level or less; all voltages of the batteries are in the level of overdischarge release voltage (VDUn) or more. (3) The VMP pin voltage is VDS / 2 or less, the S-8204A Series maintains the power-down status. 4. Power-down status In the S-8204A Series, when it reaches the overdischarge status, the VMP pin is pulled down to the VSS level by a resistor between VMP pin and VSS pin (RVMS). If the VMP pin voltage decreases to the level of VDS / 2 or less, almost every circuit in the S-8204A stops working so that the current consumption decreases to the level of current consumption during power-down (IPDN) or less. This is the power-down status. The power-down status is released if the following condition is satisfied. (1) The VMP pin voltage gets VDS / 2 or more. 14 Seiko Instruments Inc. Rev.3.3_00 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series 5. Discharge overcurrent status In the S-8204A Series, in batteries in the normal status, the discharging current increases more than a certain value. As a result, if the status in which the VINI pin voltage increases to the level of VDIOV1 or more, the DOP pin gets the VDD level. This is the discharge overcurrent status. At this time, the discharge control FET is turned off and it stops discharging. The S-8204A Series has three levels for discharge overcurrent detection (VDIOV1, VDIOV2, VSHORT). In the status of discharge overcurrent, the COP pin is set in high impedance. The VMP pin is pulled up to the VDD level by a resistor between VMP pin and VDD pin (RVMD). The S-8204A Series' operations against discharge overcurrent detection voltage 2 (VDIOV2) and load shortcircuit detection voltage (VSHORT) are as well in VDIOV1. The discharge overcurrent status is released if the following condition is satisfied. (1) The VMP pin voltage gets VDS - 1.2 V (typ.) or more. 6. Charge overcurrent status In the S-8204A Series, in batteries in the normal status, the charge current increases more than a certain value. As a result, if the status in which the VINI pin voltage decreases to the level of VCIOV or less, the COP pin is set in high impedance. This is the charge overcurrent status. At this time, the charge control FET is turned off and it stops charging. In this charge overcurrent status, the VMP pin is pulled up to the VDD level by RVMD. Also in the overdischarge status, the function of charge overcurrent detection works. The charge overcurrent status is released if the following condition is satisfied. (1) The VMP pin voltage gets VDS or less. 7. 0 V battery charge function In the S-8204A Series, regarding how to charge a discharged battery (0 V battery), users are able to select either function mentioned below. (1) Allow to charge a 0 V battery (enable to charge a 0 V battery) A 0 V battery is charged; when the voltage of a charger is 0 V battery starting charger voltage (V0CHA) or more. (2) Inhibit charging a 0 V battery (unable to charge a 0 V battery) A 0 V battery is not charged; when the voltage of a charger is 0 V battery charge inhibition battery voltage (V0INH) or less. Caution When the VDD pin voltage is less than the minimum value of operation voltage between VDD pin and VSS pin (VDSOP), the operation of the S-8204A Series is not assured. Seiko Instruments Inc. 15 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 8. Delay time setting In the S-8204A Series, users are able to set delay time for the period; from detecting any voltage of the batteries or detecting changes in the voltage at the VINI pin, to the output to the COP pin, DOP pin. Each delay time is determined by a resistor in the S-8204A Series and an external capacitor. In the overchage detection, when any voltage of the batteries gets VCUn or more, the S-8204 starts charging to the CCT pin's capacitor (CCCT) via the CCT pin's internal resistor (RINC). After a certain period, the COP pin is set in high impedance if the voltage at the CCT pin reaches the CCT pin detection voltage (VCCT). This period is overcharge detection delay time (tCU). tCU is calculated using the following equation (VDS = V1 + V2 + V3 + V4). tCU [s] = -ln (1 - VCCT / VDS ) x CCCT [F] x RINC [M] = -ln (1 - 0.7 (typ.)) x CCCT [F] x 8.31 [M] (typ.) = 10.0 [M] (typ.) x CCCT [F] Overdischarge detection delay time (tDL), discharge overcurrent detection delay time 1 (tDIOV1), discharge overcurrent detection delay time 2 (tDIOV2), charge overcurrent detection delay time (tCIOV) are calculated using the following equations as well. tDL [ms] = -ln (1 - VCDT / VDS) x CCDT [F] x RIND [k] tDIOV1 [ms] = -ln (1 - VCIT / VDS) x CCIT [F] x RINI1 [k] tDIOV2 [ms] = -ln (1 - VCIT / VDS) x CCIT [F] x RINI2 [k] tCIOV [ms] = -ln (1 - VCIT / VDS) x CCIT [F] x RINI1 [k] In case CCCT = CCDT = CCIT = 0.1 [F], each delay time tCU, tDL, tDIOV1, tDIOV2, tCIOV is calculated as follows. tCU [s] = 10.0 [M] (typ.) x 0.1 [F] = 1.0 [s] (typ.) tDL [ms] = 1000 [k] (typ.) x 0.1 [F] = 100 [ms] (typ.) tDIOV1 [ms] = 200 [k] (typ.) x 0.1 [F] = 20 [ms] (typ.) tDIOV2 [ms] = 20 [k] (typ.) x 0.1 [F] = 2.0 [ms] (typ.) tCIOV [ms] = 200 [k] (typ.) x 0.1 [F] = 20 [ms] (typ.) Load short-circuit detection delay time (tSHORT) is fixed internally. 16 Seiko Instruments Inc. Rev.3.3_00 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series 9. CTLC pin and CTLD pin The S-8204A Series has two pins to control output voltage. The CTLC pin controls the output voltage from the COP pin, the CTLD pin controls the output voltage from the DOP pin. Thus it is possible for users to control the output voltages from the COP pin and DOP pin independently. These controls precede the battery protection circuit. Table 6 Conditions Set by CTLC Pin CTLC Pin COP Pin *1 "H" "High-Z" *2 Open "High-Z" *3 "L" Normal status*4 *1. "H"; CTLC VCTLCH *2. Pulled up by ICTLCL *3. "L"; CTLC VCTLCL *4. The status is controlled by the voltage detection circuit. Table 7 Conditions Set by CTLD Pin CTLD Pin DOP Pin "H"*1 VDD level *2 Open VDD level *3 "L" Normal status*3 *1. "H"; CTLD VCTLDH *2. Pulled up by ICTLDL *3. "L"; CTLD VCTLDL *4. The status is controlled by the voltage detection circuit. Caution Note that when the power supply fluctuates, unexpected behavior might occur if an electrical potential is generated between the potentials of "L" level input to the CTLC pin / CTLD pin and IC's VSS by external filters RVSS and CVSS. Seiko Instruments Inc. 17 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 10. SEL pin The S-8204A Series has a pin to switch-control the protection for 3-cell or 4-cell battery. The overdischarge detection for V4-cell is inhibited by setting the SEL pin "L", so that short-circuiting the V4 cell does not allow the overdischarge detection. This setting makes it possible to use the S-8204A Series for 3-cell protection. The SEL pin precedes the battery protection circuit. Be sure to use the SEL pin in "H" or "L". Table 8 Protect Conditions Set by SEL Pin SEL Pin *1 "H" Open "L"*2 *1. "H"; SEL VSELH *2. "L"; SEL VSELL Condition 4-cell protection Indefinite 3-cell protection In cascade connection, it is possible to use the S-8204A Series for protecting 6-cell, 7-cell or 8-cell battery by combining the electrical level of SEL pin. Table 9 Conditions Set by SEL Pin in Cascade Connection SEL pin in S-8204A (1) "L"1 "L"*1 "H"*2 *1. "L"; SEL VSELL *2. "H"; SEL VSELH 18 SEL pin in S-8204A (2) "L"*1 "H"2 "H"*2 Seiko Instruments Inc. Condition 6-series cell protection 7-series cell protection 8-series cell protection BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 Timing Chart (Circuits in Figure 12, Figure 13) 1. Overcharge detection and overdischarge detection VCUn VCLn Battery voltage VDLn (n = 1 to 4) VDD DOP pin voltage VSS VEB+ COP pin voltage High-Z VSS VEB+ VDD 39 / 40 x VDD VMP pin voltage 1 / 2 x VDD VSS Charger connection Load connection Status*1 Overcharge detection delay time (tCU) (1) (2) Overdischarge detection delay time (tDL) (1) (3) (4) (1) *1. (1): Normal status (2): Overcharge status (3): Overdischarge status (4): Power-down status Remark The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the charger. Figure 9 Seiko Instruments Inc. 19 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 2. Discharge overcurrent detection VHC VCUn VCLn Battery voltage VDUn VDLn (n = 1 to 4) VHD VDD DOP pin voltage VSS VEB+ High-Z COP pin voltage High-Z High-Z VSS VDD VMP pin voltage VSS VDD VSHORT VINI pin voltage VDIOV2 VDIOV1 VSS Load connection Status*1 Discharge overcurrent detection delay time 1 (tDIOV1) (1) Discharge overcurrent detection Load short-circuit detection delay time 2 (tDIOV2) delay time (tSHORT) (2) (1) (2) (1) (2) (1) *1. (1): Normal status (2): Discharge overcurrent status Remark The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the charger. Figure 10 20 Seiko Instruments Inc. Rev.3.3_00 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series 3. Charge overcurrent detection VHC VCUn VCLn Battery voltage VDUn VDLn (n = 1 to 4) VHD VDD DOP pin voltage VSS VEB+ High-Z COP pin voltage High-Z VSS VEB+ VDD VMP pin voltage VSS VDD VINI pin voltage VDIOV1 VSS VCIOV Charger connection Charge overcurrent detection delay time (tCIOV) Status*1 (4) (3) (1) Charge overcurrent detection delay time (tCIOV) (2) (1) (2) (1) *1. (1): Normal status (2): Charge overcurrent status (3): Overdischarge status (4): Power-down status Remark The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the charger. Figure 11 Seiko Instruments Inc. 21 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 Connection Examples of Battery Protection IC 1. 3-series cell Pch FET2 Pch FET1 (Charge FET) (Discharge FET) EB+ RVMP RDOP RCOP 1 2 3 4 5 6 7 8 RVINI CCDT CCCT S-8204A CCIT CTLC CTLD VDD VC1 VC2 VC3 VC4 VSS COP VMP DOP VINI CDT CCT CIT SEL RCTLC 16 15 14 13 12 11 10 9 RCTLD CVC1 CVC2 CVC3 CTLC CTLD RVC1 RVC2 RVC3 RVC4 CVSS RSEL RVSS RSENSE EB- Figure 12 2. 4-series cell Pch FET1 Pch FET2 (Charge FET) (Discharge FET) EB+ RVMP RDOP RCOP RVINI CCDT CCCT CCIT S-8204A 1 2 3 4 5 6 7 8 COP VMP DOP VINI CDT CCT CIT SEL CTLC CTLD VDD VC1 VC2 VC3 VC4 VSS RCTLC 16 15 14 13 12 11 10 9 RCTLD CVC1 CVC2 CVC3 CVC4 CVSS RSEL RVSS RSENSE EB- Figure 13 22 RVC1 RVC2 RVC3 RVC4 Seiko Instruments Inc. CTLC CTLD BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 Table 10 Constants for External Components (Circuits in Figure 12, Figure 13) Symbol Min. Typ. Max. Unit RVC1*1 RVC2*1 RVC3*1 RVC4*1 0.51 1 1 k 0.51 1 1 k 0.51 1 1 k 0.51 1 1 k RDOP 2 5.1 10 k RCOP 0.1 1 1 M RVMP 1 5.1 10 k RCTLC 1 1 10 k RCTLD 1 1 10 k RVINI 1 1 10 k RSEL 1 1 100 k m RSENSE 0 - - RVSS*1 22 47 100 *1 CVC1 0 47 100 nF CVC2*1 0 47 100 nF *1 CVC3 0 47 100 nF *1 CVC4 0 47 100 nF CCCT 0.01 0.1 F - CCDT 0.01 0.1 F - CCIT 0.01 0.1 F - *1 CVSS 0 1 2.2 F Pch FET1 - - - - Pch FET2 - - - - *1. Set up a filter constant to be RVSS x CVSS = 47 F * and to be RVC1 x CVC1 = RVC2 x CVC2 = RVC3 x CVC3 = RVC4 x CVC4 = RVSS x CVSS. Caution 1. The above constants may be changed without notice. 2. It is recommended that filter constants between VDD pin and VSS pin should be set approximately to 47 F * . e.g., CVSS x RVSS = 1.0 F x 47 = 47 F * Sufficient evaluation of transient power supply fluctuation and overcurrent protection function with the actual application is needed to determine the proper constants. Contact our sales office in case the constants should be set to other than 47 F * . 3. It has not been confirmed whether the operation is normal in circuits other than the above example of connection. In addition, the example of connection shown above and the constants do not guarantee proper operation. Perform thorough evaluation using an actual application to set the constant. Seiko Instruments Inc. 23 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 3. 7-Series Cell Discharge FET Charge FET EB+ RCOP RDOP DCOP M6 R2 R3 1 2 3 4 5 6 7 8 RINV3 RVINI1 CCDT1 CCCT1 RCIT1 RSEL1 COP VMP DOP VINI CDT CCT CIT SEL CTLC CTLD VDD VC1 VC2 VC3 VC4 VSS 16 15 14 13 12 11 10 9 CVC1 CVC2 CVC3 CVC4 RVC1 RVC2 RVC3 RVC4 CVSS1 S-8204A (1) RVSS1 CEB+ RIFC RIFD REB+ M3 M1 1 COP M5 RINV2 RINV1 RVINI2 CCDT2 CCCT2 ZD1 M4 R1 M2 CCIT2 2 3 4 5 6 7 8 RSEL2 VMP DOP VINI CDT CCT CIT SEL CTLC CTLD VDD VC1 VC2 VC3 VC4 VSS 16 15 14 13 12 11 10 9 CVC5 CVC6 CVC7 RVC5 RVC6 RVC7 RVC8 CVSS2 S-8204A (2) RVSS2 RCTLD RCTLC EB- RSENSE Figure 14 Caution 1. It is recommended that filter constants between VDD pin and VSS pin should be set approximately to 47 F * . e.g., CVSS x RVSS = 1.0 F x 47 = 47 F * Sufficient evaluation of transient power supply fluctuation and overcurrent protection function with the actual application is needed to determine the proper constants. Contact our sales office in case the constants should be set to other than 47 F * . 2. It has not been confirmed whether the operation is normal in circuits other than the above example of connection. In addition, the example of connection shown above and the constants do not guarantee proper operation. Perform thorough evaluation using an actual application to set the constants. Remark Refer to the application note for constants of each external component. 24 Seiko Instruments Inc. Rev.3.3_00 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Precautions * The application conditions for the input voltage, output voltage, and load current should not exceed the package power dissipation. * Batteries can be connected in any order; however, there may be cases when discharging cannot be performed when a battery is connected. In such a case, short the VMP pin and VDD pin or connect the battery charger to return the IC to the normal mode. * If both an overcharge battery and an overdischarge battery are included among the whole batteries, the condition is set in overcharge status and overdischarge status. Therefore either charging or discharging is impossible. * Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. * SII claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. Seiko Instruments Inc. 25 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 Characteristics (Typical Data) 1. Current consumption 40 35 30 25 20 15 10 5 0 1. 2 IOPE vs. Ta 0 5 10 VDS [V] 15 20 22 1. 3 IPDN vs. VDS 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 0 -40 -25 0 25 Ta [C] 50 75 85 0 25 Ta [C] 50 75 85 1. 4 IPDN vs. Ta IPDN [A] IPDN [A] 40 35 30 25 20 15 10 5 0 IOPE [A] IOPE [A] 1. 1 IOPE vs. VDS 5 10 VDS [V] 15 20 22 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 -40 -25 2. Overcharge detection / release voltage, overdischarge detection / release voltage, overcurrent detection voltage 4.375 4.370 4.365 4.360 4.355 4.350 4.345 4.340 4.335 4.330 4.325 2. 2 VCL vs. Ta 4.20 4.18 VCL [V] VCU [V] 2. 1 VCU vs. Ta -40 -25 0 25 Ta [C] 50 4.10 75 85 -40 -25 -40 -25 0 25 Ta [C] 50 75 85 0 25 Ta [C] 50 75 85 2. 4 VDL vs. Ta VDL [V] VDU [V] 26 4.14 4.12 2. 3 VDU vs. Ta 2.80 2.78 2.76 2.74 2.72 2.70 2.68 2.66 2.64 2.62 2.60 4.16 0 25 Ta [C] 50 75 85 2.08 2.06 2.04 2.02 2.00 1.98 1.96 1.94 1.92 Seiko Instruments Inc. -40 -25 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 0.30 0.29 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 2. 6 VDIOV1 vs. Ta VDIOV1 [V] VDIOV1 [V] 2. 5 VDIOV1 vs. VDS 10 11 12 13 14 VDS [V] 15 16 0.60 0.58 0.56 0.54 0.52 0.50 0.48 0.46 0.44 0.42 0.40 10 11 12 13 14 VDS [V] 15 16 1.3 1.3 1.2 1.1 1.0 0.9 0.8 0.7 1.2 1.1 1.0 0.9 0.8 0.7 11 12 13 14 VDS [V] 15 16 10 25 Ta [C] 50 75 85 -40 -25 0 25 Ta [C] 50 75 85 -40 -25 0 25 Ta [C] 50 75 85 2. 12 VCIOV vs. Ta VCIOV [V] -0.05 -0.06 -0.07 -0.08 -0.09 -0.10 -0.11 -0.12 -0.13 -0.14 -0.15 0 2. 10 VSHORT vs. Ta 2. 11 VCIOV vs. VDS VCIOV [V] 0.60 0.58 0.56 0.54 0.52 0.50 0.48 0.46 0.44 0.42 0.40 VSHORT [V] VSHORT [V] 2. 9 VSHORT vs. VDS 10 -40 -25 2. 8 VDIOV2 vs. Ta VDIOV2 [V] VDIOV2 [V] 2. 7 VDIOV2 vs. VDS 0.30 0.29 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 11 12 14 13 VDS [V] 15 16 -0.05 -0.06 -0.07 -0.08 -0.09 -0.10 -0.11 -0.12 -0.13 -0.14 -0.15 Seiko Instruments Inc. -40 -25 0 25 Ta [C] 50 75 85 27 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 3. CCT pin internal resistance / detection voltage, CDT pin internal resistance / detection voltage, CIT pin internal resistance / detection voltage and load short-circuit detection delay time 3. 2 VCCT vs. Ta (VDS = 15.2 V) 12.0 10.9 11.0 10.8 10.0 VCCT [V] RINC [M] 3. 1 RINC vs. Ta 9.0 8.0 -40 -25 10.4 0 25 Ta [C] 50 75 85 3. 3 RIND vs. Ta VCDT [V] RIND [k] 900 800 -40 -25 25 Ta [C] 50 75 85 -40 -25 0 25 Ta [C] 50 75 85 75 85 3. 6 VCIT vs. Ta (VDS = 14.0 V) 240 10.0 220 9.9 200 VCIT [V] RINI1 [k] 75 85 8.4 8.2 0 3. 5 RINI1 vs. Ta 180 160 9.8 9.7 140 -40 -25 9.6 0 25 Ta [C] 50 75 85 3. 7 RINI2 vs. Ta -40 -25 0 25 Ta [C] 50 0 25 Ta [C] 50 3. 8 tSHORT vs. Ta 24.0 600 500 tSHORT [s] 22.0 RINI2 [k] 50 8.3 700 20.0 18.0 16.0 14.0 28 25 Ta [C] 8.5 1000 12.0 0 8.6 1100 120 -40 -25 3. 4 VCDT vs. Ta (VDS = 12.0 V) 1200 600 10.6 10.5 7.0 6.0 10.7 -40 -25 0 25 Ta [C] 50 75 85 Seiko Instruments Inc. 400 300 200 100 0 -40 -25 75 85 BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK S-8204A Series Rev.3.3_00 4. COP pin / DOP pin 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 4. 2 ICOL vs. VCOP 25 20 ICOL [mA] ICOH [A] 4. 1 ICOH vs. VCOP 0 5 0 20 22 10 15 VCOP [V] 0 3.5 7 VCOP [V] 10.5 14 3.5 7 VDOP [V] 10.5 14 4. 4 IDOL vs. VDOP 25 20 IDOL [mA] IDOH [mA] 10 5 4. 3 IDOH vs. VDOP 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 15 15 10 5 0 1.8 3.6 VDOP [V] 5.4 7.2 Seiko Instruments Inc. 0 0 29 5.10.2 0.65 16 9 1 8 0.170.05 0.220.08 No. FT016-A-P-SD-1.1 TITLE TSSOP16-A-PKG Dimensions No. FT016-A-P-SD-1.1 SCALE UNIT mm Seiko Instruments Inc. +0.1 4.00.1 o1.5 -0 0.30.05 2.00.1 8.00.1 1.50.1 o1.60.1 (7.2) 4.20.2 +0.4 6.5 -0.2 1 16 8 9 Feed direction No. FT016-A-C-SD-1.1 TITLE TSSOP16-A-Carrier Tape FT016-A-C-SD-1.1 No. SCALE UNIT mm Seiko Instruments Inc. 21.41.0 17.41.0 +2.0 17.4 -1.5 Enlarged drawing in the central part o210.8 20.5 o130.2 No. FT016-A-R-SD-2.0 TITLE TSSOP16-A- Reel No. FT016-A-R-SD-2.0 SCALE UNIT QTY. 2,000 mm Seiko Instruments Inc. 21.41.0 17.41.0 +2.0 17.4 -1.5 Enlarged drawing in the central part o210.8 20.5 o130.2 No. FT016-A-R-S1-1.0 TITLE TSSOP16-A- Reel No. FT016-A-R-S1-1.0 SCALE UNIT QTY. 4,000 mm Seiko Instruments Inc. www.sii-ic.com * * The information described herein is subject to change without notice. * When the products described herein are regulated products subject to the Wassenaar Arrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. * Use of the information described herein for other purposes and/or reproduction or copying without the express permission of Seiko Instruments Inc. is strictly prohibited. * The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, vehicle equipment, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment, without prior written permission of Seiko Instruments Inc. * * The products described herein are not designed to be radiation-proof. Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. The application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. The user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.