CY7C4121KV13/CY7C4141KV13
144-Mbit QDR™-IV HP SRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-79343 Rev. *Q Revised August 4, 2017
144-Mbit QDR™-IV HP SRAM
Features
■144-Mbit density (8M × 18, 4M × 36)
■Total Random Transaction Rate[1] of 1334 MT/s
■Maximum operating frequency of 667 MHz
■Read latency of 5.0 clock cycles and write latency of 3.0 clock
cycles
■Two-word burst on all accesses
■Dual independent bidirectional data ports
❐Double data rate (DDR) data ports
❐Supports concurrent read/write transactions on both ports
■Single address port used to control both data ports
❐DDR address signaling
■Single data rate (SDR) control signaling
■High-speed transceiver logic (HSTL) and stub series
terminated logic (SSTL) compatible signaling (JESD8-16A
compliant)
❐I/O VDDQ = 1.2 V ± 50 mV or 1.25 V ± 50 mV
■Pseudo open drain (POD) signaling (JESD8-24 compliant)
❐I/O VDDQ = 1.1 V ± 50 mV or 1.2 V ± 50 mV
■Core voltage
❐VDD = 1.3 V ±40 mV
■On-die termination (ODT)
❐Programmable for clock, address/command, and data inputs
■Internal self-calibration of output impedance through ZQ pin
■Bus inversion to reduce switching noise and power
❐Programmable on/off for address and data
■Address bus parity error protection
■Training sequence for per-bit deskew
■On-chip error correction code (ECC) to reduce soft error rate
(SER)
■JTAG 1149.1 test access port (JESD8-26 compliant)
❐1.3-V LVCMOS signaling
■Available in 361-ball FCBGA Pb-free package (21 × 21 mm)
Configurations
CY7C4121KV13 – 8M × 18
CY7C4141KV13 – 4M × 36
Functional Description
The QDR™-IV HP (High-Performance) SRAM is a
high-performance memory device that has been optimized to
maximize the number of random transactions per second by the
use of two independent bidirectional data ports.
These ports are equipped with DDR interfaces and designated
as port A and port B respectively. Accesses to these two data
ports are concurrent and completely independent of each other.
Access to each port is through a common address bus running
at DDR. The control signals are running at SDR and determine
if a read or write should be performed.
There are three types of differential clocks:
■(CK, CK#) for address and command clocking
■(DKA, DKA#, DKB, DKB#) for data input clocking
■(QKA, QKA#, QKB, QKB#) for data output clocking
Addresses for port A are latched on the rising edge of the input
clock (CK), and addresses for port B are latched on the falling
edge of the input clock (CK).
The QDR-IV HP SRAM device is offered in a two-word burst
option and is available in ×18 and ×36 bus width configurations.
For a ×18 bus width configuration, there are 22 address bits, and
for a ×36 bus width configuration, there are 21 address bits
respectively.
An on-chip ECC circuitry detects and corrects all single-bit
memory errors, including those induced by soft-error events,
such as cosmic rays and alpha particles. The resulting SER of
these devices is expected to be less than 0.01 FITs/Mb, a
four-order-of-magnitude improvement over previous generation
SRAMs.
For a complete list of related resources, click here.
Selection Guide
Description QDR-IV
1334 (MT/s)
QDR-IV
1266 (MT/s)
QDR-IV
1200 (MT/s) Unit
Maximum operating frequency 667 633 600 MHz
Maximum operating current × 18 2500 2400 2300 mA
× 36 3200 2950 2700
Note
1. Random Transaction Rate (RTR) is defined as the number of fully random memory accesses (reads or writes) that can be performed on the memory. RTR is measured
in million transactions per second.
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Logic Block Diagram – CY7C4121KV13
CY7C4121KV13/CY7C4141KV13
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Logic Block Diagram – CY7C4141KV13
CY7C4121KV13/CY7C4141KV13
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Contents
Pin Configurations ...........................................................5
Pin Definitions ..................................................................7
Functional Overview ........................................................9
Clocking .......................................................................9
Command Cycles ........................................................9
Read and Write Data Cycles ....................................... 9
Address and Data Bus Inversion .................................9
Address Parity ........................................................... 10
Port Enable ................................................................ 10
On-Die Termination (ODT) Operation .......................10
JTAG Operation ........................................................ 10
Power-Up and Reset .................................................10
Operation Modes ....................................................... 11
Deskew Training Sequence ...................................... 11
I/O Signaling Standards ............................................12
Initialization ................................................................12
Configuration Registers .............................................14
Configuration Registers Description ..........................14
Configuration Register Definitions .............................14
I/O Type and Port Enable Bit Definitions ...................16
ODT Termination Bit Definitions ................................17
Drive Strength Bit Definitions .................................... 18
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 19
Test Access Port .......................................................19
TAP Registers ........................................................... 19
TAP Instruction Set ................................................... 19
TAP Controller State Diagram ....................................... 21
TAP Controller Block Diagram ......................................22
TAP Electrical Characteristics ......................................23
TAP AC Switching Characteristics ............................... 23
TAP Timing Diagram ...................................................... 24
Identification Register Definitions ................................ 25
Scan Register Sizes ....................................................... 25
Instruction Codes ........................................................... 25
Boundary Scan Order .................................................... 26
Maximum Ratings ........................................................... 29
Operating Range ............................................................. 29
Neutron Soft Error Immunity ......................................... 29
Electrical Characteristics ............................................... 29
Capacitance .................................................................... 31
Thermal Resistance ........................................................ 31
AC Test Load and Waveform ......................................... 31
Switching Characteristics .............................................. 32
Switching Waveforms .................................................... 34
Ordering Information ...................................................... 41
Ordering Code Definitions ......................................... 41
Package Diagram ............................................................ 42
Acronyms ........................................................................ 43
Document Conventions ................................................. 43
Units of Measure ....................................................... 43
Document History Page ................................................. 44
Sales, Solutions, and Legal Information ...................... 45
Worldwide Sales and Design Support ....................... 45
Products .................................................................... 45
PSoC® Solutions ...................................................... 45
Cypress Developer Community ................................. 45
Technical Support ..................................................... 45
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Pin Configurations
Figure 1. 361-ball FCBGA Pinout
CY7C4121KV13 (8M × 18)
CY7C4121KV13/CY7C4141KV13
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Figure 2. 361-ball FCBGA Pinout
CY7C4141KV13 (4M × 36)
Pin Configurations (continued)
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Pin Definitions
Pin Name I/Os Pin Description
CK, CK# Input Clock Address/Command Input Clock. CK and CK# are differential clock inputs. All control and address
input signals are sampled on both the rising and falling edges of CK. The rising edge of CK samples
the control and address inputs for port A, while the falling edge of CK samples the control and address
inputs for port B. CK# is 180 degrees out of phase with CK.
A[x:0] Input Address Inputs. Sampled on the rising edge of both CK and CK# clocks during active read and write
operations. These address inputs are used for read and write operations on both ports.
For (× 36) data width - Address inputs A[20:0] are used and A[24:21] are reserved.
For (× 18) data width - Address inputs A[21:0] are used and A[24:22] are reserved.
The reserved address inputs are No Connects and may be tied high, tied low, or left floating.
AP Input Address Parity Input. Used to provide even parity across the address pins.
For (× 36) data width - AP covers address inputs A[20:0]
For (× 18) data width - AP covers address inputs A[21:0]
PE# Output Address Parity Error Flag. Asserted LOW when address parity error is detected. Once asserted,
PE# will remain LOW until cleared by a Configuration Register command.
AINV Input Address Inversion Pin for Address and Address Parity Inputs.
For (× 36) data width - AINV covers address inputs A[20:0] and the address parity input (AP).
For (× 18) data width - AINV covers address inputs A[21:0] and the address parity input (AP).
DKA[1:0],
DKA#[1:0],
DKB[1:0],
DKB#[1:0]
Input Data Input Clock.
DKA[0]/DKA#[0] controls the DQA[17:0] inputs for × 36 configuration and DQA[8:0] inputs for × 18
configuration respectively
DKA[1]/DKA#[1] controls the DQA[35:18] inputs for × 36 configuration and DQA[17:9] inputs for × 18
configuration respectively
DKB[0]/DKB#[0] controls the DQB[17:0] inputs for × 36 configuration and DQB[8:0] inputs for × 18
configuration respectively
DKB[1]/DKB#[1] controls the DQB[35:18] inputs for × 36 configuration and DQB[17:9] inputs for × 18
configuration respectively
QKA[1:0],
QKA#[1:0],
QKB[1:0],
QKB#[1:0]
Output Data Output Clock.
QKA[0]/QKA#[0] controls the DQA[17:0] outputs for × 36 configuration and DQA[8:0] outputs for × 18
configuration respectively
QKA[1]/QKA#[1] controls the DQA[35:18] outputs for × 36 configuration and DQA[17:9] outputs for
× 18 configuration respectively
QKB[0]/QKB#[0] controls the DQB[17:0] outputs for × 36 configuration and DQB[8:0] outputs for × 18
configuration respectively
QKB[1]/QKB#[1] controls the DQB[35:18] outputs for × 36 configuration and DQB[17:9] outputs for
× 18 configuration respectively
DQA[x:0],
DQB[x:0]
Input/Output Data Input/Output.Bidirectional data bus.
For (× 36) data width DQA[35:0]; DQB[35:0]
For (× 18) data width DQA[17:0]; DQB[17:0]
DINVA[1:0],
DINVB[1:0]
Input/Output Data Inversion Pins for DQ Data Bus.
DINVA[0] covers DQA[17:0] for × 36 configuration and DQA[8:0] for × 18 configuration respectively
DINVA[1] covers DQA[35:18] for × 36 configuration and DQA[17:9] for × 18 configuration respectively
DINVB[0] covers DQB[17:0] for × 36 configuration and DQB[8:0] for × 18 configuration respectively
DINVB[1] covers DQB[35:18] for × 36 configuration and DQB[17:9] for × 18 configuration respectively
LDA#, LDB# Input Synchronous Load Input.LDA# is sampled on the rising edge of the CK clock, while LDB# is
sampled on the falling edge of CK clock. LDA# enables commands for data port A, and LDB# enables
commands for data port B. LDx# enables the commands when LDx# is LOW and disables the
commands when LDx# is HIGH. When the command is disabled, new commands are ignored, but
internal operations continue.
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RWA#,
RWB#
Input Synchronous Read/Write Input. RWA# input is sampled on the rising edge of the CK clock, while
RWB# is sampled on the falling edge of the CK clock. The RWA# input is used in conjunction with
the LDA# input to select a read or write operation. Likewise, the RWB# input is used in conjunction
with the LDB# input to select a Read or Write Operation.
QVLDA[1:0],
QVLDB[1:0]
Output Output Data Valid Indicator. The QVLD pin indicates valid output data. QVLD is edge-aligned with
QKx and QKx#.
ZQ/ZT Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance.
CFG# Input Configuration bit. This pin is used to configure different mode registers.
RST# Input Active Low Asynchronous RST. This pin is active when RST# is LOW, and inactive when RST# is
HIGH. RST# pin has an internal pull-down resistor.
LBK0#,
LBK1#
Input Loopback mode for control and address/command/clock deskewing.
TMS Input Test Mode Select Input pin for JTAG. This pin may be left unconnected if the JTAG function is not
used in the circuit.
TDI Input Test Data Input pin for JTAG. This pin may be left unconnected if the JTAG function is not used in
the circuit.
TCK Input Test Clock Input pin for JTAG. This pin must be tied to VSS if the JTAG function is not used in the
circuit.
TDO Output Test Data Output pin for JTAG. This pin may be left unconnected if the JTAG function is not used
in the circuit.
TRST# Input Test Reset Input pin for JTAG. This pin must be tied to VDD if the JTAG function is not used in the
system. TRST# input is applicable only in JTAG mode.
DNU N/A Do Not Use. Do Not Use pins.
VREF Reference Reference Voltage Input. Static input used to set the reference level for inputs, outputs, and AC
measurement points.
VDD Power Power Supply Inputs to the Core of the Device.
VDDQ Power Power Supply Inputs for the Outputs of the Device.
VSS Ground Ground for the Device.
Pin Definitions (continued)
Pin Name I/Os Pin Description
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Functional Overview
The QDR-IV HP SRAM is a two-word burst synchronous SRAM
equipped with dual independent bidirectional data ports. The
following sections describe the operation of QDR-IV HP SRAM.
Clocking
There are three groups of clock signals: CK/CK#, DKx/DKx#,
and QKx/QKx#, where x can be A or B, referring to the respective
ports.
The CK/CK# clock is associated with the address and control
pins: A[24:0], LDA#, LDB#, RWA#, RWB#. The CK/CK#
transitions are centered with respect to the address and control
signal transitions.
The DKx/DKx# clocks are associated with write data. The
DKx/DKx# clocks are used as source-centered clocks for the
DDR DQx and DINVx pins, when acting as inputs for the write
data.
The QKx/QKx# clocks are associated with read data. The
QKx/QKx# clocks are used as source-synchronous clocks for
the DDR DQx and DINVx pins, when acting as outputs for the
read data.
Command Cycles
The QDR-IV HP SRAM read and write commands are driven by
the control inputs (LDA#, LDB#, RWA#, and RWB#) and the
Address Bus.
The port A control inputs (LDA# and RWA#) are sampled at the
rising edge of the input clock. The port B control inputs (LDB#
and RWB#) are sampled at the falling edge of the input clock.
For port A:
When LDA# = 0 and RWA# = 1, a read operation is initiated.
When LDA# = 0 and RWA# = 0, a write operation is initiated.
The address is sampled on the rising edge of the input clock.
For port B:
When LDB# = 0 and RWB# = 1, a read operation is initiated.
When LDB# = 0 and RWB# = 0, a write operation is initiated.
The address is sampled on the falling edge of the input clock.
Read and Write Data Cycles
Read data is supplied to the DQA pins exactly five clock cycles
from the rising edge of the CK signal, corresponding to the cycle
where the read command was initiated. QVLDA is asserted
one-half clock cycle prior to the first data word driven on the bus.
It is deasserted one-half cycle prior to the last data word driven
on the bus. Data outputs are tristated in the clock following the
last data word.
Read data is supplied to the DQB pins exactly five clock cycles
from the falling edge of the CK signal corresponding to the cycle
that the read command was initiated. QVLDB is asserted
one-half clock cycle prior to the first data word driven on the bus.
It is deasserted one-half cycle prior to the last data word driven
on the bus. Data outputs are tristated in the clock following the
last data word.
Write data is supplied to the DQA pins exactly three clock cycles
from the rising edge of the CK signal corresponding to the cycle
where the write command was initiated.
Write data is supplied to the DQB pins exactly three clock cycles
from the falling edge of the CK signal corresponding to the cycle
where the write command was initiated.
Address and Data Bus Inversion
To reduce simultaneous switching noise and I/O current, QDR-IV
HP SRAM provides the ability to invert all address or data pins.
The AINV pin indicates whether the address bus, A[24:0], and
the address parity bit, AP, is inverted. The address bus and parity
bit are considered one group. The function of the AINV is
controlled by the memory controller. However, the following rules
should be used in the system design.
■For a × 36 configuration part, 21 address pins plus 1 parity bit
are used for 22 signals in the address group.If the number of
0’s in the address group is >11, AINV is set to 1 by the controller.
As a result, no more than 11 pins may switch in the same
direction during each bit time.
■For a × 18 data width part, 22 address pins plus 1 parity bit are
used for 23 signals in the address group. If the number of 0s
in the address group is >12, AINV is set to 1 by the controller.
As a result, no more than 12 pins may switch in the same
direction during each bit time.
The DINVA and DINVB pins indicate whether the corresponding
DQA and DQB pins are inverted.
■For a × 36 data width part, the data bus for each port is split
into groups of 18 pins. Each 18-pin data group is guaranteed
to be driving less than or equal to 10 pins low on any given
cycle.If the number of 0’s in the data group is >10, DINV is set
to 1. As a result, no more than 10 pins may switch in the same
direction during each bit time.
■For a × 18 data width part, the data bus for each port is split
into groups of nine pins. Each 9-pin data group is guaranteed
to be driving less than or equal to five pins low on any given
cycle. If the number of 0s in the data group is >5, DINV is set
to 1. As a result, no more than five pins may switch in the same
direction during each bit time.
AINV, DINVA[1:0], DINVB[1:0] are all active high. When set to 1,
the corresponding bus is inverted. If the data inversion feature is
programmed to be OFF, then the DINVA/DINVB output bits will
always be driven to 0.
These functions are programmable through the configuration
registers and can be enabled or disabled for the address bus and
the data bus independently.
During configuration register read and write cycles, the address
inversion input is ignored and the data inversion output is always
driven to 0 when register read data is driven on the data bus.
Specifically, the register read data is driven on DQA[7:0] and the
DINVA[0] bit is driven to 0. All other DQA/DQB data bits and
DINVA/DINVB bits are tristated. In addition, the address parity
input (AP) is ignored.
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Address Parity
The QDR-IV HP SRAM provides an address parity feature to
provide integrity on the address bus. Two pins are provided to
support this function: AP and PE#.
The AP pin is used to provide an even parity across the address
pins.The value of AP is set so that the total number of 1s
(including the AP bit) is even. The AP pin is a DDR input.
Internally, when an address parity error is detected, the access
to the memory array is ignored if it was a write cycle. A read
access continues normally even if an address parity error is
detected.
Externally, the PE# pin is used to indicate that an address parity
error has occurred. This pin is Active Low and is set to 0 within
RL cycles after the address parity error is detected. It remains
asserted until the error is cleared through the configuration
registers.
The address parity function is optional and can be enabled or
disabled in the configuration registers.
During configuration register read and write cycles, the address
parity input is ignored. Parity is not checked during these cycles.
Note The memory controller should generate address parity
based on the address bus first. Address inversion is done later
on the address bus and address parity bit.
Port Enable
The QDR-IV HP SRAM has two independent bidirectional data
ports. However, some system designers may either choose to
use only one port, or use one port as read-only and one port as
write-only.
If a port is used in a unidirectional mode, disable the data clocks
(DKx/DKx# or QKx/QKx#) to reduce EMI effects in the system.
In addition, disable the corresponding control input (RWx#)l.
Port B may be programmed to be entirely disabled. If port B is
not used, then the following must happen:
■The data clocks (DKB/DKB# and QKB/QKB#) and the control
inputs (LDB# and RWB#) must be disabled.
■All data bus signals must be tristated. This includes DQB,
DINVB, and QVLDB.
■All input signals related to port B can be left floating or tied to
either 1 or 0 without any adverse effects on the port A operation.
■When port B is not used, all output signals related to port B are
inactive.
A configuration register option is provided to specify if one of the
ports is not used or is operating in a unidirectional mode.
On-Die Termination (ODT) Operation
When enabled, the ODT circuits for the chip will be enabled
during all NOP and write cycles. Only during read cycles is the
ODT temporarily disabled as the read data is driven out.
Specifically, ODT is disabled one-half clock cycle before the first
beat of the read data is driven on the data bus and remains
disabled during the entire read operation. ODT is enabled again
one-half clock cycle after the last beat of read data is driven on
the data bus.
JTAG Operation
The JTAG interface uses five signals, TRST#, TCK, TMS, TDI,
and TDO. For normal JTAG operation, the use of TRST# is not
optional for this device.
While in the JTAG mode, the following conditions are true:
■ODT for all pins is disabled.
If the JTAG function is not used in the system, then TRST# pin
must be tied to VDD and TCK input must be driven low or tied to
VSS. TMS, TDI, and TDO may be left floating.
Power-Up and Reset
The QDR-IV HP SRAM has specific power-up and reset
requirements to guarantee reliable operation.
Power-Up Sequence
■Apply VDD before VDDQ.
■Apply VDDQ before VREF or at the same time as VREF
.
Reset Sequence
Refer to the reset timing diagram (Figure 16 on page 40).
1. As the power comes up, all inputs may be in an undefined
state, except RST# and TRST#, which must be LOW during
tPWR.
2. The first signal that should be driven to the device is the input
clock (CK/CK#), which may be unstable for the duration of
tPWR.
3. After the input clock has stabilized, all the control inputs
should be driven to a valid value as follows:
a. RST# = 0
b. CFG# = 1
c. LBK0# = 1
d. LBK1# = 1
e. LDA# = 1
f. LDB# = 1
4. Reset should remain asserted, while all other control inputs
deasserted, for a minimum time of 200 µs (tRSS).
5. At the rising edge of reset, the address bits A[13:0] are
sampled to load in the ODT values and Port Enable values.
After reset, internal operations in the device may start. This
may include operations, such as PLL initialization and
resetting internal registers.
6. However, all external control signals must remain deasserted
for a minimum time of 400000 clocks (tRSH). During this time
all other signals (data and address busses) should be driven
to a valid level. All inputs to the device should be driven to a
valid level.
7. After this, the device is in the normal operating mode and
ready to respond to control inputs.
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Typically, after a reset sequence, the system starts to perform a
training sequence, involving the steps outlined in the following
section.
However, RST# may be asserted at any time by the system and
the system may wish to initiate normal read/write operations after
a reset sequence, without going through another training
sequence. The chip should be able to accept normal read/write
operations immediately following tRSH after the deassertion of
RST#.
PLL Reset Operation
The configuration registers contain a bit to reset the PLL.
Operating the QDR-IV HP SRAM device without the PLL
enabled is not supported – timing characteristics are not
guaranteed when the PLL is disabled. However, this bit is
intended to allow the system to reset the PLL locking circuitry.
Resetting the PLL is accomplished by first programming the PLL
Reset bit to 1 to disable the PLL, and then programming the bit
to 0 to enable the PLL. After these steps, the PLL will relock to
the input clock. A wait time of tPLL is required.
Operation Modes
The QDR-IV HP SRAM has three unique modes of operation:
1. Configuration
2. Loopback
3. Memory Access
These modes are defined by the level of the control signals
CFG#, LBK0#, LBK1#, LDA#, LDB#.
It is intended that these operations are mutually exclusive. In
other words, one operation mode cannot be performed
simultaneously with another operation mode.
There is no priority given for inadvertently asserting the control
signals at the wrong time. The internal chip behavior is not
defined for improper control signal assertion. The system must
strictly adhere to proper mode transitions, as defined in the
following sections, for proper device operation.
Configuration
A configuration operation mode is entered when the CFG# signal
is asserted. Memory Access or Loopback operations should not
be performed for a minimum of 32 clocks prior to entering this
mode.
While in this mode, the control signals LDB#, LBK0#, and LBK1#
must not be asserted. However, LDA# is used to perform the
actual Register Read and Write operations.
Memory Access or Loopback operations should not be
performed for a minimum of 32 clocks after exiting this mode.
Loopback
A loopback operation mode is entered when the LBK0# and/or
LBK1# signals are asserted. Memory Access or Configuration
operations should not be performed for a minimum of 32 clocks
prior to entering this mode.
Just after entering this mode, an additional 32 clocks are
required before the part is ready to accept toggling valid inputs
for training.
While in this mode, LDA# and LDB# may be toggled for training.
Memory Access or Configuration operations should not be
performed for a minimum of 32 clocks after exiting this mode.
Data inversion is not used during the Loopback mode. Even if
the configuration register has this feature enabled, it is
temporarily ignored during the Loopback mode.
Memory Access
If the control signals CFG#, LBK0#, and LBK1# are not asserted,
then the device is in the Memory Access mode. This mode is the
normal operating mode of the device.
While in this mode, a memory access cycle is performed when
the LDA# and/or LDB# signals are asserted. The control signals
CFG#, LBK0#, and LBK1# must not be asserted when
performing a memory access cycle.
A memory access should not be performed for a minimum of
32 clocks prior to leaving this mode.
Deskew Training Sequence
The QDR-IV HP SRAM provides support that allows a memory
controller to deskew signals for high-speed operation. The
memory controller provides the deskew function, if deskew is
desired. During the deskew operation, the QDR-IV HP SRAM
operates in a loopback mode.
Refer to the loopback timing diagram (Figure 15 on page 39).
Deskew is achieved in three steps:
1. Control/address deskew
2. Read data deskew
3. Write data deskew
Control/Address Deskew
Assert LBK0# to 0 and/or LBK1# to 0
The following 39 signals are looped back:
■DKA0, DKA0#, DKA1, DKA1#
■DKB0, DKB0#, DKB1, DKB1#
■LDA#, RWA#, LDB#, RWB#
■A[24:0], AINV, AP
The clock inputs DKA0, DKA0#, DKA1#, DKB0, DKB0#, DKB1,
and DKB1# are free-running clock inputs and should be
continuously running during the training sequence. In addition, a
wait time of tPLL is needed.
Refer to Table 1 on page 14 for the loopback signal mapping.
For each pin that is looped back, the input pin is sampled on both
the rising and falling edges using the input clock (CK/CK#).
The value output on the rising edge of the output clock
(QKA/QKA#) will be the value that was sampled on the rising
edge of the input clock.
The value output on the falling edge of the output clock
(QKA/QKA#) will be the inverted value that was sampled on the
falling edge of the input clock.
The delay from the input pins to the DQA outputs is tLBL, which
is 16 clocks.
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 12 of 45
Read Data Deskew
At this time, the address, control, and data input clocks are
already deskewed.
Read data deskew requires a training pattern to be written into
the memory, using data held at constant values.
Complex data patterns may be written into the memory using the
non deskewed DQA and/or DQB signals and the write training
enable bit.
Write training enable set to 1:
During Write Data Cycles:
The First Data Beat (First Data Burst) is sampled from the data
bus.
The Second Data Beat (Second Data Burst) is the inverted
sample from the data bus.
Write training enable set to 0:
During Write Data Cycles:
Both First and Second Data Beats are sampled from the data
bus, which is the normal operation.
The Write Training Enable bit has no effect on read data cycles.
After the data pattern is written into the memory, standard read
commands permit the system to deskew with respect to the
QK/QK# data output clocks the following signals:
DQA, DINVA, QVLDA, DQB, DINVB, QVLDB
Write Data Deskew
Write data deskew is performed using write commands to the
memory followed by read commands.
The deskewed read data path is used to determine whether or
not the write data was received correctly by the device.
This permits the system to deskew with respect to the DK/DK#
input data clocks the following signals:
DQA, DINVA, DQB, DINVB
I/O Signaling Standards
Several I/O signaling standards are supported by the QDR-IV HP
SRAM, which are programmable by the user. They are:
■1.2 V and 1.25 V HSTL/SSTL
■1.1 V and 1.2 V POD
The I/O Signaling Standard is programmed on the rising edge of
reset by sampling the address bus inputs. Once programmed,
the value cannot be changed. Only the rising edge of another
reset can change the value.
All address, control, and data I/O signals — with the exception
of six pins (listed as LVCMOS in the LVCMOS Signaling) — will
program to comply with HSTL/SSTL or POD.
HSTL/SSTL Signaling
HSTL/SSTL is supported at the VDDQ voltages of 1.2 V and
1.25 -V nominal.
The ODT termination values can be set to:
■40, 60, or 120 ohms with a 220-ohm reference resistor
■50 or 100 ohms with a 180-ohm reference resistor
The drive strength can be programmed to:
■40 or 60 ohms with a 220-ohm reference resistor
■50 ohms with a 180-ohm reference resistor
A reference resistor of 180 ohms or 220 ohms is supported with
HSTL/SSTL signaling.
POD Signaling
POD is supported at VDDQ voltages of 1.1 V and 1.2 V nominal.
The ODT termination values can be set to:
■50 or 100 ohms with a 180-ohm reference resistor
■60 or 120 ohms with a 220-ohm reference resistor
The drive strength can be programmed to:
■50 ohms with a 180-ohm reference resistor
■40 or 60 ohms with a 220-ohm reference resistor
A reference resistor of 180 ohms or 220 ohms is supported with
POD signaling.
LVCMOS Signaling
Six I/O signals are permanently set to use LVCMOS signaling at
voltage of 1.3 V nominal. These signals are referenced to the
core voltage supply, VDD. They are:
RST#, TRST#, TCK, TMS, TDI, and TDO
All the five JTAG signals as well as the main reset input are 1.3 V
LVCMOS.
In addition, ODT is disabled at all times on these LVCMOS
signals.
Initialization
The QDR-IV HP SRAM must be initialized before it can operate
in the normal functional mode. Initialization uses four special
pins:
■RST# pin to reset the device
■CFG# pin to program the configuration registers
■LBK0# and LBK1# pins for the loopback function
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The following flowchart illustrates the initialization procedure:
Figure 3. Flowchart illustrating initialization procedure
Power on
Apply power to the chip as described in Power-Up Sequence.
Reset Chip
Apply reset to the QDR-IV HP SRAM as described in Reset
Sequence.
Configure the Impedance
Assert Config (CFG# = 0) and program the impedance control
register.
Wait for the PLL to Lock
Since the input impedance is updated, allow the PLL time (tPLL)
to lock to the input clock.
Configure Training Options
At this time, the address and data inversion options need to be
programmed. In addition, the write training function needs to be
enabled.
Assert Config (CFG# = 0) and program:
■Write Training (Turn On)
■Address Inversion Enable
■Data Inversion Enable
Control/Address Deskew
Control and address deskew can now be performed by the
memory controller.
Read Data Deskew
After control and address deskew, the read data path is
deskewed as previously described in the deskew training
sequence.
Write Data Deskew
Write data path is deskewed following the read data path
deskew.
Configure Runtime Options
After the training is complete, disable the write training function.
Finally, enable the address parity option at this time.
Assert Config (CFG# = 0) and program:
■Write Training (Turn off)
■Parity Enable
Normal Operation
If the system detects a need to deskew again, the process must
start again from the Configure Training Options step. The
following table defines the loopback mapping.
CY7C4121KV13/CY7C4141KV13
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Configuration Registers
The QDR-IV HP SRAM contains internal registers that are
programmed by the system using a special configuration cycle.
These registers are used to enable and control several options,
as described in this section. All registers are 8-bits wide. The
write operation is performed using only the address pins to
define the register address and register write data. For a read
operation, the register read data is provided on the data port A
output pins. Refer to Figure 14 on page 38 for programming
details.
During the rising edge of RST#, the Address pins A[13:0] are
sampled. The value sampled becomes the reset value of certain
bits in the registers defined in Table 2. This is used to set
termination, impedance, and port configuration values
immediately upon reset. These values can be overwritten later
through a register write operation.
When a parity error occurs, the complete address of the first
error is recorded in Registers 4, 5, 6, and 7 along with the port
A/B error bit. The port A/B error bit indicates which port the
address parity error came from — 0 for port A and 1 for port B.
This information remains latched until cleared by writing a 1 to
the address parity error clear bit in register 3.
Two counters are used to indicate if multiple address parity errors
have occurred. Port A error count is a running count of the
number of parity errors on port A addresses, and similarly port B
error count is a running count of the number of parity errors on
port B addresses. They will each independently count to a
maximum value of 3 and then stop counting. These counters are
free-running and they are both reset by writing a 1 to the address
parity error clear bit in register 3.
Configuration Registers Description
Configuration Register Definitions
Table 1. Loopback Signal Mapping
Input Pin
LBK0# = 0
LBK1# = 0
Input Pin
LBK0# = 0
LBK1# = 1
Input Pin
LBK0# = 1
LBK1# = 0
Output Pin
A0 A13 DKA0 DQA0
A1 A14 DKA0# DQA1
A2 A15 DKA1 DQA2
A3 A16 DKA1# DQA3
A4 A17 LDA# DQA4
A5 A18 RWA# DQA5
A6 A19 DKB0 DQA6
A7 A20 DKB0# DQA7
A8 A21 DKB1 DQA8
A9 A22 DKB1# DQA9
A10 A23 LDB# DQA10
A11 A24 RWB# DQA11
A12 AINV AP DQA12
Table 2. Configuration Register Table
Register Address Description
0 Termination Control Register
1 Impedance Control Register
2 Option Control Register
3 Function Control Register
4 Address Parity Status Register 0
5 Address Parity Status Register 1
6 Address Parity Status Register 2
7 Address Parity Status Register 3
Table 3. Address 0: Termination Control Register (Read/Write)
Function
ODT Global
Enable
ODT/ZQ
Auto Update
Address /
Command
Input Group
IU[2]
Address /
Command
Input Group
IU[1]
Address /
Command
Input Group
IU[0]
Clock Input
Group KU[2]
Clock Input
Group KU[1]
Clock Input
Group KU[0]
Bit Location 76543210
Reset Value A7 A6 A5 A4 A3 A2 A1 A0
Note: ODT/ZQ Auto Update needs to be turned on if ODT/ZQ configuration is changed
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 15 of 45
Table 4. Address 1: Impedance Control Register (Read/Write)
Function Pull Down
Group PD[1]
Pull Down
Group PD[0]
Pull Up
Group PU[1]
Pull Up
Group PU[0]
Unused Data Input
Group QU[2]
Data Input
Group QU[1]
Data Input
Group QU[0]
Bit Location 76543210
Reset Value 10100A10A9A8
Table 5. Address 2: Option Control Register (Read/Write Bits 7–3) (Read-Only Bits 2–0) [2]
Function Write Train
Enable
Data Inv
Enable
Address Inv
Enable
Address
Parity Enable
PLL Reset I/O Type Port
Enable[1]
Port
Enable[0]
Bit Location 76543210
Reset Value 00000A13A12A11
Table 6. Address 3: Function Control Register (Write Only)
Function Unused Unused Unused Unused Unused Unused Unused Address Parity
Error Clear
Bit Location 7654321 0
Reset Value 0000000 0
Table 7. Address 4: Address Parity Status Register 0 (Read Only)
Function Port B Error Count
(1:0)
Port A Error Count
(1:0)
Port A/B Error AINV Bit Unused Unused
Bit Location 7:6 5:4 3 2 1 0
Reset Value 00 00 0 0 0 0
Table 8. Address 5: Address Parity Status Register 1 (Read Only)
Function Address (23:16)
Bit Location 7:0
Reset Value 00000000
Note: Unused address locations will be read as 0
Table 9. Address 6: Address Parity Status Register 2 (Read Only)
Function Address (15:8)
Bit Location 7:0
Reset Value 00000000
Table 10. Address 7: Address Parity Status Register 3 (Read Only)
Function Address (7:0)
Bit Location 7:0
Reset Value 00000000
Note
2. The Bits 2–0 are read only and can be changed only on the rising edge of reset.
CY7C4121KV13/CY7C4141KV13
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I/O Type and Port Enable Bit Definitions
Table 11. I/O Type Bit Definition specified in Address 2: Option Control Register
I/O Type Function
0 HSTL/SSTL
1POD
Table 12. Port Enable Bit Definition specified in Address 2: Option Control Register
Port Enable
[1:0] Function Port B
Mode
Port A
Mode
Port B
Clocks and
Controls
Port A
Clocks and
Controls
0 0 Fixed Port Mode Write Only Read Only DKB - On
QKB - Off
LDB# - On
RWB# - Off
DKA - Off
QKA - On
LDA# - On
RWA# - Off
0 1 Only Port A
Enable
Disabled Enabled DKB - Off
QKB - Off
LDB# - Off
RWB# - Off
DKA - On
QKA - On
LDA# - On
RWA# - On
1 0 Not supported Disabled Disabled DKB - Off
QKB - Off
LDB# - Off
RWB# - Off
DKA - Off
QKA - Off
LDA# - Off
RWA# - Off
1 1 Both Ports
Enabled
Enabled Enabled DKB - On
QKB - On
LDB# - On
RWB# - On
DKA - On
QKA - On
LDA# - On
RWA# - On
CY7C4121KV13/CY7C4141KV13
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ODT Termination Bit Definitions
Table 13. Clock Input Group Bit Definition specified in Address 0: Termination Control Register
ODT
Global
Enable
KU[2:0] Divisor
Value
Termination Value HSTL/SSTL
Mode Termination Value POD Mode
ZT 180 ohm ZT 220 ohm ZT 180 ohm ZT 220 ohm
0XXX– OFF OFF OFF OFF
1000– OFF OFF OFF OFF
10018.33%Not supported Not supported Not supported Not supported
101012.50%
Not supported Not supported Not supported Not supported
101116.67%
Not supported 40 ohm Not supported Not supported
110025%50 ohm 60 ohm 50 ohm 60 ohm
110150%
100 ohm 120 ohm 100 ohm 120 ohm
1110–
Not supported Not supported Not supported Not supported
1111–
Not supported Not supported Not supported Not supported
Note: Termination values are accurate to +/– 15%
ZQ tolerance is 1%
Table 14. Address/Command Input Group Bit Definition specified in Address 0: Termination Control Register
ODT
Global
Enable
IU[2:0] Divisor
Value
Termination Value HSTL/SSTL
Mode Termination Value POD Mode
ZT 180 ohm ZT 220 ohm ZT 180 ohm ZT 220 ohm
0XXX– OFF OFF OFF OFF
1000– OFF OFF OFF OFF
10018.33%
Not supported Not supported Not supported Not supported
101012.50%Not supported Not supported Not supported Not supported
101116.67%
Not supported 40 ohm Not supported Not supported
110025%
50 ohm 60 ohm 50 ohm 60 ohm
110150%100 ohm 120 ohm 100 ohm 120 ohm
1110–
Not supported Not supported Not supported Not supported
1111–
Not supported Not supported Not supported Not supported
Note: Termination values are accurate to +/– 15%
ZQ tolerance is 1%
Table 15. Data Input Group Bit Definition specified in Address 1: Impedance Control Register
ODT
Global
Enable
QU[2:0] Divisor
Value
Termination Value HSTL/SSTL
Mode Termination Value POD Mode
ZT 180 ohm ZT 220 ohm ZT 180 ohm ZT 220 ohm
0XXX– OFF OFF OFF OFF
1000– OFF OFF OFF OFF
10018.33%
Not supported Not supported Not supported Not supported
101012.50%
Not supported Not supported Not supported Not supported
101116.67%
Not supported 40 ohm Not supported Not supported
110025%
50 ohm 60 ohm 50 ohm 60 ohm
110150%
100 ohm 120 ohm 100 ohm 120 ohm
1110–
Not supported Not supported Not supported Not supported
1111–
Not supported Not supported Not supported Not supported
Note: Termination values are accurate to +/– 15%
ZQ tolerance is 1%
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 18 of 45
Drive Strength Bit Definitions
Table 16. Pull-Up Driver Bit Definition specified in Address 1: Impedance Control Register
PU[1:0] Divisor
Value
Impedance Value HSTL/SSTL Mode Impedance Value POD Mode
ZT 180 ohm ZT 220 ohm ZT 180 ohm ZT 220 ohm
0 0 14.17% Not Supported Not supported Not supported Not supported
0 1 16.67% Not Supported 40 ohm Not supported 40 ohm
1 0 25% 50 ohm 60 ohm 50 ohm 60 ohm
1 1 – Not Supported Not supported Not supported Not supported
Note: Termination values are accurate to +/– 15%
ZQ tolerance is 1%
Table 17. Pull-Down Driver Bit Definition specified in Address 1: Impedance Control Register
PD[1:0] Divisor
Value
Impedance Value HSTL/SSTL Mode Impedance Value POD Mode
ZT 180 ohm ZT 220 ohm ZT 180 ohm ZT 220 ohm
0 0 14.17% Not supported Not supported Not supported Not supported
0 1 16.67% Not supported 40 ohm Not supported 40 ohm
1 0 25% 50 ohm 60 ohm 50 ohm 60 ohm
1 1 – Not supported Not supported Not supported Not supported
Note: Termination values are accurate to +/– 15%
ZQ tolerance is 1%
CY7C4121KV13/CY7C4141KV13
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IEEE 1149.1 Serial Boundary Scan (JTAG)
QDR-IV HP SRAMs incorporate a serial boundary scan test
access port (TAP) in the FCBGA package. This part is fully
compliant with IEEE Standard #1149.1-2001. In the JTAG mode,
the ODT feature for all pins is disabled.
If the JTAG function is not used in the circuit, then the TCK inputs
must be driven low or tied to VSS. TRST#, TMS, TDI, and TDO
may be left floating. An internal pull-up resistor is implemented
on the TRST#, TMS, and TDI inputs to ensure that these inputs
are HIGH during tPWR.
Test Access Port
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 21. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 25).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Test Reset (TRST#)
The TRST# input pin is used to reset the TAP controller.
Alternatively, a reset may be performed by forcing TMS HIGH
(VDD) for five rising edges of TCK.
This reset does not affect the operation of the SRAM and can be
performed while the SRAM is operating. At power up, the TAP is
reset internally to ensure that TDO comes up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 22. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a RST state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
Boundary Scan Order on page 26 shows the order in which the
bits are connected. Each bit corresponds to one of the bumps on
the SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 25.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 25. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 20 of 45
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-RST state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High Z state until the next command is supplied during the
Update IR state. Both Port A and Port B are enabled once this
command has been executed.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
Remember that the TAP controller clock can only operate at a
frequency up to 20 MHz, while the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that an input or
output undergoes a transition during the Capture-DR state. The
TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device but there is no
guarantee as to the value that is captured. Repeatable results
may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state. Both Port A and Port B are
enabled after this command is executed.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has output enable control bits
located at Bit #49 and Bit #50. Bit# 49 enables the output pins
for DQB and Bit#50 enables DQA and PE# pins.
When these scan cells, called the “extest output bus tristate”, are
latched into the preload register during the Update-DR state in
the TAP controller, they directly control the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High Z condition.
These bits can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, these bits directly controls the
output Q-bus pins. Note that these bits are pre-set LOW to
disable the output when the device is powered up, and also when
the TAP controller is in the Test-Logic-RST state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
CY7C4121KV13/CY7C4141KV13
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TAP Controller State Diagram
Figure 4. TAP Controller State Diagram [3]
TEST-LOGIC
RST
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
1
0
1
1
0
1
0
1
0
0
0
1
1
1
0
10
10
0
0
1
0
1
1
0
1
0
0
1
1
0
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
Note
3. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 22 of 45
TAP Controller Block Diagram
Figure 5. TAP Controller Block Diagram
0
012..29
3031
Boundary Scan Register
Identification Register
012..
.
.135
012
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI TDO
TCK
TMS
TRST#
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Document Number: 001-79343 Rev. *Q Page 23 of 45
TAP Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min Max Unit
VOH LVCMOS high-level output
voltage
IOH =100 µA VDD × 0.8 – V
VOL LVCMOS low-level output voltage IOL = 100 µA – VDD × 0.2 V
VIH LVCMOS high-level input voltage
(DC)
VDD × 0.7 VDD + 0.2 V
VIL LVCMOS low-level input voltage
(DC)
–0.2 VDD × 0.3 V
IXLVCMOS input leakage current – 10 A
IOZ LVCMOS output leakage current – 10 A
TAP AC Switching Characteristics
Over the Operating Range
Parameter Description Min Max Unit
tTCYC TCK clock cycle time 50 – ns
tTF TCK clock frequency – 20 MHz
tTH TCK clock HIGH 20 – ns
tTL TCK clock LOW 20 – ns
Setup Times
tTMSS TMS setup to TCK clock rise 5 – ns
tTDIS TDI setup to TCK clock rise 5 – ns
tCS Capture setup to TCK rise 5 – ns
Hold Times
tTMSH TMS hold after TCK clock rise 5 – ns
tTDIH TDI hold after clock rise 5 – ns
tCH Capture hold after clock rise 5 – ns
Output Times
tTDOV TCK clock LOW to TDO valid –10 ns
tTDOX TCK clock LOW to TDO invalid 0 – ns
Note: tCS and tCH refer to setup and hold time requirements of latching data from the boundary scan register.
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 24 of 45
TAP Timing Diagram
Figure 6. TAP Timing Diagram
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 25 of 45
Identification Register Definitions
Instruction Field Value Description
CY7C4121KV13 CY7C4141KV13
Revision Number (31:29) 000 000 Version number.
Cypress Device ID (28:12) 11011010010010011 11011010010100011 Defines the type of SRAM.
Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM
vendor.
ID Register Presence (0) 1 1 Indicates the presence of an ID register.
Scan Register Sizes
Register Name Bit Size
Instruction 3
Bypass 1
ID 32
Boundary Scan 136
Instruction Codes
Instruction Code Description
EXTEST 000 Captures the input and output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 26 of 45
Boundary Scan Order
Bit Bump CY7C4141KV13 CY7C4121KV13
× 36 Device × 18 Device
012ADQA<26>DQA<17>
113BDQA<19>DQA<10>
214ADQA<25>DQA<16>
315BDQA<35>NC
416ADQA<23>DQA<14>
518BDQA<31>NC
6 17C QVLDA<1> QVLDA<1>
7 16C QKA<1> QKA<1>
8 14C DQA<20> DQA<11>
912CDQA<18>DQA<9>
10 12D DINVA<1> DINVA<1>
11 13D DQA<22> DQA<13>
12 15D DQA<21> DQA<12>
13 17D QKA#<1> QKA#<1>
14 18E DQA<32> NC
15 15F DQA<24> DQA<15>
16 16F DKA<1> DKA<1>
17 17F DKA#<1> DKA#<1>
18 18G DQA<33> NC
19 16G DQA<34> NC
20 17H DQA<27> NC
21 15H DQA<28> NC
22 16J DQA<30> NC
23 18J DQA<29> NC
24 18K RST# RST#
25 18L DQB<29> NC
26 16L DQB<30> NC
27 15M DQB<28> NC
28 17M DQB<27> NC
29 18N DQB<33> NC
30 16N DQB<34> NC
31 15P DQB<24> DQB<15>
32 16P DKB<1> DKB<1>
33 17P DKB#<1> DKB#<1>
34 18R DQB<32> NC
35 17T QKB#<1> QKB#<1>
36 15T DQB<21> DQB<12>
37 13T DQB<22> DQB<13>
38 12T DINVB<1> DINVB<1>
39 12U DQB<18> DQB<9>
40 14U DQB<20> DQB<11>
41 16U QKB<1> QKB<1>
42 17U QVLDB<1> QVLDB<1>
43 18V DQB<31> NC
44 15V DQB<35> NC
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 27 of 45
45 13V DQB<19> DQB<10>
46 12W DQB<26> DQB<17>
47 14W DQB<25> DQB<16>
48 16W DQB<23> DQB<14>
49 Internal_DQB Internal_DQB
50 Internal_DQA Internal_DQA
51 10V PE# PE#
52 8P A<15> A<15>
53 7N A<9> A<9>
54 9N NC/1152M NC/576M
55 10P AP AP
56 10N A<2> A<2>
57 11N NC/2304M NC/1152M
58 12P A<16> A<16>
59 13N A<10> A<10>
60 13L A<8> A<8>
61 12M A<12> A<12>
62 11L A<18> A<18>
63 10L RWB# RWB#
64 10M AINV AINV
65 9L A<17> A<17>
66 8M A<11> A<11>
67 7L A<7> A<7>
68 7J A<5> A<5>
69 9J A<19> A<19>
70 10K CK# CK#
71 10J CK CK
72 11J A<20> A<20>
73 13J A<6> A<6>
74 12H LDB# LDB#
75 10H RWA# RWA#
76 8H LDA# LDA#
77 7G A<3> A<3>
78 9G NC/288M A<21>
79 10G A<1> A<1>
80 11G NC/576M NC/288M
81 13G A<4> A<4>
82 12F A<14> A<14>
83 10F A<0> A<0>
84 8F A<13> A<13>
85 10D CFG# CFG#
86 10B LBK#<1> LBK#<1>
87 10A LBK#<0> LBK#<0>
88 8A DQA<8> DQA<8>
89 7B DQA<1> DQA<1>
90 6A DQA<7> DQA<7>
Boundary Scan Order (continued)
Bit Bump CY7C4141KV13 CY7C4121KV13
× 36 Device × 18 Device
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 28 of 45
91 5B DQA<17> NC
92 4A DQA<5> DQA<5>
93 2B DQA<13> NC
94 3C QVLDA<0> QVLDA<0>
95 4C QKA<0> QKA<0>
96 6C DQA<2> DQA<2>
97 8C DQA<0> DQA<0>
98 8D DINVA<0> DINVA<0>
99 7D DQA<4> DQA<4>
100 5D DQA<3> DQA<3>
101 3D QKA#<0> QKA#<0>
102 2E DQA<14> NC
103 3F DKA#<0> DKA#<0>
104 4F DKA<0> DKA<0>
105 5F DQA<6> DQA<6>
106 4G DQA<16> NC
107 2G DQA<15> NC
108 3H DQA<9> NC
109 5H DQA<10> NC
110 4J DQA<12> NC
111 2J DQA<11> NC
112 2L DQB<11> NC
113 4L DQB<12> NC
114 5M DQB<10> NC
115 3M DQB<9> NC
116 2N DQB<15> NC
117 4N DQB<16> NC
118 5P DQB<6> DQB<6>
119 4P DKB<0> DKB<0>
120 3P DKB#<0> DKB#<0>
121 2R DQB<14> NC
122 3T QKB#<0> QKB#<0>
123 5T DQB<3> DQB<3>
124 7T DQB<4> DQB<4>
125 8T DINVB<0> DINVB<0>
126 8U DQB<0> DQB<0>
127 6U DQB<2> DQB<2>
128 4U QKB<0> QKB<0>
129 3U QVLDB<0> QVLDB<0>
130 2V DQB<13> NC
131 5V DQB<17> NC
132 7V DQB<1> DQB<1>
133 8W DQB<8> DQB<8>
134 6W DQB<7> DQB<7>
135 4W DQB<5> DQB<5>
Boundary Scan Order (continued)
Bit Bump CY7C4141KV13 CY7C4121KV13
× 36 Device × 18 Device
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 29 of 45
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with Power Applied .................................. –55 °C to +125 °C
Maximum junction temperature ................................. 125 °C
Supply voltage
on VDD Relative to GND ............................–0.3 V to +1.35 V
Supply voltage
on VDDQ relative to GND ...........................–0.3 V to +1.35 V
DC input voltage ........................................–0.3 V to +1.35 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, M. 3015) ......................................... > 2001V
Latch-up current .................................................... > 200 mA
Operating Range
Range Ambient
Temperature (TA)VDD VDDQ
Commercial 0 °C to +70 °C 1.3V ±
40 mV
1.1 V ± 50 mV
1.2 V ± 50 mVIndustrial –40 °C to +85 °C
Neutron Soft Error Immunity
Parameter Description Test
Conditions Typ Max* Unit
LSBU Logical
single-bit
upsets
25 °C 0 0.01 FIT/
Mb
LMBU Logical
multi-bit
upsets
25 °C 0 0.01 FIT/
Mb
SEL Single event
latch-up
85 °C 0 0.1 FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to Application
Note, Accelerated Neutron SER Testing and Calculation of Terrestrial Failure
Rates – AN54908.
Electrical Characteristics
Over the Operating Range
Parameter Description Min Typ Max Unit
POD Signaling Mode
VDD[4] Core supply voltage (1.3 V ± 40 mV) 1.26 1.3 1.34 V
VDDQ [4] POD I/O supply voltage (1.1 V ± 50 mV) 1.05 1.1 1.15 V
POD I/O supply voltage (1.2 V ± 50 mV) 1.15 1.2 1.25 V
VREF [4, 5] POD reference voltage VDDQ × 0.69 VDDQ × 0.7 VDDQ × 0.71 V
VOL(DC) [4] POD low-level output voltage (DC) – – 0.5 V
VIH(DC) [4, 6] POD high-level input voltage (DC) VREF + 0.08 – VDDQ + 0.15 V
VIL(DC) [4, 6] POD low-level input voltage –0.15 – VREF – 0.08 V
VIH(AC) [4, 7] POD high-level input voltage (DC) VREF + 0.15 – – V
VIL(AC) [4, 7] POD low-level input voltage – – VREF – 0.15 V
VMP(DC) POD differential input mid-point voltage; Pin and Pin# VREF – 0.08 – VREF + 0.08 V
VID(DC) POD differential input differential voltage (DC); Pin and Pin# 0.16 – – V
VID(AC) POD differential input differential voltage (AC); Pin and Pin# 0.30 – – V
VIN POD single-ended input voltage; Pin and Pin# 0.27 – VDDQ + 0.15 V
VINS POD single-ended input voltage slew rate; Pin and Pin# 3 – – V/ns
VIX(AC) POD differential input crossing point voltage (AC); Pin and Pin# VREF – 0.08 – VREF + 0.08 V
Notes
4. All voltages referenced to VSS (GND).
5. Peak to Peak AC noise on VREF must not exceed ±2% VDDQ(DC).
6. VIH/VIL(DC) are specified with ODT disabled.
7. VIH/VIL(AC) is a test condition specified to guarantee at which the receiver must meet its timing specifications with ODT enabled.
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 30 of 45
IX [8] POD input leakage current – – 200 µA
IOZ [8] POD output leakage current – – 200 µA
IDD [9, 10] VDD operating supply (667 MHz, × 18) –1710 2500 mA
VDD operating supply (667 MHz, × 36) –2150 3200 mA
VDD operating supply (633 MHz, × 18) –1655 2400 mA
VDD operating supply (633 MHz, × 36) –2080 2950 mA
VDD operating supply (600 MHz, × 18) –1600 2300 mA
VDD operating supply (600 MHz, × 36) –2010 2700 mA
HSTL/SSTL Signaling Mode
VDD[11] Core supply voltage (1.3 V ± 40 mV) 1.26 1.3 1.34 V
VDDQ [11] I/O supply voltage (1.2 V ± 50 mV) 1.15 1.2 1.25 V
I/O supply voltage (1.25 V ± 50 mV) 1.2 1.25 1.3 V
VREF(DC) [11, 12] HSTL/SSTL reference voltage (DC) VDDQ × 0.48 VDDQ × 0.5 VDDQ × 0.52 V
VREF(AC) [11, 12] HSTL/SSTL reference voltage (AC) VDDQ × 0.47 VDDQ × 0.5 VDDQ × 0.53 V
VIH(DC) [11, 13] HSTL/SSTL high-level input voltage (DC) VREF + 0.08 – VDDQ + 0.15 V
VIL(DC) [11, 13] HSTL/SSTL low-level input voltage (DC) –0.15 – VREF – 0.08 V
VIH(AC) [11, 14] HSTL/SSTL high-level input voltage (AC) VREF + 0.15 – VDDQ + 0.24 V
VIL(AC) [11, 14] HSTL/SSTL low-level input voltage (AC) –0.24 – VREF – 0.15 V
VOH(DC) [11] HSTL/SSTL high-level output voltage (DC) –
IOH = –0.25 × VDDQ/ROH
VDDQ × 0.712 VDDQ × 0.75 – V
VOL(DC) [11] HSTL/SSTL low-level output voltage (DC) –
IOL = 0.25 × VDDQ/ROL
– VDDQ × 0.25 VDDQ × 0.288 V
VIX HSTL/SSTL input voltage cross point – VDDQ × 0.5 – V
VDIF(AC) HSTL/SSTL AC input differential voltage 0.30 – VDDQ + 0.48 V
VDIF(DC) HSTL/SSTL DC input differential voltage 0.16 – VDDQ + 0.30 V
VDIF(CM) HSTL/SSTL DC common mode input VDDQ × 0.4 VDDQ × 0.5 VDDQ × 0.6 V
VOX HSTL/SSTL output voltage cross point – VDDQ × 0.5 – V
VOUT(AC) HSTL/SSTL AC output voltage –0.24 – VDDQ + 0.24 V
VOUT(DC) HSTL/SSTL DC output voltage –0.15 – VDDQ + 0.15 V
IX [8] HSTL/SSTL input leakage current – – 200 µA
IOZ [8] HSTL/SSTL output leakage current – – 200 µA
IDD[9, 10] VDD operating supply (667 MHz, × 18) –1710 2500 mA
VDD operating supply (667 MHz, × 36) –2150 3200 mA
VDD operating supply (633 MHz, × 18) –1655 2400 mA
VDD operating supply (633 MHz, × 36) –2080 2950 mA
VDD operating supply (600 MHz, × 18) –1600 2300 mA
VDD operating supply (600 MHz, × 36) –2010 2700 mA
Electrical Characteristics (continued)
Over the Operating Range
Parameter Description Min Typ Max Unit
Notes
8. Output driver into High Z with ODT disabled.
9. The operation current is calculated with 50% read cycle and 50% write cycle.
10. Typical operation current specifications are tested at 1.3V VDD.
11. All voltages referenced to VSS (GND).
12. Peak to Peak AC noise on VREF must not exceed +/–2% VDDQ(DC).
13. VIH/VIL(DC) are specified with ODT disabled.
14. VIH/VIL(AC) is a test condition specified to guarantee at which the receiver must meet its timing specifications with ODT enabled.
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 31 of 45
Capacitance
Thermal Resistance
Table 18. Capacitance
Parameter [15] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VDD = 1.3 V, VDDQ = 1.25 V 4 pF
COOutput capacitance 4pF
Table 19. Thermal Resistance
Parameter [15] Description Test Conditions 361-ball FCBGA
Package Unit
JA Thermal resistance
(junction to ambient)
Test conditions follow standard
test methods and procedures for
measuring thermal impedance, in
accordance with EIA/JESD51.
With Still Air (0 m/s) 12.00 °C/W
With Air Flow (1 m/s) 10.57 °C/W
With Air Flow (3 m/s) 9.09 °C/W
JB Thermal resistance
(junction to board)
3.03 °C/W
JC Thermal resistance
(junction to case)
0.029 °C/W
AC Test Load and Waveform
Figure 7. AC Test Loads and Waveforms
Note
15. Tested initially and after any design or process change that may affect these parameters.
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 32 of 45
Switching Characteristics
Over the Operating Range [16, 17, 18, 19, 20, 21, 22, 23]
Cypress
Parameter Description 667 MHz 633 MHz 600 MHz Unit
Min Max Min Max Min Max
tCK CK, DKx, QKx clock period 1.5 3.333 1.58 3.333 1.667 3.333 ns
tCKL CK, DKx LOW time 0.45* –0.45* –0.45* – tCK
tCKH CK, DKx HIGH time 0.45* –0.45* –0.45* – tCK
tJIT(per) Clock period jitter –0.070 0.070 –0.075 0.075 –0.080 0.080 ns
tJIT(cc) Cycle-to-cycle jitter –0.140 –0.150 –0.160 ns
tAS A to CK setup 0.160 –0.170 –0.180 –ns
tAH CK to A hold 0.160 –0.170 –0.180 –ns
tASH CK to A setup-hold window 0.130 –0.135 –0.140 –ns
tCS LDx#, RWx# to CK setup 0.200 –0.220 –0.240 –ns
tCH CK to LDx#, RWx# hold 0.200 –0.220 –0.240 –ns
tCSH CK to LDx#, RWx# setup-hold window 0.130 –0.135 –0.140 –ns
tCKDK CK to DKx skew –0.24 0.24 –0.254 0.254 –0.267 0.267 ns
tIS DQx, DINVx to DKx setup 0.160 –0.170 –0.180 –ns
tIH DKx to DQx, DINVx hold 0.160 –0.170 –0.180 –ns
tISH0 DKx[0] to DQx[17:0], DINVx[0] (×36) or
DKx[0] to DQx[8:0], DINVx[0] (×18) setup-hold window
0.150 –0.155 –0.160 –ns
tISH1 DKx[1] to DQx[35:18], DINVx[1] (×36) or
DKx[1] to DQx[17:9], DINVx[1] (×18) setup-hold
window
0.150 –0.155 –0.160 –ns
tRise (se) Single-ended output signal rise time 20%-80% 2 6 2 6 2 6 V/ns
tFall (se) Single-ended output signal fall time 20%-80% 2 6 2 6 2 6 V/ns
tRise (diff) Differential output signal rise time 20%-80% 310 310 310 V/ns
tFall (diff) Differential output signal fall time 20%-80% 310 310 310 V/ns
tQKL QKx LOW time 0.45* –0.45* –0.45* – tCK
tQKH QKx HIGH time 0.45* –0.45* –0.45* – tCK
tCKQK CK to QKx skew –0.358 0.358 –0.380 0.380 –0.400 0.400 ns
tQKQ0 QKx[0] to DQx[17:0], DINVx[0] (×36) or
QKx[0] to DQx[8:0], DINVx[0] (×18)
–0.120 –0.126 –0.132 ns
tQH0 QKx[0] to DQx[17:0], DINVx[0] (×36) or
QKx[0] to DQx[8:0], DINVx[0] (×18)
0.40* –0.40* –0.40* – tCK
tQKQ1 QKx[1] to DQx[35:18], DINVx[1] (×36) or
QKx[1] to DQx[17:9], DINVx[1] (×18)
–0.120 –0.126 –0.132 ns
tQH1 QKx[1] to DQx[35:18], DINVx[1] (×36) or
QKx[1] to DQx[17:9], DINVx[1] (×18)
0.40* –0.40* –0.40* – tCK
Notes
16. x refers to Port A and Port B. For example, DQx refers to DQA and DQB.
17. All input hold timing assumes rising edge slew rate of 4V/ns measured from VIL/VIH (DC) to VREF
.
18. All input setup timing assumes falling edge slew rate of 4V/ns measured from VREF to VIL/VIH (AC).
19. All output timing assumes the load shown in Figure 8.
20. Setup/hold window, tASH, tCSH, tISH are used for pin to pin timing budgeting and cannot be directly applied without performing de-skew training.
21. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
22. Frequency drift is not allowed.
23. tQKL, tQKH,tQKQ, tQKQX, tASH, tCSH, and tISH are guaranteed by design.
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 33 of 45
tQKQV0 QKx[0] to QVLDx –0.150 –0.175 –0.200 ns
tQVH0 QKx[0] to QVLDx 0.85* –0.85* –0.85* – tCK
tQKQV1 QKx[1] to QVLDx –0.150 –0.175 –0.200 ns
tQVH1 QKx[1] to QVLDx 0.85* –0.85* –0.85* – tCK
tPWR VDD (Typical) to the first access 200 –200 –200 –ms
tRSS RST# pulse width 200 –200 –200 –µs
tRSH RST# deasserted to first active command 400000
*
–400000
*
–400000
*
– tCK
tRDS A to RST# setup 500* –500* –500* – tCK
tRDH A to RST# hold 500* –500* –500* – tCK
tTSS TRST# pulse width 200 –200 –200 –µs
tTSH TRST# deasserted to first JTAG command 200 –200 –200 –µs
tPLL Time for PLL to stabilize after being reset –100 –100 –100 µs
tLBL Loopback latency 16* 16* 16* 16* 16* 16* tCK
tCD Loopback output delay – 5 – 5 – 5 ns
tCFGS Active mode to Configuration mode 32* –32* –32* – tCK
tCFGH Configuration mode to Active mode Register Access
without ODT or PLL programming updates
32* –32* –32* – tCK
tCFGH Configuration mode to Active mode Register Access
with ODT programming updates
4096* –4096* –4096* – tCK
tCFGH Configuration mode to Active mode Register Access
with PLL programming updates
100 –100 –100 –µs
tCFGD Configuration command to Configuration command 80* –80* –80* – tCK
tCLDS CFG# assertion to LDA# assertion 32* –32* –32* – tCK
tCLDH LDA# deassertion to CFG# deassertion 32* –32* –32* – tCK
tCFGA CFG# assertion to Address assertion 16* –16* – tCK
tCLDW LDA# pulse width for Configuration command 16* –16* –16* – tCK
tCRDL LDA# assertion to Read Data Latency –32* –32* –32* tCK
tCRDH CFG# deassertion to Read Data Hold 0* 32* 0* 32* 0* 32* tCK
tDQVLD DQAx to QVLDA<0> in Configuration mode –2 2–2 2–2 2 tCK
Switching Characteristics (continued)
Over the Operating Range [16, 17, 18, 19, 20, 21, 22, 23]
Cypress
Parameter Description 667 MHz 633 MHz 600 MHz Unit
Min Max Min Max Min Max
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 34 of 45
Switching Waveforms
Figure 8. Rise and Fall Time Definitions for Output Signals
Nominal Rise-Fall Time Definition for Single-Ended Output Signals
Nominal Rise-Fall Time Definition for Differential Output Signals
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 35 of 45
Figure 9. Input and Output Timing Waveforms
Switching Waveforms (continued)
Address and Command Input Timin
g
Data Input Timing
Data Output Timing
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 36 of 45
Figure 10. Waveforms for 5.0 Cycle Read Latency (Read to Write Timing Waveform)
Figure 11. Waveforms for 5.0 Cycle Read Latency (Write to Read Timing Waveform)
Switching Waveforms (continued)
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 37 of 45
Figure 12. Configuration Write Timing Waveform
Figure 13. Configuration Read Timing Waveform
Switching Waveforms (continued)
Note: It is recommended to keep CFG# asserted during the configuration write or read operation
Note: DQA[x:8] and DQB data bus is a don’t care in Configuration Mode
Note: It is recommended to keep CFG# asserted during the configuration write or read operation
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 38 of 45
Figure 14. Configuration Write and Read Timing Waveform
Switching Waveforms (continued)
Note: DQA[x:8] and DQB data bus is a don’t care in Configuration Mode
Note: DQA[x:8] and DQB data bus is a don’t care in Configuration Mode
(a) Configuration Multiple Cycle - Write followed by Read Operation
(b) Configuration Multiple Cycle - Back to Back Read Operation
Note: It is recommended to keep CFG# asserted during the configuration write or read operation
Note: It is recommended to keep CFG# asserted during the configuration write or read operation
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 39 of 45
Figure 15. Loopback TIming
Switching Waveforms (continued)
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 40 of 45
Figure 16. Reset TImings
Switching Waveforms (continued)
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 41 of 45
Ordering Code Definitions
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page
at http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Table 20. Ordering Information
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
667 CY7C4121KV13-667FCXC 001-70319 361-ball FCBGA (21 × 21 × 2.515 mm) Pb-free Commercial
CY7C4141KV13-667FCXC
633 CY7C4121KV13-633FCXI 001-70319 361-ball FCBGA (21 × 21 × 2.515 mm) Pb-free Industrial
CY7C4141KV13-633FCXI
600 CY7C4121KV13-600FCXC 001-70319 361-ball FCBGA (21 × 21 × 2.515 mm) Pb-free Commercial
CY7C4141KV13-600FCXC
CY 7C41x1KV13 -XXX FC X X
Temperature Range : X= C or I;
C = Commercial or I = Industrial;
Pb-free
Package Type: 361-ball Flip Chip BGA
Speed Grade: 667 = 667 MHz or 633 = 633 MHz
or 600 = 600 MHz
VDD = 1.3 V
Die Revision: K = 65nm
Part Identifier: 4121 or 4141
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 42 of 45
Package Diagram
Figure 17. 361-ball FCBGA (21 × 21 × 2.515 mm) FR0AA Package Outline, 001-70319
001-70319 *D
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 43 of 45
Acronyms Document Conventions
Units of Measure
Table 21. Acronyms used in this document
Acronym Description
DDR Double Data Rate
RTR Random Transaction Rate
EIA Electronic Industries Alliance
EMI Electromagnetic Interference
FCBGA Flip-Chip Ball Grid Array
I/O Input/Output
JEDEC Joint Electron Devices Engineering Council
JTAG Joint Test Action Group
LMBU Logical Multiple Bit Upset
LSB Least Significant Bit
LSBU Logical Single Bit Upset
MSB Most Significant Bit
ODT On-Die Termination
PLL Phase Locked Loop
QDR Quad Data Rate
SDR Single Data Rate
SEL Single Event Latch-up
SER Soft Error Rate
SRAM Static Random Access Memory
TAP Test Access Port
TCK Test Clock
TDI Test Data-In
TDO Test Data-Out
TMS Test Mode Select
Table 22. Units of Measure
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
µs microsecond
mA milliampere
mm millimeter
ms millisecond
mV millivolt
ns nanosecond
ohm
% percent
pF picofarad
Vvolt
Wwatt
CY7C4121KV13/CY7C4141KV13
Document Number: 001-79343 Rev. *Q Page 44 of 45
Document History Page
Document Title: CY7C4121KV13/CY7C4141KV13, 144-Mbit QDR™-IV HP SRAM
Document Number: 001-79343
Rev. ECN Submission
Date
Orig. of
Change Description of Change
*I 4283232 03/25/2014 PRIT Post to web.
*J 4410859 06/17/2014 PRIT Updated AC Test Load and Waveform:
Updated Figure 7 (Changed value of RQ resistor from 200 to 180 ).
Updated Switching Characteristics:
Added tASH, tCSH, tISH parameters and their details.
Updated Note 20 and 23.
Completing Sunset Review.
*K 4502995 09/15/2014 PRIT Updated Switching Characteristics:
Updated Note 23.
Updated Package Diagram:
spec 001-70319 – Changed revision from *C to *D.
*L 4573944 11/19/2014 PRIT Updated Functional Description:
Added “For a complete list of related resources, click here.” at the end.
Added Errata.
*M 4710814 04/02/2015 PRIT Updated Operating Range:
Replaced “Case Temperature (TC)” with “Ambient Temperature (TA)” in column
heading.
*N 4951439 10/07/2015 PRIT Added Industrial Temperature Range related information in all instances across
the document.
Added 633 MHz speed bin related information in all instances across the
document.
Updated Logic Block Diagram – CY7C4141KV13.
Updated Electrical Characteristics:
Added values of IDD parameter corresponding to 633 MHz speed bin.
Updated Switching Characteristics:
Changed maximum value of tCK parameter from 3.0 ns to 3.333 ns for 667 MHz
speed bin.
Added values of all parameters corresponding to 633 MHz speed bin.
Updated Ordering Information:
Updated part numbers.
Removed Errata.
Updated to new template.
*O 5183472 03/21/2016 DEVM Updated Identification Register Definitions:
Updated details in “Value” column corresponding to the Instruction Field
“Cypress Device ID (28:12)”.
Updated to new template.
*P 5381153 07/29/2016 PRIT Updated Switching Characteristics:
Added tCFGA parameter and its details.
Updated Switching Waveforms:
Updated Figure 12, Figure 13, and Figure 14.
*Q 5844330 08/04/2017 AJU Updated to new template.
Completing Sunset Review.
Document Number: 001-79343 Rev. *Q Revised August 4, 2017 Page 45 of 45
CY7C4121KV13/CY7C4141KV13
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