1
FEATURES
APPLICATIONS
3 V–13 V
FAULT
typical application
NOTE: Terminal 13 is active-high on TPS2331.
VREG
IN ISET ISENSE GATE DISCH VSENSE
PWRGD
TIMER
DGND
AGND
VIN
TPS2330
+VO
1
2
3
4
5
6
7
14
13
12
11
10
9
8
GATE
DGND
TIMER
VREG
VSENSE
AGND
ISENSE
DISCH
ENABLE
PWRGD
FAULT
ISET
AGND
IN
D OR PW PACKAGE
(TOP VIEW)
ENABLE
DESCRIPTION
TPS2330
TPS2331
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............................................................................................................................................... SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006
SINGLE HOT-SWAP POWER CONTROLLERS WITHCIRCUIT BREAKER AND POWER-GOOD REPORTING
•Single-Channel High-Side MOSFET Driver•Input Voltage: 3 V to 13 V•Output dV/dt Control Limits Inrush Current•Circuit-Breaker With ProgrammableOvercurrent Threshold and Transient Timer•Power-Good Reporting With Transient Filter•CMOS- and TTL-Compatible Enable Input•Low 5- µA Standby Supply Current (Max)•Available in 14-Pin SOIC and TSSOP Package•– 40 ° C to 85 ° C Ambient Temperature Range•Electrostatic Discharge Protection
•Hot-Swap/Plug/Dock Power Management•Hot-Plug PCI, Device Bay•Electronic Circuit Breaker
The TPS2330 and TPS2331 are single-channel hot-swap controllers that use external N-channel MOSFETs ashigh-side switches in power applications. Features of these devices, such as overcurrent protection (OCP),inrush-current control, output-power status reporting, and the ability to discriminate between load transients andfaults, are critical requirements for hot-swap applications.
The TPS2330/31 devices incorporate undervoltage lockout (UVLO) and power-good (PG) reporting to ensure thedevice is off at start-up and confirm the status of the output voltage rails during operation. An internal chargepump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance the N-channelMOSFETs. The charge pump controls both the rise times and fall times (dv/dt) of the MOSFETs, reducing powertransients during power up/down. The circuit-breaker functionality combines the ability to sense overcurrentconditions with a timer function; this allows designs such as DSPs, that may have high peak currents duringpower-state transitions, to disregard transients for a programmable period.
AVAILABLE OPTIONS
PACKAGES
(1)
T
A
HOT-SWAP CONTROLLER DESCRIPTION PIN COUNT
ENABLE ENABLE
Dual-channel with independent OCP and adjustable PG 20 TPS2300IPW TPS2301IPW
Dual-channel with interdependent OCP and adjustable PG 20 TPS2310IPW TPS2311IPW
TPS2320ID TPS2321ID– 40 ° C to 85 ° C
Dual-channel with independent OCP 16
TPS2320IPW TPS2321IPW
TPS2330ID TPS2331IDSingle-channel with OCP and adjustable PG 14
TPS2330IPW TPS2331IPW
(1) The packages are available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TPS2331IPWR).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000 – 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
FUNCTIONAL BLOCK DIAGRAM
PREREG
UVLO and
Power Up
IN ISET ISENSE GATE
Clamp
Charge
Pump
75 µA
Pulldown FET
Circuit Breaker
dv/dt Rate
Protection
Deglitcher
DISCH
Logic
VSENSE
PWRGD
FAULT
TIMER
Circuit
Breaker
VREG
Deglitcher
AGND
DGND
ENABLE
50 µA
TPS2330
TPS2331
SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006 ...............................................................................................................................................
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Table 1. Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME NO.
AGND 6, 9 I Analog ground, connects to DGND as close as possibleDGND 2 I Digital groundDISCH 14 O Discharge transistorENABLE/ ENABLE 13 I Active-low (TPS2330) or active-high enable (TPS2331)FAULT 11 O Overcurrent fault, open-drain outputGATE 1 O Connects to gate of high-side MOSFETIN 8 I Input voltageISENSE 7 I Current-sense inputISET 10 I Adjusts circuit-breaker threshold with resistor connected to INPWRGD 12 O Open-drain output, asserted low when VSENSE voltage is less than reference.TIMER 3 O Adjusts circuit-breaker deglitch timeVREG 4 O Connects to bypass capacitor, for stable operationVSENSE 5 I Power-good sense input
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DETAILED DESCRIPTION
TPS2330
TPS2331
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............................................................................................................................................... SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006
DISCH – DISCH should be connected to the source of the external N-channel MOSFET transistor connected toGATE. This pin discharges the load when the MOSFET transistor is disabled. They also serve asreference-voltage connection for internal gate-voltage-clamp circuitry.
ENABLE or ENABLE – ENABLE for TPS2330 is active-low. ENABLE for TPS2331 is active-high. When thecontroller is enabled, GATE voltage powers up to turn on the external MOSFETs. When the ENABLE pin ispulled high for TPS2330 or the ENABLE pin is pulled low for TPS2331 for more than 50 µ s, the gate of theMOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge theoutput bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) whenenabled and shuts down PREREG when disabled so that total supply current is much less than 5 µA.
FAULT – FAULT is an open-drain overcurrent flag output. When an overcurrent condition is sustained longenough to charge TIMER to 0.5 V, the device latches off and pulls FAULT low. In order to turn the device backon, either the enable pin must be toggled or the input power must be cycled.
GATE – GATE connects to the gate of the external N-channel MOSFET transistor. When the device is enabled,internal charge-pump circuitry pulls this pin up by sourcing approximately 15 µA. The turnon slew rates dependupon the capacitance present at the GATE terminal. If desired, the turnon slew rates can be further reduced byconnecting capacitors between this pin and ground. These capacitors also reduce inrush current and protect thedevice from false overcurrent triggering during power up. The charge-pump circuitry generates gate-to-sourcevoltages of 9 V – 12 V across the external MOSFET transistor.
IN – IN should be connected to the power source driving the external N-channel MOSFET transistor connectedto GATE. The TPS2330/31 draws its operating current from IN, and remains disabled until the IN power supplyhas been established. The device has been constructed to support 3-V, 5-V, or 12-V operation.
ISENSE, ISET – ISENSE in combination with ISET implements overcurrent sensing for GATE. ISET sets themagnitude of the current that generates an overcurrent fault, through a external resistor connected to ISET. Aninternal current source draws 50 µA from ISET. With a sense resistor from IN to ISENSE, which is alsoconnected to the drain of the external MOSFET, the voltage on the sense resistor reflects the load current. Anovercurrent condition is assumed to exist if ISENSE is pulled below ISET.
PWRGD – PWRGD signals the presence of undervoltage conditions on VSENSE. The pin is an open-drainoutput and is pulled low during an undervoltage condition. To minimize erroneous PWRGD responses fromtransients on the voltage rail, the voltage sense circuit incorporates a 20- µs deglitch filter. When VSENSE islower than the reference voltage (about 1.23 V), PWRGD is active-low to indicate an undervoltage condition onthe power-rail voltage. PWRGD may not correctly report power conditions when the device is disabled becausethere is no gate drive power for the PWRGD output transistor in the disable mode, or, in other words, PWRGD isfloating. Therefore, PWRGD is pulled up to its pullup power supply rail in disable mode.
TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turningoff. When the overcurrent protection circuits sense an excessive current, a current source is enabled whichcharges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breakerlatch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled torestart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is stronglyrecommended from TIMER to ground, to prevent any false triggering.
VREG – VREG is the output of an internal low-dropout voltage regulator, where IN1 is the input. The regulator isused to generate a regulated voltage source, less than 5.5 V, for the device. A 0.1- µF ceramic capacitor shouldbe connected between VREG and ground to aid in noise rejection. In this configuration, upon disabling thedevice, the internal low-dropout regulator also is disabled, which removes power from the internal circuitry andallows the device to be placed in low-quiescent-current mode. In applications where IN1 is less than 5.5 V,VREG and IN1 may be connected together. However, under these conditions, disabling the device may not placethe device in low-quiescent-current mode, because the internal low-dropout voltage regulator is being bypassed,thereby keeping internal circuitry operational. If VREG and IN1 are connected together, a 0.1- µF ceramiccapacitor between VREG and ground is not needed if IN1 already has a bypass capacitor of 1 µF to 10 µF.
VSENSE – VSENSE can be used to detect undervoltage conditions on external circuitry. If VSENSE senses avoltage below approximately 1.23 V, PWRGD is pulled low.
Copyright © 2000 – 2006, Texas Instruments Incorporated Submit Documentation Feedback 3
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
TPS2330
TPS2331
SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006 ...............................................................................................................................................
www.ti.com
over operating free-air temperature range (unless otherwise noted)
(1) (2)
VALUE UNIT
V
I(IN1)
, V
I(ISENSE)
, V
I(VSENSE)
, V
I(ISET)
, V
I(ENABLE)
, – 0.3 to 15 VInput voltage range
V
I(VREG)
– 0.3 to 7 VV
O(GATE)
– 0.3 to 30 VOutput voltage range
V
O(DISCH)
, V
O(PWRGD)
, V
O(FAULT)
, V
O(TIMER)
– 0.3 to 15 VI
(GATE)
, I
(DISCH)
0 to 100 mASink current range
I
(PWRGD)
, I
(TIMER)
, I
(FAULT)
0 to 10 mAOperating virtual junction temperature range, T
J
– 40 to 100 ° CStorage temperature range, T
stg
– 55 to 150 ° CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are respect to DGND.
T
A
≤25 ° C DERATING FACTOR T
A
= 70 ° C T
A
= 85 ° CPACKAGE
POWER RATING ABOVE T
A
= 25 ° C POWER RATING POWER RATING
PW-14 755 mW 10.07 mW/ ° C 302 mW 151 mWD-14 613 mW 8.18 mW/ ° C 245 mW 123 mW
MIN NOM MAX UNIT
V
I(IN)
, V
I(ISENSE)
, V
I(VSENSE)
, V
I(ISET)
3 13V
I
Input voltage VV
I(VREG)
3 5.5T
J
Operating virtual junction temperature 40 100 ° C
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ELECTRICAL CHARACTERISTICS
(2) Test I
O
of ENABLE at V
I(ENABLE)
= 1 V and 0 V, then R
I(ENABLE)
=
1 V
IO_0V *IO_1V
TPS2330
TPS2331
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............................................................................................................................................... SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006
over recommended operating temperature range ( – 40 ° C < T
A
< 85 ° C), 3V ≤V
I(IN1)
≤13V, 3V ≤V
I(IN2)
≤5.5V (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GENERAL
V
I(ENABLE)
= 5 V (TPS2331),I
I(IN)
Input current, IN 0.5 1 mAV
I(ENABLE)
= 0 V (TPS2330)
Standby current (sum of currents into V
I(ENABLE)
= 0 V (TPS2331),I
I(stby)
5 µ AIN, ISENSE, and ISET) V
I(ENABLE)
= 5 V (TPS2330)
GATE
V
G(GATE_3V)
V
I(IN)
= 3 V 9 11.5
V
G(GATE_4.5V)
Gate voltage I
I(GATE)
= 500 nA, DISCH open V
I(IN)
= 4.5 V 10.5 14.5 V
V
G(GATE_10.8V)
V
I(IN)
= 10.8 V 16.8 21
V
C(GATE)
Clamping voltage, GATE to DISCH 9 10 12 V
3 V ≤V
I(IN)
≤13.2 V, 3 V ≤V
O(VREG)
≤5.5 V,I
S(GATE)
Source current, GATE 10 14 20 µAV
I(GATE)
= V
I(IN)
+ 6 V
3 V ≤V
I(IN)
≤13.2 V, 3 V ≤V
O(VREG)
≤5.5 V,Sink current, GATE 50 75 100 µ AV
I(GATE)
= V
I(IN)
V
I(IN)
= 3 V 0.5
t
r(GATE)
Rise time, GATE C
g
to GND = 1 nF
(1)
V
I(IN)
= 4.5 V 0.6 ms
V
I(IN)
= 10.8 V 1
V
I(IN)
= 3 V 0.1
t
f(GATE)
Fall time, GATE C
g
to GND = 1 nF
(1)
V
I(IN)
= 4.5 V 0.12 ms
V
I(IN)
= 10.8 V 0.2
TIMER
V
(TO_TIMER)
Threshold voltage, TIMER 0.4 0.5 0.6 V
Charge current, TIMER V
I(TIMER)
= 0 V 35 50 65 µ A
Discharge current, TIMER V
I(TIMER)
= 1 V 1 2.5 mA
CIRCUIT BREAKER
R
ISET
= 1 k Ω40 50 60
R
ISET
= 400 Ω, T
A
= 25 ° C 14 19 24V
IT(CB)
Threshold voltage, circuit breaker mVR
ISET
= 1 k Ω, T
A
= 25 ° C 44 50 53
R
ISET
= 1.5 k Ω, T
A
= 25 ° C 68 73 78
I
(IB_ISENSE)
Input bias current, I
SENSE
0.1 5 µ A
V
O(GATE)
= 4 V 400 800Discharge current, GATE mAV
O(GATE)
= 1 V 25 150
Propagation (delay) time, comparator C
g
= 50 pF, 10 mV overdrive,t
pd(CB)
1.3 µ sinputs to gate output (50% to 10%), C
TIMER
= 50 pF
ENABLE, ACTIVE LOW (TPS2330)
V
IH(ENABLE)
High-level input voltage, ENABLE 2 V
V
IL(ENABLE)
Low-level input voltage, ENABLE 0.8 V
R
I(ENABLE)
Input pullup resistance, ENABLE See
(2)
100 200 300 k Ω
Turnoff delay time, ENABLE V
I(ENABLE)
increasing above stop threshold;t
d(off_ENABLE)
60 µs100 ns rise time, 20 mV overdrive
(1)
Turnon delay time, ENABLE V
I(ENABLE)
decreasing below start threshold;t
d(on_ENABLE)
125 µs100 ns fall time, 20 mV overdrive
(1)
(1) Specified, but not production tested.
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ELECTRICAL CHARACTERISTICS (Continued)
TPS2330
TPS2331
SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006 ...............................................................................................................................................
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over recommended operating temperature range ( – 40 ° C < T
A
< 85 ° C), 3V ≤V
I(IN1)
≤13V, 3V ≤V
I(IN2)
≤5.5V (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ENABLE, ACTIVE HIGH (TPS2331)
V
IH(ENABLE)
High-level input voltage, ENABLE 2 VV
IL(ENABLE)
Low-level input voltage, ENABLE 0.7 VR
I(ENABLE)
Input pulldown resistance, ENABLE 100 150 300 k Ω
V
I(ENABLE)
increasing above start threshold;t
d(on_ENABLE)
Turnon delay time, ENABLE 85 µs100 ns rise time, 20 mV overdrive
(1)
V
I(ENABLE)
decreasing below stop threshold;t
d(off_ENABLE)
Turnoff delay time, ENABLE 100 µ s100 ns fall time, 20 mV overdrive
(1)
PREREG
V
(VREG)
PREREG output voltage 4.5 ≤V
I(IN)
≤13 V 3.5 4.1 5.5 VV
(drop_PREREG)
PREREG dropout voltage V
I(IN)
= 3 V 0.1 V
VREG UVLO
V
(TO_UVLOstart)
Output threshold voltage, start 2.75 2.85 2.95 VV
(TO_UVLOstop)
Output threshold voltage, stop 2.65 2.78 VV
hys(UVLO)
Hysteresis 50 75 mVUVLO sink current, GATE V
I(GATE)
= 2 V 10 mA
PWRGD1 and PWRGD2
V
I(VSENSE)
decreasing 1.22V
IT(ISENSE)
Trip threshold, VSENSE 1.2 1.25 V5Hysteresis voltage, power-goodV
hys
20 30 40 mVcomparatorV
O(sat_PWRGD)
Output saturation voltage, PWRGD I
O
= 2 mA 0.2 0.4 VMinimum V
O(VREG)
for valid I
O
= 100 µA, V
O(PWRGD)
= 1 VV
O(VREG_min)
1 Vpower-good
Input bias current, power-good V
I(VSENSE)
= 5.5 V
1µAcomparatorI
lkg(PWRGD)
Leakage current, PWRGD V
O(PWRGD)
= 13 V 1 µAV
I(VSENSE)
increasing, Overdrive = 20 mV,t
dr
Delay time, rising edge, PWRGD 25 µst
r
= 100 ns
(1)
V
I(VSENSEx)
decreasing,Overdrive = 20 mV,t
df
Delay time, falling edge, PWRGDx 2 µst
r
= 100 ns
(1)
FAULT OUTPUT
V
O(sat_FAULT)
Output saturation voltage, FAULT I
O
= 2 mA 0.4 VI
lkg(FAULT)
Leakage current, FAULT V
O(FAULT)
= 13 V 1 µ A
DISCH
I
(DISCH)
Discharge current, DISCH V
I(DISCH)
= 1.5 V, V
I(VIN)
= 5 V 5 10 mAV
IH(DISCH)
Discharge on high-level input voltage 2 VV
IL(DISCH)
Discharge on low-level input voltage 1 V
(1) Specified, but not production tested.
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PARAMETER MEASUREMENT INFORMATION
V
5V/div
I( )ENABLE
V
10V/div
O(GATE)
V
5V/div
O(DISCH)
t – Time – 10ms/div
Load12 W
V
5V/div
I( )ENABLE
V
10V/div
O(GATE)
V
5V/div
O(DISCH)
t – Time – 10ms/div
Load12 W
V
5V/div
I( )ENABLE
V
10V/div
O( )FAULT
V
10V/div
O(GATE)
I
2 A/div
O(OUT)
t – Time – 5ms/div
NoCapacitoronTimer
V
5V/div
I( )ENABLE
V
10V/div
O( )FAULT
V
10V/div
O(GATE)
I
2 A/div
O(OUT)
t – Time – 1ms/div
NoCapacitoronTimer
TPS2330
TPS2331
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............................................................................................................................................... SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006
Figure 1. Turnon Voltage Transition Figure 2. Turnoff Voltage Transition
Figure 3. Overcurrent Response: Figure 4. Overcurrent Response: an OvercurrentEnabled Into Overcurrent Load Load Plugged Into the Enabled Board
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V
5V/div
I( )ENABLE
V
10V/div
O( )FAULT
V
10V/div
O(GATE)
I
2 A/div
I(IN)
t – Time – 1ms/div
NoCapacitoronTimer
V
10V/div
I(IN)
V
10V/div
O(OUT)
V
10V/div
O(GATE)
I
1 A/div
O(OUT)
t – Time – 5ms/div
NoCapacitoronTimer
V
10V/div
I(IN)
V
10V/div
O(OUT)
V
10V/div
O(GATE)
I
1 A/div
O(OUT)
t – Time – 1ms/div
NoCapacitoronTimer
TPS2330
TPS2331
SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006 ...............................................................................................................................................
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PARAMETER MEASUREMENT INFORMATION (continued)
Figure 5. Enabled Into Short Circuit Figure 6. Hot Plug
Figure 7. Hot Removal
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TYPICAL CHARACTERISTICS
49
46
45
43
4 5 6 7 8 9 10
I– InputCurrent – A
Im
50
51
52
11 12 13 14
48
47
44
V – InputV
Ioltage – V
IN=5Vto13V
TA=85°C
TA=25°C
TA=0°C
TA= –40°C
I– InputCurrent – nA
I
V – InputV
Ioltage – V
TA=85°C
TA=25°C
TA=0°C
TA= –40°C
IN=5Vto13V
4 5 6 7 8 9 10 11 12 13 14
15
14
13
12
11
10
9
8
7
16
14
12
10
2 3 4 5 6 7 8
–GATEOutputVoltage – V
18
20
22
9 10 11 12
VO
VI– InputVoltage – V
TA=85°C
TA=25°C
TA=0°C
TA= –40°C
CL(GATE) =1000pF
0 3 6 9 12
18
15
12
9
6
3
0
–GATEVoltageRiseTime – mstr
C – GATELoadCapacitance
L(GATE) – nF
IN=12V
T =25 C
A
°
TPS2330
TPS2331
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............................................................................................................................................... SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006
INPUT CURRENT (ENABLED) INPUT CURRENT (DISABLED)vs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 8. Figure 9.
GATE OUTPUT VOLTAGE GATE VOLTAGE RISE TIMEvs vsINPUT VOLTAGE GATE LOAD CAPACITANCE
Figure 10. Figure 11.
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V – GATEVoltage – V
13.5
13
12
11
14 15 16 17 18 19 20
I– GA
OTEOutputCurrent – Am
14
14.5
15
21 22 23 24
12.5
11.5
TA=85°C
TA=25°C
TA=0°C
TA= –40°C
IN=13V
1
0
0 3 6
2
3
4
9 12
–GATEVoltageFallTime – mstf
CL(GATE) – GATELoadCapacitance – nF
IN=12V
TA=25°C
6
3
0
0 0.2 0.4 0.6
9
12
0.8 1
C – TIMERCapacitance – nF
TIMER
t – Circuit-BreakerResponseTime – s
(res) m
IN=12V
TA=25°C
CL– LoadCapacitance – Fm
200
160
120
0
0 100 200 300
t– LoadV
oltageDischargeT
ime – ms
240
280
320
400 500
80
40
IN=12V
IO=0 A
TA=25°C
TPS2330
TPS2331
SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006 ...............................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
GATE VOLTAGE FALL TIME GATE OUTPUT CURRENTvs vsGATE LOAD CAPACITANCE GATE VOLTAGE
Figure 12. Figure 13.
CIRCUIT-BREAKER RESPONSE TIME LOAD VOLTAGE DISCHARGE TIMEvs vsTIMER CAPACITANCE LOAD CAPACITANCE
Figure 14. Figure 15.
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TPS2330
TPS2331
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............................................................................................................................................... SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
UVLO START AND STOP THRESHOLDS PWRGD INPUT THRESHOLDvs vsTEMPERATURE TEMPERATURE
Figure 16. Figure 17.
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APPLICATION INFORMATION
VREG
0.1 µF
IN ISET
RISET
ISENSE
RSENSE
GATE DISCH VSENSE
RVSENSE_TOP
RVSENSE_BOTTOM
+
FAULT
PWRGD FAULT
PWRGD
TIMER
ENABLE
DGND
AGND
VO
ENABLE
1 µF ∼ 10 µF
3 V ∼ 13 V IN
TPS2331
System Board
INPUT CAPACITOR
OUTPUT CAPACITOR
EXTERNAL FET
TPS2330
TPS2331
SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006 ...............................................................................................................................................
www.ti.com
This diagram shows a typical dual hot-swap application. The pullup resistors at PWRGD and FAULT should berelatively large (e.g. 100 k Ω) to reduce power loss unless they are required to drive a large load.
Figure 18. Typical Hot-Swap Application
A 0.1- µF ceramic capacitor in parallel with a 1- µF ceramic capacitor should be placed on the input powerterminals near the connector on the hot-plug board to help stabilize the voltage rails on the cards. TheTPS2330/31 does not need to be mounted near the connector or these input capacitors. For applications withmore severe power environments, a 2.2- µF or higher ceramic capacitor is recommended near the input terminalsof the hot-plug board. A bypass capacitor for IN should be placed close to the device.
A 0.1- µF ceramic capacitor is recommended per load on the TPS2330/31; these capacitors should be placedclose to the external FETs and to TPS2330/31. A larger bulk capacitor on the load is also recommended. Thevalue of the bulk capacitor should be selected based on the power requirements and the transients generated bythe application.
To deliver power from the input sources to the loads, the controller needs an external N-channel MOSFET. A fewwidely used MOSFETs are shown in Table 2 . But many other MOSFETs on the market can also be used withTPS23xx in hot-swap systems.
12 Submit Documentation Feedback Copyright © 2000 – 2006, Texas Instruments Incorporated
Product Folder Link(s): TPS2330 TPS2331
TIMER
OUTPUT-VOLTAGE SLEW-RATE CONTROL
dVs
dt +15 mA
Cgd
(1)
VREG CAPACITOR
GATE DRIVE CIRCUITRY
TPS2330
TPS2331
www.ti.com
............................................................................................................................................... SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006
Table 2. Some Available N-Channel MOSFETs
CURRENT RANGE
PART NUMBER DESCRIPTION MANUFACTURER(A)
IRF7601 N-channel, r
DS(on)
= 0.035 Ω, 4.6 A, Micro-8 International RectifierMTSF3N03HDR2 N-channel, r
DS(on)
= 0.040 Ω, 4.6 A, Micro-8 ON Semiconductor0 to 2
IRF7101 Dual N-channel, r
DS(on)
= 0.1 Ω, 2.3 A, SO-8 International RectifierMMSF5N02HDR2 Dual N-channel, r
DS(on)
= 0.04 Ω, 5 A, SO-8 ON SemiconductorIRF7401 N-channel, r
DS(on)
= 0.022 Ω, 7 A, SO-8 International RectifierMMSF5N02HDR2 N-channel, r
DS(on)
= 0.025 Ω, 5 A, SO-8 ON Semiconductor2 to 5
IRF7313 Dual N-channel, r
DS(on)
= 0.029 Ω, 5.2 A, SO-8 International RectifierSI4410 N-channel, r
DS(on)
= 0.020 Ω, 8 A, SO-8 Vishay DaleIRLR3103 N-channel, r
DS(on)
= 0.019 Ω, 29 A, d-Pak International Rectifier5 to 10
IRLR2703 N-channel, r
DS(on)
= 0.045 Ω, 14 A, d-Pak International Rectifier
For most applications, a minimum capacitance of 50 pF is recommended to prevent false triggering. Thiscapacitor should be connected between TIMER and ground. The presence of an overcurrent condition on of theTPS2330/31 causes a 50- µA current source to begin charging this capacitor. If the overcurrent condition persistsuntil the capacitor has been charged to approximately 0.5 V, the TPS2330/31 latches off the transistor and pullsthe FAULT pin low. The timer capacitor can be made as large as desired to provide additional time delay beforeregistering a fault condition. The time delay is approximately:
dt(sec) = C
(TIMER)
(F) × 10,000( Ω)
When enabled, the TPS2330/TPS2331 controllers supply the gate of an external MOSFET transistor with acurrent of approximately 15 µA. The slew rate of the MOSFET source voltage is thus limited by the gate-to-draincapacitance C
gd
of the external MOSFET capacitor to a value approximating:
If a slower slew rate is desired, an additional capacitance can be connected between the gate of the externalMOSFET and ground.
The internal voltage regulator connected to VREG requires an external capacitor to ensure stability. A 0.1- µF or0.22- µF ceramic capacitor is recommended.
The TPS2330/TPS2331 includes four separate features associated with each gate-drive terminal:•A charging current of approximately 15 µA is applied to enable the external MOSFET transistor. This currentis generated by an internal charge pump that can develop a gate-to-source potential (referenced to DISCH) of9 V – 12 V. DISCH must be connected to the external MOSFET source terminal to ensure proper operation ofthis circuitry.
•A discharge current of approximately 75 µ A is applied to disable the external MOSFET transistor. Once thetransistor gate voltage has dropped below approximately 1.5 V, this current is disabled and the UVLOdischarge driver is enabled instead. This feature allows the part to enter a low-current shutdown mode whileensuring that the gate of the external MOSFET transistor remains at a low voltage.•During a UVLO condition, the gate of the MOSFET transistor is pulled down by an internal PMOS transistor.This transistor continues to operate even if the voltage at IN is 0 V. This circuitry also helps hold the externalMOSFET transistor off when power is suddenly applied to the system.•During an overcurrent fault condition, the external MOSFET transistor that exhibited an overcurrent conditionis rapidly turned off by an internal pulldown circuit capable of pulling in excess of 400 mA (at 4 V) from the
Copyright © 2000 – 2006, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS2330 TPS2331
SETTING THE CURRENT-LIMIT CIRCUIT-BREAKER THRESHOLD
ILMT +RISET 50 10–6
RISENSE
(2)
SETTING THE POWER-GOOD THRESHOLD VOLTAGE
RVSENSE_TOP +VO_min *1.225
1.225 RVSENSE_BOT
(3)
UNDERVOLTAGE LOCKOUT (UVLO)
POWER-UP CONTROL
TPS2330
TPS2331
SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006 ...............................................................................................................................................
www.ti.com
pin. Once the gate has been pulled below approximately 1.5 V, this driver is disengaged and the UVLO driveris enabled instead.
The current sensing resistor R
ISENSE
and the current limit setting resistor R
ISET
determine the current limit of thechannel, and can be calculated by the following equation:
Typically R
ISENSE
is usually very small (0.001 Ωto 0.1 Ω). If the trace and solder-junction resistances between thejunction of R
ISENSE
and ISENSE and the junction of R
ISENSE
and R
ISET
are greater than 10% of the R
ISENSE
value,then these resistance values should be added to the R
ISENSE
value used in the calculation above.
Table 3 shows some of the current-sense resistors available in the market.
Table 3. Some Current-Sense Resistors
CURRENT RANGE
PART NUMBER DESCRIPTION MANUFACTURER(A)
0 to 1 WSL-1206, 0.05 1% 0.05 Ω, 0.25 W, 1% resistor1 to 2 WSL-1206, 0.025 1% 0.025 Ω, 0.25 W, 1% resistor2 to 4 WSL-1206, 0.015 1% 0.015 Ω, 0.25 W, 1% resistor
Vishay Dale4 to 6 WSL-2010, 0.010 1% 0.010 Ω, 0.5 W, 1% resistor6 to 8 WSL-2010, 0.007 1% 0.007 Ω, 0.5 W, 1% resistor8 to 10 WSR-2, 0.005 1% 0.005 Ω, 0.5 W, 1% resistor
The two feedback resistors R
VSENSE_TOP
and R
VSENSE_BOT
connected between V
O
and ground form a resistordivider, setting the voltage at the VSENSE pins. VSENSE voltage equals:V
I(SENSE)
= V
O
נR
VSENSE_BOT
/(R
VSENSE_TOP
+ R
VSENSE_BOT
)
This voltage is compared to an internal voltage reference (1.225 V ± 2%) to determine whether the output voltagelevel is within a specified tolerance. For example, given a nominal output voltage at V
O
, and defining V
O_min
asthe minimum required output voltage, then the feedback resistors are defined by:
Start the process by selecting a large standard resistor value for R
VSENSE_BOT
to reduce power loss. ThenR
VSENSE_TOP
can be calculated by inserting all of the known values into the equation above. When V
O
is lowerthan V
O_min
, PWRGD is low as long as the controller is enabled.
The TPS2330/TPS2331 includes an undervoltage lockout (UVLO) feature that monitors the voltage present onthe VREG pin. This feature disables the external MOSFET if the voltage on VREG drops below 2.78 V (nominal)and re-enables normal operation when it rises above 2.85 V (nominal). Because VREG is fed from IN through alow-dropout voltage regulator, the voltage on VREG tracks the voltage on IN within 50 mV. While theundervoltage lockout is engaged, GATE is held low by an internal PMOS pulldown transistor, ensuring that theexternal MOSFET transistor remain off at the times, even if the power supply has fallen to 0 V.
The TPS2330/TPS2331 includes a 500- µs (nominal) start-up delay that ensures that internal circuitry hassufficient time to start before the device begins turning on the external MOSFETs. This delay is triggered onlyupon the rapid application of power to the circuit. If the power supply ramps up slowly, the undervoltage lockoutcircuitry provides adequate protection against undervoltage operation.
14 Submit Documentation Feedback Copyright © 2000 – 2006, Texas Instruments Incorporated
Product Folder Link(s): TPS2330 TPS2331
3-CHANNEL HOT-SWAP APPLICATION
VREG
0.1 µF
IN ISET
RISET
ISENSE
RSENSE
GATE DISCH VSENSE
RVSENSE_TOP
RVSENSE_BOTTOM
+
FAULT
PWRGD FAULT
PWRGD
TIMER
ENABLE
DGND
AGND
Rg1
+
VO1
VO2
ENABLE
1 µF ∼ 10 µF
1 µF ∼ 10 µF
12 V IN1
3.3 V IN2
TPS2331
+VO3
1 µF ∼ 10 µF
5 V IN3
System Board
Rg3
Rg2
TPS2330
TPS2331
www.ti.com
............................................................................................................................................... SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006
Some applications require hot-swap control of up to three voltage rails, but may not explicitly require the sensingof the status of the output power on all three of the voltage rails. One such application is device bay, where dv/dtcontrol of 3.3 V, 5 V, and 12 V is required. By using TPS2330/TPS2331 to drive all three power rails, as is shownin Figure 19 , TPS2330/31 can deliver three different voltages to three loads while monitoring the status of one ofthe loads.
Figure 19. Three-Channel Application
Figure 20 shows ramp-up waveforms of the three output voltages.
Copyright © 2000 – 2006, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS2330 TPS2331
t – Time – 2.5ms/div
V – OutputVoltage – 2V/div
O
VO1
VO3
VO2
TPS2330
TPS2331
SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006 ...............................................................................................................................................
www.ti.com
Figure 20.
16 Submit Documentation Feedback Copyright © 2000 – 2006, Texas Instruments Incorporated
Product Folder Link(s): TPS2330 TPS2331
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS2330ID ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2330IDG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2330IDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2330IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2330IPW ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2330IPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2330IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2330IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2331ID ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2331IDG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2331IDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2331IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2331IPW ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2331IPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2331IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2331IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 6-Dec-2006
Addendum-Page 1
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Dec-2006
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2330IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TPS2330IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPS2331IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TPS2331IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2330IDR SOIC D 14 2500 367.0 367.0 38.0
TPS2330IPWR TSSOP PW 14 2000 367.0 367.0 35.0
TPS2331IDR SOIC D 14 2500 367.0 367.0 38.0
TPS2331IPWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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