SPICE Device Model Si2302DS
Vishay Siliconix
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 7098 3 www.vishay.com
17-Apr-01 1
N-Channel 1.25-W, 2.5-V Rated MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switc hi ng Application
• Accurate over the −55 to 125°C Temperat ure Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-to-5V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold vol tage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge charact erist ics while avoiding convergenc e difficulties
of the switched C
g
d model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of t he devic e.
SUBCIRCUIT MODEL SCHEMA TIC
SPICE Device Model Si2302DS
Vishay Siliconix
www.vishay.com Docu ment Number: 70983
217-Apr-01
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Conditions Typical Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA0.91 V
VDS ≥ 5 V, VGS = 4.5 V 62
On-State Drain CurrentaID(on) VDS ≥ 5 V, VGS = 2.5 V 16 A
VGS = 4.5 V, ID = 3.6 A 0.071
Drain-Source On-State ResistancearDS(on) VGS = 2.5 V, ID = 3.1 A 0.081 Ω
Forward Transconductanceagfs VDS = 5 V, ID = 3.6 A 11 S
Diode Forward VoltageaVSD IS = 1.6 A, VGS = 0 V 0 .79 V
Dynamic
Total Gate Charge Qg4.9
Gate-Source Charge Qgs 0.65
Gate-Drain Charge Qgd
VDS = 10 V, VGS = 4.5 V, ID = 3.6 A
1.60
nC
Input Capacitance Ciss 336
Output Capacitance Coss 113
Reverse Transfer Capacitance Crss
VDS = 10 V, VGS = 0 V, f = 1 MHz
40
pf
Turn-On Delay Time td(on) 8
Rise Time tr12
Turn-Off Delay Time td(off) 21
Fall Time tf
VDD = 10 V, RL = 5.5 Ω
ID ≅ 3.6 A, VGEN = 4.5 V, RG = 6 Ω
30
ns
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%
SPICE Device Model Si2302DS
Vishay Siliconix
Document Number: 7098 3 www.vishay.com
17-Apr-01 3
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
