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VRXUFHFRGHH[DPSOHDSSOLFDWLRQV0DQ\RIWKHWHFKQLFDOGRFXPHQWVDUHDYDLODEOHRQOLQHLQ3')IRUP 4XHVWLRQVUHTXHVWVDQGLQSXWFRQFHUQLQJ$0'V:::SDJHVFDQEHVHQWYLDHPDLOWR ZHEPDVWHU#DPGFRP Documentation and Literature Support 'DWDERRNVXVHUVPDQXDOVGDWDVKHHWVDSSOLFDWLRQQRWHVDQGSURGXFW&'VDUHIUHHZLWKDVLPSOH SKRQHFDOO,QWHUQDWLRQDOO\FRQWDFW\RXUORFDO$0'VDOHVRIILFHIRUSURGXFWOLWHUDWXUH 7RRUGHUOLWHUDWXUHFDOO 7ROOIUHHIRU86DQG&DQDGD 'LUHFWGLDOZRUOGZLGH )D[ Third-Party Support $0')XVLRQ(60SDUWQHUVSURYLGHDQDUUD\RISURGXFWVGHVLJQHGWRPHHWFULWLFDOWLPHWRPDUNHWQHHGV 3URGXFWVDQGVROXWLRQVDYDLODEOHLQFOXGHHPXODWRUVKDUGZDUHDQGVRIWZDUHGHEXJJHUVERDUGOHYHOSURGXFWV DQGVRIWZDUHGHYHORSPHQWWRROVDPRQJRWKHUV7KH:::VLWHDQGWKH()DPLO\3URGXFWV 'HYHORSPHQW7RROV&'RUGHU GHVFULEHWKHVHVROXWLRQV,QDGGLWLRQPDWXUHGHYHORSPHQW WRROVDQGDSSOLFDWLRQVIRUWKH[SODWIRUPDUHZLGHO\DYDLODEOHLQWKHJHQHUDOPDUNHWSODFH TIP.book Page iv Friday, April 23, 1999 10:38 AM TIP.book Page v Friday, April 23, 1999 10:38 AM Contents About the Test Interface Port Board 7,3%RDUG)HDWXUHV [L 'RFXPHQWDWLRQ [LL $ERXW7KLV0DQXDO [LLL 6XJJHVWHG5HIHUHQFH0DWHULDO [LLL 'RFXPHQWDWLRQ&RQYHQWLRQV [LY Chapter 1 Getting Started %RDUG3RZHU ,QWHUIDFH&DEOH 0DLQ,QWHUIDFH&RQQHFWRU Chapter 2 System Features and Components /D\RXWDQG3ODFHPHQW 6HULDO3RUWV 3URJUDPPLQJWKH6HULDO3RUWV &RQILJXULQJWKH6HULDO3RUWIRU'7( 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDO Y TIP.book Page vi Friday, April 23, 1999 10:38 AM 3DUDOOHO3RUW 3URJUDPPLQJWKH3DUDOOHO3RUW (WKHUQHW&RQWUROOHU3RUW /&' 2YHUYLHZ &RQILJXULQJWKH/&' +H[DGHFLPDO'LVSOD\ *HQHUDO3XUSRVH/('V (LJKW/('V 'LVFUHWH/('2XWSXWV5HJLVWHU 'HEXJ+HDGHUV *HQHUDO3XUSRVH,QSXWVDQG2XWSXWV 'LVFUHWH,QSXWV5HJLVWHU 'LVFUHWH2XWSXWV5HJLVWHU ',36ZLWFK (LJKW3RVLWLRQ',36ZLWFK ',36ZLWFK,QSXWV5HJLVWHU 5HVHW%XWWRQ )ODVK0HPRU\ 8VLQJWKH)ODVK0HPRU\ 6HOHFWLQJWKH)ODVK0HPRU\ ,QWHUUXSWV 0$&+'HYLFH ,2$GGUHVV0RGH ,20DSV 7LPLQJ 9HUVLRQ5HJLVWHU YL 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDO TIP.book Page vii Friday, April 23, 1999 10:38 AM Appendix A MACH(R) Device Equations 0$&+'HYLFH(TXDWLRQV $ Index ,QGH[ ,QGH[ 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDOO YLL TIP.book Page viii Friday, April 23, 1999 10:38 AM List of Figures )LJXUH %DUUHO3 DQG5LEERQ&DEOH3 &RQQHFWRUV/RFDWLRQV )LJXUH 7,3%RDUG5LEERQ&DEOH )LJXUH 5LEERQ&DEOH&RQQHFWRU2ULHQWDWLRQ )LJXUH 0DLQ,QWHUIDFH&RQQHFWRU3LQRXW )LJXUH 7,3&LUFXLW%RDUG/D\RXW )LJXUH 7,3%RDUG%ORFN'LDJUDP )LJXUH 6HULDO3RUW&RQQHFWRU3LQRXW )LJXUH 3DUDOOHO3RUW&RQQHFWRU3LQRXW )LJXUH /&''LVSOD\ )LJXUH (LJKW6HJPHQW'LVSOD\ )LJXUH /('3LQRXW )LJXUH +3/RJLF$QDO\]HU+HDGHU )LJXUH *HQHUDO3XUSRVH,QSXW2XWSXW+HDGHU )LJXUH ',36ZLWFK )LJXUH 5HVHW%XWWRQ )LJXUH %LW)ODVK0HPRU\,GHQWLILFDWLRQ )LJXUH -33LQ/RFDWLRQV YLLL 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDO TIP.book Page ix Friday, April 23, 1999 10:38 AM List of Tables 7DEOH 1RWDWLRQDO&RQYHQWLRQV [LY 7DEOH ,QWHUIDFH&RQQHFWRU6LJQDO'HVFULSWLRQV 7DEOH ,20DSIRU%LW$GGUHVVLQJIRU6HULDO3RUW 7DEOH ,20DSIRU%LW$GGUHVVLQJIRU6HULDO3RUW 7DEOH ,20DSIRU%LW$GGUHVVLQJIRU3DUDOOHO3RUW 7DEOH ,20DSIRU%LW$GGUHVVLQJIRU3DUDOOHO3RUW 7DEOH ,20DSIRU%LW$GGUHVVLQJIRU$6&,,'LVSOD\ 7DEOH ,20DSIRU%LW$GGUHVVLQJIRU$6&,,'LVSOD\ 7DEOH ,20DSIRU%LW$GGUHVVLQJIRU+H[DGHFLPDO'LVSOD\ 7DEOH ,20DSIRU%LW$GGUHVVLQJIRU+H[DGHFLPDO'LVSOD\ 7DEOH 'LVFUHWH/('2XWSXWV5HJLVWHU%LW'HILQLWLRQV 7DEOH 'LVFUHWH,QSXWV5HJLVWHU%LW'HILQLWLRQV 7DEOH 'LVFUHWH2XWSXWV5HJLVWHU%LW'HILQLWLRQV 7DEOH ',36ZLWFK,QSXWV5HJLVWHU%LW'HILQLWLRQV 7DEOH ,20DSIRU%LW$GGUHVVLQJ 7DEOH ,20DSIRU%LW$GGUHVVLQJ 7DEOH 9HUVLRQ5HJLVWHU%LW'HILQLWLRQV 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDO L[ TIP.book Page x Friday, April 23, 1999 10:38 AM [ 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDO TIP.book Page xi Friday, April 23, 1999 10:38 AM About the Test Interface Port Board The Test Interface Port (TIP) board was developed as a software debug and development board. For many reasons, it is often impractical to put extra peripherals on a target system just for development and software debugging. Serial ports are a good example. Often, adding extra peripherals makes development more difficult because the target peripherals are used by the application and cannot be used for software development and debugging. However, a target containing a small, 60-pin connector can host the TIP, a board rich in peripherals for development and software debugging. The TIP board is a set of peripherals contained in one convenient location for software debugging, diagnostics, evaluation, and reference designs. The TIP board is designed to make it easy and convenient for the software to communicate the status with an engineer, tester, or even an end user. The TIP board is designed to support flexible, present-day applications and is used with a target board containing a microcontroller that can connect to the TIP board through the main interface connector (60-wire ribbon cable). TIP Board Features The TIP board provides the following features: * Two 16550 RS-232 serial ports (9-pin, DCE). * One PC-compatible parallel port. * A 10BaseT Ethernet controller port that can be run in interrupt-driven mode. * A 2 x 20 character ASCII-decoded display. * An 8-segment (32-bit) hexadecimal display. * Eight discrete LEDs (green). * Three HP logic analyzer debug headers for easy address, data, and control signal debug access. Test Interface Port Board User's Manual xi TIP.book Page xii Friday, April 23, 1999 10:38 AM * Eight discrete TTL/CMOS outputs (can connect directly to a logic analyzer). * Eight inputs connected to a DIP switch and header. * A reset button that resets the target. * An 8-bit DIP Flash memory, socketed to allow for upgrading. * A jumper block (JP1) for selecting between internal (TIP board) or external (host board) Flash memory. * A flexible interface for simple and inexpensive connection to a target board. * An interrupt button. * Five interrupt sources on the board: two serial ports, the parallel port, the Ethernet controller port, and the user-interrupt button. All these interrupts go to the main interface connector separately. In addition, all these interrupts are logic ORed into a single signal that also goes to the connector. * A macro array CMOS high-density/high-performance (MACH(R)) device that provides individual chip selects for each on-board peripheral device (except the Ethernet controller port). * Support for 16-bit addressing or 8-bit addressing, selected with the SW3 switch. * Five programmable registers for controlling the TIP board's operation. Documentation The AMD Test Interface Port Board User's Manual, order #22505, provides information on the system and board features, functionality, and interfaces. Additional information can be found in the documentation listed on page xiii. xii Test Interface Port Board User's Manual TIP.book Page xiii Friday, April 23, 1999 10:38 AM About This Manual Chapter 1, "Getting Started" describes the power supply requirements and the main interface connector configuration for the TIP board. This chapter also explains the proper procedure for powering up the TIP board. Chapter 2, "System Features and Components" describes in detail the peripherals, memory, main interface connector signals and pin out, and interrupts of the TIP board, including the jumper settings and programmable registers used to control the operation of the TIP board. Appendix A, "MACH(R) Device Equations" contains a current listing of the MACH device program code. Suggested Reference Material The following AMD documentation may be of interest to the TIP board user. * AMD Am79C961 Ethernet Controller specifications, order #18183 For current application notes and technical bulletins, see our World Wide Web page at www.amd.com. The following non-AMD documentation may also be of interest to the TIP board user. * Hitachi's HD44780U (LCD-II) Dot Matrix Liquid Crystal Display Controller/ Driver data sheet. For more information, refer to the Hitachi specification by accessing the web site http://www.hitachi.com and searching on HD44780U. * Texas Instruments' TL16C552 Dual Asynchronous Communications Element With FIFO data sheet. For more information, refer to the Texas Instruments TL16C552 specification by accessing the web site http://www.ti.com and searching on TL16C552. Test Interface Port Board User's Manual xiii TIP.book Page xiv Friday, April 23, 1999 10:38 AM Documentation Conventions The Test Interface Port Board User's Manual uses the notational conventions shown in Table 0-1 (unless otherwise noted). Table 0-1. Notational Conventions xiv Symbol Usage Boldface Indicates that characters must be entered exactly as shown, except that the alphabetic case is only significant when indicated. Italic Indicates a descriptive term to be replaced with a user-specified term. Typewriter face Indicates computer text input or output in an example or listing. [] Encloses an optional parameter. To include the information described within the brackets, type only the parameter, not the brackets themselves. SIGNAL An overbar over a signal name indicates that it is active low. SIGNAL# A pound sign after a signal name is used to indicate an active low in schematics. Test Interface Port Board User's Manual TIP.book Page 1 Friday, April 23, 1999 10:38 AM Chapter 1 Getting Started The Test Interface Port (TIP) board comes prepared for immediate use. Connect the supplied flexible ribbon cable to the TIP board and to the host's interface connector, then follow the correct power-up procedure (see "Board Power" on page 1-1), and the TIP board is ready to use. You can program the on-board Flash memory with board diagnostics, a monitor program, or application software. NOTE: To use any application that may be programmed on the TIP board's Flash memory, set the Flash Select jumper to the INT position. Board Power The TIP board requires an external 5-V DC power supply with a 2.0-A current rating. Although the external power supply provides the 5-V power for the board, the board still does not power up (even with the external power supply connected) unless a host board is also properly connected. This condition is caused by the two power sources being routed through two MOSFETs that are managed by a comparator. The comparator gets its power from the host VCC. This MOSFET/ comparator routing prevents any power to the board without the presence of both the external and host power sources. ! CAUTION: Do not provide power to the TIP board through a host board without first connecting an external power source to the TIP board. Failure to correctly follow this procedure causes back powering of the FETs which could damage the TIP board. Use the following procedure to power up the TIP board: 1. Be sure the host board is not powered up. Test Interface Port Board User's Manual 1-1 TIP.book Page 2 Friday, April 23, 1999 10:38 AM 2. Attach the interface ribbon cable connector between the TIP board and the host board. On the TIP board, the ribbon cable connector attaches to connector P1, shown in Figure 1-1 3. Connect the external 5-V DC power supply to the TIP board's barrel connector (P2), shown in Figure 1-1. ! CAUTION: Failure to follow this procedure can result in irregular results or damage to the TIP board. 4. Perform the normal power-up procedures on the host board. Barrel Connector (P2) Ribbon Cable Connector (P1) Figure 1-1. Barrel (P2) and Ribbon Cable (P1) Connectors Locations 1-2 Test Interface Port Board User's Manual TIP.book Page 3 Friday, April 23, 1999 10:38 AM Interface Cable The TIP board requires a 60-wire ribbon cable assembly to connect to the host interface. Figure 1-2 illustrates the interface cable assembly. Figure 1-3 on page 1-4 illustrates the orientation of the host interface connector and the connector on the interface cable assembly that connects to the host. For a description of the interface signals, see "Main Interface Connector" on page 1-5. 7 47 49 51 53 55 57 59 8 48 50 52 54 56 58 60 3 1 5 Top View With female end of connectors facing upward (out of the page) Guide bars facing outward Connector (AMP 1-111196) 6 4 2 AMP 59 57 55 53 51 49 47 7 5 3 1 Ribbon Cable (AMP 2-57038) Connector (AMP 1-111196) 60 58 56 54 52 50 48 8 6 4 2 AMP Guide bars facing outward Figure 1-2. TIP Board Ribbon Cable Test Interface Port Board User's Manual 1-3 59 1 2 60 AMP 1-111196 Top/Side Angle View Orientation of Interface Cable Assembly that connects to the host Interface Connector 60 2 Top View AMP 104068- 1 59 Vertical Conn 60 Side View Orientation of the host interface connector (AMP 104068-6 vertical connector) 2 AMP 104069-7 59 1 Right Angle Conn. Orientation of the host interface connector (AMP 104069-7 right-angle connector) Figure 1-3. Ribbon Cable Connector Orientation 1-4 Test Interface Port Board User's Manual TIP.book Page 5 Friday, April 23, 1999 10:38 AM Main Interface Connector The 60-wire ribbon cable connects to the TIP board on the main interface connector (P1). Table 1-1 describes each of the 60 signals on the connector. Figure 1-4 on page 1-9 illustrates the pinout of P1. Table 1-1. Interface Connector Signal Descriptions Pin No. Signal Name Input/ Description Output 1-10, 13-22 TA0-TA19 I 11, 12, 23, 24 GND -- Ground Pins 25-32 TD0-TD7 I/O Data Bus: Input and output data during respective read or write cycle. 33 - - Pin is blank. 34 - - Pin is blank. 35 TIPSEL O TIP Select #: The hardware method of identifying that the TIP board is physically connected to the host. The TIP board has a 10-K pullup resistor on TIPSEL. If the host board wants to use TIPSEL to indicate that the TIP board is connected, then the host board should have a weak pulldown resistor (100 K) on the signal connected to TIPSEL. Then, when the TIP board is connected to the host board, TIPSEL signal goes Low, indicating that the TIP board is properly connected to the host. 36 - - Pin is blank. Address Lines: Receive the physical memory latched address for the Flash memory or Ethernet controller and the physical I/O latched address for all other TIP board peripherals through the MACH device. Test Interface Port Board User's Manual 1-5 TIP.book Page 6 Friday, April 23, 1999 10:38 AM Table 1-1. Interface Connector Signal Descriptions (Continued) 1-6 Pin No. Signal Name Input/ Description Output 37 TIPSEL O TIP Select: The hardware method of indentifying that the TIP board is physically connected to the host. The TIP board has a 1-K pulldown resistor on TIPSEL. If the host board wants to use TIPSEL to indicate that the TIP board is connected, then the host board should have a weak pullup resistor (10 K) on the signal connected to TIPSEL. When the TIP board is connected to the host board, TIPSEL signal goes High, indicating that the TIP board is properly connected to the host. 38 TAEN I Address Enable: For ISA systems: When asserted High, TAEN enables DMACs on the buses and prevents I/O devices from responding. For the Am186TMCC CDP: a chip select that, when asserted Low, allows for communication with the Ethernet controller. 39 - - Pin is blank. 40 TRD I Read Strobe: Indicates to the system that the host microcontroller is performing a memory or I/O read cycle. 41 - - Pin is blank. 42 TWR I Write Strobe: Indicates to the system that the host microcontroller is performing a memory or I/O write cycle. 43 ENETIRQ O Ethernet Interrupt Request: Indicates that one of several status flags is set (consult Ethernet controller specification for details). Test Interface Port Board User's Manual TIP.book Page 7 Friday, April 23, 1999 10:38 AM Table 1-1. Interface Connector Signal Descriptions (Continued) Pin No. Signal Name Input/ Description Output 44 TS2 I Bus Cycle Status: Used by Am186 family of microcontrollers as a logical memory or I/O indicator. 45 PARINT O Printer Port Interrupt: Dedicated parallel port interrupt signal. 46 - - Pin is blank. 47 SERINT1 O Serial Port 1 Interrupt: Dedicated serial port 1 interrupt signal. 48 MAIN_IRQ O Main Interrupt Line: A shared interrupt line. MAIN_IRQ is asserted if any of the five interrupts on the TIP board are asserted. 49 SERINT0 O Serial Port 0 Interrupt: Dedicated serial port 0 interrupt signal. 50 HRESET O Host Reset: Toggled by the TIP board reset button, which then indicates to the host microcontroller to perform a systemwide hardware reset. 51 IOCHRDY O I/O Channel Ready: Indication by the Ethernet controller that valid data exists on the data bus for reads and that data has been latched for writes. 52 TRESET I TIP Reset: Generated by the host microcontroller when performing a hardware reset. TRESET affects the TIP board's Ethernet controller, and parallel and serial ports. 53 - - Pin is blank. 54 FLASHRD I Flash Read Enable: Output enable. Test Interface Port Board User's Manual 1-7 TIP.book Page 8 Friday, April 23, 1999 10:38 AM Table 1-1. Interface Connector Signal Descriptions (Continued) 1-8 Pin No. Signal Name Input/ Description Output 55 SEL186 I Select Am186: Identifies that a Am186 microcontroller board is connected and is hosting the TIP board. This helps to determine when the Ethernet controller should respond to read and write cycles. There is a 1-K pulldown resistor connected to this pin for when a Am186 board is not connected. SEL186 should be driven High by any Am186 host boards connecting to the TIP board. 56 FLASHWR I Flash Write Enable: Write enable. 57, 59 VCC I Host Power: +5 V DC provides power to the comparator, which in turn provides power to the MOSFET driver, which drives the FETs, allowing the external power supply to provide +5 V DC to the board. 58 FLASHCS -- Flash Chip Select: Flash memory chip enable. 60 EXTFLHCS I External Flash Chip Select: An optional external Flash memory chip select jumper. The host boards can take advantage of EXTFLHCS by making the TIP board's Flash memory select jumper the primary Flash memory select component of the two boards (theTIP board and the host board). This minimizes components on the host board. Test Interface Port Board User's Manual '$7$%86 $''5(66%86 3 *5281' ,17(558376 +2679&& 7$ 7$ 7$ 7$ 7$ 7$ 7$ 7$ 7$ 7$ *1' *1' 7$ 7$ 7$ 7$ 7$ 7$ 7$ 7$ 7$ 7$ *1' *1' 7' 7' 7' 7' 7' 7' 7' 7' 1& 1& 7,36(/ 1& 7,36(/ 7$(1 1& 75' 1& 7:5 (1(7,54 76 3$5,17 1& 6(5,17 6(5,17 ,2&+5'< 1& 6(/ 0$,1B,54 +5(6(7 75(6(7 )/$6+5' )/$6+:5 9&& )/$6+&6 9&& (;7)/+&6 *5281' &21752/6,*1$/6 5(6(76 )/$6+&21752/6 Figure 1-4. Main Interface Connector Pinout Test Interface Port Board User's Manual 1-9 TIP.book Page 10 Friday, April 23, 1999 10:38 AM 1-10 Test Interface Port Board User's Manual TIP.book Page 1 Friday, April 23, 1999 10:38 AM Chapter 2 System Features and Components The Test Interface Port (TIP) board is a set of peripherals at one convenient location for software debugging, diagnostics, evaluation, and reference designs. The TIP board is designed to make it easy and convenient for the software to indicate to an engineer, tester, or an end user the tasks that are being performed. The TIP board is designed to support flexible, present-day applications, and is intended to be used with any host board containing a microcontroller that can connect to the TIP board through the small, 60-pin, main interface connector. The TIP board supports either I/O-mapped or memory-mapped operation and can be used in either mode. The TIP board requires minimal software initialization for basic operation. This chapter provides detailed information about the features and components of the TIP board. The following sections explain the operation of the board in detail, including jumper settings, switch settings, and programmable registers: * "Layout and Placement" on page 2-2 * "Serial Ports" on page 2-5 * "Parallel Port" on page 2-10 * "Ethernet Controller Port" on page 2-13 * "LCD" on page 2-14 * "Hexadecimal Display" on page 2-16 * "General-Purpose LEDs" on page 2-18 * "Debug Headers" on page 2-20 * "General-Purpose Inputs and Outputs" on page 2-21 * "DIP Switch" on page 2-24 * "Reset Button" on page 2-26 * "Flash Memory" on page 2-27 * "Interrupts" on page 2-30 Test Interface Port Board User's Manual 2-1 TIP.book Page 2 Friday, April 23, 1999 10:38 AM * "MACH(R) Device" on page 2-30 * "I/O Address Mode" on page 2-31 * "I/O Maps" on page 2-32 * "Timing" on page 2-34 * "Version Register" on page 2-34 Layout and Placement The TIP board is laid out for convenient connection to the host board and to the various external devices. It has connectors for DC power, parallel port, RJ-45, and the serial ports along one side of the board. On a side adjacent to the port connector side are the main interface connector, the general-purpose input/output header, the debug headers, and the MACH device programming header. The LCD, hex displays, and LEDs are arranged close together in the middle of the board. Refer to Figure 2-1 on page 2-3 for layout and component placement. Figure 2-2 on page 2-4 is a block diagram of the TIP board showing the connections between the various peripherals on the board. 2-2 Test Interface Port Board User's Manual TIP.book Page 3 Friday, April 23, 1999 10:38 AM DC Power Connector UARTs and Parallel Port Chip Parallel Port (under the LCD) Ethernet Serial Ports EEPROM Outline of LCD MACH(R) 4-128 Device (under the LCD) LEDs Debug Headers Hex Displays (8) Input DIP Switch Flash Memory SRAM MACH(R) Programming Header GPIO Input and Output Header Main Interface Connector Figure 2-1. TIP Circuit Board Layout Test Interface Port Board User's Manual 2-3 TIP.book Page 4 Friday, April 23, 1999 10:38 AM Ethernet Controller 10BaseT Connector E-NET ISA II HP Header HP Header HP Header Debug Headers EEPROM SRAM Transformer Board Peripherals Control Signals Address Data Bus Main Interface Connector ASCII LCD Program. Header Address (20) 245 Control Signals MACH(R) Device 244 60-Pin Connector Hex Displays (8) Data Bus (8) Flash Memory Control Signal Chip Selects LEDs (8) PAL(R) Device GPIO Header FLASH DIP Switch VCC Management Circuit Dual 16C550 UART & Parallel Controller Board VCC Comp Host VCC FET Driver Ext. Power Plug MOSFET Figure 2-2. TIP Board Block Diagram 2-4 Test Interface Port Board User's Manual Parallel Serial Serial Serial Ports NOTE: For more information about initializing or programming the serial ports, refer to the Texas Instruments TL16C552 data sheet. The TIP board provides two 16550 RS-232 serial ports (9-pin, DCE). The TIP board contains a Texas Instruments TL16C552 chip that controls two 16550 Universal Asynchronous Receiver Transmitters (UARTs) and a parallel port. For more information about the parallel port, refer to page 2-10. These serial ports run up to 115200 baud and can be used with or without interrupts. The interrupt line from each serial port connects to a dedicated pin on the interface connector or through a shared interrupt circuit, which has one dedicated pin on the interface connector. Figure 2-3 illustrates the serial-port connector pinout. Serial port 0 typically serves as a system debugging console. The TIP board typically sends debugging messages, such as asserts, fault messages, and trace statements, to this port. This interface can also support a command line or other method of accepting user input. For information about the I/O address locations, refer to Table 2-1 and Table 2-2. Serial port 1 is typically dedicated for use by a software debugger. For example, the CAD-UL debugger can communicate with the board-level monitor using this port. 50 5 *1 (6 '6 57 6, & 62 '7 '& ' (7 5 6 1 76 87 5 ' $03 Figure 2-3. Serial-Port Connector Pinout Test Interface Port Board User's Manual 2-5 TIP.book Page 6 Friday, April 23, 1999 10:38 AM Table 2-1. I/O Map for 8-Bit Addressing for Serial Port Address Read/Write Description 310h-317h R/W Serial port 0 318h-31Fh R/W Serial port 1 Table 2-2. I/O Map for 16-Bit Addressing for Serial Port 2-6 Address Read/Write Description 320h-32Eh R/W Serial port 0 330h-33Eh R/W Serial port 1 Test Interface Port Board User's Manual TIP.book Page 7 Friday, April 23, 1999 10:38 AM Programming the Serial Ports This section contains general information about the programming operations and functions of the serial ports including operating mode, UART operation, interrupts, and registers. Operating Mode The 16550-compatible UART mode (FIFO mode) contains two 16-byte FIFOs for transmitting and receiving to off-load the CPU from repetitive service routines. The CPU can write 16 bytes to the transmit FIFO and use the THRE interrupt or poll the THRE bit to trigger another 16 bytes. The receive FIFO has a programmable trigger level that can interrupt the CPU at 1, 4, 8, or 16 bytes present. Writing a byte to a full transmit FIFO results in the last byte being lost. If the receive FIFO is full, receiving one more character generates an overrun error. The last character received is lost. The remaining 16 bytes in the FIFO are unchanged. UART Operation The UART converts serial data received on the serial input line (SIN) into parallel data that can be processed by the microcontroller. The UART also converts parallel data into serial data for transmission off the chip on the serial output line (SOUT). Data can be transmitted and received at the same time. To generate the baud rate of the transfer, the UART clock is divided by a divisor value chosen by the programmer. The UART baud-rate generator automatically calculates the baud rate from the divisor value that is programmed into the two baud rate divisor registers (divisor latch LSB and divisor latch MSB). These registers are read at initialization to set the baud rate for the transfer. Each byte of data is transferred using a format called a frame. The transmitter and receiver must agree on the frame format, in addition to the baud rate, or the transmission is not successful. The frame format is determined by the value written into the Line Control register. A frame consists of a start bit, five to eight data bits, an optional parity bit, and either 1, 1.5, or 2 stop bits. Transmission of a frame is initiated when software writes a byte to the Transmit Holding register. Reception of a frame is initiated when a start bit is received (the SIN input is driven Low for one baud-rate clock period). This start bit allows the receiver to synchronize its clock with the sender's clock. Errors are reported in the Line Status register. Test Interface Port Board User's Manual 2-7 TIP.book Page 8 Friday, April 23, 1999 10:38 AM Interrupts The serial port supports the standard UART interrupts as follows: * Received Data Available * Transmit Holding Register Empty * Modem Status * Receiver Line Status If two interrupt sources are pending simultaneously, only the highest priority interrupt is indicated by the ID2-ID0 field of the Interrupt ID Register. When the interrupt source is cleared, a subsequent read from this port will return the next highest priority interrupt source. Registers The registers store three types of information: control, status, and data. The divisor latch access bit (DLAB) in the Line Control register (bit 7) is used with the address, read, and write inputs to select the register that is written to or read from. The Transmit Holding register and Receive Buffer register are data registers that hold from five to eight bits of data. If less than eight bits of data are transmitted, data is right justified to the least significant bit. Bit 0 of a data word is always the first serial data bit received and transmitted. The data registers are double-buffered so that read and write operations can be performed when the serial port is performing the parallel-to-serial or serial-to-parallel conversion. The following registers are available on the serial port. The bits for these registers are described in the TI TL16C552 Specification. * Line Control Register: This register is used to configure the format of the UART frame for data transfer, including character length, stop bits, and parity. * Divisor Latch LSB: This register holds the least significant byte of a 16-bit baud rate clock divisor that is used to generate the 16x baud clock (when DLAB is 1). * Divisor Latch MSB: This register holds the most significant byte of the clock divisor (when DLAB is 0). * Transmitter Holding Register: The byte to be transmitted is written to this write-only register (when DLAB is 0). * Receive Buffer Register: The received byte is read from this read-only register (when DLAB is 0). This register shares an address with the Transmit Holding Register. 2-8 Test Interface Port Board User's Manual TIP.book Page 9 Friday, April 23, 1999 10:38 AM * Interrupt Enable Register: This register enables the following serial port interrupts: modem status, receiver line status, transmitter holding empty, received data available, and time-out interrupts (when DLAB is 0). * Interrupt Identification Register: This is a read-only register used to identify UART interrupts. * FIFO Control Register: This is a write-only register used to enable and control the FIFO in 16650-compatible mode. * Line Status Register: This register shows the status of the data transfer, including parity and framing errors, in addition to break and empty indicators. * Modem Control Register: This register is used to enable interrupts and loopback diagnostic mode, and to assert RTS and DTR. * Modem Status Register: This register contains both real-time and latched status bits for DCD, RIN, DSR, and CTS. * Scratch Pad Register: This is a general purpose I/O location used to hold temporary data and is not required for serial data transfer. Configuring the Serial Port for DTE Because the TIP board provides information to a terminal, it is considered data carrier equipment (DCE), and the serial ports are configured accordingly in its default design. You can also configure the TIP board to serve as data terminal equipment (DTE) if necessary. To reconfigure serial port 0 to operate as DTE, use the following procedure: 1. Depopulate resistors R24 through R31. 2. Populate resistors R44 through R50, located on the back of the board. 3. A gender changer is now required for serial port 0, either on the TIP board end or the connecting cable end. To reconfigure serial port 1 to operate as DTE, use the following procedure: 1. Depopulate resistors R34 through R41. 2. Populate resistors R51 through 57, located on the back of the board. 3. A gender changer is now required for serial port 1, either on the TIP board end or the connecting cable end. Test Interface Port Board User's Manual 2-9 Parallel Port NOTE: For more information about initializing the parallel port, refer to the Texas Instruments TL16C552 specification. The TIP board contains a Texas Instruments TL165552 chip that controls the parallel port and two serial ports (for more information about the serial ports, refer to "Serial Ports" on page 2-5). The parallel port can be used for very fast downloads or for connecting to a printer for logging purposes. The interrupt line from this port is connected to a dedicated pin on the interface connector, or connected to a shared interrupt circuit with one signal feeding back to the interrupt connector. Figure 24 illustrates the parallel port connector pinout. For information about the I/O address locations, refer to Table 2-3 and Table 2-4. 6/ * * &7 1' 3( 1' 6 ' 1' ( ' $6 %8 * $ * * * * * 6< 1' &. 1' ' 1' ' 1' ' 1' ' 1' ' /,1 ,7 55 )% 7% $03 Figure 2-4. Parallel-Port Connector Pinout 2-10 Test Interface Port Board User's Manual TIP.book Page 11 Friday, April 23, 1999 10:38 AM Table 2-3. I/O Map for 8-Bit Addressing for Parallel Port Address Read/Write Description 320h 321h 322h R/W Parallel port Table 2-4. I/O Map for 16-Bit Addressing for Parallel Port Address Read/Write Description 340h 342h 344h R/W Parallel port Test Interface Port Board User's Manual 2-11 TIP.book Page 12 Friday, April 23, 1999 10:38 AM Programming the Parallel Port The TI TL16C552 parallel port interface is controlled primarily by software and provides all the status inputs, control outputs, and the control signals necessary for the external parallel port data buffers. Communication between the host and the peripheral is asynchronous. The parallel port data path is external to the microcontroller. The parallel port can be physically mapped to one of two different I/O locations or can be completely disabled. Only edge-triggered interrupts are supported. The parallel port can connect to a Centronics-style printer interface. The parallel port is selected when chip select 2 (CS2) is low. The state of the read (IOR) and write (IOW) terminal controls the read or write function of the register. The Read Data register controls when the microprocessor can read information on the parallel bus. The parallel port interface is mapped to 320h-322h (8-bit) or 340h-344h (16-bit). The following direct-mapped registers are available. * Read Data Register: This register enables the microprocessor to read the information on the parallel bus. * Read Status Register: This register enables the microprocessor to read the status of the printer in the six most significant bits. The status bits are: printer busy (BSY); acknowledge (ACK), a handshake function; paper empty (PE); printer selected (SLCT); error (ERR); and printer interrupt (PRINT). * Read Control Register: This register enables the state of the control lines to be read. * Write Data Register: This register enables the microprocessor to write a byte to the parallel bus. * Write Control Register: This register sets the state of the control lines. These states are: direction (DIR); interrupt enable (IN2 EN); select in (SLIN); initialize the printer (INIT); autofeed the paper (AFD); and strobe (STR), which informs the printer of the presence of a valid byte on the parallel bus. 2-12 Test Interface Port Board User's Manual TIP.book Page 13 Friday, April 23, 1999 10:38 AM Ethernet Controller Port NOTE: For information about initializing the 10BaseT Ethernet controller port and for correct setup and configuration of the Ethernet, refer to the AMD Am79C961A PCnet-ISA+ Single Chip, Plug & Play Full Duplex Ethernet Controller for ISA specification, order #18183. The following are the 8-bit and 16-bit base addresses for the Ethernet: Base addresses: 8-bit = 220h, 16-bit = 220h The TIP board provides an Ethernet controller port that can be run in interruptdriven mode. The Ethernet controller port supports software downloading and debugging over a network. For example, the CAD-UL debugger uses this capability. Many devices already have an Ethernet controller port for use by the device application. However, it is usually not possible to use the device port for running the debugger. For example, if the system is stopped at a break point, and in the context of the debug monitor, then the driver and TCP/IP stack cannot run. However, the TIP board Ethernet controller port can be driven in a polled manner and can function independently from the application drivers and protocol stacks. All of the interrupts from the Ethernet controller are gathered into a single interrupt signal that is connected to a dedicated pin on the interface connector or through a shared interrupt circuit. The Ethernet controller port can run in interrupt-driven mode. Test Interface Port Board User's Manual 2-13 TIP.book Page 14 Friday, April 23, 1999 10:38 AM LCD NOTE: For more information about the LCD driver, refer to the Hitachi HD44780U-II LCD Driver data sheet. Overview The LCD, illustrated in Figure 2-5, is a 2 x 20 character, ASCII-decoded display for displaying text. The display can contain any type of text. Being ASCII-decoded, the LCD enables the user to represent alphabetical characters in the display. For example, writing 41h to a display location causes an A to appear on the LCD. Software can only write to this display; it cannot read the data back. For information about the I/O address locations, refer to Table 2-5 and Table 2-6. The R67 potentiometer adjusts the contrast on the LCD. With the front of the board facing you (the main interface connector on the right), turn the thumb wheel on the R67 counterclockwise to dark the contrast on the LCD, making the characters more visible. When the LCD appears to be off and the board is powered up, try adjusting the potentiometer. MDLS-20265K Figure 2-5. LCD Display 2-14 Test Interface Port Board User's Manual TIP.book Page 15 Friday, April 23, 1999 10:38 AM Table 2-5. I/O Map for 8-Bit Addressing for ASCII Display Address Read/Write 30Ch 30Dh 30Eh 30Fh W Description ASCII display--write control instructions ASCII display--busy flag / address read ASCII display--write data to LCD ASCII display--read data Table 2-6. I/O Map for 16-Bit Addressing for ASCII Display Address Read/Write 308h 30Ah 30Ch 30Eh W Description ASCII display--write control instructions ASCII display--busy flag / address read ASCII display--write data to LCD ASCII display--read data Configuring the LCD You must set up the LCD for 8-bit operation and 8-digit x 2-line display. The powerup procedure detailed in "Board Power" on page 1-1 should initialize the LCD and leave it ready for configuration. For a quick configuration of the LCD, use the following procedure. If you encounter any problems or need more detailed information, refer to the Hitachi spec, HD44780U (LCD-II) (Dot Matrix Liquid Crystal Controller/Driver). 1. To set the LCD to 8-bit operation, 2-line display, and 5x8 dot character font, write 38h to the ASCII Display-Write Control Instructions address listed in the tables in "I/O Maps" on page 2-32. This write should clear the LCD screen. 2. To turn on the display and the cursor, write OEh to the ASCII Display-Write Control Instructions address. After this write, the cursor should appear on the LCD screen. Test Interface Port Board User's Manual 2-15 3. To set the LCD mode to increment the address by one and to shift the cursor to the right at the time of writing, write 06h to the ASCII Display-Write Control Instructions address. The LCD is now ready to display the character for the respective 8-bit ASCII code. For example, writing 41h, 4Dh, and 44h in sequence to the ASCII Display-Write Data address should display "AMD" on the LCD screen. Hexadecimal Display The eight-segment hexadecimal display, illustrated in Figure 2-6, behaves much like the ASCII-decoded display, but displays binary information in hexadecimal format instead of ASCII-decoded data. This display contains eight hexadecimal digits for displaying values up to 32 bits wide. For example, during debugging, the value of a CPU or peripheral register can be written to the display for viewing without software decoding. Software can only write to this display; it cannot read back the value. To display a hexadecimal value on the eight-segment display, write the bytes of the value to the appropriate I/O addresses as shown in Table 2-7 and Table 2-8. T o p V ie w T IL 3 1 1 Figure 2-6. Eight-Segment Display 2-16 Test Interface Port Board User's Manual TIP.book Page 17 Friday, April 23, 1999 10:38 AM Table 2-7. I/O Map for 8-Bit Addressing for Hexadecimal Display Address Read/Write 306h 307h 308h 309h W Description Hex Display--Byte0: Hex digits 1 and 0 Hex Display--Byte 1: Hex digits 3 and 2 Hex Display--Byte 2: Hex digits 5 and 4 Hex Display--Byte 3: Hex digits 7 and 6 Table 2-8. I/O Map for 16-Bit Addressing for Hexadecimal Display Address Read/Write 310h 312h 314h 316h W Description Hex display--Byte 0: Hex digits 1 and 0 Hex display--Byte 1: Hex digits 3 and 2 Hex display--Byte 2: Hex digits 5 and 4 Hex display--Byte 3: Hex digits 7 and 6 Test Interface Port Board User's Manual 2-17 General-Purpose LEDs NOTE: For information about programming the information, refer to "Discrete LED Outputs Register" on page 2-19. Eight LEDs The eight general-purpose LEDs indicate status events or errors. Software can write to and read from the LED buffer. This capability supports a read-modify-write style of operation. For the TIP board, the green cathode (light) is used. Figure 2-7 illustrates the pinout of one of the LEDs. SSL-LX15YGC Figure 2-7. LED Pinout 2-18 Test Interface Port Board User's Manual TIP.book Page 19 Friday, April 23, 1999 10:38 AM Discrete LED Outputs Register The following are the 8-bit and 16-bit addresses for the Discrete LED Outputs register: Address: 8-bit = 305h, 16-bit = 300h The Discrete LED Outputs register controls the eight individual LEDs on the TIP board, as shown in Table 2-9. This is a read/write register and can be used in a read-modify-write manner. * When an LED bit is set to 1, the corresponding LED is turned on. * When an LED bit is cleared to 0, the LED is turned off. When writing to this register, the new value is latched at the LED drivers and the LEDs immediately reflect the state of the newly written bits. Table 2-9. Discrete LED Outputs Register Bit Definitions Bit LED Description 0 D0 The least significant LED (right-most LED) 1 D1 The next most significant LED 2 D2 The next most significant LED 3 D3 The next most significant LED 4 D4 The next most significant LED 5 D5 The next most significant LED 6 D6 The next most significant LED 7 D7 The most significant LED (left-most LED) Test Interface Port Board User's Manual 2-19 Debug Headers The TIP board provides three HP logic analyzer debug headers for easy address, data, and control signal debug access. These headers (2 x 10-pin shrouded, lowprofile header connector) allow connection between the logic analyzer and the test points using the HP flex cable header. The debug signals are on the following header as shown in Figure 2-8: * Address bus * Data bus and control signals * Port chip selects and interrupts, and Ethernet interrupt For pinout information, refer to the TIP board schematics included in your kit. . / & 9 ' . /& ' ' ' ' ' ' ' ' ' '1 * ' ' ' ' ' ' +3/2*,&$1$/<=(5+($'(5 Figure 2-8. HP Logic Analyzer Header 2-20 Test Interface Port Board User's Manual General-Purpose Inputs and Outputs The TIP board provides eight discrete inputs and eight discrete outputs through a standard 20-pin header, and eight discrete inputs through a DIP switch (illustrated in Figure 2-9). These are TTL/CMOS signals. *3,2 6 ,13876 1& 1& ' ' ' ' ' ' ' ' *1' 1& ' ' ' ' ' ' ' ' 2873876 Figure 2-9. General-Purpose Input/Output Header The inputs are general-purpose and allow the software to only read the input buffer. Therefore, these inputs do not support a read-modify-write style of operation. For information about reading the input buffer, see "Discrete Inputs Register" on page 2-22. The outputs can be directly connected to a logic analyzer by a straight-through ribbon cable. These outputs support the tracing of software operation, not hardware. For example, to measure the interrupt latency of an interrupt and the interrupt handler execution time, simply toggle a bit on entry to and exit from the interrupt service routine (ISR). You can measure this with an in-circuit emulator (ICE), but it can be difficult to set up. However, using the TIP board, you can measure the above operation by adding simple instructions to the ISR and using a logic analyzer. Software can write to and read from the output buffer thereby supporting a read-modify-write operation. For information about reading or writing the output buffer, see "Discrete Outputs Register" on page 2-23. Test Interface Port Board User's Manual 2-21 TIP.book Page 22 Friday, April 23, 1999 10:38 AM Discrete Inputs Register The following are the 8-bit and 16-bit addresses for the Discrete Inputs register: Address: 8-bit = 303h, 16-bit = 306h The Discrete Inputs register returns the state of the eight general-purpose inputs on the TIP board, as shown in Table 2-10. These inputs appear on the INPUT side of connector P7. The value of each bit indicates the current state of its associated input. * When a bit reads 1, the input is currently active (turned on/set to 5 V at the output). * When a bit reads 0, the input is currently inactive (turned off/set to 0 V at the output). Writing to this register has no effect on the state or operation of the TIP board. Table 2-10. Discrete Inputs Register Bit Definitions 2-22 Bit Pin Description 0 15 The most significant (left most) output 1 13 The next most significant output 2 11 The next most significant output 3 9 The next most significant output 4 7 The next most significant output 5 5 The next most significant output 6 3 The next most significant output 7 1 The least significant (right most) output Test Interface Port Board User's Manual TIP.book Page 23 Friday, April 23, 1999 10:38 AM Discrete Outputs Register The following are the 8-bit and 16-bit addresses for the Discrete Outputs register: Address: 8-bit = 302h, 16-bit = 304h The Discrete Outputs register controls the eight individual general-purpose outputs on the TIP board, as shown in Table 2-11. These outputs appear on the OUTPUT side of connector P7. This read/write register can be used in a read-modify-write manner. When this register is read, the value of each bit indicates the current state of its associated output. * When an output bit is set to 1, the output is currently active (turned on/set to 5 V at the output). * When an output bit is cleared to 0, the output is currently inactive (turned off/set to 0 V at the output) When writing to this register, the new value is latched to the output drivers and the output pins immediately reflect the state of the newly written bits. Table 2-11. Discrete Outputs Register Bit Definitions Bit Pin Description 0 2 The least significant (right most) output 1 4 The next most significant output 2 6 The next most significant output 3 8 The next most significant output 4 10 The next most significant output 5 12 The next most significant output 6 14 The next most significant output 7 16 The most significant (left most) output Test Interface Port Board User's Manual 2-23 TIP.book Page 24 Friday, April 23, 1999 10:38 AM DIP Switch NOTE: For information about reading the state of the DIP switch, refer to "DIP Switch Inputs Register" on page 2-25. Eight-Position DIP Switch D0 D1 D2 D3 D4 D5 D6 D7 The TIP board provides an eight-position DIP switch, illustrated in Figure 2-10, that provides configuration information and mode control of the host software. For example, a DIP switch could enable special debugging features or change the system mode of operation. These switch inputs do not cause interrupts. O F F 1 2 3 4 5 6 7 8 AMP 3-435640-9 Figure 2-10. DIP Switch 2-24 Test Interface Port Board User's Manual TIP.book Page 25 Friday, April 23, 1999 10:38 AM DIP Switch Inputs Register The following are the 8-bit and 16-bit addresses for the DIP Switch Inputs register: Address: 8-bit = 304h, 16-bit = 302h The DIP Switch Inputs register (read-only) returns the state of the eight-position DIP switch (SW4) on the TIP board, as shown in Table 2-12. When this register is read, the value of each bit indicates the current state of its associated DIP switch. * When a bit reads 1, the input is currently active (turned on). * When a bit reads 0, the input is currently inactive (turned off). Writing to this register has no effect on the state or operation of the TIP board. Table 2-12. DIP Switch Inputs Register Bit Definitions Bit SW Description 0 0 The first (least significant/left-most) switch 1 1 The second switch 2 2 The third switch 3 3 The fourth switch 4 4 The fifth switch 5 5 The sixth switch 6 6 The seventh switch 7 7 The eighth (most significant/right-most) switch Test Interface Port Board User's Manual 2-25 Reset Button The following are the 8-bit and 16-bit addresses for the Interrupt Reset register: Address: 8-bit = 34Ah, 16-bit = 34Ah The TIP board provides a reset button, illustrated in Figure 2-11. The reset button toggles a signal to the host board which then performs a system-wide hardware reset. The signal connected to the RESET pin on the interface connector (pin 50) should be an input to the host board and should connect to the main microcontroller reset. For example, on the ElanTM SC400 microcontroller, this signal is connected to the RESET input, which is corresponds to the POWERGOOD pin in the AT system architecture. Alcoswitch FSM4J Figure 2-11. Reset Button This same reset can also be performed remotely through pin 9 of the serial ports. To use this feature, you must remove resistor R32 (for serial port 1) and R42 (for serial port 0) from the TIP board, then populate resistors R33 and R43 for serial ports 0 and 1 respectively. The TIP board discrete registers should not respond to the hardware reset signal. However, this condition is not certain, even under normal conditions. For example, a hardware reset should not change the state of the LCD, hex display, discrete LEDs, discrete inputs, or discrete outputs. A hardware reset does reset the serial ports and the parallel port. 2-26 Test Interface Port Board User's Manual Flash Memory NOTE: For more information about the flash memory, refer to the Am29F040 data sheet. The TIP board is equipped with Flash memory. The socket in which the Flash memory is mounted supports a variety of Flash memory options (any 8-bit device) that can be installed in place of the existing unit. Figure 2-12 illustrates the Flash memory for identification purposes. $0) Figure 2-12. 8-Bit Flash Memory Identification Test Interface Port Board User's Manual 2-27 TIP.book Page 28 Friday, April 23, 1999 10:38 AM Using the Flash Memory You can program the Flash memory with diagnostics, a monitor, or a small application. However, a primary design function of the Flash memory is to provide the host board with an alternate boot location. For example, if the host board has a soldered-down Flash memory device and that Flash memory becomes corrupted, you can reprogram the Flash memory without removing it from the board by using the functions of the TIP board. You can accomplish this task by programming the TIP board Flash memory with a utility program, like the AMD E86MONTM software, which has a reprogram function to allow copying the contents of the TIP board Flash memory to the host board Flash memory. More specifically, when the TIP board is hosted by an Am186TMCC/CH/CU device microcontroller that is connected to a monitor, the TIP board can reprogram the Customer Development Platform (CDP) on-board Flash memory. With the Flash memory on the TIP board being programmed with E86MON software, the CDP can be booted through the TIP board. Now you can begin the reprogramming sequence by entering z on the keyboard. Follow a few simple instructions, and the Flash memory on the Am186CC/CH/CU CDP device is reprogrammed. This is a simpler process than removing the soldered down Flash memory on the CDP board, programming it on a programmer, then re-soldering the Flash memory back on to the CDP device. 2-28 Test Interface Port Board User's Manual TIP.book Page 29 Friday, April 23, 1999 10:38 AM Selecting the Flash Memory Jumper block 1 (JP1) selects which Flash memory is used, either the internal (TIP board) or the external (host board) Flash memory. To select the use of the internal 8-bit DIP Flash, jumper pins 2 and 3 on JP1 and drive a logic low to the FLASHCS signal (pin 58 of P1 of the main interface connector). To select the use of the host board Flash, jumper pins 1 and 2 on JP1. Figure 2-13 indicates the pin locations on JP1. JP1 Pin 1 Pin 3 Ext Int Figure 2-13. JP1 Pin Locations Test Interface Port Board User's Manual 2-29 TIP.book Page 30 Friday, April 23, 1999 10:38 AM Interrupts WARNING: The peripheral interrupt signals on the TIP board are not terminated. As a result, the software must ensure that each peripheral interrupt is enabled so the interrupt input to the OR gate that is driving the MAIN_IRQ signal is not floating. Refer to the peripheral data sheets for information about how this is done. Alternately, the target board may use pull-down resistors on the peripheral interrupt signals. The TIP board supports interrupts with the following features: * An interrupt push button (SW2) * Five interrupt sources on the board: two serial ports, the parallel port, the Ethernet controller port, and the user-interrupt button For designs that can accommodate all the individual signals and want to have dedicated interrupts, the serial ports, parallel port, and Ethernet controller port have individual interrupt signals going to the main interface connector (P1). For designs that have limited connector space, these same signals are also logically ORed together on the MAIN_IRQ signal, which is also routed to the main connector. The interrupt generated by the interrupt push button is routed to the main connector only through the MAIN_IRQ signal. When the interrupt button is pressed, the SW_IRQ signal (generated from the MACH), goes high causing the MAIN_IRQ signal to also go high. The SW_IRQ signal will remain high until the Interrupt Reset register (address 34Ah) in the MACH is written to. For the address of this register, refer to "I/O Maps" on page 2-32. MACH(R) Device The peripherals on the TIP board are interfaced to the host system through a macro array CMOS high-density/high-performance (MACH(R)) device that provides individual chip selects for each on-board peripheral device (except the Ethernet controller port). This interface gives the TIP board a degree of independence from the host system. For a complete listing of the current MACH(R) device code, see Appendix A, "MACH(R) Device Equations". 2-30 Test Interface Port Board User's Manual TIP.book Page 31 Friday, April 23, 1999 10:38 AM I/O Address Mode The TIP board supports 8-bit addressing or 16-bit addressing. The 8-bit or 16-bit addressing is determined by the SW3 switch. Selecting the optional 8-bit cycle mode changes the MACH device I/O map address. Note that the peripheral access addresses change. For the I/O map addresses in the different addressing modes, see "I/O Maps" on page 2-32. If you need to run the TIP board in 8-bit mode on a 186 family board, you must select the 8-bit mode. For example, to select the 8-bit I/O addressing mode on the Am186ED processor, write 01b to the Auxiliary Configuration register at physical location FFF2h. By default, this register is set to 00b for 16-bit I/O addressing. Consult the host microcontroller documentation for the correct 8- or 16-bit I/O addressing configuration. Test Interface Port Board User's Manual 2-31 TIP.book Page 32 Friday, April 23, 1999 10:38 AM I/O Maps Table 2-13 lists the 8-bit I/O address locations for the respective peripherals, and Table 2-14 lists the 16-bit I/O address locations. Table 2-13. I/O Map for 8-Bit Addressing 2-32 Address Read/Write Description 302h R/W 303h R Discrete Inputs register 304h R DIP Switch Inputs register 305h R/W 306h 307h 308h 309h W Hex Display-Byte 0: Hex digits 1 and 0 Hex Display-Byte 1: Hex digits 3 and 2 Hex Display-Byte 2: Hex digits 5 and 4 Hex Display-Byte 3: Hex digits 7 and 6 30Ch 30Dh 30Eh 30Fh W ASCII display-write control instructions ASCII display-busy flag / address read ASCII display-write data to LCD ASCII display-read data 310h-317h R/W Serial port 0 318h-31Fh R/W Serial port 1 320h 321h 322h R/W Parallel port 34Ah W Interrupt reset (write to this address to reset the push button interrupt signal) 348h R Version register 220h R/W Discrete Outputs register Discrete LED Outputs register Ethernet base address Test Interface Port Board User's Manual TIP.book Page 33 Friday, April 23, 1999 10:38 AM Table 2-14. I/O Map for 16-Bit Addressing Address Read/Write Description 300h R/W 302h R 304h R/W Discete Outputs register 306h R Discrete Inputs register 308h 30Ah 30Ch 30Eh W ASCII display-write control instructions ASCII display-busy flag / address read ASCII display-write data to LCD ASCII display-read data 310h 312h 314h 316h W Hex display-Byte 0: Hex digits 1 and 0 Hex display-Byte 1: Hex digits 3 and 2 Hex display-Byte 2: Hex digits 5 and 4 Hex display-Byte 3: Hex digits 7 and 6 320h-32Eh R/W Serial port 0 330h-33Eh R/W Serial port 1 340h 342h 344h R/W Parallel port 34Ah W Interrupt reset (write to this address to reset the push button interrupt signal) 348h* R Version register 220h R/W Discrete LED Outputs register DIP Switch Inputs register Ethernet base address * Currently, the Version register is only accessible by the Am186 microcontrollers. Test Interface Port Board User's Manual 2-33 TIP.book Page 34 Friday, April 23, 1999 10:38 AM Timing Certain 186 microcontroller boards require added wait states to accommodate the timing specifications of the 16C550 UARTs. For example, on the SD186ED demonstration board, the PCS and MCS Auxiliary (MPCS) register needs to be set to a defined state by writing 8038h to physical location FFA8h. Then, insert three wait states to the Peripheral Chip Select (PCS) register by writing 0073h to physical location FFA4h. Refer to the 16C550 specification and the microcontroller manual of the host board to determine the correct configuration and the appropriate method of adding wait states. Version Register NOTE: Currently, the Version register is only accessible by the Am186 microcontrollers. The following are the 8-bit and 16-bit addresses for the Version register: Address: 8-bit = 348h, 16-bit = 348h The Version register contains the version of the code that is running in the MACH(R) programmable device and in the revision of the TIP board. This is a read-only register. Table 2-15 lists the bit mappings for this register. 2-34 Test Interface Port Board User's Manual TIP.book Page 35 Friday, April 23, 1999 10:38 AM Table 2-15. Version Register Bit Definitions Bits Read/Write 0-3 R Description MACH Device Code Version These read-only bits reflect the version of the code in the MACH programmable part, which controls the TIP board. This value starts at one and is incremented every time a new version of the MACH device code is released from AMD. This value enables software to detect which version of the MACH device is resident on the TIP board and to modify its behavior accordingly. This value also helps you determine when to upgrade the MACH device code. Writing to these bits has no effect on the state of these bits, the MACH device, or any other devices on the TIP board. 4-7 R TIP Board Revision These read-only bits reflect the revision of the physical TIP board. These bits are not necessarily incremented with every spin of the TIP board; incrementing depends on the significance of any changes made to the board. Writing to these bits has no effect on the state of these bits, the MACH device, or any other devices on the TIP board. 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>VHUFV D D D D D D D D D D D D D D D D D@ &203RUWK)K VHUFV >D D D D D D D D D D D D D D D D D V@ >VHUFV D D D D D D D D D D D D D D D D D@ 3DUDOOHO3RUWKK SDUFV >D D D D D D D D D D D D D D D D D D V@ >SDUFV D D D D D D D D D D D D D D D D D D@ (/6( ??????????????????????????????,6$6<67(0%,7,2$''5(66(48$7,216 ',6&5(7(*322XWSXW KGUOWFON >DGGU K ZU DHQ@ ',6&5(7(*32,QSXW KGUOWRH >DGGU K UG DHQ@ ',6&5(7(*3,,QSXW KGUEIRH >DGGU K UG DHQ@ ',36:,QSXWV GLSVZRH >DGGU K UG DHQ@ /('2XWSXW OHGFON >DGGU K ZU DHQ@ /(',QSXW OHGRH >DGGU K UG DHQ@ !!!!!!!!!!!!+(;',63/$<6 %\WH2XWSXW KH[FV >DGGU K ZU DHQ@ $ 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDO TIP.book Page 9 Friday, April 23, 1999 10:38 AM %\WH2XWSXW KH[FV >DGGU K ZU DHQ@ %\WH2XWSXW KH[FV >DGGU K ZU DHQ@ %\WH2XWSXW KH[FV >DGGU K ZU DHQ@ !!!!!!!!!!/&' (1$%/(&K)K OFGHQ >D D D D D D D D D D D D D D D D D D UG DHQ@ >D D D D D D D D D D D D D D D D D D ZU DHQ@ 6(/(&765(*,67(56 OFGUV D >D D D D D D D D D D D D D D D D D D@ ^,IDLVD]HUR \RXDUHFRPPXQLFDWLQJWRWKH,QVWUXFWLRQ 5HJLVWHU ^,IDLVDQRQH \RXDUHFRPPXQLFDWLQJWRWKH'DWD5HJLVWHU 6(/(&76'$7$5($'25:5,7( OFGUZ D >D D D D D D D D D D D D D D D D D D@ ^,IDLV]HUR LWLVDZULWHF\FOH ^,IDLVRQH LWLVDUHDGF\FOH !!!!!!!!!!!!32576 &203RUWKK VHUFV >D D D D D D D D D D D D D D D D D DHQ@ &203RUWK)K VHUFV >D D D D D D D D D D D D D D D D D DHQ@ 3DUDOOHO3RUWKK SDUFV >D D D D D D D D D D D D D D D D D D DHQ@ (1',) (1',) '$7$%8675$16&(,9(5(1$%/( GEJ D D D D D D D D D D D D D WLSIOKFV 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDO $ TIP.book Page 10 Friday, April 23, 1999 10:38 AM >VHO DHQ >UGZU@@(QDEOHGDWDEXIIHUIRU V$(1 >GEJ VHO DHQ@)RU(QHWGDWDKDGUHTXLUHGKROGWLPHDIWHUULVLQJ HGJHRIUHDG WKHUHIRUHKDGWRODWFKWKHEXIIHUHQDEOHZLWK V $(1 '$7$75$16&(,9(5',5(&7,21'$7$',5(&7,21'()$8/7672:$5'67+(7,3 GEGLU UG>IODVKUG WLSIOKFV@ $ 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDO TIP.book Page 1 Friday, April 23, 1999 10:38 AM Index Numerics B 10BaseT ethernet, xi 16770 RS-232 serial ports, xi 16-bit addressing feature, xii 8-bit addressing, xii 8-bit DIP Flash memory, xii 8-bit Flash memory identification, 2-27 8-segment (32 bit) hexadecimal display, xi barrel (P2) and ribbon cable (P1) connectors locations, 1-2 bit definitions DIP Switch Inputs register, 2-25 Discrete Inputs register, 2-22 Discrete LED Outputs register, 2-19 Discrete Outputs register, 2-23 Version register, 2-35 block diagram TIP board, 2-4 board description, xi features, xi host connecting to, xii, 2-1 layout, 2-3 power, 1-1 serial ports, 2-5 TIP block diagram, 2-4 BSY, 2-12 A ACK, 2-12 address bus, 2-20 addressing 16-bit, xii 8-bit, xii AFD, 2-12 Am29F010 Flash memory, 2-27 Am79C961, xiii, 2-13 ASCII display 16-bit addressing, 2-33 8-bit addressing, 2-32 I/O map 8- and 16-bit addressing, 2-15 ASCII-decoded display, xi hexadecimal, 2-16 LCD, 2-14 C CDP, See customer development platform, 228 code MACH(R) device, 2-30, 2-35 configuring LCD, 2-15 serial port for DTE, 2-9 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDO ,QGH[ TIP.book Page 2 Friday, April 23, 1999 10:38 AM connector, 1-5 60-pin, xi main interface, 1-5 pinout parallel port, 2-10 serial port, 2-5 control signals debug header, 2-20 parallel port, 2-12 Customer Development Platform (CDP), 228 D data bus and control signals, 2-20 debug header description, 2-20 signals address bus, 2-20 data bus and control, 2-20 port chip selects and interrupts and Ethernet interrupts, 2-20 device MACH(R), xii, A-1 DIP switch description, 2-24 inputs register, xii, 2-3 8-bit addressing, 2-32 layout, 2-24 DIP Switch Inputs register 16-bit addressing, 2-25, 2-33 8-bit addressing, 2-25 bit definitions, 2-25 description, 2-25 DIR, 2-12 Discrete Inputs register 16-bit addressing, 2-22, 2-33 8-bit addressing, 2-22, 2-32 bit defintions, 2-22 description, 2-22 Discrete LED Outputs register, 2-19 ,QGH[ 16-bit addressing, 2-33 8-bit addressing, 2-32 bit definitions, 2-19 discrete LEDs (green), xi Discrete Outputs register, 2-23 16-bit addressing, 2-33 8-bit addressing, 2-32 bit definitions, 2-23 discrete TTL/CMOS outputs, xii display LCD, xi, 2-14 Divisor Latch LSB register, 2-8 Divisor Latch MSB register, 2-8 documentation conventions, xiv order number, xii support, iii E E86MONTM, 2-28 eight-segment display hexadecimal, 2-16 ENETIRQ, 1-6 equations MACH(R) device, A-1 ERR, 2-12 ethernet 10BaseT, xi controller port, 2-13 Ethernet base address 16-bit addressing, 2-33 8-bit addressing, 2-32 Ethernet interrupt debug header, 2-20 ENETIRQ, 1-6 EXTFLHCS, 1-8 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDO TIP.book Page 3 Friday, April 23, 1999 10:38 AM F H features, xi 10BaseT Ethernet controller port, xi 16550 RS-232 serial ports, xi 2 x 20 character ASCII decoded display, xi 8-bit and 16-bit addressing, xii 8-bit DIP Flash memory, xii 8-segment (32 bit) hexadecimal display, xi discrete LEDs (green), xi discrete TTL/CMOS outputs, xii eight inputs connected to DIP switch and header, xii flexible interface, xii HP logic analyzer debug headers, xi, 220 interrupt button, xii interrupt sources, xii, 2-30 jumper block (JP1), xii MACH(R) device, xii, 2-30, A-1 PC-compatible parallel port, xi programmable registers, xii reset button, xii, 2-26 FIFO Control register, 2-9 figures, list of, viii Flash memory 8-bit identification, 2-27 description, 2-27 selecting, 2-29 using, 2-28 Flash select jumper diagram, 2-29 FLASHCS, 1-8 FLASHRD, 1-7 FLASHWR, 1-8 hexadecimal display, 2-16 16-bit addressing, 2-33 8-bit addressing, 2-32 I/O map 8- and 16-bit addressing, 2-17 Hitachi HD44780U data sheet, xiii HP logic analyzer debug headers, xi, 2-20 HP logic analyzer header layout, 2-20 HRESET, 1-7 I I/O address mode description, 2-31 I/O map 16-bit addressing, 2-33 ASCII display, 2-15, 2-33 DIP Switch Inputs register, 2-33 Discrete Inputs register, 2-33 Discrete LED Outputs register, 2-33 Discrete Outputs register, 2-33 Ethernet base address, 2-33 hexadecimal display, 2-17, 2-33 interrupt reset, 2-33 parallel port, 2-11, 2-33 serial port, 2-6, 2-33 Version register, 2-33 G GND, 1-5 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDO ,QGH[ TIP.book Page 4 Friday, April 23, 1999 10:38 AM 8-bit addressing, 2-32 ASCII display, 2-15, 2-32 DIP Switch Inputs register, 2-32 Discrete Inputs register, 2-32 Discrete LED Outputs register, 2-32 Discrete Outputs register, 2-32 Ethernet base address, 2-32 hexadecimal display, 2-17, 2-32 interrupt reset, 2-32 parallel port, 2-11, 2-32 serial port, 2-6, 2-32 Version register, 2-32 IN2 EN, 2-12 INIT, 2-12 initializing ethernet controller port, 2-13 serial ports, 2-7 input/output header layout, 2-21 inputs, 2-21 DIP switch, 2-24 DIP switch and header, xii inputs and outputs general-purpose, 2-21 interface cable 60-wire, 1-3 orientation, 1-3 interface connector signal descriptions, 1-5 interrupt push button, 2-30 interrupt button feature, xii Interrupt Enable register, 2-9 Interrupt Identification register, 2-9 interrupt reset 16-bit addressing, 2-33 8-bit addressing, 2-32 interrupt sources feature, xii interrupts debug headers, 2-20 ,QGH[ description, 2-30 DIP switch, 2-24 main interface connector, 2-30 serial port, 2-7, 2-8 UART, 2-8 IOCHRDY, 1-7 J JP1, xii, 2-29 jumper block (JP1), xii jumper block 1 (JP1), 2-29 L layout DIP switch, 2-24 HP logic analyzer header, 2-20 input/output header, 2-21 TIP board, 2-2, 2-3 layout and placement, 2-2 LCD, 2-3 configuring, 2-15 description, 2-14 display, 2-14 Hitachi data sheet, xiii layout, 2-2 LEDs, 2-3 eight, 2-18 feature, xi general-purpose, 2-18 layout, 2-2 pinout, 2-18 Line Control register, 2-7, 2-8 Line Status register, 2-7, 2-9 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDO TIP.book Page 5 Friday, April 23, 1999 10:38 AM M MACH device code, A-1 MACH(R) device description, 2-30 equations, 2-30, A-1 feature, xii main interface connector signals, 1-5 main interface connector, xiii 60-wire ribbon cable, xi connecting to host board, 2-1 interrupt source, xii interrupts, 2-30 pinout, xiii, 1-9 pinout signals, 1-5 signal descriptions, 1-5 signals ENETIRQ, 1-6 EXTFLHCS, 1-8 FLASHCS, 1-8 FLASHRD, 1-7 FLASHWR, 1-8 GND, 1-5 HRESET, 1-7 IOCHRDY, 1-7 MAIN_IRQ, 1-7 PARINT, 1-7 SEL186, 1-8 SERINT0, 1-7 SERINT1, 1-7 TA1-TA19, 1-5 TAEN, 1-6 TD0-TD7, 1-5 TIPSEL, 1-6 TIPSEL, 1-5 TRD, 1-6 TRESET, 1-7 TS2, 1-7 TWR, 1-6 VCC, 1-8 MAIN_IRQ, 1-7 interrupts, 2-30 Modem Control register, 2-9 modem status serial port interrupts, 2-8 Modem Status register, 2-9 O operating mode serial port, 2-7 outputs, 2-21 TTL/CMOS, xii P P1 main interface connector, 1-5 ribbon cable connector, 1-2, 1-5 interrupts, 2-30 P2 barrel connector, 1-2 parallel port 16-bit addressing, 2-33 8-bit addressing, 2-32 connector pinout, 2-10 description, 2-10 feature, xi I/O map 8- and 16-bit addressing, 2-11 programming, 2-12 registers Read Control, 2-12 Read Data, 2-12 Read Status, 2-12 Write Control, 2-12 Write Data register, 2-12 PARINT, 1-7 PC-compatible parallel port, xi PE, 2-12 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDO ,QGH[ TIP.book Page 6 Friday, April 23, 1999 10:38 AM pinout LEDs, 2-18 main interface connector, 1-9 parallel port, 2-10 serial port, 2-5 port chip selects, 2-20 power, 2-3 power supply, external 5-V DC, 1-1 powering up, xiii PRINT, 2-12 programmable registers, xii programming parallel port, 2-12 serial port, 2-7 R Read Control register, 2-12 Read Data register, 2-12 Read Status register, 2-12 signal bits ACK, 2-12 BSY, 2-12 ERR, 2-12 PE, 2-12 PRINT, 2-12 SLCT, 2-12 Receive Buffer register, 2-8 received data available serial port interrupt, 2-8 receiver line status serial port interrupts, 2-8 registers DIP Switch Inputs 16-bit, 2-33 feature, xii Interrupt Reset 8-Bit, 2-26 parallel port Read Control, 2-12 Read Data, 2-12 ,QGH[ Read Status, 2-12 Write Control, 2-12 Write Data, 2-12 serial port, 2-7 Divisor Latch LSB, 2-8 Divisor Latch MSB, 2-8 FIFO Control, 2-9 Interrupt Enable, 2-9 Interrupt Identification, 2-9 Line Control, 2-7, 2-8 Line Status, 2-9 Modem Control, 2-9 Modem Status, 2-9 Receive Buffer, 2-8 Scratch Pad, 2-9 Transmitter Holding, 2-8 Version 16-bit, 2-33 16-bit addressing, 2-34 8-bit, 2-32 8-bit addressing, 2-34 bits 0-3, 2-35 bits (0-3, 4-7), 2-35 bits 4-7, 2-35 reset button, xii, 2-26 ribbon cable 60-wire, xi connecting to TIP and host, 1-3 connecting to main interface connector, 1-5 connecting to TIP and host, 1-2 connecting to TIP and host board, 1-1 input/output header, 2-21 orientation, 1-4 S Scratch Pad register, 2-9 SD186ED, 2-34 SEL186, 1-8 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDO TIP.book Page 7 Friday, April 23, 1999 10:38 AM serial port 16550 RS-232, xi 16-bit addressing, 2-33 8-bit addressing, 2-32 configuring for DTE, 2-9 connector pinout, 2-5 description, 2-5 I/O map 8- and 16-bit addressing, 2-6 initializing, 2-7 interrupt transmit holding register empty, 2-8 interrupts, 2-8 modem status, 2-8 received data available, 2-8 receiver line status, 2-8 main interface connector, 2-5 operating mode, 2-7 programming, 2-7 programming information, 2-9 registers, 2-5 Divisor Latch LSB, 2-7, 2-8 Divisor Latch MSB, 2-7, 2-8 FIFO Control, 2-9 Interrupt Enable, 2-9 Interrupt Identification, 2-9 Line Control, 2-8 Line Status, 2-7, 2-9 Modem Control, 2-9 Modem Status, 2-9 Receive Buffer, 2-8 Scratch Pad, 2-9 Transmit Holding, 2-7 Transmitter Holding, 2-8 UART operation, 2-7 SERINT0, 1-7 SERINT1, 1-7 signal descriptions main interface connector, 1-5 SLCT, 2-12 SLIN, 2-12 STR, 2-12 suggested reference material, xiii support third-party, iii SW2 switch interrupts, 2-30 SW3 switch, xii I/O address mode, 2-31 system features and components, 2-1 T TA1-TA19, 1-5 tables, list of, ix TAEN, 1-6 TD0-TD7, 1-5 technical support, iii Texas Instruments TL16C552 parallel port, 2-10 serial port, 2-5 serial port registers, 2-8 specification, xiii timing description, 2-34 TIPSEL, 1-5, 1-6 TL16C552, See Texas Instruments TL16C552, xiii TL16C552, Texas Instruments specification, 2-5, 2-10 Transmit Holding register, 2-7, 2-8 transmit holding register empty serial port interrupt, 2-8 TRD, 1-6 TRESET, 1-7 TS2, 1-7 TWR, 1-6 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDO ,QGH[ TIP.book Page 8 Friday, April 23, 1999 10:38 AM U UART interrupts, 2-8 see also serial port, 2-7 UART operation, 2-7 V VCC main interface connector signal, 1-8 power, 1-1 Version register 16-bit addressing, 2-33 8-bit addressing, 2-32 bit definitions, 2-35 description, 2-34 MACH device code version, 2-35 TIP board revision, 2-35 W Write Control register, 2-12 control line states AFD, 2-12 DIR, 2-12 IN2 EN, 2-12 INIT, 2-12 SLIN, 2-12 STR, 2-12 Write Data register, 2-12 WWW support, iii www.amd.com AMD home page, xiii, A-1 technical support, iii ,QGH[ 7HVW,QWHUIDFH3RUW%RDUG8VHUV0DQXDO