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Contents
About the Test Interface Port Board
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Chapter 1
Getting Started
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System Features and Components
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Appendix A
MACH® Device Equations
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TIP.book Page x Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual xi
About the Test Interface Port
Board
The Test Interface Port (TIP) board was developed as a software debug and
development board. For many reasons, it is often impractical to put extra
peripherals on a target system just for development and software debugging. Serial
ports are a good example. Often, adding extra peripherals makes development more
difficult because the target peripherals are used by the application and cannot be
used for software development and debugging. However, a target containing a
small, 60-pin connector can host the TIP, a board rich in peripherals for
development and software debugging.
The TIP board is a set of peri pherals contained in one convenient location for
software debugging, diagnostics, evaluation, and reference designs. The TIP board
is designed to make it easy and convenient for the software to communicate the
status with an engineer, tester, or even an end user. The TIP board is designed to
support flexible, present-day applications and is used with a target board containing
a microcontroller that can connect to the TIP board through the main interface
connector (60-wire ribbon cable).
TIP Board Features
The TIP board provides the following features:
• Two 16550 RS-232 serial ports (9-pin, DCE).
• One PC-compatible parallel port.
• A 10BaseT Ethernet controller port that can be run in interrupt-driven mode.
• A 2 x 20 character ASCII-decoded display.
• An 8-segment (32-bit) hexadecimal display.
• Eight discrete LEDs (green).
• Three HP logic analyzer debug headers for easy address, data, and control signal
debug access.
TIP.book Page xi Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
xii
• Eight discrete TTL/CMOS outputs (can connect directly to a logic analyzer).
• Eight inputs connected to a DIP switch and header.
• A reset butto n that resets the target.
• An 8-bit DIP Flash memory, socketed to allow for upgrading.
• A jumper block (J P1) for selecting between internal (TIP board) or external
(host board) Fl as h memory.
• A flexible interface for simple and inexpensive connection to a target board.
• An interrupt button.
• Five interrupt sources o n the board: two serial ports, the parallel port, the
Ethernet controller port, and the user-interrupt button. All these interrupts go to
the main interface connector separately . In addition, all these interrupts are logic
ORed into a single signal that also goes to the connector.
• A macro array CMOS high-density/high-performance (MACH®) device that
provides individual chip selects for each on-board peripheral device (except the
Ethernet controller port).
• Support for 16-bit addressing or 8-bit addressing, selected with the SW3 switch.
• Five programmable registers for controlling the TIP board’s operation.
Documentation
The AMD Test Interface Por t Board User’s Manual, order #22505, provides
information on the system and board features, functionality, and interfaces.
Addition al information can be found in the documentation listed on page xiii.
TIP.book Page xii Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual xiii
About This Manual
Chapter 1, “Getting Started” describes the power supply requirements and the main
interface connector configuration for the TIP board. This chapter also explains the
proper procedure for powering up the TIP board.
Chapter 2, “System Features and Components” describes in detail the peripherals,
memory, main interface connector s ignals and pin out, and interrupts of the TIP
board, including the jumper settings and prog rammable registers used to control
the operation of the TIP board.
Appendix A, “MACH® Device Equations” contains a current listing of the MACH
device program code.
Suggested Reference Material
The following AMD documentation may be of interest to the TIP board user.
•AMD Am79C961 Ethernet Controller specifications, order #18183
For current application notes and technical bulletins, see our W orld Wide W eb page
at www.amd.com.
The following no n-AMD documentat ion may also be of in terest to the TIP board
user.
• Hitachi’s HD44780U (LCD-II) Dot Matrix Liquid Crystal Display Controller/
Driver data sheet. For more inform ation, refer to the Hitachi specification by
accessing the web site http://www.hitachi.com and searching on HD44780U.
• Texas Instruments’ TL16C552 Dual Asynchronous Communications Element
With FIFO data sheet. For more information, refer to the Texas Instruments
TL16C552 specification by accessing the web site http://www.ti.com and
searching on TL16C552.
TIP.book Page xiii Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
xiv
Documentation Conventions
The Test Interface Port Board User’s Manual uses the notational conventio ns
show n in Table 0-1 (u nless otherwise no ted).
Table 0-1. Notational Conventions
Symbol Usage
Boldface Indicates that characters must be entered
exactly as shown, except that the alphabetic case is
only significant when indicated.
Italic Indicates a descriptive term to be replaced with a
user-specified term.
Typewriter face Indicates computer text input or output in an example
or list ing.
[] Encloses an optional parameter. To include the
information described within the brackets, type only
the parameter, not the brackets themselves.
SIGNAL An overbar over a signal name indicates that it is
active low.
SIGNAL# A pound sign aft er a sign al name i s used to indi cate
an active low in schema tics.
TIP.book Page xiv Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 1-1
Chapter 1
Getting Started
The Test Interface Port (TIP) board comes prepared for immediate use. Connect
the supplied flexible ribbon cable to the TIP board and to the host’s interface
connector, then follow the correct power- up procedure (see “Board Power” on
page 1-1), and the TIP bo ard is ready to use. You can pr ogram the on- board Flas h
memory with board diagnostics, a monitor program, or application software.
NOTE: T o use any application that may be programmed on the TIP board’ s Flash
memory, set the Flash Select jump er to th e INT position.
Board Power
The TIP board requires an external 5-V DC power supply with a 2.0-A current
rating. Alt hough the ext ernal power supp ly provides the 5 -V power for th e board,
the boar d still does not power up (even wit h the external po wer supply connected )
unless a host board is also properly connected. This condition is caused by the two
power sources being routed through two MOSFETs that are managed by a
comparator. The comparator gets its power from the host VCC. This MOSF ET/
comparator rou ting prevents any power to the board without the presence of b oth
the external and host power sources.
CAUTION: Do not provide power to the TIP board through a
host board without first connecting an external power source to
the TIP board. Failure to correctly follow this procedure causes
back powering of the FETs which could damage the TIP board.
Use the following procedure to power up the TIP board :
1. Be sure the host board is not powered up.
!
TIP.book Page 1 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
1-2
2. Attach the interface ribbon cable connector between the TIP board and the host
board. On the TIP board, the ribbo n cable connector attaches to connector P1,
show n in Figure 1 -1
3. Connect the external 5-V DC power supply to the TIP board’ s barrel connector
(P2), shown in Figure 1-1.
CAUTION: Failure to follow this procedure can result in
irregular results or damage to the TIP bo ard.
4. Perform the normal power-up procedures on the host board.
Figure 1-1. Barrel (P2) and Ribbon Cable (P1) Connectors Locations
!
Barrel Connector (P2)
Ribbon Cable Connector (P1)
TIP.book Page 2 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 1-3
Interface Cable
The TIP board requires a 60-wire ribbon cable ass embly to connect to the host
interface. Figure 1-2 illustrates the interface cable assembly. Figure 1-3 on page 1-4
illustrates the orientation of the host interface connector and the connector on the
interface cable assembly that connects to the host. For a description of the interface
signals, see “Main Interface Connector” on page 1-5.
Figure 1-2. TIP Board Ribb on Cabl e
1
23
45
67
8
51
49
50
47
52
48
60
58
59
57
56 55
53
54
AMP
23
45
67
8
49
50
52
48
60
58
59
57
56 55
54
1
47
51
53
AMP
Top View
With female end of connectors facing upward (out of the page)
Guide bars facing outward
Guide bars facing outward
Connector
(AMP 1-111196)
Connector
(AMP 1-111196)
Ribbon Cable
(AMP 2-57038)
TIP.book Page 3 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
1-4
Figure 1-3. Ribbon Cabl e Conne cto r Ori enta tion
Orientation of Interface Cable Assembly that
connects to the host Interface Connector
Orientation of the host interface connector
(AMP 104069-7 right-angle connector)
Orientation of the host interface connector
(AMP 104068-6 ve rtic al co nnector)
60
59
1
2
AMP 1-111196
Top/Side An
g
le Vie w
59
2
1
60 Side View
AMP 104069-7
Right Angle Conn.
59
Top View
2
1
AMP 104068-
60
Vertical Conn
Test Interface Port Board User’s Manual 1-5
Main Interface Connector
The 60-wire ribbon cable connects to the TIP board on the main interface connector
(P1). Table 1-1 describes each of the 60 signals on the connector. Figure 1-4 on
page 1-9 illustrates the pin out of P1.
Table 1-1. Interface Connector Signal Descriptions
Pin No. Signal Name Input/
Output Description
1–10,
13–22 TA0–TA19 I Address Lines: Receive the physical
memory latched address for the Flash
memory or Ethernet controller and the
physical I/O latched address for all other
TIP board peripherals through the MACH
device.
11, 12,
23, 24 GND — Ground Pins
25–32 TD0–TD7 I/O Data Bus: Input and output data during
respective read or write cycle.
33 – – Pin is blank.
34 – – Pin is blank.
35 TIPSEL OTIP Select #: The hardware method of
identifying that the TIP board is physically
connected to the h ost. The TIP bo ard has
a 10-KΩ pullup resistor on TIPSEL. If the
host board wants to use TIPSEL to
indicate that the TIP board is connected,
then the host board should have a weak
pull down resist or (100 KΩ) on the si gnal
connected to TIPSEL. Then, when the TIP
board is connected to the host board,
TIPSEL signal goes Low, indicating that
the TIP board is properly connected to the
host.
36 – – Pin is blank.
TIP.book Page 5 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
1-6
37 TIPSEL O TIP Select: The hardware method of
indentifying t ha t the TIP bo ard is
physically conn ected to the host. The TI P
board has a 1-KΩ pulldown resistor on
TIPSEL. If the host board wants to use
TIPSEL to indicate that the TIP board is
connected, then the ho st board should
have a weak pullup resistor (10 KΩ) on
the signal connected to TIPSEL. When the
TIP boar d is connected to the host board,
TIPSEL signal goes High, in dicating that
the TIP board is properly connected to the
host.
38 TAEN I Address Enable: For ISA systems: When
asserted High, T AEN enables DMACs on
the buses and prevents I/O devices from
responding.
For the Am186™CC CDP: a chip select
that, when asserted Low, allows for
communication with the Ethernet
controller.
39 – – Pin is blank.
40 TRD IRead Strobe: Indicates to the system that
the host microcontroller is performing a
memory or I/O read cycle.
41 – – Pin is blank.
42 TWR IWrite Strobe: Indicates to the system that
the host microcontroller is performing a
memory or I/O write cycle.
43 ENETIRQ O Ethernet Interrupt Request: Indicates
that one of several status flags is set
(consult Ethernet controller specification
for details).
Table 1-1. Interface Connector Signal Descriptions (Continued)
Pin No. Signal Name Input/
Output Description
TIP.book Page 6 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 1-7
44 TS2 IBus Cycle Status: Used by Am186 family
of microcontrollers as a logical memory
or I/O indicator.
45 PARINT O Printer Port Interrupt: Dedicated
parallel port interrupt signal.
46 – – Pin is blank.
47 SERINT1 O Serial Port 1 Interrupt: Dedicated serial
port 1 interrupt signal.
48 MAIN_IRQ O Main Interrupt Line: A shared interrupt
line. MAIN_IRQ is asserted if an y o f th e
five interrupts on the TIP board are
asserted.
49 SERINT0 O Serial Port 0 Interrupt: Dedicated serial
port 0 interrupt signal.
50 HRESET OHost Reset: Toggled by the TIP board
reset button, which then indicates to the
host microcontroller to perform a system-
wide hardware reset.
51 IOCHRDY O I/O Channel Ready: Indication by th e
Ethernet controller that valid data exists
on the d ata bus for r eads and that dat a has
been latched for writes.
52 TRESET I TIP Reset: Generated by the host
microcontroller when performing a
hardware reset. TRESET affects the TIP
board’s Ethernet controller, and parallel
and serial ports.
53 – – Pin is blank.
54 FLASHRD IFlash Read Enable: Output enable.
Table 1-1. Interface Connector Signal Descriptions (Continued)
Pin No. Signal Name Input/
Output Description
TIP.book Page 7 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
1-8
55 SEL186 I Select Am186: Identifies that a Am186
microcontroller bo ard is connected and is
hosting the TIP board. This helps to
determine when the Ethernet controller
should respond to read and write cycles.
There is a 1-KΩ pulldown resistor
connected to this pin for when a Am186
board is not connected. SEL186 should be
driven High by any Am186 host boards
connecting to the TIP board.
56 FLASHWR IFlash Write Enable: Write enable.
57, 59 V CC I Host Power: +5 V DC provides power to
the comparator, which in turn provides
power to the MOSFET driver, which
drives the FETs, allowing the external
power supply to provide +5 V DC to the
board.
58 FLASHCS —Flash Chip Select: Flash memory chip
enable.
60 EXTFLHCS IExternal Flash Chip Select: An optional
external Flash memory chip select jumper.
The host boards can take advantage of
EXTFLHCS by making the TIP board’s
Flash memory select jumper t he primary
Flash memory select component of the
two boards (theTIP board and the host
board). This minimizes components on
the host board.
Table 1-1. Interface Connector Signal Descriptions (Continued)
Pin No. Signal Name Input/
Output Description
TIP.book Page 8 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 1-9
Figure 1-4. Main Interface Connector Pinout
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Test Interface Port Board User’s Manual
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TIP.book Page 10 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 2-1
Chapter 2
System Features and Components
The Test Interface Port (TIP) board is a set of peripherals at one convenient location
for software debugging, diagnostics, evaluation, and reference designs. The TIP
board is designed to make it easy and convenient for the software to indicate to an
engineer, tester, or an end user the tasks that are being perf ormed . The TIP board
is designed to support flexible, present-day applications, and is intended to be used
with any host board containing a microcontroller that can connect to the TIP board
through the small, 60-pin, main interface connector . The TIP board supports either
I/O-mapped or memory-mapped operation and can be used in either mode.
The TIP board requires minimal software initialization for basic operation. This
chapter provides detailed information about the features and components of the
TIP board. The following sections explain the op eration of the board in detail,
including ju mper settings, sw itch settings, and programmable registers:
• “Layout and Placement” on page 2-2
• “Serial Ports” on page 2-5
• “Parallel Port” on page 2-10
• “Ethernet Controller Port” on page 2-13
• “LCD” on page 2-14
• “Hexadecimal Display” on page 2-16
• “General-Purpose LEDs” on page 2-18
• “Debug Headers” on page 2-20
• “General-Purpose Inputs and Outputs” on page 2-21
• “DIP Switch” on page 2-24
• “Reset Button” on page 2-26
• “Flash Memory” on page 2-27
• “Interrupts” on page 2-30
TIP.book Page 1 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
2-2
• “MACH® Device” on page 2-30
• “I/O Address Mode” on page 2-31
• “I/O Maps” on page 2-32
• “Timing” on page 2-34
• “Version Register” on page 2-34
Layout and Placement
The TIP board is laid out for convenient connection to the host board and to the
various external devices. It has connecto rs for DC power , parallel por t, RJ-45, and
the serial ports along one side of the board. On a side adjacent to the port connector
side are the main interface connector, the general-purpose input/output header , the
debug headers, and the MACH device programming header. The LCD, hex
displays, and LEDs are arranged close together in the middle of the board. Refer
to Figure 2-1 on page 2-3 for layout and component placement.
Figure 2-2 on page 2-4 is a block diagram of the TIP board showing the connections
between the various peripherals on the board.
TIP.book Page 2 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 2-3
Figure 2-1. TIP Circuit Board Layout
DC Power
Connector Parallel Port
MACH® 4-12 8 Devi ce
(under the LCD)
Serial Ports
Input DIP
Switch Flash
Memory GPIO Input and
Output Head er
Debug Headers
Main Interfac e
Connector
Ethernet
EEPROM
SRAM
LEDs
Hex Displays (8)
MACH® Programming
Header
Outline of
LCD
UARTs and Parall el
Port Chip
(under the LCD)
TIP.book Page 3 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
2-4
Figure 2-2. TIP Board Block Diagram
Address (20)
Ethernet Controller
E-NET ISA II
EEPROM SRAM
Transformer
Debug Headers
HP Header
HP Header
HP Header
Main Interface
Connector
60-Pin Connector
Board Peripherals
DIP Switch
GPIO Header
ASCII LCD
Hex Displays (8)
LEDs (8)
Dual 16C550 UART
& Parallel Controller
Parallel
Serial
Serial
MACH®
Device
FLASH
PAL® Device
Chip Selects
VCC Management Circuit
Program.
Header
FET Driver
MOSFET
Comp
Board VCC
Ext. Power
Plug
245244
Data Bus (8)
Control
Signals
Control Signals
Address
Data Bus
Flash Memory
Control Signal
Host VCC
10BaseT
Connector
TIP.book Page 4 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 2-5
Serial Ports
NOTE: For more information about initializing or programming the serial ports,
refer to the Texas Instruments TL16C552 data sh eet.
The TIP board provides two 16550 RS-232 serial ports (9-pin, DCE). The TIP
board contains a Texas Instruments TL16C552 chip that controls two 16550
Universal Asynchronou s Receiver Transmitters (UARTs) and a p arallel por t. Fo r
more inform ation about the parallel port, refer to page 2-10. Thes e serial ports run
up to 115200 baud and can be used with o r w ithout interrupts. The interrupt line
from each serial port connects to a dedicated pin on the interface connector or
through a shared interrupt circuit, which has one dedicated pin on the interface
connector. Figure 2-3 illustrates the serial-port connector pinout.
Serial port 0 typically serves as a system debugging console. The TIP board
typically sends debugging mes sages, such as asserts, fault messages, and trace
statements, to this port. This interface can also support a command line or other
method of accepting user input. For information about the I/O address locations,
refer to Table 2-1 and Table 2-2.
Serial port 1 is typically dedicated for use by a software debugger. For example,
the CAD-UL debugger can communicate with the board-level monitor using this
port.
Figure 2-3. Serial-Port Connector Pinout
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Test Interface Port Board User’s Manual
2-6
Table 2-1. I/O Map for 8-Bit Addressing for Serial Port
Table 2-2. I/O Map for 16-Bit Addressing for Serial Port
Address Read/Write Description
310h–317h R/W Serial port 0
318h–31Fh R/W Serial port 1
Address Read/Write Description
320h–32Eh R/W Serial port 0
330h–33Eh R/W Serial port 1
TIP.book Page 6 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 2-7
Programming the Serial Ports
This sec tion contai ns gen eral infor matio n about th e pro grammin g operati ons and
functions of the serial ports including operating mode, UART operation, interrupts,
and registers.
Operating Mode
The 16550-compatible UAR T mode (FIFO mode) contains two 16-byte FIFOs for
transmitting and receiving to off-load the CPU from repetitive service routines.
The CPU can write 16 bytes to the transmit FIFO and use the THRE interrupt or
poll the THRE bit to trigger another 16 bytes. The receive FIFO has a
programmable trigger level that can interrupt the CPU at 1, 4, 8, or 16 bytes present.
Writing a byte to a full transmit FIFO results in the last byte being lost. If the receive
FIFO is full, receiving one mo re character generates an overrun error. The last
character received is lost. The remaining 16 bytes in the FIFO are unchanged.
UART Operation
The UAR T co nverts serial data received on the serial input line (SIN) into parallel
data that can be processed by the microcontroller . The UAR T also converts parallel
data into serial data for transmission off the chip on the serial output line (SOUT).
Data can be transmitted and received at the same time.
To generate the baud rate of the transfer, the UART clock is divided by a divisor
value chosen by the programmer. The UART baud-rate generator automatically
calculates the baud rate from the diviso r value that is programmed into the two
baud rate divisor registers (divisor latch LSB and divisor latch MSB). These
registers are read at initialization to set the baud rate for the transfer.
Each byte of data is transferred using a format called a frame. The transmitter and
receiver must agree on the frame format, in addition to the baud rate, or the
transmission is not successful. The frame format is determined by the value written
into the Line Control register . A frame consists of a start bit, five to eight data bits,
an optional parity bit, and either 1, 1.5 , or 2 stop bits. Transmission of a frame is
initiated when software writes a byte to the Transmit Holding register. Reception
of a frame is initiated when a start bit is received (the SIN input is driven Low for
one baud-rate clock period). This start bit allows the receiver to synchronize its
clock with the sender’s clock. Errors are reported in the Li ne Stat us register.
TIP.book Page 7 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
2-8
Interrupts
The serial port supports the standard UART interrupts as follows:
• Received Data Available
• Transmit Holdin g Register Empty
• Modem Status
• Receiver Line Status
If two interrupt sources are pending simultaneously, only the highest priority
interrupt is indicated by the ID2–ID0 field of the Interrupt ID Register. When the
interrupt source is cleared, a subsequent read from this port will return the next
highest p r iority interrupt source.
Registers
The registers store three types of information: control, status, and data. The divisor
latch access bit (DLAB) in the Line Control register (bit 7) is used with the address,
read, and write inputs to select the register that is written to or read from. The
T ransm it Holding register and Receive Buf fer register are data registers that hold
from five to eight bits of data. If less than eight bits of data are transmitted, data is
right justified to the leas t significant bit. Bit 0 of a data word is always the first
serial data bit received and tran smitted. The d ata reg isters are d ouble- buffered so
that read and write operations can be performed when the serial port is performing
the parallel-to-serial or serial-to-parallel conversion.
The following registers are available on the serial port. The bits for these registers
are described in the TI TL16C552 Specification.
• Line Control Register: This register is used to configure the format of the
UART frame for data transfer, including character length, stop bits, and parity.
• Divisor Latch LSB: This register holds the least significant byte of a 16-bit
baud rate clock divisor that is used to generate the 16x baud clock (when DLAB
is 1).
• Divisor Latch MSB: This register holds the most significant byte of the clock
divisor (when DLAB is 0).
• Transmitter Holding Register: The byte to be transmitted is written to this
write-only register (when DLAB is 0).
• Receive Buffer Register: The received byte is read from this read-only register
(when DLAB is 0). This register shares an address with the Transmit Holding
Register.
TIP.book Page 8 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 2-9
•Interrupt Enable Register: This register enables the following serial port
interrupts: modem status, receiver line status, transmitter holding empty,
received data available, and tim e-out interrupts (when DLAB is 0).
•Interrupt Identification Register: This is a read -only register used to identify
UART interrupts.
• FIFO Control Register: This is a write-only register used to enable and control
the FIFO in 16650-compat ible mode.
•Line Status Register: This register shows the status of the data transfer,
including parity and framing errors, in addition to break and empty indicators.
•Modem Control Register: This register is used to enable interrupts and
loopback diagnostic mode, and to assert RTS and DTR.
•Modem Stat us Register: This register contains both real-time and latched
status bits for DCD, RIN, DSR, and CTS.
•Scratch Pad Register: This is a general purpose I/O location used to hold
temporary data and is not required for serial data transfer.
Configuring the Serial Port for DTE
Because the TIP board provides information to a terminal, it is considered data
carrier equipment (DCE), and the serial ports are configured accordingly in its
default design. You can also configure the TIP board to serve as data terminal
equipment (DTE) if necessary.
To reconfigure serial port 0 to operate as DTE, use the following procedure:
1. Depopulate resistors R24 through R31.
2. Populate resistors R44 through R50, located on the back of the board.
3. A gender chang er is now required for serial port 0, either on the TIP board end
or the connecting cable end.
To reconfigure serial port 1 to operate as DTE, use the following procedure:
1. Depopulate resistors R34 through R41.
2. Populate resistors R51 through 57, located on the back of the board.
3. A gender chang er is now required for serial port 1, either on the TIP board end
or the connecting cable end.
TIP.book Page 9 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
2-10
Parallel Port
NOTE: For more information about initializing the parallel port, refer to the T exas
Instruments TL16C552 specification.
The TIP board contains a Texas Instruments TL165552 chip that controls the
parallel port and two serial ports (for mor e information abou t the serial ports, refer
to “Serial Ports” on page 2-5). The parallel port can be used for very fast downloads
or for connecting to a printer for logging purposes. The interrupt line from this port
is connected to a dedicated pin on the interface connector , or connected to a shared
interrupt circuit with one signal feeding back to the interrupt connector . Figure 2-
4 illustrates the parallel port connector pinout. For information about the I/O
address locations, refer to Table 2-3 and Table 2-4.
Figure 2-4. Parallel-Port Connector Pinout
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Test Interface Port Board User’s Manual 2-11
Table 2-3. I/O Map for 8-Bit Addressing for Parallel Port
Table 2-4. I/O Map for 16-Bit Addressing for Parallel Port
Address Read/Write Description
320h
321h
322h
R/W Parallel port
Address Read/Write Description
340h
342h
344h
R/W Parallel port
TIP.book Page 11 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
2-12
Programming the Parallel Port
The TI TL16C552 parallel port interface is controlled primarily by software and
provides all the status inputs, control outputs, and the control signals necessary for
the external parallel port data buffers. Communication between the host and the
peripheral is asynchronous. The parallel port data path is external to the
microcontroller . The parallel port can be physically mapped to one of two different
I/O locations or can be completely disabled. Only edge-triggered interrupts are
supported.
The parallel port can connect to a Centronics-style printer interface. The parallel
port is selected when chip select 2 (CS2) is low. The state of the read (IOR) and
write (IOW) terminal controls the read or write function of the register . The Read
Data register controls when the microprocessor can read information on the parallel
bus.
The parallel port interface is mapp ed to 320h–322h (8-b it) or 3 40h–344h (16- bit).
The following direct-mapped registers are available.
•Read Data Register: This register enables the microprocessor to read the
information on the parallel bus.
•Read Status Register: This register enables the microprocessor to read the
status of the printer in the six most significant bits. The status bits are: prin ter
busy (BSY); acknowledge (ACK), a handshake function; paper empty (PE);
printer selected (SLCT); error (ERR); and printer interrupt (PRINT).
• Read Control Register: This register enables the state of the control lines to
be read.
•Write Data Register: Th is register enables the microprocessor to write a byte
to the parallel bus.
•Write Contr ol Register: This reg ister sets the state o f the control lines. These
states are: direction (DIR); interrupt enable (IN2 EN); select in (SLIN); initialize
the printer (INIT); autofeed the paper (AFD); and strob e (STR), which informs
the printer of the presence of a valid byte on the parallel bus.
TIP.book Page 12 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 2-13
Ethernet Controller Port
NOTE: For information abou t initializing the 10BaseT Ethernet controller port
and for correct setup and configuration of the Ethernet, refer to the AMD
Am79C961A PCnet-ISA+ Single Chip, Plug & Play Full Duplex Ethernet
Controller for ISA specification, order #18183.
The following are the 8-bit and 16-bit base addresses for the Ethernet:
Base addresses: 8-bit = 220h, 16-bit = 220h
The TIP board provides an Ethernet controller port that can be run in interrupt-
driven mode. The Ethernet controller port supports software downloading and
debugging over a network. For example, the CAD-UL debugger uses this
capability.
Many devices already have an Ethernet controller port fo r use by the device
application. However , it is usually not possible to use the device port for running
the debugger. For example, if the system is stopped at a break point, and in the
context of the debug monitor, then the driver and TCP/IP stack cannot run.
However , the TIP board Ethernet controller port can be driven in a polled manner
and can function independently from the application drivers and protocol stacks.
All of the interrupts from the Ethernet controller are gathered into a single interrupt
signal that is connected to a dedicated pin on the interface con nector or throug h a
shared interrupt circuit. The Ethernet controller port can run in interrupt-driven
mode.
TIP.book Page 13 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
2-14
LCD
NOTE: For more information about the LCD driver, refer to the Hitachi
HD44780U-II LCD Driver data sheet.
Overview
The LCD, illustrated in Figure 2-5, is a 2 x 20 character, ASC II-decoded display
for displaying text. The display can contain any type of text. Being ASCII-decoded,
the LCD enables the user to represent alphabetical characters in the display. For
example, writing 41h to a display location causes an A to appear on the LCD.
Software can only write to this display; it cannot read the data back. For information
about the I/O address locations, refer to Table 2-5 and Table 2-6.
The R67 potentiometer adjusts the contrast on the LCD. With the front of the board
facing you (the main interface connector on the right), turn the thumb wheel on
the R67 countercloc kwise to dark the contrast on the LCD, making the char acters
more visible. When the LCD appears to be off and the board is powered up, try
adjustin g the potentiometer.
Figure 2-5. LCD Display
MDLS-20265K
TIP.book Page 14 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 2-15
Table 2-5. I/O Map for 8-Bit Addressing for ASCII Display
Table 2-6. I/O Map for 16-Bit Addressing for ASCII Display
Configuring the LCD
Y ou must set up the LCD for 8-bit operation and 8-digit x 2-line display . The power-
up procedure detailed in “Board Power” on page 1-1 should initialize the LCD and
leave it ready for configuration. For a quick configuration of the LCD, use the
following procedure. If you encounter any problems or need more detailed
information, refer to the Hitachi spec, HD44780U (LCD-II) (Dot Matrix Liquid
Crystal Controller/Driver).
1. To set the LCD to 8-bit operation, 2-line display, and 5x8 dot character font,
write 38h to the ASCII Display–Write Control Instructions address listed in the
tables in “I/O Maps” on page 2-32. This write should clear the LCD screen.
2. To turn on the disp lay and the cursor, write OEh to the ASCII Display–Write
Control Instructions address. After this write, the cursor should appear on the
LCD screen.
Address Read/Write Description
30Ch
30Dh
30Eh
30Fh
W ASCII display —write control instructions
ASCII display—busy flag / address read
ASCII display—write data to LCD
ASCII display—read data
Address Read/Write Description
308h
30Ah
30Ch
30Eh
W ASCII display —write control instructions
ASCII display—busy flag / address read
ASCII display—write data to LCD
ASCII display—read data
TIP.book Page 15 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
2-16
3. To set the LCD mode to in crem ent th e address by one and to shift the cursor
to the right at the time of writing, write 06h to the ASCII Display–Write Control
Instructions address.
The LCD is now ready to display the character for the respective 8-bit ASCII code.
For example, writing 4 1h, 4Dh , and 44h in sequ ence to the ASCII Disp lay–Write
Data address should display “AMD” on the LCD screen.
Hexadecimal Display
The eight-segme nt hexadecimal dis play, illu strated in Figure 2-6, behav e s much
like the ASCII-decoded display, but displays binary information in hexadecimal
form at instead of ASCII-dec oded data. This displa y contai ns eight he xadec imal
digits for displaying values up to 32 bits wide. For example, during debugging, the
value of a CPU or peripheral register can be written to the display for viewing
without software decoding. Software can only write to this display; it cannot read
back the value.
To display a hexadecimal value on the eight-segment display, write the bytes of
the value to the appropriate I/O addresses as shown in Table 2-7 and Table 2-8.
Figure 2-6. Eight-Segment Display
Top View
TIL311
Test Interface Port Board User’s Manual 2-17
Table 2-7. I/O Map for 8-Bit Addressing for Hexadecimal Display
Table 2-8. I/O Map for 16-Bit Addressing for Hexadecimal Display
Address Read/Write Description
306h
307h
308h
309h
WHex Display—Byte0: Hex digits 1 and 0
Hex Display—Byte 1: Hex digits 3 and 2
Hex Display—Byte 2: Hex digits 5 and 4
Hex Display—Byte 3: Hex digits 7 and 6
Address Read/Write Description
310h
312h
314h
316h
W Hex display—Byte 0: Hex digits 1 and 0
Hex display—Byte 1: Hex digits 3 and 2
Hex display—Byte 2: Hex digits 5 and 4
Hex display—Byte 3: Hex digits 7 and 6
TIP.book Page 17 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
2-18
General-Purpose LEDs
NOTE: For information about programming the information, refer to “Discrete
LED O utputs Register ” on page 2-19.
Eight LEDs
The eight general-purpose LEDs indicate status events or errors. Software can write
to and read from the LED buffer . This capability supports a read-modify-write style
of operation. For the TIP board, the green cathode (light) is used. Figure 2-7
illustrates the pin out of o ne of the LEDs.
Figure 2-7. LED Pinout
SSL-LX15YGC
Test Interface Port Board User’s Manual 2-19
Discrete LED Outputs Register
The following are the 8-bit and 16-bit addresses for the Discrete LED Outputs
register:
Address: 8-b it = 305h, 16-bit = 300h
The Discrete LED Outputs register controls the eight individual LEDs on the TIP
board, as shown in Table 2-9. This is a read/write register and can be used in a
read-modify-write manner.
• When an LED bit is set to 1, the corresponding LED is turned on.
• When an LED bit is cleared to 0, the LED is turned off.
When writing to this register, the new value is latched at the LED drivers and the
LEDs immediately reflect the state of the newly written bits.
Table 2-9. Discrete LED Outputs Register Bit Definitions
Bit LED Description
0 D0 The least significant LED (right-most LED)
1 D1 The next most significant LED
2 D2 The next most significant LED
3 D3 The next most significant LED
4 D4 The next most significant LED
5 D5 The next most significant LED
6 D6 The next most significant LED
7 D7 The most significant LED (left-most LED)
TIP.book Page 19 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
2-20
Debug Headers
The TIP board provides three HP logic analyzer debug headers for easy address,
data, and control signal debug access. These headers (2 x 10-pin shrouded, low-
profile header connector) allow connection between the logic analyzer and the test
points using the HP flex cable header. The debug s ignals are on the following
header as shown in Figure 2-8:
•Address bus
• Data bus and contro l sig nals
• Port chip selects and interrupts, and Ethernet interrupt
For pinout information, refer to the TIP board schematics included in your kit.
Figure 2-8. HP Logic Analyzer Header
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Test Interface Port Board User’s Manual 2-21
General-Purpose Inputs and Outputs
The TIP board pro vides eig ht di screte i nputs and eight discret e outp uts throug h a
standard 20-pin header , and eight discrete inputs through a DIP switch (illustrated
in Figure 2-9). These are TTL/CMOS signals.
Figure 2-9. General-Purpose Input/Output Header
The inputs are general-purpose and allow the software to only read the input buffer.
Therefore, these inputs do not support a r ead-modify-write style of o peration. For
information about reading the input buffer, see “Discrete Inputs Register” on
page 2-22.
The outputs can be directly connected to a logic analyzer by a straight-through
ribbon cable. These outputs support the tracing of software operation, not hardware.
For example, to measure the interrupt latency of an interrupt and th e interrupt
handler execution time, simply toggle a bit on entry to and exit from the interrupt
service routine (ISR). You can measure this with an in-circuit emulator (ICE), but
it can be difficult to set up.
However, using the TIP board, you can measure the above operati on by adding
simple instructions to the ISR and using a logic analyzer. Software can write to
and read from the output buffer thereby supporting a read-modify-write operation.
For information about reading or writing the output buf fer, see “Discrete Outputs
Register” on page 2-23.
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2-22
Discrete Inputs Register
The following are the 8-bit and 16-bit addresses for the Discrete Inputs register:
Address: 8-bit = 303h, 16-bit = 306h
The Discrete Inputs register retu rns the state of the eight general-purpose inputs
on the TIP board, as sho wn in Table 2-10. These inpu ts appear on the INPUT side
of connector P7. Th e valu e of each b it indicates the cur rent state of its associated
input.
• When a bit reads 1, the input is currently active (turned on/set to 5 V at the
output).
• When a bit reads 0, the input is currently inacti ve (turned off/s e t to 0 V at the
output).
Writing to this register has no effect on the state or operation of the TIP board.
Table 2-10. Discrete Inputs Register Bit Definitions
Bit Pin Description
0 15 The most significant (left most) output
1 13 The next most significan t output
2 11 The next most significan t output
3 9 The next most significant output
4 7 The next most significant output
5 5 The next most significant output
6 3 The next m ost signif ic ant output
7 1 The least significant (right most) output
TIP.book Page 22 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 2-23
Discrete Outputs Register
The following are the 8 -bit an d 16-bit addresses for the Discrete Outputs register:
Address: 8- bit = 302h, 16-bit = 30 4h
The Discrete Outputs register controls the eight individual general-purpose outputs
on the TIP board, as sho wn in Table 2-11. These outputs appear on the OUTPUT
side of connector P7. This read/write register can be used in a read-modify- write
manner. When this register is read, the va lue of each bit indicates the current state
of its associated output.
• When an output bit is set to 1, the output is currently active (turned on/set to
5 V at the output).
• When an output bit is cleared to 0, the output is currently inactive (turned off/set
to 0 V at the output)
When writing to this register , the new value is latched to the output drivers and the
output pins immediately reflect the state of the newly written bits.
Table 2-11. Discrete Outputs Register Bit Definitions
Bit Pin Description
0 2 The least significant (right most) output
1 4 T he next mo st significant output
2 6 T he next mo st significant output
3 8 T he next mo st significant output
4 10 The next most sign ificant ou tput
5 12 The next most sign ificant ou tput
6 14 The next most sign ificant ou tput
7 16 The most significant (left most) output
TIP.book Page 23 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
2-24
DIP Switch
NOTE: For information about reading the state of the DIP switch, refer to “DIP
Switch Inputs Register” on page 2-25.
Eight-Position DIP Switch
The TIP board provides an eight-position DIP switch, illustrated in Figure 2-10,
that provides configuration information and mode control of the host software. For
example, a DIP switch could enable special debugging features or change the
system mode of operation. These switch inputs do not cause interrupts.
Figure 2-10. DIP Switch
O18
234567
AMP 3-435640-9
F
F
D0
D1
D2
D3
D4
D5
D6
D7
TIP.book Page 24 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 2-25
DIP Switch Inputs Register
The following are the 8-bit and 16-bit addresses for the DIP Switch Inputs register:
Address: 8- bit = 304h, 16-bit = 30 2h
The DIP Switch Inputs register (read-only ) returns the state of the eight-positio n
DIP switch (SW4) on the TIP board, as shown in Table 2-12. When this register
is read, the value of each bit indicates the current state of its associated DIP switch.
• When a bit reads 1, the input is currently active (turned on).
• When a bit reads 0, the input is currently inactive (turned off).
Writing to this register has no effect on the state or operation of the TIP board.
Table 2-12. DIP Switch Inputs Register Bit Definitions
Bit SW Description
0 0 The first (least significant/left-most) switch
1 1 The second switch
2 2 The third switch
3 3 The fourth switch
4 4 The fifth switch
5 5 T he sixth switch
6 6 The seventh switch
7 7 The eighth (most significant/right-most) switch
TIP.book Page 25 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
2-26
Reset Button
The following are the 8-bit and 16-bit addresses for the Interrupt Reset register:
Address: 8-bit = 34Ah, 16-bit = 34Ah
The TIP boar d provides a res et button , illustrated in Fig ure 2-11. The reset button
toggles a signal to the host board which then performs a system-wide hardware
reset. The signal connected to the R ESET pin o n the interface co nnecto r (p in 50 )
should be an input to the host board and should connect to the main microcontroller
reset. For examp le, on the Élan™ SC400 microcontroller, this signal is connected
to the RESET input, which is corresponds to the POWERGOOD pin in the AT
system architecture.
Figure 2-11. Reset Button
This same reset can als o be performed remotely thr oug h pi n 9 of t he ser ial po rt s.
To use this feature, you must r emov e res i st or R3 2 (for serial port 1) an d R 42 (for
serial port 0) from the TIP board, then populate resistors R33 and R43 for serial
ports 0 and 1 respectively.
The TIP board discrete registers should not respond to the hardware reset signal.
However, this condition is not certain, even under normal conditions. For example,
a hardware reset should not change the state of the LCD, hex display, discrete
LEDs, discrete inputs, or discrete outputs. A hardware reset does reset the serial
ports and the parallel port.
Alcoswitch FSM4J
Test Interface Port Board User’s Manual 2-27
Flash Memory
NOTE: For more information about the flash memory , refer to the Am29F040 data
sheet.
The TIP board is equipped with Flas h memory. The socket in which the Flash
memory is mounted supports a variety of Flash memory options (any 8-bit device)
that can be installed in place of the existing unit. Figure 2-12 illustrates the Flash
memory for identification p urposes.
Figure 2-12. 8-Bit Flash Memory Identification
$0)
Test Interface Port Board User’s Manual
2-28
Using the Flash Memory
You can program the Flash memory with diagnos tics, a monitor, or a small
application. However, a primary design function of the Flash memory is to provide
the host board with an alternate boot location. For example, if the host board has
a soldered-down Flash memory device and that Flash memory becomes corrupted,
you can reprogram the Flash memory without removing it from the board by using
the functions of the TIP board. You can accomplish this task by prog ramming the
TIP board Flash memory with a utility program, like the AMD E86MON™
software, which has a reprogram function to allow copying the contents of the TIP
board Flash memory to the host board Flash memory.
More specifically , when the TIP board is hosted by an Am186™CC/CH/CU device
microcontroller that is connected to a monitor, the TIP board can reprogram the
Customer Developmen t Platform ( CDP) on -bo ard F las h mem ory. With the Flash
memory on the TIP board being programmed with E86MON software, the CDP
can be booted through the TIP board. Now you can begin the reprogramming
sequence by enter ing z on the keyboard. Follow a few simple instructions, and the
Flash memory on the Am186CC /CH/CU CDP devi ce is reprog rammed. This is a
simpler process than removing the soldered down Flash memory on the CDP board,
programmi ng it on a programmer, then re-soldering t he Flash memory back on to
the CDP device.
TIP.book Page 28 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 2-29
Selecting the Flash Memory
Jumper block 1 (JP1) selects which Flash memory is used, either the internal (TIP
board) or the external (host board) Flash memory. To select the use of the internal
8-bit DIP Flash, jumper pins 2 and 3 on JP1 and drive a logic low to the FLASHCS
signal (pin 58 of P1 of the main interface co nnector). To select the use of the ho st
board Flash, jumper pins 1 and 2 on JP1. Figure 2-13 indicates the pin locations
on JP 1.
Figure 2-13. JP 1 Pin Locat ion s
JP1
Int
Pin 1
Ext
Pin 3
TIP.book Page 29 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
2-30
Interrupts
WARNING: The peripheral interrupt signals on the TIP board are not
terminated. As a result, the software must ensure that each peripheral
interrupt is enabled so the interrupt input to the OR gate that is driving
the MAIN_IRQ signal is not floating. Refer to the peripheral data sheets
for information about how this is done. Alternately, the target board
may use pull-down resistors on the peripheral interrupt signals.
The TIP board supports interrupts with the following features:
• An interrupt push button (SW2)
• Five interrupt sources o n the board: two serial ports, the parallel port, the
Ethernet controller port, and the user-interrupt button
For designs that can accommodate all the individual signals and want to have
dedicated interrupts, the serial ports, parallel port, and Ethernet controller port have
individual interrupt signals going to the main interface connector (P1). For designs
that have limited connector space, these same signals are also logically ORed
together on the MAIN_IRQ signal, which is also routed to the main connector.
The interrupt generated by the interrupt push button is routed to the main connector
only through the MAIN_IRQ signal. When the interrupt bu tton is pressed, the
SW_IRQ signal (generated from the MACH), goes high causing the MAIN_IRQ
signal to also go high. The SW_IRQ signal will remain hig h until the Interrupt
Reset register (address 34Ah) in the MACH is written to. For the address of this
register, refer to “I/O Maps” on page 2-32.
MACH® Device
The peripherals on the TIP board are interfaced to the host system through a macro
array CMOS high-density/high-performance (MACH®) devi ce that provides
individual chip selects for each on-board peripheral device (except the Ethernet
controller port). This interface gives the TIP board a degree of independe nce from
the host system. For a complete listing of the current MACH® device code, see
Appendix A, “MAC H® Device Equations”.
TIP.book Page 30 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 2-31
I/O Address Mode
The TIP bo ard s up port s 8-bit addressing or 16-bit addressi n g. Th e 8-bit or 16-bit
addressing is determined by the SW3 switch.
Selecting the optional 8-bit cycle mode changes the MACH device I/O map
address. Note that the peripheral access addresses change. For the I/O map
addresses i n the d if ferent ad dress ing modes , see “I/O Maps ” on pag e 2-32. If you
need to run the TIP board in 8-bit mode on a 186 family board, you must select
the 8-bit mode.
For example, to select the 8-b it I/O addressing m ode on the Am186ED pro cessor ,
write 01b to the Au xiliary Configuration register at physical location FFF2h. By
default, this register is set to 00b for 16-bit I/O addressing. Consult the host
microcontroller documentation for the correct 8- or 16-bit I/O addressing
configuration.
TIP.book Page 31 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
2-32
I/O Maps
Table 2-13 lists the 8-bit I/O address locations for the respective peripherals, and
Table 2-14 lists the 16-bit I/O address locations .
Table 2-13. I/O Map for 8-Bit Addressing
Address Read/Write Description
302h R/W Discrete Outputs register
303h R Discrete Inputs register
304h R DIP Switch Inputs register
305h R/W Discrete LED Outputs register
306h
307h
308h
309h
WHex Display–Byte 0: Hex digits 1 and 0
Hex Display–Byte 1: Hex digits 3 and 2
Hex Display–Byte 2: Hex digits 5 and 4
Hex Display–Byte 3: Hex digits 7 and 6
30Ch
30Dh
30Eh
30Fh
W ASCII display –write control instructions
ASCII display–busy flag / address read
ASCII display–write data to LCD
ASCII displ ay– read dat a
310h–317h R/W Serial port 0
318h–31Fh R/W Serial port 1
320h
321h
322h
R/W Parallel port
34Ah W Interrupt reset (write to this address to reset the
push button interrupt signal)
348h R Versi on register
220h R/W Ethe rnet base address
TIP.book Page 32 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 2-33
* Currently, the Version register is only accessible by the Am186 microcontrollers.
Table 2-14. I/O Map for 16-Bit Addressing
Address Read/Write Description
300h R/W Discrete LED Outputs register
302h R DIP Switch Inputs register
304h R/W Disc ete Outputs re gister
306h R Discrete Inputs register
308h
30Ah
30Ch
30Eh
WASCII display–write control in structions
ASCII display–busy flag / address read
ASCII display–write data to LCD
ASCII displ ay– read dat a
310h
312h
314h
316h
W Hex display–Byte 0: Hex digi ts 1 and 0
Hex display–Byte 1: Hex digits 3 and 2
Hex display–Byte 2: Hex digits 5 and 4
Hex display–Byte 3: Hex digits 7 and 6
320h–32Eh R/W Serial port 0
330h–33Eh R/W Serial port 1
340h
342h
344h
R/W Parallel port
34Ah W Interrupt reset (write to this address to reset the
push button interrupt signal)
348h* R Versio n registe r
220h R/W Ethe rnet base address
TIP.book Page 33 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
2-34
Timing
Certain 186 micr ocontroller boards require ad ded wait states to accommodate the
timing specifications of the 16C550 UARTs . For example, on the SD186ED
demonstration board, the PCS and MCS Auxiliary (MPCS) register needs to be set
to a defined state by writing 8038h to physical location FFA8h. Then, insert three
wait states to the Peripheral Chip Select (PCS) register by writing 0073h to physical
location FFA4h. Refer to the 16C550 specification and the microcontroller manual
of the host board to determine the correct configuration and the appropriate method
of adding wait states.
Version Register
NOTE: Currently, the Version register is only accessible by the Am186
microcontrollers.
The following are the 8-bit and 16-bit addresses for the Version register:
Address: 8-bit = 348h, 16-bit = 348h
The V ersion register contains the version of the code that is running in the MACH®
programmable device and in the revision of the TIP bo ard. This is a read-only
register. Table 2-15 lists the bit mapping s for th is register.
TIP.book Page 34 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual 2-35
Table 2-15. Version Register Bit Definitions
Bits Read/Write Description
0–3 R MAC H Device Code Version
These read-only bits reflect the version of the code in the
MACH programmable part, which controls the TIP
board. This value starts at one and is increme nted every
time a new version of the MACH device code is released
from AMD.
This value enables software to detect which version of
the MACH device is resident on the TIP board and to
modify its behavior accordingly. This value also helps
you determine when to upgrade the MACH device code.
Writing to these bits has no effect on the state of these
bits, t he MACH device, or a ny other d evices on th e TIP
board.
4–7 R TIP Board Revision
These read-only bits reflect the revision of the physical
TIP board. These bits are not necessarily incremented
with every sp in of the TIP board; i ncrementing depend s
on the significance of any changes made to the board.
Writing to these bits has no effect on the state of these
bits, t he MACH device, or a ny other d evices on th e TIP
board.
TIP.book Page 35 Friday, April 23, 1999 10:38 AM
Test Interface Port Board User’s Manual
2-36
TIP.book Page 36 Friday, April 23, 1999 10:38 AM
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Appendix A
MACH® Device Equations
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TIP.book Page 10 Friday, April 23, 1999 10:38 AM
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Numerics
10BaseT
ethernet, xi
16770 RS-232 serial ports, xi
16-bit addr essing
feature, xii
8-bit addressi ng, xii
8-bit DI P Flash memor y, xii
8-bit Flash mem ory identification, 2-27
8-se gment (32 bit) hexadecimal display, xi
A
ACK, 2-12
address bus, 2-20
addressing
16-bit, x ii
8-bit, xii
AFD, 2-12
Am29F010
Flash memory, 2-27
Am79C961, xiii, 2-13
ASCII display
16-bit addr essing, 2-33
8-bit addressi ng, 2-32
I/O map
8- an d 16-bit address i ng, 2-1 5
ASCII-decoded display, xi
hexadecimal, 2-16
LCD, 2-14
B
barrel (P2) and ribbon cable (P1) connectors
locations, 1- 2
bit definitions
DIP Switch Inputs register, 2-25
Discrete Inputs register, 2-22
Discrete LED Outputs register, 2-19
Discrete Outputs re gister, 2-23
Version register, 2-35
block diagram
TIP board, 2-4
board
description, xi
features, xi
hostconnecting to, xii, 2-1
layout, 2-3
powe r, 1-1
serial ports, 2-5
TIP block diagram, 2-4
BSY, 2-12
C
CDP, See customer developm ent platform, 2-
28
codeMACH® device, 2-30, 2-35
configuring
LCD, 2-15
serial port for DTE, 2-9
Index
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connector, 1-5
60-pin, xi
main interface, 1-5
pinout
parallel port, 2-10
serial port, 2-5
control signals
debug header, 2-20
parallel port, 2-12
Customer Development Platform (CDP), 2-
28
D
data bus and control signals, 2-20
debug header
desc ription , 2-20
signals
address bus, 2-20
data bus and control, 2-20
port chip selects and interrupts and
Ethernet interrupts, 2-20
device
MACH®, xii, A-1
DIP switch
desc ription , 2-24
inputs register, xii , 2- 3
8-bit addressi ng, 2-32
layout, 2-24
DIP Switch Inputs register
16-bit addr essing, 2-25, 2-33
8-bit addressi ng, 2-25
bit definitions, 2-25
desc ription , 2-25
DIR, 2-12
Discrete Inputs register
16-bit addr essing, 2-22, 2-33
8-bit a ddressing, 2-22, 2-32
bit defintions , 2-22
desc ription , 2-22
Discrete LED Outputs register, 2-19
16-b it addressing, 2-3 3
8-bit addressing, 2-32
bit definitions, 2-19
discrete LEDs (green), xi
Discrete Outputs re gister, 2-23
16-b it addressing, 2-3 3
8-bit addressing, 2-32
bit definitions, 2-23
discrete TTL/CMOS outputs, xii
display
LCD, xi, 2-14
Divisor Latch LSB register, 2-8
Divisor Latch MSB register, 2-8
documentation
conventions, xiv
order number, xii
support, iii
E
E86MON™, 2-28
eight-segment display
hexadecimal, 2-16
ENETIRQ, 1-6
equations
MACH® device, A-1
ERR, 2-12
ethernet
10BaseT, xi
controll er port , 2-1 3
Ethernet base address
16-b it addressing, 2-3 3
8-bit addressing, 2-32
Ethernet interrupt
debug header, 2-20
ENETIRQ, 1-6
EXTFLHCS, 1-8
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F
features, xi
10BaseT Ethernet controller port, xi
16550 RS-232 serial ports, xi
2 x 20 character ASCII decoded display,
xi
8-bit and 16-bit a ddressing, xii
8-bit DI P Flash memor y, xii
8-se gment (32 bi t) hexad ecimal dis play,
xi
discrete LEDs (green), xi
discrete TTL/CMOS outputs, xii
eight inputs connected to DIP switch and
header, xii
flexible interface, xii
HP logic analyzer debug headers, xi, 2-
20
interrupt button, xii
interrupt sources, xii, 2-3 0
jumper block (JP1), xii
MACH® device, xii, 2-30, A-1
PC-compatible parallel port, xi
programmable registers, xii
reset button, xii, 2-26
FIFO Control register, 2-9
figures, list of, viii
Flash memory
8-bit ident ifi cation, 2-27
desc ription , 2-27
selecting, 2-29
using, 2-28
Flash select jumper diagram, 2-29
FLASHCS, 1-8
FLASHRD, 1-7
FLASHWR, 1-8
G
GND, 1-5
H
hexadecimal display, 2-16
16-b it addressing, 2-3 3
8-bit addressing, 2-32
I/O map
8- an d 16-bit address i ng, 2-17
Hitachi HD44780U data sheet, xiii
HP logic analyzer debug headers, xi, 2-20
HP logic analyzer header
layout, 2-20
HRESET, 1-7
I
I/O address mode
desc ription , 2-31
I/O map
16-b it addressing, 2-3 3
ASCII display, 2-15, 2-33
DIP Switch Inputs register, 2-33
Discrete Inputs register, 2-33
Discrete LED Outputs register, 2-33
Discrete Outputs re gister, 2-33
Ethernet base address, 2-33
hexadecimal display, 2-17, 2-33
interrupt reset, 2-33
parallel port, 2-11, 2-33
serial port, 2-6, 2-33
Version register, 2-33
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8-bit addressi ng, 2-32
ASCII display, 2-15, 2-32
DIP Switch Inputs register, 2-32
Discrete Inputs register, 2-32
Discrete LED Outputs register, 2-32
Discrete Outputs register, 2-32
Ethernet base address, 2-32
hexadecim al displa y, 2-17, 2-32
interrupt reset, 2-32
parallel port, 2-11, 2-32
serial port, 2-6, 2-32
Version register, 2-32
IN2 EN, 2-12
INIT, 2-12
initializing
ethernet controller po rt, 2-13
serial ports, 2-7
input/o utput header
layout, 2-21
inputs, 2-2 1
DIP switch, 2-24
DIP switch and header, xii
inputs and outputs
general-purpose, 2-21
interface cable
60-wire, 1-3
orientation, 1-3
interface connector
signal descriptions, 1-5
interrupt
push button, 2-30
interrupt button
feature, xii
Interrupt Enable register, 2-9
Interrupt Identification register, 2-9
interrupt reset
16-bit addr essing, 2-33
8-bit addressi ng, 2-32
interrupt sources
feature, xii
interrupts
debug headers, 2-20
desc ription , 2-30
DIP switch, 2-24
main interface connector, 2-30
serial port, 2-7, 2-8
UART, 2-8
IOCHRDY, 1-7
J
JP1, xii, 2-29
jumper block (JP1), xii
jumper block 1 (JP1), 2-29
L
layout
DIP switch, 2-24
HP logic analyzer header, 2-20
input/ou tput header, 2-21
TIP board, 2-2, 2- 3
layout and placement, 2-2
LCD, 2-3
configuring, 2-15
desc ription , 2-14
display, 2-14
Hitachi data sheet, xiii
layout, 2-2
LEDs, 2-3
eight, 2-18
feature, xi
general-purpose, 2-18
layout, 2-2
pinout, 2-18
Line Control register, 2-7, 2-8
Line Status register, 2-7, 2-9
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M
MACH device
code, A-1
MACH® device
desc ription , 2-30
equations, 2-30, A-1
feature, xii
main interface connector signal s, 1-5
main interface connector, xiii
60-w ire ribb on cable, xi
conn ecting to host boa rd, 2-1
interrupt source, xii
interrupts, 2-30
pinout, xiii, 1-9
pinout signals, 1-5
signal descriptions, 1-5
signals
ENETIRQ, 1-6
EXTFLHCS, 1-8
FLASHCS, 1-8
FLASHRD, 1-7
FLASHWR, 1-8
GND, 1-5
HRESET, 1-7
IOCHRDY, 1-7
MAIN_IRQ, 1-7
PARINT, 1-7
SEL186, 1-8
SERINT0, 1-7
SERINT1, 1-7
TA1–TA19, 1-5
TAEN, 1-6
TD0–TD7, 1-5
TIPSEL, 1-6
TIPSEL, 1-5
TRD, 1-6
TRESET, 1-7
TS2, 1-7
TWR, 1-6
VCC, 1-8
MAIN_IRQ, 1-7
interrupts, 2-30
Modem Control register, 2-9
modem status
serial port interrupts, 2-8
Modem Status register, 2-9
O
operating mode
serial port, 2-7
outputs, 2-21
TTL/CMOS, xii
P
P1 main interface connector, 1-5
ribbon cable connector, 1-2, 1-5
interrupts, 2-30
P2 barrel connector, 1-2
parallel port
16-b it addressing, 2-3 3
8-bit addressing, 2-32
connector pinout, 2-10
desc ription , 2-10
feature, xi
I/O map
8- an d 16-bit address i ng, 2-11
programming, 2-12
registers
Read Control, 2-12
Read Data, 2-12
Read Status, 2-12
Write Control, 2-12
Write Data register, 2-12
PARINT, 1-7
PC-compatible parallel port, xi
PE, 2-12
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pinout
LEDs, 2-18
main interface connector, 1-9
parallel port, 2-10
serial port, 2-5
port chip selects, 2-20
powe r, 2-3
power supply, external 5-V DC, 1-1
powering up, xiii
PRINT, 2-12
programmable registers, xii
programming
parallel port, 2-12
serial port, 2-7
R
Read Control register, 2-12
Read Data register, 2-12
Read Status register, 2-12
signal bits
ACK, 2-12
BSY, 2-12
ERR, 2-12
PE, 2-12
PRINT, 2-12
SLCT, 2-12
Receive Buffer register, 2-8
received data available
serial port interrupt, 2-8
receiver line status
serial port interrupts, 2-8
registers
DIP Switch Inputs
16-bit, 2 -33
feature, xii
Interrupt Reset
8-Bit, 2-26
parallel port
Read Control, 2-12
Read Data, 2-12
Read Status, 2-12
Write Control, 2-12
Write Data, 2-12
serial port, 2-7
Divisor Latch LSB, 2-8
Divisor Latch MSB, 2-8
FIFO Control, 2 - 9
Interrupt Enable, 2-9
Interrupt Identification, 2-9
Line Control, 2-7, 2-8
Line Status, 2-9
Modem Control, 2-9
Modem Status, 2-9
Receive Buffer, 2-8
Scratch Pad, 2-9
Transmitter Holding, 2 -8
Version
16-bit, 2-33
16-b it addressing, 2-3 4
8-bit, 2-32
8-bit addressing, 2-34
bits 0-3, 2-35
bits (0-3, 4-7), 2-35
bits 4-7, 2-35
reset button, xii, 2-26
ribbon cable
60-wire, xi
connecting to TIP and host, 1-3
connecting to main interface connector,
1-5
connecting to TIP and host, 1-2
connecting to TIP and host board, 1-1
input/ou tput header, 2-21
orientation, 1-4
S
Scratch Pad register, 2-9
SD186ED, 2-34
SEL186, 1-8
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serial port
16550 RS-232, xi
16-bit addr essing, 2-33
8-bit addressi ng, 2-32
configuring for DTE, 2-9
connector pinout, 2-5
desc ription , 2-5
I/O map
8- an d 16-bit address i ng, 2-6
initializing, 2 - 7
interrupt
transmit holding register empty, 2-8
interrupts, 2-8
modem status, 2-8
received data available, 2-8
receiver line status, 2-8
main interface connector, 2-5
operating mode , 2-7
programming, 2-7
programming information, 2-9
registers, 2- 5
Divisor Latch LSB, 2-7, 2-8
Divisor Latch MSB, 2-7, 2-8
FIFO Control, 2-9
Interrupt Enable, 2-9
Interrupt Identification, 2-9
Line Control, 2-8
Line Status, 2-7, 2-9
Modem Control, 2-9
Modem Status, 2-9
Receive Buffer, 2-8
Scratch Pad, 2-9
Transmit Holding, 2 -7
Transmitter Holding, 2-8
UAR T opera tion, 2-7
SERINT0, 1-7
SERINT1, 1-7
signal descriptions
main interface connector, 1-5
SLCT, 2-12
SLIN, 2-12
STR, 2-12
suggested reference material, xiii
support
third-party, iii
SW2 switch
interrupts, 2-30
SW3 switch, xii
I/O address mode, 2-31
system features and components, 2-1
T
TA1–TA19, 1-5
tables, list of, ix
TAEN, 1-6
TD0–TD7, 1-5
technical support, iii
Texas Instruments TL16C552
paralle l por t, 2-10
serial port, 2-5
serial port registers, 2-8
specification, xiii
timing
desc ription , 2-34
TIPSEL, 1-5, 1-6
TL16C552, See Texas Instruments
TL16C552, xiii
TL16C552, Texas Instruments specification,
2-5, 2-10
Transmit Holding reg ister, 2-7, 2-8
transmit holding register empty
serial port interrupt, 2-8
TRD, 1-6
TRESET, 1-7
TS2, 1-7
TWR, 1-6
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U
UART
interrupts, 2-8
see also serial port, 2-7
UAR T opera tion, 2-7
V
VCC
main interface connector signal, 1-8
powe r, 1-1
Version register
16-bit addr essing, 2-33
8-bit addressi ng, 2-32
bit definitions, 2-35
desc ription , 2-34
MACH device code version, 2-35
TIP board revision, 2-35
W
Write Control register, 2-12
control line states
AFD, 2-12
DIR, 2-12
IN2 EN, 2-12
INIT, 2-12
SLIN, 2-12
STR, 2-12
Write Data register, 2-12
WWW support, iii
www.amd.com
AMD home page, xiii, A-1
technical support, iii
TIP.book Page 8 Friday, April 23, 1999 10:38 AM
