82527 SERIAL COMMUNICATIONS CONTROLLER AREA NETWORK PROTOCOL Express Advance Information Datasheet Product Features Supports CAN Specification 2.0 -- Standard Data and Remote Frames -- Extended Data and Remote Frames Programmable Global Mask -- Standard Message ldentifier -- Extended Message ldentifier 15 Message Objects of 8-Byte Data Length -- 14 Tx/Rx Buffers -- 1 Rx Buffer with Programmable Mask Flexible CPU Interface -- 8-Bit Multiplexed -- 16-Bit Multiplexed -- 8-Bit Non-Multiplexed (Synchronous/ Asynchronous) -- Serial Interface Programmable Bit Rate Programmable Clock Output Flexible Interrupt Structure Flexible Status Interface Configurable Output Driver Configurable Input Comparator Two 8-Bit Bidirectional I/O Ports 44-Lead PLCC Package Pinout Compatibility with the 82526 Notice: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Order No: 273150-002 August 2004 82527 - Express Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82527 - Express may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation PO Box 5937 Denver CO 80217-9808 call 1-800-548-4725 Copyright (c) Intel Corporation 1997, 2004 *Third-party brands and names are the property of their respective owners. ii Advance Information Datasheet 82527 - Express Contents 1.0 INTRODUCTION ..................................................................................................... 1 2.0 PIN DESCRIPTIONS ............................................................................................. 3 3.0 ELECTRICAL CHARACTERISTICS ................................................................. 5 3.1 3.2 3.3 3.4 4.0 DC CHARACTERISTICS ................................................................................ 5 PHYSICAL LAYER SPECIFICATIONS........................................................... 6 CLOCKOUT SPECIFICATIONS ..................................................................... 6 AC CHARACTERISTICS ................................................................................ 7 3.4.1 8/16-Bit Multiplexed Intel Modes (Modes 0, 1) ................................... 7 3.4.2 8-Bit Multiplexed Non-Intel Mode (Mode 2) ...................................... 10 3.4.3 8-Bit Non-Multiplexed Asynchronous Mode (Mode 3) ...................... 12 3.4.4 8-Bit Non-Multiplexed Synchronous Mode (Mode 3)........................ 14 3.4.5 Serial Interface Mode ....................................................................... 16 3.4.6 AC Testing Input............................................................................... 18 DATASHEET REVISION HISTORY ................................................................18 Advance Information Datasheet iii 82527 - Express Figures 1 2 3 4 6 7 8 9 10 11 12 13 xx82527 Block Diagram ..................................................................................2 xx82527 44-Pin PLCC Package .....................................................................2 82527 System Timings (Modes 0, 1) ...............................................................8 Ready Output Timing for a Write Cycle if No Previous Write is Pending (Modes 0, 1) ...................................................................................9 Ready Output Timing for Write Cycle if Previous Write Cycle is Active (Modes 0, 1 ........................................................................................9 Ready Output Timing for Read Cycle (Modes 0, 1) .........................................9 82527 System Bus Timing (Mode 2) ..............................................................11 Timing of the Asynchronous Mode Read Cycle (Mode 3)..............................13 Timing of the Asynchronous Mode Write Cycle (Mode 3) ..............................13 Timing of the Synchronous Read Cycle (Mode 3) .........................................15 Timing of the Synchronous Write Cycle (Mode 3)..........................................15 Serial Interface Mode (Priority = 0, Phase = 0) ..............................................17 Serial Interface Mode (Priority = 1, Phase = 1) ..............................................17 1 2 3 4 5 6 7 8 9 10 Pin Type Legend ..............................................................................................3 Pin Descriptions ...............................................................................................3 DC Characteristics ...........................................................................................5 DC Characteristics ...........................................................................................6 Clockout Specifications ....................................................................................6 AC Characteristics 8/16-Bit Multiplexed Intel Modes (Modes 0, 1) ..................7 AC Characteristics 8-Bit Multiplexed Non-Intel Mode (Mode 2) .....................10 AC Characteristics 8-Bit Non-Multiplexed Asynchronous Mode (Mode 3) .....12 AC Characteristics 8-Bit Non-Multiplexed Synchronous Mode (Mode 3).......14 AC Characteristics for Serial Interface Mode .................................................16 5 Tables iv Advance Information Datasheet 82527 - Express 1.0 INTRODUCTION The 82527 serial communications controller is a highly integrated device that performs serial communication according to the CAN protocol. It performs all serial communication functions such as transmission and reception of messages, message filtering, transmit search, and interrupt search with minimal interaction from the host microcontroller, or CPU. The 82527 is Intel's first device to support the standard and extended message frames in CAN Specification 2.0 Part B. It has the capability to transmit, receive, and perform message filtering on extended message frames. Due to the backwardly compatible nature of CAN Specification 2.0, the 82527 also fully supports the standard message frames in CAN Specification 2.0 Part A. The 82527 features a powerful CPU interface that offers flexibility to directly interface to many different CPUs. It can be configured to interface with CPUs using an 8-bit multiplexed, 16-bit multiplexed, or 8-bit non-multiplexed address/data bus for Intel and non-Intel architectures. A flexible serial interface (SPI) is also available when a parallel CPU interface is not required. The 82527 provides storage for 15 message objects of 8-byte data length. Each message object can be configured as either transmit or receive except for the last message object. The last message object is a receive-only buffer with a special mask design to allow select groups of different message identifiers to be received. The 82527 also implements a global masking feature for message filtering. This feature allows the user to globally mask any identifier bits of the incoming message. The programmable global mask can be used for both standard and extended messages. The 82527 PLCC offers hardware, or pinout, compatibility with the 82526. It is pin-to-pin compatible with the 82526 except for pins 9, 30, and 44. These pins are used as chip selects on the 82526 and are used as CPU interface mode selection pins on the 82527. The 82527 is fabricated using Intel's reliable CHMOS III 5V technology and is available in 44-lead PLCC for the express temperature range (-40C to +85C). ADVANCE INFORMATION Datasheet 1 82527 - Express Figure 1. xx82527 - Express Block Diagram Port 1 Port 2 Port 1 Port 2 TX0 Address/ Data Bus CAN Controller CPU Interface Logic Control Bus RAM TX1 RX0 RX1 CLKOUT Mode 0 Mode 1 CLKOUT A4577-01 6 5 4 3 2 1 44 43 42 41 40 RD# / E ALE / AS AD0 AD1 AD2 VCC MODE0 AD3 AD4 / MOSI AD5 AD6 / SCLK Figure 2. xx82527 44-Pin PLCC Package 7 8 9 10 11 12 13 14 15 16 17 xx82527 View of component as mounted on PC board 39 38 37 36 35 34 33 32 31 30 29 AD7 P1.0 / AD8 P1.1 / AD9 P1.2 / AD10 P1.3 / AD11 P1.4 / AD12 P1.5 / AD13 P1.6 / AD14 P1.7 / AD15 MODE1 RESET# XTAL1 XTAL2 VSS2 RX1 RX0 VSS1 V INT#( CC/2) TX1 TX0 CLKOUT READY/MISO 18 19 20 21 22 23 24 25 26 27 28 (WR# / WRL#)/(R/W#) CS# DSACK0 P2.7 / WRH# P2.6 / INT# P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 A4578-01 2 ADVANCE INFORMATION Datasheet 82527 - Express 2.0 PIN DESCRIPTIONS The 82527 - Express pins are described in this section. Table 1 presents the legend for interpreting the pin types. Table 1. Pin Type Legend Symbol Description I Input Only Pin O Output Only Pin I/O Pin can be either Input or Output Table 2. Pin Descriptions (Sheet 1 of 2) Name Type Description VSS1 Ground GROUND connection must be connected externally to a VSS board plane. Provides digital ground. VSS2 Ground GROUND connection must be connected externally to a VSS board plane. Provides ground for analog comparator. VCC Power POWER connection must be connected externally to +5 V DC. Provides power for entire device. I Input for an external clock. XTAL1 (along with XTAL2) are the crystal connections to an internal oscillator. XTAL2 O Push-pull output from the internal oscillator. XTAL2 (along with XTAL1) are the crystal connections to an internal oscillator. If an external oscillator is used, XTAL2 must be floated, or not be connected. XTAL2 must not be used as a clock output to drive other CPUs. CLKOUT O Programmable clock output. This output may be used to drive the oscillator of the host microcontroller. XTAL1 Warm Reset: (VCC remains valid while RESET# is asserted), RESET# must be driven to a valid low level for 1 ms minimum. RESET# I Cold Reset: (VCC is driven to a valid level while RESET# is asserted), RESET# must be driven low for 1 ms minimum measured from a valid VCC level. No falling edge on the reset pin is required during a cold reset event. CS## I A low level on this pin enables CPU access to the 82527 device. INT# O (VCC/2) O The interrupt pin is an open-drain output to the host microcontroller. VCC/2 is the power supply for the ISO low speed physical layer. The function of this pin is determined by the MUX bit in the CPU Interface Register (Address 02H) as follows: MUX e 1: pin 24 (PLCC) = VCC /2, pin 11 = INT# MUX e 0: pin 24 (PLCC) = INT# RX0 I RX1 I TX0 O TX1 O ADVANCE INFORMATION Datasheet Inputs from the CAN bus line(s) to the input comparator. A recessive level is read when RX0 > RX1. A dominant level is read when RX1 > RX0. When the CoBy bit (Bus Configuration register) is programmed as a "1", the input comparator is bypassed and RX0 is the CAN bus line input. Serial data push-pull output to the CAN bus line. During a recessive bit TX0 is high and TX1 is low. During a dominant bit TX0 is low and TX1 is high. 3 82527 - Express Table 2. Pin Descriptions (Sheet 2 of 2) Name Type Description Address/Data bus in 8-bit multiplexed mode. AD0/A0/ICP AD1/A1/CP AD2/A2/CSAS AD3/A3/STE AD4/A4/MOSI AD5/A5 AD6/A6/SCLK AD7/A7 I/O-I-I I/O-I-I I/O-I-I I/O-I I/O-I-I I/O-I I/O-I-I I/O-I AD8/D0/P1.0 AD9/D1/P1.1 AD10/D2/P1.2 AD11/D3/P1.3 AD12/D4/P1.4 AD13/D5/P1.5 AD14/D6/P1.6 AD15/D7/P1.7 I/O-O-I/O I/O-O-I/O I/O-O-I/O I/O-O-I/O I/O-O-I/O I/O-O-I/O I/O-O-I/O I/O-O-I/O P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6/INT# P2.7/WRH# I/O I/O I/O I/O I/O I/O I/O-O I/O-I Address bus in 8-bit non-multiplexed mode. Low byte of A/D bus in 16-bit multiplexed mode. In Serial Interface mode, the following pins have the following meaning: AD0: AD1: AD2: AD3: AD6: AD4: ICP CP CSAS STE SCLK MOSI Idle Clock Polarity Clock Phase Chip Select Active State Sync Transmit Enable Serial Clock Input Serial Data Input High byte of A/D bus in 16-bit multiplexed mode. Data bus in 8-bit non-multiplexed mode. Low speed I/O port. P1 pins in 8-bit multiplexed mode and serial mode. Port pins have weak pullups until the port is configured by writing to 9FH and AFH. P2 in all modes. P2.6 is INT# when MUX = 1 and is open-drain. P2.7 is WRH# in 16-bit multiplexed mode. These pins select one of the four parallel interfaces. These pins are weakly held low during reset. Mode1 Mode0 Mode1 ALE/AS 4 I I I-I RD# E I I WR#/WRL# R/W# I I Mode0 0 0 0 0 0 1 1 1 0 1 8-bit multiplexed -- Intel Serial Interface mode entered when RD# = 0, WR# = 0 upon reset. 16-bit multiplexed -- Intel 8-bit multiplexed -- non-Intel 8-bit non-multiplexed ALE used for Intel modes. AS used for non-Intel modes, except Mode 3 this pin must be tied high. RD#used for Intel modes. E used for non-Intel modes, except Mode 3 Asynchronous this pin must be tied high. WR#in 8-bit Intel mode and WRL# in 16-bit Intel mode. R/W# used for non-Intel modes. READY MISO O O READY is an output to synchronize accesses from the host microcontroller to the 82527. READY is an open-drain output to the host microcontroller. MISO is the serial data output for the serial interface mode. DSACK0# O DSACK0# is an open-drain output to synchronize accesses from the host microcontroller to the 82527. ADVANCE INFORMATION Datasheet 82527 - Express 3.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS* Storage Temperature -60C to +150C Voltage from Any Pin to VSS ................................................. -0.5 V to +7.0 V Laboratory testing shows the 82527 will withstand up to 10 mA of injected current into both RX0 and RX1 pins for a total of 20 days without sustaining permanent damage. This high current condition may be the result of shorted signal lines. The 82527 will not function properly if the RX0/RX1 input voltage exceeds VCC +0.5 V. 3.1 NOTICE: This is a production data sheet. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. DC CHARACTERISTICS Operating Conditions: * VCC = 5 V 10% * TA = -40C to +85C Table 3. DC Characteristics Sym Parameter Min Max VIL Input Low Voltage (All except RX0, RX1, AD0AD7 in Mode 3) -0.5 0.8 V VIL1 Input Low Voltage for AD00-D7 in Mode 3 -0.5 0.5 V VIL2 Input Low Voltage (RX0) for Comparator Bypass Mode 0.5 V VIL3 Input Low Voltage for Port 1 and Port 2 Pins Not Used for Interface to Host CPU 0.3 VCC VIH Input High Voltage (All except RX0, RX1, RESET#) VIH1 Input High Voltage (RESET#) Hysteresis on RESET# VIH2 Input High Voltage (RX0) for Comparator Bypass Mode 4.0 V VIH3 Input High Voltage for Port 1 and Port 2 Pins Not Used for Interface to Host CPU 0.7 VCC VOL Output Low Voltage (All Outputs except TX0, TX1) VOH Output High Voltage (All Outputs except TX0, TX1, CLOCKOUT) VOHR1 Output High Voltage (CLOCKOUT) ILK Input Leakage Current 3.0 V VCC + 0.5 V 3.0 V 200 mV VCC + 0.5 V 0.45 V VCC - 0.8 V Conditions IOL = 1.6 mA IOH = -200 A 0.8 V IOH = -80 A 10 A VSS < VIN < VCC CIN PIN Capacitance** 10 pF FXTAL = 1 KHz ICC Supply Current 50 mA FXTAL = 16 KHz(1) ISLEEP Sleep Current with VCC/2 Output Enabled, No Load with VCC/2 Output Disabled 700 A 100 A (1) IPD Powerdown Current 25 A XTAL1 Clocked(1) NOTES: **Typical value based on characterization data. Port pins are weakly held after reset until the port configuration registers are written (9FH, AFH). 1. All pins are driven to VSS or VCC including RX0 and RX1. ADVANCE INFORMATION Datasheet 5 82527 - Express 3.2 PHYSICAL LAYER SPECIFICATIONS Operating Conditions: * Load = 100 pF * VCC = 5 V 10% * TA = -40C to +85C Table 4. DC Characteristics RX0/RX1 and TX0/TX1 Min Max -0.5 V VCC + 0.5 V Common Mode Range VSS + 1 V VCC - 1 V Differential Input Threshold 100 mV Input Voltage Conditions Internal Delay 1: Sum of the Comparator Input Delay and the TX0/TX1 Output Driver Delay 60 ns Load on TX0, TX1 = 100 pF, +100 mV to -100 mV RX0/RX1 differential Internal Delay 2: Sum of the RX0 Pin Delay (if the Comparator is Bypassed) and the TX0/TX1 Output Driver Delay 50 ns Load on TX0, TX1 = 100 pF Source Current on Each TX0, TX1 -10 mA VOUT = VCC - 1 V Sink Current on Each TX0, TX1 10 mA VOUT = 1 V Input Hysteresis for RX0/RX12 0V VCC/2 V CC/2 3.3 2.38 V 2.62 V IOUT 75 A, VCC = 5 V CLOCKOUT SPECIFICATIONS Operating Conditions: * Load = 50 pF Table 5. Clockout Specifications Parameter CLOCKOUT Frequency 6 Min Max XTAL/15 XTAL ADVANCE INFORMATION Datasheet 82527 - Express 3.4 AC CHARACTERISTICS 3.4.1 8/16-Bit Multiplexed Intel Modes (Modes 0, 1) Operating Conditions: * VCC = 5 V 10% * VSS = 0 V * TA = -40C to +85C * CL = 100 pF Table 6. AC Characteristics 8/16-Bit Multiplexed Intel Modes (Modes 0, 1) (Sheet 1 of 2) Symbol Parameter Min Max 1/TXTAL Oscillator Frequency 8 MHZ 16 MHz 1/TSCLK System Clock Frequency 4 MHZ 10 MHZ 1/TMCLK Memory Clock Frequency 2 MHZ 8 MHZ TAVLL Address Valid to ALE Low 7.5 ns TLLAX Address Hold after ALE Low 10 ns TLHLL ALE High Time 30 ns TLLRL ALE Low to RD# Low 20 ns TCLLL CS# Low to ALE Low 10 ns TQVWH Data Setup to WR# High 27 ns TWHQX Input Data Hold after WR# High 10 ns TWLWH WR# Pulse Width 30 ns TWHLH WR# High to Next ALE High 8 ns TWHCH WR# High to CS# High 0 ns RD# Pulse Width TRLRH Conditions 40 ns This time is long enough to initiate a double read cycle by loading the High Speed Registers (04H, 05H), but is too short to READ from 04H and 05H (See t RLDV ) TRLDV RD# Low to Data Valid (Only for Registers 02H, 04H, 05H) TRLDV1 RD# Low Data to Data Valid (for Registers except 02H, 04H, 05H) for Read Cycle without a Previous Write (1) for Read Cycle with a Previous Write (1) TRHDZ Data Float after RD# High TCLYV CS# Low to READY Setup Condition: Load Capacitance on the READY Output: 50 pF 32 ns 40 ns TWLYZ WR# Low to READY Float for a Write Cycle if No Previous Write is Pending (2) 145 ns TWHYZ End of Last Write to READY Float for a Write Cycle if a Previous Write Cycle is Active (2) 2 TMCLK + 100 ns 0 ns 55 ns 1.5 TMCLK + 100 ns 3.5 TMCLK + 100 ns 0 ns 45 ns VOL=1 V VOL=0.45 V NOTES: References to WR# also pertain to WRH#. 1. Definition of "read cycle without a previous write": The time between the rising edge of WR#/WRH# (for the previous write cycle) and the falling edge of RD# (for the current read cycle) is greater than 2 TMCLK. 2. Definition of "write cycle with a previous write'". The time between the rising edge of WR#/WRH# (for the previous write cycle) and the rising edge of WR#/WRH# (for the current write cycle) is less than 2 TMCLK. 3. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor. ADVANCE INFORMATION Datasheet 7 82527 - Express Table 6. AC Characteristics 8/16-Bit Multiplexed Intel Modes (Modes 0, 1) (Sheet 2 of 2) Symbol Parameter Min TRLYZ RD# Low to READY Float (for registers except 02H, 04H, 05H) for Read Cycle without a Previous Write (1) for Read Cycle with a Previous Write (1) TWHDV WR# High ti Output Data Valid on Port 1/2 TCOPO CLKOUT Period TCHCL CLKOUT High Period Max Conditions 2 TMCLK + 100 ns 4 TMCLK + 100 ns TMCLK 2 TMCLK + 100 ns (CDV+1) * TOSC (3) (CDV+1) * 1/2TOSC -10 (CDV+1) * 1/2TOSC -15 NOTES: References to WR# also pertain to WRH#. 1. Definition of "read cycle without a previous write": The time between the rising edge of WR#/WRH# (for the previous write cycle) and the falling edge of RD# (for the current read cycle) is greater than 2 TMCLK. 2. Definition of "write cycle with a previous write'". The time between the rising edge of WR#/WRH# (for the previous write cycle) and the rising edge of WR#/WRH# (for the current write cycle) is less than 2 TMCLK. 3. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor. Figure 3. 82527 - Express System Timings (Modes 0, 1) tLHLL ALE tAVLL BUS tLLAX Address Data Out tRLDV tRHDZ RD# tLLRL tRLRH tCLLL tWHCH CS# tWLWH tWHLH WR# tQVWH tWHQX BUS Address Data In tWHDV PORT 1 / 2 A4580-01 8 ADVANCE INFORMATION Datasheet 82527 - Express Figure 4. Ready Output Timing for a Write Cycle if No Previous Write is Pending (Modes 0, 1) CS# WR# Ready tCLYV tWLYZ Figure 5. Ready Output Timing for Write Cycle if Previous Write Cycle is Active (Modes 0, 1) CS# WR# Ready tWHYZ Figure 6. Ready Output Timing for Read Cycle (Modes 0, 1) tCLYV CS# ALE RD# Ready tRLYZ ADVANCE INFORMATION Datasheet 9 82527 - Express 3.4.2 8-Bit Multiplexed Non-Intel Mode (Mode 2) Operating Conditions:: * VCC = 5 V 10% * VSS = 0 V * TA = -40C to +85C * CL = 100 pF Table 7. AC Characteristics 8-Bit Multiplexed Non-Intel Mode (Mode 2) Symbol Parameter Min Max 1/TXTAL Oscillator Frequency 8 MHZ 16 MHz 1/TSCLK System Clock Frequency 4 MHZ 10 MHZ 1/TMCLK Memory Clock Frequency 2 MHZ 8 MHZ TAVLL Address Valid to AS Low 7.5 ns TSLAX Address Hold after AS Low 10 ns TELDZ Data Float after E Low 0 ns 45 ns E High to Data Valid for Registers 02H, 04H, 05H 0 ns 45 ns TEHDV for Read Cycle without a Previous Write (1) for Read Cycle with a Previous Write (for Registers except for 02H, 04H, 05H) 1.5 TMCLK + 100 ns 3.5 TMCLK + 100 ns TQVEL Data Setup to E Low 30 ns TELQX Input Data Hold after E Low 20 ns TELDV E Low to Output Data Valid on Port 1/2 TMCLK TEHEL E High Time 45 ns TELEL End of Previous Write (Last E Low) to E Low for a Write Cycle TSHSL AS High Time 30 ns TRSEH Setup Time of R/W# to E High 30 ns TSLEH AS Low to E High 20 ns TCLSL CS# Low to AS Low 20 ns TELCH E Low to CS# High 0 ns TCOPD CLKOUT Period TCHCL CLKOUT High Period 2 TMCLK + 500 ns 2 TMCLK (CDV+1) * TOSC (3) (CDV+1) * 1/2TOSC - 10 (CDV+1) * 1/2TOSC + 15 NOTES: 1. Definition of "Read Cycle without a Previous Write": The time between the falling edge of E (for the previous write cycle) and the rising edge of E (for the current read cycle) is greater than 2 TMCLK. 2. Definition of "Write Cycle with a Previous Write'". The time between the falling edge of E (for the previous write cycle) and the falling edge of E (for the current write cycle) is less than 2 TMCLK. 3. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor. 10 ADVANCE INFORMATION Datasheet 82527 - Express Figure 7. 82527 - Express System Bus Timing (Mode 2) tSHSL AS tAVSL Bus tSLAX Data Out Address tEHDV tSLEH tELDZ E tEHEL R/W# tCLSL tRSEH tELCH CS# R/W# tELQX tQVEL Bus Address Data In tELDV Port 1/2 A4588-01 ADVANCE INFORMATION Datasheet 11 82527 - Express 3.4.3 8-Bit Non-Multiplexed Asynchronous Mode (Mode 3) Operating Conditions: * VCC = 5 V 10% * VSS = 0 V * TA = -40C to +85C * CL = 100 pF Table 8. AC Characteristics 8-Bit Non-Multiplexed Asynchronous Mode (Mode 3) Sym Parameter Min Max 1/TXTAL Oscillator Frequency 8 MHZ 16 MHz 1/TSCLK System Clock Frequency 4 MHZ 10 MHZ 1/TMCLK Memory Clock Frequency 2 MHZ 8 MHZ TAVLL Address or R/W# Valid to CS# Low Setup TCLDV TKLDV 3 ns CS# Low to Data Valid for High Speed Registers (02H, 04H, 05H) 0 ns 55 ns For Low Speed Registers (Read Cycle without Previous Write) (1) 0 ns 1.5 TMCLK + 100 ns For Low Speed Registers (Read Cycle with Previous Write) (1) 0 ns 3.5 TMCLK + 100 ns DSACK0# Low to Output Data Valid for High Speed Read Register 23 ns For Low Speed Read Register < 0 ns TCHDV 82527 Input Data Hold after CS# High 15 ns TCHDH 82527 Output Data Hold after CS# High 0 ns TCHDZ CS# High to Output Data Float TCHKH1 CS# High to DSACK0# = 2.4V (3) TCHKH2 CS# High to DSACK0# = 2.8V TCHKZ CS# High to DSACK0# Float 0 ns TCHCL CS# Width between Successive Cycles 25 ns TCHAI CS# High to Address Invalid 7 ns TCHRI CS# High to R/W# Invalid 5 ns TCLCH CS# Width Low 65 ns TDVCH CPU Write Data Valid to CS# High 20 ns TCLKL CS# Low to DSACK0# Low for High Speed Registers and Low Speed Registers Write Access without Previous Write (2) 0 ns 67 ns TCHKL End of Previous Write (CS# High) to DSACK0# Low for a Write Cycle with a Previous Write (2) 0 ns 2 TMCLK + 145 ns TCOPD CLKOUT Period TCHCL CLKOUT High Period 35 ns 0 ns 55 ns 150 ns 100 ns (CDV+1) * TOSC (4) (CDV+1) * 1/2TOSC-10 (CDV+1) * 1/2TOSC+15 NOTES: E and AS must be tied high in this mode. 1. Definition of "Read Cycle without a Previous Write": The time between the rising edge of CS# (for the previous write cycle) and the falling edge of CS# (for the current read cycle) is greater than 2 TMCLK. 2. Definition of "Write Cycle with a Previous Write'". The time between the rising edge of CS# (for the previous write cycle) and the rising edge of CS# (for the current write cycle) is less than 2 TMCLK. 3. An on-chip pullup will drive DSACK0# to approximately 2.4 V. An external pullup is required to drive this signal to a higher voltage. 4. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor. 12 ADVANCE INFORMATION Datasheet 82527 - Express Figure 8. Timing of the Asynchronous Mode Read Cycle (Mode 3) Address tCHAI R/W# tAVCL tCHCL tCLCH CS# tCHDZ tCHDH tCLDV Data tCHKZ tCHKH tKLDV tCLKL DSACK0# A4589-01 Figure 9. Timing of the Asynchronous Mode Write Cycle (Mode 3) Address tCHAI R/W# tAVCL tCHCL tCLCH CS# tDVCH tCHDV Data tCLKL tCHKH tCHKZ DSACK0# A4590-01 ADVANCE INFORMATION Datasheet 13 82527 - Express 3.4.4 8-Bit Non-Multiplexed Synchronous Mode (Mode 3) Operating Conditions: * VCC = 5 V 10% * VSS = 0 V * TA = -40C to +85C * CL = 100 pF Table 9. AC Characteristics 8-Bit Non-Multiplexed Synchronous Mode (Mode 3) Sym Parameter Min Max 1/TXTAL Oscillator Frequency 8 MHZ 16 MHz 1/TSCLK System Clock Frequency 4 MHZ 10 MHZ 1/TMCLK Memory Clock Frequency 2 MHZ 8 MHZ E High to Data Valid out of High Speed Register (02H, 04H, 05H) TEHDV Read Cycle without Previous Write for Low Speed 55 ns Registers(1) 1.5 TMCLK + 100 ns (1) 3.5 TMCLK + 100 ns Read Cycle with Previous Write for Low Speed Registers TELDH Data Hold after E Low for a Read Cycle 5 ns TELDZ Data Float after E Low TELDV Data Hold after E Low for a Write Cycle TAVEH Address and R/W# to E Setup 25 ns TELAV Address and R/W# Valid after E Falls 15 ns TCVEH CS# Valid to E High 0 ns TELCV CS# Valid after E Low 0 ns TDVEL Data Setup to E Low 55 ns TEHEL E Active Width 100 ns TAVAV Start of a Write Cycle after a Previous Write Access 35 ns 15 ns 2 TMCLK TAVCL Address or R/W# to CS# Low Setup 3 ns TCHAI CS# High to Address Invalid 7 ns TCOPD CLKOUT Period TCHCL CLKOUT High Period (CDV+1) * TOSC (2) (CDV+1) * 1/2TOSC-10 (CDV+1) * 1/2TOSC+15 NOTES: 1. Definition of "Read Cycle without a Previous Write": The time between the falling edge of E (for the previous write cycle) and the rising edge of E (for the current read cycle) is greater than 2 TMCLK. 2. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor. 14 ADVANCE INFORMATION Datasheet 82527 - Express Figure 10. Timing of the Synchronous Read Cycle (Mode 3) tAVAV Address tELAV R/W# tAVEH tAVCL tELCV tCHAI tCVEH CS# tEHEL E tDVEL tELDV Data A4592-01 Figure 11. Timing of the Synchronous Write Cycle (Mode 3) tAVAV Address tELAV R/W# tAVEH tAVCL tELCV tCHAI tCVEH CS# tEHEL E tDVEL tELDV Data A4591-01 ADVANCE INFORMATION Datasheet 15 82527 - Express 3.4.5 Serial Interface Mode Operating Conditions: * * * * VCC = 5.0 V 10% VSS = 0 V TA = -40C +85C CL = 100 pF Table 10. AC Characteristics for Serial Interface Mode Sym Parameter Min Max 0.5 MHZ 8 MHZ 2000 ns 1/TMCLK SPI Clock TELDH 1/SCLK 125 ns TELDZ Minimum Clock High Time 84 ns TELDV Minimum Clock Low Time 84 ns TAVEH ENABLE Lead Time 70 ns TELAV Enable Lag Time 109 ns TCVEH Access Time TELCV Maximum Data Out Delay Time TDVEL Minimum Data Out Hold Time TEHEL Maximum Data Out Disable Time TAVAV Minimum Data Setup Time 35 ns TAVCL Minimum Data Hold Time 84 ns TCHAI Maximum Time for Input to go from VOL to VOH TCHAI Maximum Time for Input to go from VOH to VOL TCHAI Minimum Time between Consecutive CS# Assertions TCOPD CLKOUT Period TCHCL CLKOUT High Period 60 ns 59 ns 0 ns 665 ns 100 ns 100 ns 670 ns (CDV+1) * TOSC(1) (CDV+1) * 1/2TOSC-10 (CDV+1) * 1/2TOSC+15 NOTE: 1. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor. 16 ADVANCE INFORMATION Datasheet 82527 - Express Figure 12. Serial Interface Mode (Priority = 0, Phase = 0) tLAG tLEAD tCS CS# tSKHI tSKL0 tRISE tFALL tCYC SCLK tACC tPD0 tH0 tDIS MIS0 tSETUP tHOLD MOSI NOTE: Polarity = 0, Phase = 0 A4593-01 Figure 13. Serial Interface Mode (Priority = 1, Phase = 1) tLAG tLEAD tCS CS# tSKLO tSKHI tCYC tFALL tRISE SCLK tACC tH0 tPD0 tDIS MIS0 tSETUP tHOLD MOSI NOTE: Polarity = 1, Phase = 1 A4594-01 ADVANCE INFORMATION Datasheet 17 82527 - Express 3.4.6 AC Testing Input Figure 1. Input, Output Waveforms VCC - 0.5 0.1 V VCC - 0.8V 0.45V NOTE: AC inputs during testing are driven at VCC - 0.5V for a Logic "1" and 0.1V for a Logic "0". Timing measurements are made at VOH Min for a Logic "1" and VOL Max for a Logic "0". A4598-01 4.0 DATASHEET REVISION HISTORY Package prefix variables in this document are now indicated with an "x". 18 ADVANCE INFORMATION Datasheet