1/9
■OUTPUT VOLTAGE CAN SWING TO
GROUND
■EXCELLENT PHASE MARGIN ON
CAPACITIVE LOADS
■GAIN BANDWIDTH PRODUCT: 3.5MHz
■STABLE AND LOW OF FSET VOLTAG E
■THREE INPUT OFFSET VOLTAGE
SELECTIONS
DESCRIPTION
The TS272 devices are low cost, dual operational
ampl ifiers des igned to o perate with single or dual
sup plies. The se operational amplifiers use the ST
silicon gate CMOS process allowing an excellent
consumption-speed ratio. These series are ideally
suited for low consumption applications.
Three p ower c onsum pt ions are av ailable a llowing
to have always the best consumpt ion-speed ratio:
❑ICC = 10µA/amp.: TS27L2 (very low power)
❑ICC = 150µA/amp.: TS27M2 (low power)
❑ICC = 1mA/amp.: TS272 (standard)
These CMOS amplifiers offer very high input im-
pedance and extremely low input currents. The
majo r advantage versu s JFET devices is the very
low input currents drift with temperature (see fig-
ure 2).
ORDER CODE
N = Dual in Line Package (DIP)
D = Small Outline Package (SO) - also available in Tape & Reel (DT)
P = Thin Shrink Small Outline Package (TSSOP) - only available
in Tape & Reel (PT)
PIN CONNECTIONS (top view)
Part Number Temperature Range Package
NDP
TS272C/AC/BC 0°C, +70°C •••
TS272I/AI/BI -40°C, +125°C •••
TS272M/AM/BM -55°C, +125°C •••
Example : TS272ACN
N
DIP8
(Plastic Package)
D
SO8
(Plastic Micropackage)
P
TSSOP8
(Thin Shrink Small Outline Package)
1
2
3
45
6
7
8
CC
+
-
-
+-
+
CC
1 - Output 1
2 - Inverting Input 1
3 - Non-inverting Input 1
4 - V
5 - Non-inverting Input 2
6 - Inverting Input 2
7 - Output 2
8 - V
TS272C,I,M
HIGH PERFORMANCE
CMOS DUAL OPE RATIONAL AMPLIFIERS
November 2001
TS272C,I,M
2/9
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
E
E
Input
differential Second
stage Output
stage Output
CC
V
CC
V
Current
source x I
Symbol Parameter TS272C/AC/BC TS272I/AI/BI TS272M/AM/BM Unit
VCC+Supply Voltage 1) 18 V
Vid Differential Input Voltage 2) ±18 V
ViInput Voltage 3) -0.3 to 18 V
IoOutput Current for VCC+ ≥ 15V ±30 mA
Iin Input Current ±5 mA
Toper Operating Free-Air Temperature Range 0 to +70 -40 to +125 -55 to +125 °C
Tstg Storage Temperature Range -65 to +150 °C
1. All values, except differential voltag e are with respect to network ground terminal.
2. Differenti al voltages are th e non-i nver ting i nput termi nal with res pect to t he i nver ting i nput termi nal .
3. The magnit ude of the input and the output vol t ages must never exceed t he m agni tude of the positive suppl y v ol tage.
Symbol Parameter Value Unit
VCC+Supply Voltage 3 to 16 V
Vicm Common Mode Input Voltage Range 0 to VCC+ - 1.5 V
TS272C,I,M
3/9
SCHEMATIC DIAGRAM (for 1/2 TS272)
T
T
25
2
T
17 18
R
T
20
T
21
T
T
23
22
Input
Output
T
24
T
19
V
CC
V
CC
T
26
T
27
T
28
T
29
Input
T
3
T
4
T
5
T
2
T
1
R1
C1
T
7
T
6
T
8
T
9
T
13
T
14
T
11
T
12
T
10
T
16
T
15
TS272C,I,M
4/9
ELECTRICAL CHARACTERISTICS
VCC+ = +10V , VCC-= 0V, Tamb = +25°C (unless otherwise specified)
Symbol Parameter TS272C/AC/BC TS272I/AI/BI
TS272M/AM/BM Unit
Min. Typ. Max. Min. Typ. Max.
Vio
Input Offset Vo ltage
VO = 1.4V, Vic = 0V TS272C/I/M
TS272AC/AI/AM
TS272B/C/I/M
Tmin ≤ Tamb ≤ Tmax TS272C/I/M
TS272AC/AI/AM
TS272B/C/I/M
1.1
0.9
0.25
10
5
2
12
6.5
3
1.1
0.9
0.25
10
5
2
12
6.5
3
mV
DVio Input Offset Voltage Drift 2 2 µV/°C
Iio Input Offset Current note 1)
Vic = 5V, VO = 5V
Tmin ≤ Tamb ≤ Tmax
1. Maximum values including unavoidable inaccuracies of the industrial test.
1100 1200 pA
Iib Input Bias Current - see note 1
Vic = 5V, VO = 5V
Tmin ≤ Tamb ≤ Tmax
1150 1300 pA
VOH
High Level Output Voltage
Vid = 100mV, RL = 10kΩ
Tmin ≤ Tamb ≤ Tmax 8.2
8.1 8.4 8.2
88.4 V
VOL Low Level Output Voltage
Vid = -100mV 50 50 mV
Avd
Large Signal Voltage Gain
ViC = 5V, RL = 10kΩ, Vo = 1V to 6V
Tmin ≤ Tamb ≤ Tmax 10
715 10
615 V/mV
GBP Gain Bandwidth Produ ct
Av = 40dB, RL = 10kΩ, CL = 100pF, fin = 100kHz 3.5 3.5 MHz
CMR Common Mode Rejection Ratio
ViC = 1V to 7.4V, Vo = 1.4V 65 80 65 80 dB
SVR Supply Voltage Rejection Ratio
VCC+ = 5V to 10V, Vo = 1.4V 60 70 60 70 dB
ICC
Supply Current (per amplifier)
Av = 1, no load, Vo = 5V
Tmin ≤ Tamb ≤ Tmax 1000 1500
1600 1000 1500
1700 µA
IoOutput Short Circuit Current
Vo = 0V, Vid = 100mV 60 60 mA
Isink Output Sink Current
Vo = VCC, Vid = -100mV 45 45 mA
SR Slew Rate at Unity Ga in
RL = 10kΩ, CL = 100pF, Vi = 3 to 7V 5.5 5.5 V/µs
φmPhase Margin at Unity Gain
Av = 40dB, RL = 10kΩ, CL = 100pF 40 40 Degrees
KOV Overshoot Facto r 30 30 %
enEquivalent Input Noise Voltage
f = 1kHz, Rs = 100Ω30 30
Vo1/Vo2 Channel Separation 120 120 dB
nV
Hz
------------
TS272C,I,M
5/9
TYPICAL CHARACTERISTICS
Figure 1 : S u ppl y Cu r re n t ( each am pl if i e r) versu s
Supply Voltage
Figu re 2 : Input Bias Current versus Free Air
Temperature
Figu re 3a : High Level Output Voltage versus
High Level Output Current
Figu re 3b : High Level Output Voltage versus
High Level Output Current
Figure 4a : Low Level Output Voltage versus Low
Level Output Curre nt
Figure 4b : Low Level Output Voltage versus Low
Level Output Curre nt
CC
SUPPLY VOLTAGE, V (V)
CC
amb
V
OCC
°
04 8 12 16
2.0
m
SUPPLY CURRENT, I ( A)
T=25C
A=1
V=V /2
1.5
1.0
0.5
25 50 75 100 125
amb
INPUT BIAS CURRENT, I (pA)
IB
TEMPERATURE, T ( °C)
V = 10V
V=5V
CC
i
100
10
1
5
4
3
2
1
0
-10 -8 -6 -4 -2 0
OH
OUTPUT CURRENT, I (mA)
OUTPUT VOLTAGE, V (V)
OH
amb
id
T = 25 C
V = 100mV
°
V=5V
V=3V
CC
CC
20
16
12
8
4
0-50 -40 -30 -20 -10 0
amb
id
°
T = 25 C
V = 100mV V = 16V
CC
CC
V = 10V
OUTPUT CURRENT, I (mA)
OH
OH
OUTPUT VOLTAGE, V (V)
1.0
0.8
0.6
0.4
0.2 amb
ic
id
T=25°C
V = 0.5V
V = -100mV
V=3V
V=5V
CC
CC
OL
OUTPUT VOLTAGE, V (V)
0123
OUTPUT CURRENT, I (mA)
OL
0 4 8121620
OUTPUT VOLTAGE, V (V)
OL
amb
id
i
T = 25°C
V=0.5V
V = -100mV
V=10V
CC
V=16V
OUTPUT CURRENT, I (mA)
OL
3
2
1
CC
TS272C,I,M
6/9
Fi gure 5 : Open Loop F requency Respons e and
Phase S hift
Fi gure 6 : Gain Bandwidth Product versus Supply
Voltage
Fi gure 7 : Phase Margin versus Suppl y Voltage
Fi gure 8 : Phase M argin ve rsus Capa c it ive Load
Fi gure 9 : Slew Rate versus Supply Voltage
Fi gure 10 : Input Voltage Noise ve rsus
Frequency
50
40
30
20
10
0
-10 6
10
1023
10 4
10 5
10 7
10
GAIN (dB)
PHASE (Degrees)
0
45
90
135
180
FREQUENCY, f (Hz)
T = 25°C
V=10V
R = 10k
Ω
C = 100pF
A=100
amb
CC
L
L
VCL
PHASE
GAIN
Phase
Margin
Gain
Bandwidth
Product
+
04 8 12 16
GAIN BANDW. PROD., GBP (MHz)
amb
L
L
V
T= 25°C
R = 10k
Ω
C = 100pF
A=1
SUPPLY VOLTAGE, V (V)
CC
5
4
3
2
1
48
04 8 12 1
6
SUPPLY VOLTAGE, V (V)
CC
PHASE MARGIN, m (Degrees)
φ
44
36
32
amb
L
L
V
T= 25°C
R = 10k
Ω
C = 100pF
A=1
28
40
70
60
50
40
30
L
CAPACITANCE, C (pF)
PHASE MARGIN, m(Degrees)
φ
200 80 100
6040
amb
L
V
T= 25°C
R = 10k
Ω
A=1
V=10V
CC
24 6 8 10 12 14 16
SUPPLY VOLTAGE, V (V)
CC
SLEW RATES, SR (V/
µ
s)
SR
SR
amb
L
L
T= 25°C
R = 10k
Ω
C = 100pF
3
4
5
6
7
300
200
100
0
EQUIVALENT INPUT NOISE
VOLTAGE (nV/VHz)
110
100 1000
FREQUENCY (Hz)
= 10V
= 25°C
T
amb
V
CC
=100
Ω
R
S
TS272C,I,M
7/9
PACKAGE MECHANICAL DATA
8 PINS - PLASTIC DIP
Dimensions Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 3.32 0.131
a1 0.51 0.020
B 1.15 1.65 0.045 0.065
b 0.356 0.55 0.014 0.022
b1 0.204 0.304 0.008 0.012
D 10.92 0.430
E 7.95 9.75 0.313 0.384
e 2.54 0.100
e3 7.62 0.300
e4 7.62 0.300
F 6.6 0260
i 5.08 0.200
L 3.18 3.81 0.125 0.150
Z 1.52 0.060
TS272C,I,M
8/9
PACKAGE MECHANICAL DATA
8 PINS - PLASTIC MICROPACKAGE (SO)
Dimensions Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 1.75 0.069
a1 0.1 0.25 0.004 0.010
a2 1.65 0.065
a3 0.65 0.85 0.026 0.033
b 0.35 0.48 0.014 0.019
b1 0.19 0.25 0.007 0.010
C 0.25 0.5 0.010 0.020
c1 45° (typ.)
D 4.8 5.0 0.189 0.197
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 3.81 0.150
F 3.8 4.0 0.150 0.157
L 0.4 1.27 0.016 0.050
M 0.6 0.024
S 8° (max.)
b
e3
A
a2
s
L
C
E
c1
a3
b1
a1
DM
85
14
F
TS272C,I,M
9/9
PACKAGE MECHANICAL DATA
8 PINS - THI N SHRINK SMALL OUTLIN E PACKAGE (TSSOP)
Dimensions Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 1.20 0.05
A1 0.05 0.15 0.01 0.006
A2 0.80 1.00 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.15
c 0.09 0.20 0.003 0.012
D 2.90 3.00 3.10 0.114 0.118 0.122
E 6.40 0.252
E1 4.30 4.40 4.50 0.169 0.173 0.177
e 0.65 0.025
k0° 8° 0° 8°
l 0.50 0.60 0.75 0.09 0.0236 0.030
L 0.45 0.600 0.75 0.018 0.024 0.030
L1 1.000 0.039
C
L
14
8
5
L1
c0.25mm
.010 inch
GAGE PLANE
E1
k
LL1
E
SEATING
PLANE
A
A2
D
A1
b
5
8
4
1
PIN 1 IDENTIFICATION
e
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