74AC373 74ACT373 Octal Transparent Latch with 3-STATE Outputs General Description The AC/ACT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip- flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. Features November 1988 Revised October 1998 BI lec and loz reduced by 50% lf Eight latches in a single package M 3-STATE outputs for bus interfacing Hf Outputs source/sink 24 mA B ACT373 has TTL-compatible inputs Ordering Code: Order Number | Package Number Package Description 74AC3738SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body 74AC3738J M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE Il, 5.8mm Wide 74AC373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC373PG N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT3738C M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body 74ACT3738J M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.8mm Wide 74ACT373MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE Il, 5.8mm Wide 74ACT373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT373PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP}, JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering information Logic Symbols Ltit {| FLeE O}or Do Dy Dy O3 Dg Ds 0g Dy Oy 0, 0 03 04 O5 Og 07 Prrtt | IEEE/IEC OE EN i) oy Oy 03 % 05, 06 07 FACT" is a trademark of Fairchild Semiconductor Corporation. Connection Diagram Pin Assignment for DIP, SOIC, SSOP, and TSSOP V/s ot 20 Voc 0-42 t9f-0, Dyo-43 18|Dy D444 17 Dg 0,45 16-0, 0-46 15,05 Do47 14}ds D348 13;-D, 03-49 12-0, GND]10 11 Pele Pin Descriptions Pin Names Description Do-D7 Data Inputs LE Latch Enable Input OE Output Enable Input Op-O7 3-STATE Latch Outputs 1998 Fairchild Semiconductor Corporation DS009958.prf www.fairchildsemi.com S1NdiNO ALVLS- YUM Yo}e7 JUsIedsuBIL [2190 EZELOVHZ * EZEOVEL74AC373 - 74ACT373 Functional Description The AC/ACT373 contains eight D-type latches with 3- STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the D, inputs enters the latches. In this condition the latches are transparent, i.e., a latch out- put will change state each time its D-type input changes. When LE is LOW, the latches store the information that was present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs _are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram Truth Table Inputs Outputs LE OE Dy, 0, x H x Z H L L L H L H H L L x Oo H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial Oo = Previous O, before HIGH to Low transition of Latch Enable L D ol Olo +_} Oo |_| Oo ol _] Olo ol _] Olo ol ;_ | Olo ol _] Qio al > 0 07 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com NoAbsolute Maximum Ratingsinote 1) Supply Voltage (Vcc) DC Input Diode Current (I)x) Vv, =-0.5V Vi =Vec + 0.5V DC Input Voltage (V)) DC Output Diode Current (lox) Vo =-0.5V Vo =Voc + 0.5V DC Output Voltage (Vo) DC Output Source or Sink Current (lo) DC Voc or Ground Current per Output Pin (l or Ienp) Storage Temperature (Tstq) Junction Temperature (Ty) (PDIP) DC Electrical Characteristics for AC -0.5V to +7.0V -20 mA +20 mA -0.5V to Vec +0.5V -20 mA +20 mA -0.5V to Vec +0.5V +50 mA +50 mA -65C to +150C 140C Recommended Operating Conditions Supply Voltage (Vcc) AC ACT Input Voltage (Vj) Output Voltage (Vo) Operating Temperature (Ta) Minimum Input Edge Rate (AV/At) AC Devices Vin from 30% to 70% of Veco Voc @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (AV/At) ACT Devices Vin from 0.8V to 2.0V Voc @ 4.5V, 5.5V 2.0V to 6.0V 4.5V to 5.5V OV to Voc OV to Voc 40C to +85C 125 mV/ns 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. Voc Ta =+28C Ta =40C to +85C . - Symbol Parameter Units Conditions (Vv) Typ Guaranteed Limits Vin Minimum High Level 3.0 1.5 24 2.1 Vout =0.1V Input Voltage 4.5 2.25 3.15 3.15 v or Veg 0.1V 5.5 2.75 3.85 3.85 VIL Maximum Low Level 3.0 1.5 0.9 0.9 Vout = 0.1V Input Voltage 4.5 2.25 1.35 1.35 Vv or Veg 0.1V 5.5 2.75 1.65 1.65 Vou Minimum High Level 3.0 2.99 29 29 lour =-50 pA Output Voltage 45 4.49 44 44 Vv 5.5 5.49 54 5.4 Vin= Vit or Vin 3.0 2.56 2.46 loy=-12 mA 45 3.86 3.76 Vv lo =24 mA 5.5 4.86 4.76 lo. = 24 mA (Note 2) VoL Maximum Low Level 3.0 0.002 0.1 0.1 lout =50 pA Output Voltage 45 0.001 0.1 0.1 Vv 5.5 0.001 0.1 0.1 Vin = Vit or Vin 3.0 0.36 0.44 lol =12mA 45 0.36 0.44 Vv lol =24 mA 5.5 0.36 0.44 lo. = 24 mA (Note 2) lin (Note 4) | Maximum Input Leakage Current 5.5 +0.1 +1.0 Vi =Veco, GND loz Maximum 3-STATE Current V, (OE) = Vit Vin 5.5 +0.25 +2.5 Vi=Vec, GND Vo =Vec, GND lotp Minimum Dynamic Output Current 5.5 75 mA | Vo_p = 1.65V Max (Note 3) lonD 5.5 75 MA | Voup = 3-85V Min loc (Note 4) | Maximum Quiescent Supply Current 5.5 4.0 40.0 BA |Vin= Veco or GND Note 2: All outputs loaded, thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: |), and Ig @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Veg. www.fairchildsemi.com EZELOVPZ EZEDVPL74AC373 - 74ACT373 DC Electrical Characteristics for ACT Symbol Parameter Veco Ta, =+25C Ta =40C to +85 Units Conditions (V) Typ Guaranteed Limits Vin Minimum High Level 45 1.5 2.0 2.0 Vv Vout = 0.1V Input Voltage 5.5 1.5 2.0 2.0 or Veg 0.1V VIL Maximum Low Level 4.5 1.5 0.8 0.8 v Vout = 0.1V Input Voltage 5.5 1.5 0.8 0.8 or Veg 0.1V Vou Minimum High Level 45 4.49 44 44 Vv lout =-50 pA Output Voltage 5.5 5.49 5.4 5.4 Vin = Vit or Vin 45 3.86 3.76 Vv low =-24 mA 5.5 4.86 4.76 loy=24 mA (Note 5) Voi Maximum Low Level 4.5 0.001 0.1 0.1 v lout = 50 pA Output Voltage 5.5 0.001 0.1 0.1 Vin = Vit or Vin 45 0.36 0.44 Vv lo, =24 mA 5.5 0.36 0.44 lo. = 24 mA (Note 5) In Maximum Input 5.5 +0.1 +1.0 pA Vi= Veco, GND Leakage Current loz Maximum 3-STATE 5.5 +0.25 +2.5 pA Vi=Vin Vin Current Vo = Voc, GND loot Maximum lIgo/Input 5.5 0.6 1.5 mA Vi=Veo-2.1V lot Minimum Dynamic 5.5 75 mA Vowp = 1.65V Max loup Output Current (Note 6) 5.5 75 mA Voup =3.85V Min loc Maximum Quiescent 5.5 4.0 40.0 pA Vin=Vec Supply Current or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Voc Ta =+25C Ta = 40C to +85C Symbol Parameter (v) C, =50 pF C, = 50 pF Units (Note 7) Min Typ Max Min Max tpLy Propagation Delay 3.3 1.5 10.0 13.5 1.5 15.0 ns D, to O, 5.0 1.5 7.0 9.5 1.5 10.5 tPHL Propagation Delay 3.3 1.5 9.5 13.0 1.5 14.5 ns D, to O, 5.0 1.5 7.0 9.5 1.5 10.5 teLH Propagation Delay 3.3 1.5 10.0 13.5 1.5 15.0 ns LE to O, 5.0 1.5 75 9.5 1.5 10.5 teu Propagation Delay 3.3 1.5 9.5 12.5 1.5 14.0 ns LE to O, 5.0 1.5 7.0 9.5 1.5 10.5 tpzH Output Enable Time 3.3 1.5 9.0 11.5 1.0 13.0 ns 5.0 1.5 7.0 8.5 1.0 9.5 tez Output Enable Time 3.3 1.5 8.5 11.5 1.0 13.0 ns 5.0 1.5 65 8.5 1.0 9.5 tpuz Output Disable Time 3.3 1.5 10.0 12.5 1.0 14.5 ns 5.0 1.5 8.0 11.0 1.0 12.5 tpLz Output Disable Time 3.3 1.5 8.0 11.5 1.0 12.5 ns 5.0 1.5 65 8.5 1.0 10.0 Note 7: Voltage Range 3.3 is 3.3V +0.3V Voltage Range 5.0 is 5.0V +0.5V www.fairchildsemi.com 4AC Operating Requirements for AC Veco Ta =+28C Ta =40C to +85C Symbol Parameter (V) C, = 50 pF C, = 50 pF Units (Note 8) Typ Guaranteed Minimum ts Setup Time, HIGH or LOW 3.3 3.5 5.5 6.0 ns D, to LE 5.0 2.0 4.0 45 ty Hold Time, HIGH or LOW 3.3 -3.0 1.0 1.0 ns D, to LE 5.0 -1.5 1.0 1.0 tw LE Pulse Width, 3.3 4.0 5.5 6.0 ns HIGH 5.0 2.0 4.0 45 Note 8: Voltage Range 3.3 is 3.3V +0.3V Voltage Range 5.0 is 5.0V +0.5V AC Electrical Characteristics for ACT Veco Ta =+28C Ta =40C to +85C Symbol Parameter (V) C, = 50 pF C_ =50 pF Units (Note 9) Min Typ Max Min Max teLH Propagation Delay 5.0 2.5 8.5 10.0 1.5 11.5 ns D, to O, teu Propagation Delay 5.0 2.0 8.0 10.0 1.5 11.5 ns D, to O, teLH Propagation Delay 5.0 2.5 8.5 11.0 2.0 11.5 ns LE to , tPHL Propagation Delay 5.0 2.0 8.0 10.0 1.5 11.5 ns LE to O, tpzH Output Enable Time 5.0 2.0 8.0 9.5 1.5 10.5 ns tezL Output Enable Time 5.0 2.0 7.5 9.0 1.5 10.5 ns tpyz Output Disable Time 5.0 2.5 9.0 11.0 2.5 12.5 ns tpiz Output Disable Time 5.0 1.5 7.5 8.5 1.0 10.0 ns Note 9: Voltage Range 5.0 is 5.0V +0.5V AC Operating Requirements for ACT Veco Ta =+28C Ta =40C to +85C Symbol Parameter (V) C,_ = 50 pF C, =50 pF Units (Note 10) Typ Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 0.8 2.5 3.5 ns D, to LE ty Hold Time, HIGH or LOW 5.0 0 0 1.0 ns D, to LE tw LE Pulse Width, HIGH 5.0 2.0 7.0 8.0 ns Note 10: Voltage Range 5.0 is 5.0V +0.5V Capacitance Symbol Parameter Typ Units Conditions Cn Input Capacitance 45 pF Veco = OPEN Cpp Power Dissipation Capacitance 40.0 pF Voc = 5.0V 5 www.fairchildsemi.com EZELOVPZ EZEDVPL74AC373 - 74ACT373 Physical DimensiON$ inches (millimeters) unless otherwise noted 0.496 0.512 (12.598 13,005) i 0.394 ~D.419 410.008 10.643) Hl LEADNG 1 f----7q . IDENT a Suu UCU Ue eu eo 1 2 3 4 a 6 7 8 9 10 0.010 MAX (0.254) 0.281 n.29a (7.391 -7.595) 0.010-0.029 0.093-0.104 (0.2540.737) 42 >| [* naa 0.004-0.012 sf aeMAXTYP A ALL t (0.102 0.305) SEATING sontoos 0.009 -0.013. one 0) ag 0.016 0.050. 0356) >| (0:2290.320) ALL LEAD TIPS (0.406 1.270) (0.386) TYP ALL LEADS. TYP ALL LEADS |< _ e| (1.270) TYP 0.008 Typ (0.203) 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Body Package Number M20B 4 PLANE 0,014 0.020 typ (0.356 0.508) 20B (REV FY 20 1 0.295-0.319 (7.5-8.1) 0.205-0.213 (5.2- | 4) 0.71 (Gay? 0.492-0.500 0.067-0.083 0.006-0.010 (12.5-12.7) [ (1,.7-2.1) (0.15-0.25) TYP _ THEE __\ \__ SEATING PLANE _. | 0.000-0.010 (0-0.25) 0.014-0.020 (0.35-0.50) TYP >| [ 0.049 ( (1.25) 0.016-0.031 (0.4-0.8) TYP 20-Lead Small Outline Package (SOP), EIAJ TYPE Il, 5.3mm Wide Package Number M20D |_| 1 TYP) M20D (REV B) www.fairchildsemi.com 6Physical DimensiONS inches (millimeters) unless otherwise noted (Continued) 20 11 L235 [7.40 MAX 7.20 + 0.05 0.684 0.12 1 [ar] | [-A=] sand as 0.304 0.10 ona | 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE Il, 5.3mm Wide Package Number MSA20 | fgletol 7.90 0.20 + 5.304 0.05 0.05 TT 15 20:10 0.204 0.05 [ L/r THICKNESS [f 4e% 30 TYP _ | o.60 0.15 TYP MSA20 (REV A) www.fairchildsemi.com EZELOVPZ EZEDVPL74AC373 - 74ACT373 Physical DimensiONS inches (millimeters) unless otherwise noted (Continued) = TW LI HJUUUUCOUU ss o 7 | | EON Hae WUE UU UU comer ALL LEAD TIPS PIM #1 IDENT. LAND PATTERN RECOMMENDATION EE DETAIL & ALL LEAD TIPS 5 qt dls qiagtit: ' =H1d ans ll SS oft Vey Wo 7 et At ba ey aeons soe (UH. | i | t DIMENSIONS ARE IN MILLIMETERS MOTES: | A, CONFORMS TO JEDEC REGISTRATION REF NCTE 6, DATE 7/93. MO-1S2, VARIATION Ac, B. DIMENSIONS ARE IM MILLIMETERS. C. DIMENSIONS ARE EXCLUSIVE OF BURRS. MOLDS FLASH, AND TIE BAR EXTRUSIUNS. DETAIL A D. DIMENSIONS ANC! TOLERANCES PER ANSI +14.5M, 1982. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 EATING Wes PLANE nari www.fairchildsemi.com 8Physical DimensiONS inches (millimeters) unless otherwise noted (Continued) 1.013-1.040 (25.73-26.42} 0.092 x 0.030 {2.337 X 0.762) 0.032 +0.005 MAX DP T (0.813 +0.127) RAD 0.260 +0.005 =0.127) PIN NO. 1 IDENT OPTION 1 0.090 0.280 [~7.112) MIN 0.300-0.320 2286) (7.620-8.128) 0.060 NOM 0.040 0.065 (1.524) (1.016) (1.651) NP n = | 2 5 f 0.009-0.015 ys 229-0.381) OPTION 2 0.430 0.005 (3.302 0.127} 0.145-0.200 OPTION 2 een | \! | (g1983=5.080) 90+0.004 { dt 0.020 Typ 0.10020, Banosoar0 | L 0.125-0.140 (0.508) 0.060:0.005 (2.540 0.254) 0.018 0.003 (3.175-3.556) MIN 305 |_| (1.52420.127) (0.45720.076) 0.015 41.016 (0255 (e.2ss *108) N20A (REV G) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. Accritical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. S1NdiNO ALVLS- YUM Yo}e7 JUsIedsuBIL [2190 EZELOVHZ * EZEOVEL