Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LP38856 SNVS336F - JUNE 2006 - REVISED AUGUST 2015 LP38856 3-A Fast-Response High-Accuracy LDO Linear Regulator With Enable 1 Features 3 Description * * * * * The LP38856 is a high-current, fast-response regulator which can maintain output voltage regulation with an extremely low input-to-output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: VBIAS provides power for the internal bias and control circuits, as well as drive for the gate of the N-MOS power transistor, while VIN supplies power to the load. The use of an external bias rail allows the part to operate from ultra-low VIN voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an N-MOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. 1 * * * Input Voltage: 1.1 V to 5.5 V Wide VBIAS Supply Operating Range: 3 V to 5.5 V Standard VOUT: 0.8 V and 1.2 V Stable with 10-F Ceramic Capacitors Dropout Voltage of 240 mV (Typical) at 3-A Load Current Precision Output Voltage Across All Line and Load Conditions: - 1% for TJ = 25C - 2% for 0C TJ +125C - 3% for -40C TJ +125C Overtemperature and Overcurrent Protection -40C to +125C Operating Temperature Range The fast transient response of this device makes it suitable for use in powering DSP, microcontroller core voltages, and switch mode power supply post regulators. The LP38856 is available in 5-pin TO-220 and DDPAK/TO-263 packages. * Dropout Voltage: 240 mV (typical) at 3-A load current. * Low Ground Pin Current: 10 mA (typical) at 3-A load current. * Shutdown Current: 1 A (typical) IIN(GND) when EN pin is low. * Precision Output Voltage: 1% for TJ = 25C and 2% for 0C TJ +125C, across all line and load conditions. 2 Applications * * * * ASIC Power Supplies In: - Desktops, Notebooks, and Graphics Cards, Servers - Gaming Set Top Boxes, Printers and Copiers Server Core and I/O Supplies DSP and FPGA Power Supplies SMPS Post-Regulator Device Information(1) PART NUMBER LP38856 PACKAGE BODY SIZE (NOM) DDPAK/TO-263 (5) 10.16 mm x 8.42 mm TO-220 (5) 14.986 mm x 10.16 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit LP38856-x.x VIN VBIAS VEN IN VOUT OUT CIN 10 PF Ceramic BIAS CBIAS 1 PF COUT 10 PF Ceramic EN GND GND GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP38856 SNVS336F - JUNE 2006 - REVISED AUGUST 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 3 3 4 4 4 6 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information ................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 10 7.3 Feature Description................................................. 10 7.4 Device Functional Modes........................................ 11 8 Application and Implementation ........................ 12 8.1 Application Information............................................ 12 8.2 Typical Application ................................................. 12 9 Power Supply Recommendations...................... 14 10 Layout................................................................... 15 10.1 Layout Guidelines ................................................. 15 10.2 Layout Example .................................................... 15 11 Device and Documentation Support ................. 16 11.1 11.2 11.3 11.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 16 16 16 16 12 Mechanical, Packaging, and Orderable Information ........................................................... 17 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (April 2013) to Revision F * Added Device Information and Pin Configuration and Functions sections, ESD Ratings table, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections; remove lead temp from Abs Max (in POA), remove obsolete heatsinking content ...................................................................................................... 1 Changes from Revision D (April 2013) to Revision E * 2 Page Page Changed layout of National data sheet to TI format ............................................................................................................ 14 Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP38856 LP38856 www.ti.com SNVS336F - JUNE 2006 - REVISED AUGUST 2015 5 Pin Configuration and Functions KTT Package 5-Pin DDPAK/TO-263 Top View EN 1 GND 3 OUT 4 TAB IS GND TAB IS GND EN 1 LP38856T-x.x LP38856S-x.x IN 2 NDH Package 5-Pin TO-220 Top View IN 2 GND 3 OUT 4 BIAS 5 BIAS 5 Pin Functions PIN NO. TYPE NAME DESCRIPTION 1 EN I The device enable pin. 2 IN I The unregulated input voltage pin 3 GND -- Ground 4 OUT O The regulated output voltage pin 5 BIAS I The supply for the internal control and reference circuitry TAB TAB -- The TAB is a thermal connection that is physically attached to the backside of the die, and is used as a thermal heat-sink connection. See the Application and Implementation section for details 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN Power dissipation (3) MAX UNIT Internally limited VIN Supply voltage (survival) -0.3 6 V VBIAS Supply voltage (survival) -0.3 6 V VEN Voltage (survival) -0.3 6 V VOUT Voltage (survival) -0.3 6 V IOUT Current (survival) Internally Limited TJ Junction temperature -40 150 C Tstg Storage temperature -65 150 C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, contact the TI Sales Office/ Distributors for availability and specifications. Device power dissipation must be de-rated based on device power dissipation (TD), ambient temperature (TA), and package junction to ambient thermal resistance (RJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See Application and Implementation for details. 6.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT 2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP38856 3 LP38856 SNVS336F - JUNE 2006 - REVISED AUGUST 2015 www.ti.com 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN NOM MAX VIN Supply voltage (VOUT + VDO) VBIAS Supply voltage 3 5.5 VEN Enable input voltage 0.0 VBIAS IOUT Output current 0 3 -40 125 Junction temperature range (1) (2) (2) UNIT VBIAS V mA/A C Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits (see Electrical Characteristics). Specifications do not apply when operating the device outside of its rated operating conditions. Device power dissipation must be de-rated based on device power dissipation (TD), ambient temperature (TA), and package junction to ambient thermal resistance (RJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See Application and Implementation for details. 6.4 Thermal Information LP38856 THERMAL METRIC (1) KTT (DDPAK/TO-263) NDH (TO-220) UNIT 5 PINS RJA Junction-to-ambient thermal resistance 41.8 32.0 C/W RJC(top) Junction-to-case (top) thermal resistance 45.0 43.8 C/W RJB Junction-to-board thermal resistance 24.8 18.6 C/W JT Junction-to-top characterization parameter 13.1 8.8 C/W JB Junction-to-board characterization parameter 23.8 18.0 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 2.4 1.2 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics Unless otherwise specified: VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, IOUT = 10 mA, CIN = COUT = 10 F, CBIAS = 1 F, VEN = VBIAS. Limits apply for TJ = 25C only unless otherwise specified. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. PARAMETER VOUT Output Voltage Tolerance MIN TYP MAX VOUT(NOM) + 1 V VIN VBIAS 3 V VBIAS 5.5 V, 10 mA IOUT 3 A TEST CONDITIONS -1% 0% +1% VOUT(NOM) + 1 V VIN VBIAS 3 V VBIAS 5.5 V, 10 mA IOUT 3 A TJ = -40C to 125C -3% VOUT(NOM) + 1V VIN VBIAS 3 V VBIAS 5.5 V, 10 mA IOUT 3.0A 0C TJ 125C -2% UNIT 3% 0% 2% VOUT/VIN Line regulation, VIN (1) VOUT(NOM) + 1 V VIN VBIAS 0.04 %/V VOUT/VBIAS Line regulation, VBIAS (1) 3 V VBIAS 5.5 V 0.10 %/V VOUT/IOUT Output voltage load regulation (2) 10 mA IOUT 3 A 0.2 IOUT = 3 A 240 VDO (1) (2) (3) 4 Dropout voltage, VIN - VOUT (3) IOUT = 3 A, TJ = -40C to 125C %/A 300 450 mV Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load. Dropout voltage is defined the as input to output voltage differential (VIN - VOUT) where the input voltage is low enough to cause the output voltage to drop no more than 2% from the nominal value Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP38856 LP38856 www.ti.com SNVS336F - JUNE 2006 - REVISED AUGUST 2015 Electrical Characteristics (continued) Unless otherwise specified: VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, IOUT = 10 mA, CIN = COUT = 10 F, CBIAS = 1 F, VEN = VBIAS. Limits apply for TJ = 25C only unless otherwise specified. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. PARAMETER TEST CONDITIONS MIN LP38856-0.8: 10 mA IOUT 3 A TYP MAX 7 8.5 LP38856-0.8: 10 mA IOUT 3 A TJ = -40C to 125C IGND(IN) Ground pin current drawn from VIN supply 9 LP38856-1.2: 10 mA IOUT 3 A 11 LP38856-1.2: 10 mA IOUT 3 A TJ = -40C to 125C 1 VEN 0.5 V, TJ = -40C to 125C 3 10 mA IOUT 3 A TJ = -40C to 125C Undervoltage lock-out threshold UVLO(HYS) Undervoltage lock-out hysteresis VEN 0.5 V 100 2.20 VBIAS rising until device is functional TJ = -40C to 125C 2 60 2.45 150 Output short-circuit current VIN = VOUT(NOM) + 1 V, VBIAS = 3 V VOUT = 0 V A mA A 2.70 2.9 50 ISC 170 200 VBIAS rising until device is functional VBIAS falling from UVLO threshold until device is non-functional mA 3.8 4.5 VEN 0.5 V, TJ = -40C to 125C UVLO 10 300 10 mA IOUT 3 A Ground pin current drawn from VBIAS supply 12 15 VEN 0.5 V IGND(BIAS) UNIT 300 V mV 350 6.2 A ENABLE PIN VEN = VBIAS IEN ENABLE pin current 0.01 VEN = 0 V, VBIAS = 5.5 V -19 VEN = 0 V, VBIAS = 5.5 V TJ = -40C to 125C -13 VEN rising until Output = ON 1 VEN rising until Output = ON TJ = -40C to 125C 0.9 VEN falling from VEN(ON) until Output = OFF 50 VEN falling from VEN(ON) until Output = OFF TJ = -40C to 125C 30 -30 -40 A -51 1.25 VEN(ON) Enable voltage threshold VEN(HYS) Enable voltage hysteresis tOFF Turn-OFF delay time RLOAD x COUT << tOFF 20 tON Turn-ON delay time RLOAD x COUT << tON 15 VIN = VOUT +1 V, = 120 Hz 80 VIN = VOUT + 1V, = 1 kHz 65 VBIAS = VOUT + 3 V, = 120 Hz 58 VBIAS = VOUT + 3 V, = 1 kHz 58 1.50 1.55 100 V 150 200 mV s AC PARAMETERS PSRR (VIN) Ripple rejection for VIN input voltage PSRR (VBIAS) Ripple rejection for VBIAS voltage Output noise density en Output noise voltage = 120 Hz 1 BW = 10 Hz - 100 kHz 150 BW = 300 Hz - 300 kHz 90 dB dB V/Hz V(RMS) THERMAL PARAMETERS TSD Thermal shutdown junction temperature TSD(HYS) Thermal shutdown hysteresis 160 C 10 Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP38856 5 LP38856 SNVS336F - JUNE 2006 - REVISED AUGUST 2015 www.ti.com 6.6 Typical Characteristics Unless otherwise specified: TJ = 25C, VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, IOUT = 10 mA, CIN = COUT = 10-F ceramic, CBIAS = 1-F ceramic, VEN = VBIAS. 6 Figure 1. VBIAS Ground Pin Current (IGND(BIAS)) vs VBIAS Figure 2. VBIAS Ground Pin Current (IGND(BIAS)) vs Temperature Figure 3. VIN Ground Pin Current (IGND(IN)) vs Temperature Figure 4. Load Regulation vs Temperature Figure 5. Dropout Voltage (VDO) vs Temperature Figure 6. Output Current Limit (ISC) vs Temperature Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP38856 LP38856 www.ti.com SNVS336F - JUNE 2006 - REVISED AUGUST 2015 Typical Characteristics (continued) Unless otherwise specified: TJ = 25C, VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, IOUT = 10 mA, CIN = COUT = 10-F ceramic, CBIAS = 1-F ceramic, VEN = VBIAS. Figure 7. VOUT vs Temperature Figure 8. UVLO Thresholds vs Temperature Figure 9. Enable Thresholds (VEN) vs Temperature Figure 10. Enable Pull-Down Current (IEN) vs Temperature Figure 11. Enable Pull-Up Resistor (REN) vs Temperature Figure 12. VIN Line Transient Response Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP38856 7 LP38856 SNVS336F - JUNE 2006 - REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) Unless otherwise specified: TJ = 25C, VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, IOUT = 10 mA, CIN = COUT = 10-F ceramic, CBIAS = 1-F ceramic, VEN = VBIAS. Figure 13. VBIAS Line Transient Response Figure 14. VBIAS Line Transient Response COUT = 100-F Ceramic Figure 15. Load Transient Response, COUT = 10-F Ceramic COUT = 100-F Ceramic Figure 16. Load Transient Response COUT = 100-F Tantalum Figure 17. Load Transient Response 8 Submit Documentation Feedback Figure 18. Load Transient Response Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP38856 LP38856 www.ti.com SNVS336F - JUNE 2006 - REVISED AUGUST 2015 Typical Characteristics (continued) Unless otherwise specified: TJ = 25C, VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, IOUT = 10 mA, CIN = COUT = 10-F ceramic, CBIAS = 1-F ceramic, VEN = VBIAS. COUT = 100-F Tantalum Figure 19. Load Transient Response Figure 20. VBIAS PSRR Figure 21. VIN PSRR Figure 22. Output Noise Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP38856 9 LP38856 SNVS336F - JUNE 2006 - REVISED AUGUST 2015 www.ti.com 7 Detailed Description 7.1 Overview The LP38556 is a fast-response, high-current, low-dropout regulator, available in output voltages 0.8 V and 1.2 V. This device is capable of delivering 3-A continuous load current. Standard regulator features, such as overcurrent and overtemperature protection, are also included. The LP38556 contains several features: * Low dropout voltage, typical 240 mV at 3-A load. * Low GND pin current, typical 10 mA at 3-A load. * A shutdown feature is available, allowing the regulator to consume only 1 A when EN pin is low. 7.2 Functional Block Diagram OUT IN LP38856-x.x BIAS Under-Voltage Lock-Out Thermal Shut Down rEN EN Enable 1.2V VREF ILIMIT GND 0.6V 7.3 Feature Description 7.3.1 Enable Operation The enable pin (EN) provides a mechanism to enable, or disable, the regulator output stage. The EN pin has an internal pullup, through a typical 180-k resistor, to VBIAS. If the EN pin is actively driven, pulling the EN pin above the VEN threshold of 1.25 V (typical) will turn the regulator output on, while pulling the EN pin below the VEN threshold will turn the regulator output off. There is approximately 100 mV of hysteresis built into the enable threshold provide noise immunity. If the enable function is not needed, the EN pin must be left open, or connected directly to VBIAS. If the EN pin is left open, stray capacitance on this pin must be minimized, otherwise the output turnon will be delayed while the stray capacitance is charged through the internal resistance (rEN). 7.3.2 Input Voltage The input voltage (VIN) is the high current external voltage rail that will be regulated down to a lower voltage, which is applied to the load. The input voltage must be at least VOUT + VDO, and no higher than whatever value is used for VBIAS. 10 Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP38856 LP38856 www.ti.com SNVS336F - JUNE 2006 - REVISED AUGUST 2015 Feature Description (continued) 7.3.3 Bias Voltage The bias voltage (VBIAS) is a low current external voltage rail required to bias the control circuitry and provide gate drive for the N-FET pass transistor. The bias voltage must be in the range of 3 V to 5.5 V to ensure proper operation of the device. 7.3.4 Undervoltage Lockout The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is below the undervoltage lock-out (UVLO) threshold of approximately 2.45 V. As the bias voltage rises above the UVLO threshold the device control circuitry become active. There is approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity. When the bias voltage is between the UVLO threshold and the minimum operating rating value of 3 V the device will be functional, but the operating parameters will not be within the specified limits. 7.3.5 Supply Sequencing There is no requirement for the order that VIN or VBIAS are applied or removed. However, the output voltage cannot be specified until both VIN and VBIAS are within the range of specified operating values. If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground. A Schottky diode is recommend for this diode clamp. 7.3.6 Reverse Voltage A reverse voltage condition will exist when the voltage at the OUT pin is higher than the voltage at the input pin. Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output voltage becomes reversed. The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass element is not driven, there will not be any reverse current flow through the pass element during a reverse voltage event. The gate of the pass element is not driven when VBIAS is below the UVLO threshold. When VBIAS is above the UVLO threshold the control circuitry is active and will attempt to regulate the output voltage. Because the input voltage is less than the output voltage, the control circuit will drive the gate of the pass element to the full VBIAS potential when the output voltage begins to fall. In this condition, reverse current will flow from the OUT pin to the IN pin, limited only by the RDS(ON) of the pass element and the output-to-input voltage differential. This condition is outside the specified operating range and must be avoided. 7.4 Device Functional Modes 7.4.1 Operation with 3 V VBIAS 5.5 V , VOUT(TARGET) + 0.3 V VIN VBIAS The device operates if the bias voltage is equal to, or exceeds, 3 V; input voltage is equal to, or exceeds, VOUT(TARGET) + 0.3 V. At bias voltages below the minimum VBIAS requirement, the device does not operate correctly, and output voltage may not reach target value. 7.4.2 Operation with VEN Control If the voltage on the EN pin is less than 1 V, the device is disabled. Raising VEN above 1.5 V initiates the start-up sequence of the device. Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP38856 11 LP38856 SNVS336F - JUNE 2006 - REVISED AUGUST 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LP38856 can provide 3-A output current with 240-mV dropout voltage (typical). The bias voltage must be in the range of 3 V to 5.5 V to ensure proper operation of the device. The input voltage must be at least VOUT + VDO, and no higher than whatever value is used for VBIAS. Minimal input and output capacitor are 10 F. The capacitor on the bias pin must be at least 1 F. 8.2 Typical Application LP38856-x.x VIN IN VOUT OUT CIN 10 PF Ceramic VBIAS BIAS CBIAS 1 PF VEN COUT 10 PF Ceramic EN GND GND GND Figure 23. LP38856 Typical Application 8.2.1 Design Requirements For LP38856 typical applications, use the parameters listed in Table 1 as the input parameters. Table 1. Design Parameters DESIGN PARAMETERS VALUE Bias voltage 3 V to 5.5 V Input voltage VOUT+0.3 V to VBIAS Output voltage 0.8 V or 1.2 V Output current 3 A (maximum) Bias capacitor 1 F (minimum) Input capacitor 10 F (minimum) Output capacitor 10 uF (minimum) 8.2.2 Detailed Design Procedure 8.2.2.1 External Capacitors To assure regulator stability, capacitors are required on the IN, OUT, and BIAS pins as shown in Figure 23. 8.2.2.1.1 Output Capacitor A minimum output capacitance of 10 F, ceramic, is required for stability. The amount of output capacitance can be increased without limit. The output capacitor must be located less than 1 cm from the output pin of the device and returned to the device ground pin with a clean analog ground. Only high quality ceramic types such as X5R or X7R should be used, as the Z5U and Y5F types do not provide sufficient capacitance over temperature. 12 Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP38856 LP38856 www.ti.com SNVS336F - JUNE 2006 - REVISED AUGUST 2015 Tantalum capacitors will also provide stable operation across the entire operating temperature range. However, the effects of ESR may provide variations in the output voltage during fast load transients. Using the minimum recommended 10 F ceramic capacitor at the output will allow unlimited capacitance, tantalum and/or aluminum, to be added in parallel. 8.2.2.1.2 Input Capacitor The input capacitor must be at least 10 F, but can be increased without limit. Its purpose is to provide a low source impedance for the regulator input. A ceramic capacitor, X5R or X7R, is recommended. Tantalum capacitors may also be used at the input pin. There is no specific ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytic capacitors can be used, but are not recommended as their ESR increases very quickly at cold temperatures. They are not recommended for any application where the ambient temperature falls below 0C. 8.2.2.1.3 Bias Capacitor The capacitor on the bias pin must be at least 1 F. It can be any good quality capacitor (ceramic is recommended). 8.2.2.2 Power Dissipation and Heatsinking A heat-sink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is the sum of three different points of dissipation in the device. The first part is the power that is dissipated in the NMOS pass element, and can be determined with the formula: PD(PASS) = (VIN - VOUT) x IOUT (1) The second part is the power that is dissipated in the bias and control circuitry, and can be determined with the formula: PD(BIAS) = VBIAS x IGND(BIAS) where * IGND(BIAS) is the portion of the operating ground current of the device that is related to VBIAS. (2) The third part is the power that is dissipated in portions of the output stage circuitry, and can be determined with the formula: PD(IN) = VIN x IGND(IN) where * IGND(IN) is the portion of the operating ground current of the device that is related to VIN. (3) The total power dissipation is then: PD = PD(PASS) + PD(BIAS) + PD(IN) (4) The maximum allowable junction temperature rise (TJ) depends on the maximum anticipated ambient temperature (TA(MAX)) for the application, and the maximum allowable operating junction temperature (TJ(MAX)): TJ = TJ(MAX) - TA(MAX) (5) The maximum allowable value for junction to ambient thermal resistance, RJA, can be calculated using the formula: RJA TJ / PD (6) The LP38856 is available in TO-220 and DDPAK/TO-263 packages. The thermal resistance in the application depends on amount of copper area or heat-sink, and on air flow. If the maximum allowable value of R JA calculated above is 32C/W for TO-220 package and 41C/W for DDPAK/TO-263 package no heat-sink is needed because the package alone can dissipate enough heat to satisfy these requirements. If the value needed for allowable RJA falls below these limits, a heat-sink is required. Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP38856 13 LP38856 SNVS336F - JUNE 2006 - REVISED AUGUST 2015 www.ti.com 8.2.3 Application Curves COUT = 10-F Ceramic Figure 24. VIN Line Transient Response Figure 25. Load Transient Response 9 Power Supply Recommendations The LP38856 device is designed to operate from an bias voltage supply range between 3 V and 5.5 V, and the input voltage in the range between VOUT + 0.3 V and VBIAS. Input supply must be well regulated. An input capacitor of at least 10 F is required. 14 Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP38856 LP38856 www.ti.com SNVS336F - JUNE 2006 - REVISED AUGUST 2015 10 Layout 10.1 Layout Guidelines Good layout practices will minimize voltage error and prevent instability which can result from ground loops. The input and output capacitors must be directly connected to the device pins with short traces that have no other current flowing in them (Kelvin connect). The best way to do this is to place the capacitors very near the device and make connections directly to the device pins via short traces on the top layer of the PCB. The regulator's ground pin must be connected through vias to the internal or backside ground plane so that the regulator has a single point ground. The external resistors which set the output voltage must also be located very near the device with all connections directly tied via short traces to the pins of the device (Kelvin connect). Do not connect the resistive divider to the load point or DC error will be induced. 10.2 Layout Example EN VIN IN CIN GND COUT OUT BIAS VOUT CBIAS Figure 26. LP38856 Layout Example Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP38856 15 LP38856 SNVS336F - JUNE 2006 - REVISED AUGUST 2015 www.ti.com 11 Device and Documentation Support 11.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 16 Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP38856 LP38856 www.ti.com SNVS336F - JUNE 2006 - REVISED AUGUST 2015 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2006-2015, Texas Instruments Incorporated Product Folder Links: LP38856 17 PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LP38856S-0.8/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38856S 0.8 LP38856S-1.2/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38856S 1.2 LP38856SX-1.2/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38856S 1.2 LP38856T-1.2/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP38856T 1.2 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device LP38856SX-1.2/NOPB Package Package Pins Type Drawing SPQ DDPAK/ TO-263 500 KTT 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 14.85 5.0 16.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP38856SX-1.2/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA NDH0005D www.ti.com MECHANICAL DATA KTT0005B TS5B (Rev D) BOTTOM SIDE OF PACKAGE www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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