Standard Products QCOTSTM UT7Q512 512K x 8 SRAM Data Sheet August, 2002 INTRODUCTION FEATURES 100ns (5 volt supply) maximum address access time Asynchronous operation for compatibility with industrystandard 512K x 8 SRAMs TTL compatible inputs and output levels, three-state bidirectional data bus Typical radiation performance - Total dose: 30krad(Si) - 30krad(Si) to 300krad(Si), depending on orbit, using Aeroflex UTMC patented shielded package The QCOTSTM UT7Q512 Quantified Commercial Off-theShelf product is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (E), an active LOW Output Enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected. Writing to the device is accomplished by taking the Chip Enable One (E) input LOW and the Write Enable (W) input LOW. Data on the eight I/O pins (DQ0 through DQ7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable One (E) and Output Enable (G) LOW while forcing Write Enable (W) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the eight I/ O pins. - SEL Immune >80 MeV-cm2/mg - LETTH(0.25) = 5MeV-cm2/mg - Saturated Cross Section (cm2) per bit, ~1.0E-7 - 1.5E-8 errors/bit-day, Adams 90% geosynchronous heavy ion Packaging options: - 32-lead ceramic flatpack (weight 2.5-2.6 grams) The eight input/output pins (DQ0 through DQ7) are placed in a high impedance state when the device is deselected (E, HIGH), the outputs are disabled (G HIGH), or during a write operation (E LOW and W LOW). Standard Microcircuit Drawing 5962-99606 - QML T and Q compliant Clk. Gen. Pre-Charge Circuit I/O Circuit Column Select A9 DQ 0 - DQ 7 Memory Array 1024 Rows 512x8 Columns Data Control A10 A11 CLK Gen. A12 A13 A14 A15 A16 A17 A18 A3 A4 A5 A6 A7 A8 Row Select A0 A1 A2 E W G Figure 1. UT7Q512 SRAM Block Diagram 1 PIN NAMES A18 A16 A14 A12 A7 A6 A5 A4 VDD VSS A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 DEVICE OPERATION A(18:0) Address DQ(7:0) Data Input/Output E Chip Enable W Write Enable G Output Enable VDD Power VSS Ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 The UT7Q512 has three control inputs called Enable 1 (E), Write Enable (W), and Output Enable (G); 19 address inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). The E Device Enable controls device selection, active, and standby modes. Asserting E enables the device, causes IDD to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. W controls read and write operations. During a read cycle, G must be asserted to enable the outputs. Table 1. Device Operation Truth Table NC A15 A17 W A13 A8 A9 A11 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 W E I/O Mode Mode X1 X 1 3-state Standby X 0 0 Data in Write 1 1 0 3-state Read2 0 1 0 Data out Read Notes: 1. "X" is defined as a "don't care" condition. 2. Device active; outputs disabled. VDD READ CYCLE G A10 E DQ7 DQ6 DQ5 DQ4 NC A combination of W greater than VIH (min), G and E less than VIL (max) defines a read cycle. Read access time is measured from the latter of Device Enable, Output Enable, or valid address to valid data output. SRAM read Cycle 1, the Address Access in figure 3a, is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as Device Enable and Output Enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV). Figure 2a. UT7Q512 100ns SRAM Shielded Package Pinout (36) A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS G VDD SRAM read Cycle 2, the Chip Enable-Controlled Access in figure 3b, is initiated by E going active while G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQ(7:0). A15 A17 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 SRAM read Cycle 3, the Output Enable-Controlled Access in figure 3c, is initiated by G going active while E is asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied. Figure 2b. UT7Q512 100ns SRAM Package Pinout (32) 2 WRITE CYCLE A combination of W less than VIL(max) and E less than VIL(max) defines a write cycle. The state of G is a "don't care" for a write cycle. The outputs are placed in the high-impedance state when either G is greater than VIH(min), or when W is less than VIL(max). Write Cycle 1, the Write Enable-Controlled Access in figure 4a, is defined by a write terminated by W going high, with E still active. The write pulse width is defined by tWLWH when the write is initiated by W, and by tETWH when the write is initiated by E. Unless the outputs have been previously placed in the highimpedance state by G, the user must wait tWLQZ before applying data to the nine bidirectional pins DQ(7:0) to avoid bus contention. Write Cycle 2, the Chip Enable-Controlled Access in figure 4b, is defined by a write terminated by the latter of E going inactive. The write pulse width is defined by tWLEF when the write is initiated by W, and by tETEF when the write is initiated by the E going active. For the W initiated write, unless the outputs have been previously placed in the high-impedance state 3 by G, the user must wait tWLQZ before applying data to the eight bidirectional pins DQ(7:0) to avoid bus contention. TYPICAL RADIATION HARDNESS Table 2. Typical Radiation Hardness Design Specifications1 Total Dose 30 krad(Si) nominal Heavy Ion Error Rate2 1.5E-7 Errors/Bit-Day Notes: 1. The SRAM will not latchup during radiation exposure under recommended operating conditions. 2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of Aluminum. ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS) SYMBOL PARAMETER LIMITS VDD DC supply voltage -0.5 to 7.0V VI/O Voltage on any pin -0.5 to 7.0V TSTG Storage temperature -65 to +150C PD Maximum power dissipation TJ Maximum junction temperature2 +150C Thermal resistance, junction-to-case3 10C/W DC input current 10 mA JC II 1.0W Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175C during burn-in and steady-static life. 3. Test per MIL-STD-883, Method 1012. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS VDD Positive supply voltage 4.5 to 5.5V TC Case temperature range -55 to +125C VIN DC input voltage 0V to VDD 4 DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (VDD = 5.0V10%) (-55C to +125C) SYMBOL PARAMETER CONDITION MIN MAX VIH High-level input voltage VIL Low-level input voltage VOL Low-level output voltage IOL = 2.1mA,VDD =4.5V VOH High-level output voltage IOH = -1mA,VDD =4.5V CIN1 Input capacitance = 1MHz @ 0V 10 pF CIO1 Bidirectional I/O capacitance = 1MHz @ 0V 10 pF IIN Input leakage current VSS < VIN < VDD , VDD = VDD (max) -2 2 A IOZ Three-state output leakage current 0V < VO < VDD VDD = VDD (max) G = VDD (max) -2 2 A Short-circuit output current 0V <VO <VDD -80 80 mA IDD(OP) Supply current operating @ 1MHz Inputs: VIL = VSS + 0.8V, VIH = 2.2V IOUT = 0mA VDD = VDD (max) 50 mA IDD1(OP) Supply current operating @10MHz Inputs: VIL = VSS + 0.8V, VIH = 2.2V IOUT = 0mA VDD = VDD (max) 100 mA IDD2(SB) Nominal standby supply current @0MHz Inputs: VIL = VSS IOUT = 0mA E = VDD - 0.5 VDD = VDD (max) VIH = VDD - 0.5V -55C and 25C 35 A +125C 1 mA IOS2, 3 2.2 UNIT .8 V 0.4 V 2.4 Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second. 5 V V AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)* (VDD = 5.0V10%) (-55C to +125C) SYMBOL PARAMETER MIN MAX tAVAV1 Read cycle time tAVQV Read access time tAXQX2 Output hold time 10 ns tGLQX2 G-controlled Output Enable time 5 ns tGLQV G-controlled Output Enable time (Read Cycle 3) 50 ns tGHQZ2 G-controlled output three-state time 30 ns tETQX2,3 E-controlled Output Enable time tETQV3 tEFQZ1,2,4 100 UNIT ns 100 10 ns ns E-controlled access time 100 ns E-controlled output three-state time 30 ns Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Functional test. 2. Three-state is defined as a 500mV change from steady-state output voltage (see Figure 3). 3. The ET (enable true) notation refers to the falling edge of E. SEU immunity does not affect the read parameters. 4. The EF (enable false) notation refers to the rising edge of E. SEU immunity does not affect the read parameters. High Z to Active Levels Active to High Z Levels VH - 500mV VLOAD + 500mV } VLOAD { { } VLOAD - 500mV VL + 500mV Figure 3. 5-Volt SRAM Loading tAVAV A(18:0) DQ(7:0) Previous Valid Data Valid Data tAVQV tAXQX Assumptions: 1. E and G < VIL (max) and W > VIH (min) Figure 4a. SRAM Read Cycle 1: Address Access A(18:0) E tETQV tEFQZ DQ(7:0) tETQX DATA VALID Assumptions: 1. G < VIL (max) and W > VIH (min) Figure 4b. SRAM Read Cycle 2: Chip Enable - Controlled Access tAVQV A(18:0) G tGHQZ tGLQX DATA VALID DQ(7:0) Assumptions: 1. E< VIL (max) and W > VIH (min) tGLQV Figure 4c. SRAM Read Cycle 3: Output Enable - Controlled Access AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)* (VDD = 5.0V10%) (-55C to +125C) SYMBOL PARAMETER MIN MAX UNIT tAVAV1 Write cycle time 100 ns tETWH Device Enable to end of write 80 ns tAVET Address setup time for write (E - controlled) 0 ns tAVWL Address setup time for write (W - controlled) 0 ns tWLWH Write pulse width 60 ns tWHAX Address hold time for write (W - controlled) 0 ns tEFAX Address hold time for Device Enable (E - controlled) 0 ns tWLQZ2 W - controlled three-state time tWHQX2 W - controlled Output Enable time 5 ns tETEF Device Enable pulse width (E - controlled) 80 ns tDVWH Data setup time 40 ns tWHDX Data hold time 0 ns tWLEF Device Enable controlled write pulse width 80 ns tDVEF Data setup time 40 ns tEFDX Data hold time 0 ns tAVWH Address valid to end of write 80 ns tWHWL1 Write disable time 5 ns Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019 1. Functional test performed with outputs disabled (G high). 2. Three-state is defined as 500mV change from steady-state output voltage (see Figure 3). 30 ns A(18:0) tAVAV2 E tAVWH tETWH tWHWL W tAVWL tWLWH tWHAX Q(7:0) tWLQZ D(7:0) tWHQX APPLIED DATA Assumptions: 1. G < VIL (max). If G > VIH (min) then Q(7:0) will be in three-state for the entire cycle. 2. G high for tAVAV cycle. tDVWH tWHDX Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access tAVAV3 A(18:0) tETEF tAVET tEFAX E or tAVET E tETEF tEFAX tWLEF W APPLIED DATA D(7:0) tWLQZ tDVEF Q(7:0) tEFDX Assumptions & Notes: 1. G < VIL (max). If G > VIH (min) then Q(7:0) will be in three-state for the entire cycle. 2. Either E scenario above can occur. 3. G high for tAVAV cycle. Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access CMOS VDD-0.05V 90% 90% 300 ohms 10% VLOAD = 1.75V 10% 0.5V < 5ns < 5ns 50pF Input Pulses Notes: 1. 50pF including scope probe and test socket capacitance. 2. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = VDD/2). Figure 6. AC Test Loads and Input Waveforms 10 DATA RETENTION MODE VDD 50% 50% VDR > 4.5V tR tEFR E Figure 7. Low VDD Data Retention Waveform (100ns) DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) (TC = 25C, 1 Sec Data Retention Test) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT VDR VDD for data retention 4.5 -- V IDDR 1 Data retention current -- .4 mA tEFR1,2 Chip deselect to data retention time 0 ns tAVAV ns tR1,2 Operation recovery time Notes: 1. E = VSS, all other inputs = VDR or VSS. 2. Not guaranteed or tested. DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) (TC = 25C, 10 Second Data Retention Test) SYMBOL VDD1 tEFR2, 3 tR2, 3 PARAMETER VDD for data retention Chip select to data retention time Operation recovery time Notes: 1. Performed at VDD (min) and VDD (max). 2. E = VSS, all other inputs = VDR or VSS. 3. Not guaranteed or tested. MINIMUM MAXIMUM UNIT 4.5 5.5 V 0 ns tAVAV ns PACKAGING 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance to MIL-PRF-38535. 4. Lead position and coplanarity are not measured. 5. ID mark is vendor option. 6. With solder increase maximum by 0.003". 7. Weight 2.5-2.6 grams. Figure 8. 32-pin Ceramic FLATPACK package 12 ORDERING INFORMATION 512K x 8 SRAM: UT7Q512 - * * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (P) = Prototype flow (W) = Extended Industrial Temperature Range Flow (-40oC to +125oC) Package Type: (U) = 32-lead ceramic flatpack package (bottom brazed) - = 100ns access time, 5V operation Aeroflex UTMC Core Part Number Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55C, room temp, and +125C. Radiation neither tested nor guaranteed. 5. Extended Industrial Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -40C to +125C. Radiation neither tested nor guaranteed. Gold Lead Finish Only. 13 512K x 8 SRAM: SMD 5962 - 99606 ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (U) = 32-lead ceramic flatpack package (bottom-brazed) Class Designator: (T) = QML Class T (Q) = QML Class Q Device Type 01 = 100ns access time, 5.0 volt operation, Mil-Temp 02 = 100ns access time, 5.0 volt operation, Extended Industrial Temp (-40oC to +125oC) Drawing Number: 99606 Total Dose (-) = none (D) = 1E4 (10krad(Si)) (P) = 3E4 (30krad(Si)), Contact Factory Federal Stock Class Designator: No Options Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3.Total dose radiation must be specified when ordering. 14 NOTES COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com Aeroflex UTMC Microelectronic Systems Inc. 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