SLLS236G − O C TOBER 1996 − REVISED FEBRUARY 2009
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DIntegrated Transient Voltage Suppression
DESD Protection for Bus Terminals Exceeds:
±30 kV IEC 61000-4-2, Contact Discharge
±15 kV IEC 61000-4-2, Air-Gap Discharge
±15 kV EIA/JEDEC Human Body Model
DCircuit Damage Protection of 400-W Peak
(Typical) Per IEC 61000-4-5
DControlled Driver Output-Voltage Slew
Rates Allow Longer Cable Stub Lengths
D250-kbps in Electrically Noisy
Environments
DOpen-Circuit Fail-Safe Receiver Design
D1/4 Unit Load Allows for 128 Devices
Connected on Bus
DThermal Shutdown Protection
DPower-Up/-Down Glitch Protection
DEach Transceiver Meets or Exceeds the
Requirements of TIA/EIA-485 (RS-485) and
ISO/IEC 8482:1993(E) Standards
DLow Disabled Supply Current 300 µA Max
DPin Compatible With SN75176
DApplications:
− Industrial Networks
− Utility Meters
− Motor Control
description
The SN75LBC184 and SN65LBC184 are differ-
ential data line transceivers in the trade-standard
footprint of the SN75176 with built-in protection
against high-energy noise transients. This feature
provides a substantial increase in reliability for
better immunity to noise transients coupled to the
data cable over most existing devices. Use of
these circuits provides a reliable low-cost
direct-coupled (with no isolation transformer) data
line interface without requiring any external
components.
The SN75LBC184 and SN65LBC184 can with-
stand overvoltage transients of 400-W peak
(typical). The conventional combination wave
called out in IEC 61000-4-5 simulates the
overvoltage transient and models a unidirectional
surge caused by overvoltages from switching and
secondary lightning transients.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
R
RE
DE
D
VCC
B
A
GND
functional logic diagram (positive logic)
DE
RE
R
6
7
3
1
2
B
ABus
D4
Figure 1. Surge Waveform — Combination Wave
1.2 µs50 µs
V
t
± VP
± 1/2 VP
SN65LBC184D (Marked as 6LB184)
SN75LBC184D (Marked as 7LB184)
SN65LBC184P (Marked as 65LBC184)
SN75LBC184P (Marked as 75LBC184)
(TOP VIEW)
!"#$ % &'!!($ #% )'*+&#$ ,#$(-
!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($%
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(
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Copyright 2009, Texas Instruments Incorporated
SLLS236G − O C TOBER 1996 − REVISED FEBRUARY 2009
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
A biexponential function defined by separate rise and fall times for voltage and current simulates the
combination wave. The standard 1.2 µs/50 µs combination waveform is shown in Figure 1 and in the test
description in Figure 15.
The device also includes additional desirable features for party-line data buses in electrically noisy environment
applications including industrial process control. The dif ferential-driver design incorporates slew-rate-controlled
outputs su fficient to transmit data up to 250 kbps. Slew-rate control allows longer unterminated cable runs and
longer stub lengths from the main backbone than possible with uncontrolled and faster voltage transitions. A
unique receiver design provides a fail-safe output of a high level when the inputs are left floating (open circuit).
The SN75LBC184 and SN65LBC184 receiver also includes a high input resistance equivalent to one-fourth unit
load allowing connection of up to 128 similar devices on the bus.
The SN75LBC184 is characterized for operation from 0°C to 70°C. The SN65LBC184 is characterized from
−40°C to 85°C.
schematic of inputs and outputs
A Port
Only
12 µA
Nominal
A or B
I/O
B Port
Only
12 µA
Nominal
72 kΩ
16 kΩ
16 kΩ
V
CC
SLLS236G − O C TOBER 1996 − REVISED FEBRUARY 2009
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DRIVER FUNCTION TABLE
INPUT ENABLE OUTPUTS
D DE A B
H H H L
L H L H
X L Z Z
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
RECEIVER FUNCTION TABLE
DIFFERENTIAL INPUTS ENABLE OUTPUT
A − B RE R
VID ≥ 0.2 V L H
−0.2 V < VID < 0.2 V L ?
VID ≤ −0.2 V L L
X H Z
Open L H
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
AVAILABLE OPTIONS
PACKAGE
TAPLASTIC SMALL-OUTLINE†
(JEDEC MS-012) PLASTIC DUAL-IN-LINE PACKAGE
(JEDEC MS-001)
0°C to 70°C SN75LBC184D SN75LBC184P
−40°C to 85°C SN65LBC184D SN65LBC184P
†Add R suffix for taped and reel.
logic symbol†
RE
DE
1
1
2
B
A
7
6
EN2
EN1
R
D
1
4
2
3
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SLLS236G − O C TOBER 1996 − REVISED FEBRUARY 2009
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free−air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous voltage range at any bus terminal −15 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data input/output voltage −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver output current, IO ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge: Contact discharge (IEC61000-4-2) A, B, GND (see Note 2) ±30 kV. . . . . . . . . . . . . .
Air discharge (IEC61000-4-2) A, B, GND (see Note 2) ±15 kV. . . . . . . . . . . . . .
Human body model (see Note 3) A, B, GND (see Note 2) ±15 kV. . . . . . . . . . . . . .
All pins ±3 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All terminals (Class 3A) (see Note 2) ±8 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All terminals (Class 3B) (see Note 2) ±200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Fast Transient/Burst (IEC 61000−4−4) A, B, GND ±4 kV. . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation (see Note 4) Internally Limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
2. GND and bus terminal ESD protection is beyond readily available test equipment capabilities for IEC 61000-4-2, EIA/JEDEC test
method A114-A and MIL-STD-883C method 3015. Ratings listed are limits of test equipment; device performance exceeds these
limits.
3. Tested in accordance with JEDEC Standard 22, Test Method A114-A and IEC 60749−26.
4. The driver shuts down at a junction temperature of approximately 160°C. To operate below this temperature, see the Dissipation
Rating Table.
DISSIPATION RATING TABLE
PACKAGE
TA
≤
25
°
C
DERATING FACTOR
TA = 70
_
C
TA = 85
_
C
PACKAGE
TA ≤ 25 C
POWER RATING
DERATING FACTOR
ABOVE T
A
= 25°C
TA = 70 C
POWER RATING
TA = 85 C
POWER RATING
D725 mW 5.8 mW/°C464 mW 377 mW
P1150 mW 9.2 mW/°C736 mW 598 mW
recommended operating conditions
MIN‡TYP MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
Voltage at any bus terminal (separately or common mode), VI or VIC −7 12 V
High-level input voltage, VIH D, DE, and RE 2 V
Low-level input voltage, VIL D, DE, and RE 0.8 V
Differential input voltage, |VID| 12 V
High-level output current, IOH
Driver −60 mA
High-level output current, IOH Receiver −8 mA
Low-level output current, IOL
Driver 60
mA
Low-level output current, IOL Receiver 4 mA
Operating free-air temperature, TA
SN75LBC184 0 70 °C
Operating free-air temperature, T
ASN65LBC184 −40 85 °C
‡The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet.
SLLS236G − O C TOBER 1996 − REVISED FEBRUARY 2009
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DRIVER SECTION
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER ALTERNATE
SYMBOLS TEST CONDITIONS MIN TYP†MAX UNIT
DE = RE = 5 V, No Load 12 25 mA
ICC Supply current NA DE = 0 V, RE = 5 V,
No Load 175 300 µA
IIH High-level input current (D, DE, RE) NA VI = 2.4 V 50 µA
IIL Low-level input current (D, DE, RE) NA VI = 0.4 V −50 µA
Short-circuit output current
VO = −7 V −250 −120
IOS Short-circuit output current
(see Note 5)
NA VO = VCC 250 mA
IOS
(see Note 5)
NA
VO = 12 V 250
mA
IOZ High-impedance output current NA See Receiver IImA
VOOutput voltage Voa, Vob IO = 0 0 VCC V
VOC(PP) Peak-to-peak change in common-
mode output voltage during state
transitions NA See Figures 5 and 6 0.8 V
VOC Common-mode output voltage |Vos|See Figure 4 1 3 V
|∆VOC(SS)|Magnitude of change, common-
mode steady-state output voltage |Vos − Vos|See Figure 5 0.1 V
|VOD|
Magnitude of differential output
Vo
IO = 0 1.5 6 V
|VOD|
Magnitude of differential output
voltage |VA − VB|VoRL = 54 Ω, See Figure 4 1.5 V
∆|VOD|Change in differential voltage mag-
nitude between logic states ||Vt| − |Vt|| RL = 54 Ω0.1 V
†All typical values are measured with TA = 25°C and VCC = 5 V.
NOTE 5: This parameter is measured with only one output being driven at a time.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(DH) Differential output delay time, low-to-high-level output 1.3 µs
td(DL) Differential-output delay time, high-to-low-level output 1.3 µs
tPLH Propagation delay time, low-to-high-level output
RL = 54 Ω,
CL = 50 pF,
0.5 1.3 µs
tPHL Propagation delay time, high-to-low-level output RL = 54 Ω,
See Figure 5
CL = 50 pF, 0.5 1.3 µs
tsk(p) Pulse skew (|td(DH) − td(DL)|)
See Figure 5
75 150 ns
trRise time, single ended 0.25 1.2 µs
tfFall time, single ended 0.25 1.2 µs
tPZH Output enable time to high level RL = 110 Ω, See Figure 2 3.5 µs
tPZL Output enable time to low level RL = 110 Ω, See Figure 3 3.5 µs
tPHZ Output disable time from high level RL = 110 Ω, See Figure 2 2µs
tPLZ Output disable time from low level RL = 110 Ω, See Figure 3 2µs
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6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RECEIVER SECTION
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
DE = RE = 0 V, No Load 3.9 mA
ICC Supply current (total package) RE = 5 V,
No Load DE = 0 V, 300 µA
VI = 12 V 250
II
Input current
Other input = 0 V
VI = 12 V, VCC = 0 250
A
IIInput current Other input = 0 V VI = −7 V −200 µA
VI = −7 V, VCC = 0 −200
IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ±100 µA
Vhys Input hysteresis voltage 70 mV
VIT+ Positive-going input threshold voltage 200 mV
VIT− Negative-going input threshold voltage −200 mV
VOH High-level output voltage IOH = −8 mA Figure 7 2.8 V
VOL Low-level output voltage IOL = 4 mA Figure 7 0.4 V
†All typical values are at VCC = 5 V, TA = 25°C.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output
CL = 50 pF,
See Figure 7
150 ns
tPHL Propagation delay time, high-to-low-level output CL = 50 pF, See Figure 7 150 ns
tsk(p) Pulse skew (|tpHL − tpLH|) 50 ns
trRise time, single ended
See Figure 7
20 ns
tfFall time, single ended See Figure 7 20 ns
tPZH Output enable time to high level 100 ns
tPZL Output enable time to low level
See Figure 8
100 ns
tPHZ Output disable time from high level
See Figure 8
100 ns
tPLZ Output disable time from low level 100 ns
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PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
tPHZ
1.5 V
2.3 V
0.5 V
0 V
3 V
tPZH
Output
Input 1.5 V
S1
0 or 3 V
Output
CL = 50 pF
(see Note B)
TEST CIRCUIT
50 Ω
VOH
Voff ≈ 0 V
RL = 110 Ω
Generator
(see Note A)
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 2. Driver tPZH and tPHZ Test Circuit and Voltage Waveforms
VOLTAGE WAVEFORMS
5 V
VOL
0.5 V
tPZL
3 V
0 V
tPLZ
2.3 V
1.5 V
Output
Input
TEST CIRCUIT
Output
RL = 110 Ω
5 V
S1
CL = 50 pF
(see Note B)
50 Ω
0 or 3 V
Generator
(see Note A)
1.5 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 3. Driver tPZL and tPLZ Test Circuit and Voltage Waveforms
IO(A)
A
B
IO(B)
CLCL
VOD
VO(B)
VOC
27 Ω
27 ΩVO(A)
D
II
Input Output
NOTES: A. Resistance values are in ohms and are 1% tolerance.
B. CL includes probe and jig capacitance.
Figure 4. Driver Test Circuit, Voltage, and Current Definitions
SLLS236G − O C TOBER 1996 − REVISED FEBRUARY 2009
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% 50%
90% 90%
50% 50%
10% 10%
90%90% 50% 50%
10%
10%
3 V
0 V
∼ 3.5 V
∼ 2.3 V
∼ 1 V
∼ 3.5 V
∼ 2.3 V
∼ 1 V
∼ 2.5 V
0 V
∼ −2.5 V
Input
VO(A)
VO(B)
VOD
tPLH tPHL
trtf
tPHL tPLH
trtf
td(DH) td(DL)
VOC(PP)
∆VOC(SS)
VOC
Figure 5. Driver Timing, Voltage and Current Waveforms
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PARAMETER MEASUREMENT INFORMATION
A
B
CLCL
VOD
VOC
27 Ω
27 Ω
D
Inputs
Output
DE
3 V
0 V
3 V
0 V
DE
D
Inputs
VOC(PP)
Output
NOTES: A. Resistance values are in ohms and are 1% tolerance.
B. CL includes probe and jig capacitance (± 10%).
Figure 6. Driver VOC(PP) Test Circuit and Waveforms
R
50 pF
(see Note A)
VO
A
Input Output
3 V
0 V
Inputs
Output
IO
VID
1.5 V
B
RE
VI
I
I
tPLH tPHL
t
r
t
f
1.5 V
VOH
VOL
50%
90% 10%
50%
90%
10%
50%
NOTE A: This value includes probe and jig capacitance (± 10%).
Figure 7. Receiver tPLH and tPHL Test Circuit and Voltage Waveforms
SLLS236G − O C TOBER 1996 − REVISED FEBRUARY 2009
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
Inputs
Output
tPHZ tPZH
VOH
∼ 2.5 V
0.5 V
R
50 pF
(see Note A)
VO
A
Input
B
RE
620 Ω
620 Ω
5 V
0 V or 3 V
1.5 V
0.5 V
RE
VO
3 V
0 V
tPLZ tPZL
VOL
∼ 2.5 V
0.5 V
1.5 V
0.5 V
3 V
0 V
A
NOTE A: This value includes probe and jig capacitance (± 10%).
Figure 8. Receiver tPZL, tPLZ, tPZH, and tPHZ Test Circuit and Voltage Waveforms
SLLS236G − O C TOBER 1996 − REVISED FEBRUARY 2009
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TYPICAL CHARACTERISTICS
1.0
1.5
2.0
2.5
3.0
−40 −20 0 20 40 60 80
Figure 9
TA − Free-Air Temperature − °C
RL = 54 Ω
VOD − Driver Differential Output Voltage − V
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VCC = 4.75 V
VCC = 5 V
VCC = 5.25 V
TA − Free-Air Temperature − °C
640
660
680
700
720
740
760
780
800
−40 −20 0 20 40 60 80
tpd − Driver Propagation Delay Time − ns
DRIVER PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
tPLH
tPHL
Figure 10
300
400
500
600
700
800
900
−40 −20 0 20 40 60 80
Figure 11
TA − Free-Air Temperature − °C
t
t
− Driver Transition T ime − ns
DRIVER TRANSITION TIME
vs
FREE-AIR TEMPERATURE
tf
tr
IO − Output Current − mA
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0 102030405060708090100
VOD − Differential Output Voltage − V
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VCC = 5.5 V
VCC = 5 V
VCC = 4.5 V
Figure 12
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12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
VI − Input Voltage − V
−0.20
−0.15
−0.10
−0.05
−0.00
0.05
0.10
0.15
0.20
0.25
−10 −5 0 5 10 15
I(I) − Receiver Input Current − mA
RECEIVER INPUT CURRENT
vs
INPUT VOLTAGE
A, B (VCC = 0 V)
A (VCC = 5 V)
B (VCC = 5 V)
Figure 13
APPLICATION INFORMATION
Up to 128
Transceivers
SN65LBC184
SN75LBC184 SN65LBC184
SN75LBC184
RTRT
NOTE A: The line should be terminated at both ends in its characteristic impedance (R T = ZO). Stub lengths off the main line should be kept
as short as possible.
Figure 14. Typical Application Circuit
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APPLICATION INFORMATION
’LBC184 test description
The ’LBC184 is tested against the IEC 61000−4−5 recommended transient identified as the combination wave.
The combination wave provides a 1.2-/50-µs open-circuit voltage waveform and a 8-/20-µs short-circuit current
waveform shown in Figure 15. The testing is performed with a combination/hybrid pulse generator with an
effective output impedance of 2 Ω. The setup for the overvoltage stress is shown in Figure 16 with all testing
performed with power applied to the ’LBC184 circuit.
NOTE
High voltage transient testing is done on a sampling basis.
VI(peak) II(peak)
0.5 VP0.5 IP
1.2 µs50 µs20 µs
8 µs
tt
Figure 15. Short-Circuit Current Waveforms
The ’LBC184 is tested and evaluated for both maximum (single pulse) as well as life test (multiple pulse)
capabilities. The ’LBC184 is evaluated against transients of both positive and negative polarity and all testing
is performed with the worst-case transient polarity. Transient pulses are applied to the bus pins (A & B) across
ground as shown in Figure 16.
SN75LBC184
Key Tech
1.2/50 − 8/20
Combination Pulse
Generator
2-Ω Internal Impedance
7
5
IP
41.9 Ω
3 ΩImpedance Matching
and Wave Shaping
VP
High
Low
GND
B/A
Figure 16. Overvoltage-Stress Test Circuit
An example waveform as seen by the ’LBC184 is shown in Figure 17. The bottom trace is current, the middle
trace shows the clamping voltage of the device and the top trace is power as calculated from the voltage and
current waveforms. This example shows a peak clamping voltage of 33.6 V and peak current of 16 A, thus
yielding an absorbed peak power of 538 W.
NOTE
A circuit reset may be required to ensure normal data communications following a transient noise
pulse of greater than 250 W peak.
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14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Power
Clamping Voltage
Input Current
0204060
t − 20 µs/Div
538 W Peak
33.6 V Peak,
VI(peak)
16 A Peak,
II(peak)
0
0
0
80 100 120 140 160 180
Figure 17. Typical Surge Waveform Measured At Terminals 5 and 7
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LBC184D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC184DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC184DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC184DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC184P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN65LBC184PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75LBC184D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC184DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC184DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC184DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC184P ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75LBC184PE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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PACKAGE OPTION ADDENDUM
www.ti.com 12-Feb-2009
Addendum-Page 1
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 12-Feb-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LBC184DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75LBC184DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Feb-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LBC184DR SOIC D 8 2500 340.5 338.1 20.6
SN75LBC184DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Feb-2009
Pack Materials-Page 2
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