SiT5
157
60 MHz to
220 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Description
The SiT5157 is a ±0.5 ppm to ±2.5 ppm MEMS Super-TCXO
that is engineered for best dynamic performance. It is ideal
for high reliability telecom, wireless and networking,
industrial, precision GNSS and audio/video applications.
Leveraging SiTime’s unique DualMEMS™ temperature
sensing and TurboCompensation™ technologies, the
SiT5157 delivers the best dynamic performance for timing
stability in the presence of environmental stressors such as
air flow, temperature perturbation, vibration, shock, and
electromagnetic interference. This device also integrates
multiple on-chip regulators to filter power supply noise,
eliminating the need for a dedicated external LDO.
The SiT5157 offers three device configurations that can be
ordered using Ordering Codes for:
The SiT5157 can be factory programmed for any
combination of frequency, stability, voltage, and pull range.
Programmability enables designers to optimize clock
configurations while eliminating long lead times and
customization costs associated with quartz devices where
each frequency is custom built.
Refer to Manufacturing Guideline for proper reflow profile
and PCB cleaning recommendations for best performance.
Features
Output 60–189 MHz, and 208–220 MHz, in 1 Hz steps
Factory programmable options for short lead time
Best dynamic stability under airflow, thermal shock
±0.5 ppm stability across temperature
±15 ppb/°C typical frequency slope (ΔF/ΔT)
-40°C to +105°C operating temperature
No activity dips or micro jumps
Resistant to shock, vibration and board bending
On-chip regulators eliminate the need for external LDOs
Digital frequency pulling (DCTCXO) via I2C
Digital control of output frequency and pull range
Up to ±3200 ppm pull range
Frequency pull resolution down to 5 ppt
2.5 V, 2.8 V, 3.0 V and 3.3 V supply voltage
LVCMOS output
RoHS and REACH compliant,
Pb-free, Halogen-free, Antimony-free
Applications
Precision GNSS systems
Microwave backhaul
Network routers and switches
Professional audio and video equipment
Storage and servers
Test and measurement
Block Diagram
Figure 1. SiT5157 Block Diagram
5.0 mm x 3.2 mm Package Pinout
OE / VC / NC 1
2
3
456
7
8
910
SCL / NC
NC
GND
NC
NC
VDD
CLK
A0 / NC
SDA / NC
Figure 2. Pin Assignments (Top view)
(Refer to Table 11 for Pin Descriptions)
Rev 1.05
May 29, 2020
www.sitime.com
SiT5157
60 MHz to 220 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Rev 1.05
Page 2 of 34
www.sitime.com
Ordering Information
The part number guide illustrated below is for reference only, in which boxes identify order codes having more than one option.
To customize and build an exact part number, use the SiTime Part Number Generator. To validate the part number, use the
SiTime Part Number Decoder.
Frequency Stability
"K": for
±
0.5 ppm
"A": for
±1
.0 ppm
"D": for
±2
.5 ppm
Part Family
Silicon Revision Letter
Pull Range
– DCTCXO mode only
"T":
±
6.25 ppm
"R":
±
10 ppm
"Q":
±
12.5 ppm
"M":
±
25 ppm
"B":
±
50 ppm
"C":
±
80 ppm
"E":
±
100 ppm
"F":
±
125 ppm
"G": ±150 ppm
"H": ±200 ppm
"X": ±400 ppm
"L": ±600 ppm
"Y": ±800 ppm
"S": ±1200 ppm
"Z": ±1600 ppm
"U": ±3200 ppm
Supply Voltage
"25": 2.5 V
±
10%
"28": 2.8 V
±
10%
"30": 3.0 V
±
10%
"33": 3.3 V
±
10%
Pin 1 Function – DCTCXO mode only
"I": Output Enable
"J": No Connect, software OE control
Temperature Range
"I": Industrial, -40 to 85
°C
"C": Extended Commercial, -20 to 70
°C
"E": Extended Industrial, -40 to 105
°C
Package Size "F": 5.0 mm x 3.2 mm
Pin 1 Function – TCXO mode only
"E": Output Enable
"N": No Connect
I
2
C Address Mode
– DCTCXO mode only
“0”, “1”, “2”, “3”, “4”, “5”, “6”, “7”, “8”, “9”, “A”, “B”,
“C”, “D”, “E”, “F”: Order code representing hex
value of I
2
C address. When the I
2
C address is
factory programmed using this code, pin A0 is no
connect (NC).
“G”: I
2
C pin addressable mode. Address is set by
the logic on A0 pin.
Packaging
"T": 12 mm Tape & Reel, 3 ku reel
"Y": 12 mm Tape & Reel, 1 ku reel
“X”: 12 mm Tape & Reel, 250 u reel
(blank): bulk
[2]
Frequency
60.000001 MHz to 189.000000 MHz
200.000000 MHz to 220.000000 MHz
Output Waveform "-" : LVCMOS[1]
SiT5157AC - FK - 33
E
0 - 98.123456
T
SiT5157AC - FK - 33
V
T
-
98.123456
T
SiT5157AC - FKG33
J R -
98.123456
T
TCXO
VCTCXO
DCTCXO
Notes:
1. “-“ corresponds to the default rise/fall time for LVCMOS output as specified in Table 1 (Electrical Characteristics). Contact SiTime for other rise/fall time
options for best EMI or driving multiple loads. For differential outputs, contact SiTime.
2. Bulk is available for sampling only.
SiT5157
60 MHz to 220 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Rev 1.05
Page 3 of 34
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TABLE OF CONTENTS
Description ................................................................................................................................................................................... 1
Features ....................................................................................................................................................................................... 1
Applications ................................................................................................................................................................................. 1
Block Diagram ............................................................................................................................................................................. 1
5.0 mm x 3.2 mm Package Pinout ............................................................................................................................................... 1
Ordering Information .................................................................................................................................................................... 2
Electrical Characteristics .............................................................................................................................................................. 4
Device Configurations and Pin-outs ............................................................................................................................................. 8
Pin-out Top Views................................................................................................................................................................. 8
Test Circuit Diagrams for LVCMOS Outputs ................................................................................................................................ 9
Waveforms ................................................................................................................................................................................. 10
Timing Diagrams ........................................................................................................................................................................ 10
Typical Performance Plots ......................................................................................................................................................... 11
Architecture Overview ................................................................................................................................................................ 12
Frequency Stability ............................................................................................................................................................. 12
Output Frequency and Format ............................................................................................................................................ 12
Output Frequency Tuning ................................................................................................................................................... 12
Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 13
Device Configurations ................................................................................................................................................................ 13
TCXO Configuration ........................................................................................................................................................... 13
VCTCXO Configuration ...................................................................................................................................................... 14
DCTCXO Configuration ...................................................................................................................................................... 15
VCTCXO-Specific Design Considerations ................................................................................................................................. 16
Linearity .............................................................................................................................................................................. 16
Control Voltage Bandwidth ................................................................................................................................................. 16
FV Characteristic Slope KV ................................................................................................................................................. 16
Pull Range, Absolute Pull Range ........................................................................................................................................ 17
DCTCXO-Specific Design Considerations ................................................................................................................................. 18
Pull Range and Absolute Pull Range .................................................................................................................................. 18
Output Frequency ............................................................................................................................................................... 19
I2C Control Registers .......................................................................................................................................................... 21
Register Descriptions .......................................................................................................................................................... 21
Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 21
Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) ......................................... 22
Register Address: 0x02. DIGITAL PULL RANGE CONTROL[15] ........................................................................................ 23
Serial Interface Configuration Description .......................................................................................................................... 24
Serial Signal Format ........................................................................................................................................................... 24
Parallel Signal Format ........................................................................................................................................................ 25
Parallel Data Format ........................................................................................................................................................... 25
I2C Timing Specification ...................................................................................................................................................... 27
I2C Device Address Modes ................................................................................................................................................. 28
Schematic Example ............................................................................................................................................................ 29
Dimensions and Patterns ........................................................................................................................................................... 30
Layout Guidelines ...................................................................................................................................................................... 31
Manufacturing Guidelines .......................................................................................................................................................... 31
Additional Information ................................................................................................................................................................ 32
Revision History ......................................................................................................................................................................... 33
SiT5157
60 MHz to 220 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Rev 1.05
Page 4 of 34
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Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and 3.3 V Vdd.
Table 1. Output Characteristics
Parameters
Symbol
Min.
Unit
Condition
Frequency Coverage
Nominal Output Frequency Range F_nom
60.000001
MHz
208 – 220 MHz
Temperature Range
Operating Temperature Range T_use
-20
°C
Extended Commercial, ambient temperature
-40
°C
Industrial, ambient temperature
-40 – +105 °C Extended Industrial, ambient temperature
Frequency Stability
Frequency Stability over
Temperature
F_stab
–
ppm
Referenced to (max frequency + min frequency)/2 over the
rated temperature range. Vc=Vdd/2 for VCTCXO
–
ppm
–
ppm
Initial Tolerance
F_init
–
ppm
Initial frequency at 25°C at 48 hours after 2 reflows
Supply Voltage Sensitivity F_Vdd
–
ppb
±0.5 ppm F_stab, Vdd ±5%
–
ppb
±1.0 ppm F_stab, Vdd ±5%
–
ppb
±2.5 ppm F_stab, Vdd ±5%
Output Load Sensitivity F_load
–
ppb
±0.5 ppm F_stab. LVCMOS output, 15 pF ±10%
–
ppb
±1.0 ppm F_stab. LVCMOS output, 15 pF ±10%
–
ppb
±2.5 ppm F_stab. LVCMOS output, 15 pF ±10%
Frequency vs. Temperature Slope ΔF/ΔT
–
ppb/°C
±0.5 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C
–
ppb/°C
±1.0 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C
–
ppb/°C
±2.5 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C
Dynamic Frequency Change during
Temperature Ramp
F_dynamic
–
ppb/s
±0.5 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C
– ±0.21 ±0.42 ppb/s ±1.0 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C
–
ppb/s
±2.5 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C
One-Year Aging F_1y – ±1 – ppm At 25°C, after 2-days of continued operation. Aging is
measured with respect to day 3
20-Year Aging F_20y – ±2 – ppm At 25°C, after 2-days of continued operation. Aging is
measured with respect to day 3
LVCMOS Output Characteristics
Duty Cycle
DC
45
%
60 to 150 MHz
42
%
150 to 189 MHz, 200 to 220 MHz
Rise/Fall Time
Tr, Tf
0.8
ns
10% - 90% Vdd
Output Voltage High
VOH
90%
Vdd
IOH = +3 mA
Output Voltage Low
VOL
–
Vdd
IOL = -3 mA
Output Impedance Z_out_c
–
Ohms
Impedance looking into output buffer, Vdd = 3.3 V
–
Ohms
Impedance looking into output buffer, Vdd = 3.0 V
–
Ohms
Impedance looking into output buffer, Vdd = 2.8 V
– 19 – Ohms
Impedance looking into output buffer, Vdd = 2.5 V
Start-up Characteristics
Start-up Time T_start – 2.5 3.5 ms Time to first pulse, measured from the time Vdd reaches
90% of its final value. Vdd ramp time = 100 µs from 0 V to
Vdd
Output Enable Time
T_oe
–
ns
See Timing Diagrams section below.
Time to Rated Frequency Stability T_stability – 5 45 ms Time to first accurate pulse within rated stability, measured
from the time Vdd reaches 90% of its final value. Vdd
ramp time = 100 µs
SiT5157
60 MHz to 220 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Rev 1.05
Page 5 of 34
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Table 2. DC Characteristics
Parameters
Symbol
Unit
Condition
Supply Voltage
Supply Voltage
Vdd
V
Contact SiTime for 2.25 V to 3.63 V continuous supply
voltage support
V
V
V
Current Consumption
Current Consumption
Idd
– 48 62
mA F_nom = 100 MHz, No Load, TCXO and DCTCXO modes
66
mA
F_nom = 100 MHz, No Load, VCTCXO mode
OE Disable Current
I_od
52
mA
OE = GND, output weakly pulled down. TCXO, DCTCXO
56
mA
OE = GND, output weakly pulled down. VCTCXO mode
Table 3. Input Characteristics
Parameters
Symbol
Unit
Condition
Input Characteristics – OE Pin
Input Impedance
Z_in
kΩ
Internal pull up to Vdd
Input High Voltage
VIH 70% – – Vdd
Input Low Voltage
VIL
Vdd
Frequency Tuning Range – Voltage Control or I2C mode
Pull Range PR
±6.25 – – ppm VCTCXO mode; contact SiTime for ±12.5 and ±25 ppm
±6.25
±10
±12.5
±25
±50
±80
±100
±125
±150
±200
±400
±600
±800
±1200
±1600
– – ppm DCTCXO mode
Absolute Pull Range[3]
APR
ppm
±0.5 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
±2.25 – – ppm
±1.0 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
ppm
±2.5 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
Upper Control Voltage
VC_U 90% – – Vdd
VCTCXO mode
Lower Control Voltage
VC_L
Vdd
VCTCXO mode
Control Voltage Input Impedance
VC_z 8 – – MΩ
VCTCXO mode
Control Voltage Input Bandwidth
VC_bw
kHz
VCTCXO mode; contact SiTime for other bandwidth options
Frequency Control Polarity
F_pol Positive VCTCXO mode
Pull Range Linearity
PR_lin
%
VCTCXO mode
I
2
C Interface Characteristics, 200 Ohm, 550 pF (Max I
2
C Bus Load)
Bus Speed F_I2C
≤ 400
kHz
-40 to 105°C
≤ 1000
kHz
-40 to 85°C
Input Voltage Low
VIL_I2C
Vdd
DCTCXO mode
Input Voltage High
VIH_I2C
Vdd
DCTCXO mode
Output Voltage Low
VOL_I2C
V
DCTCXO mode
Input Leakage current IL 0.5 – 24 µA 0.1 VDD< VOUT < 0.9 VDD. Includes typical leakage current
from 200 kΩ pull resister to VDD; DCTCXO mode
Input Capacitance
CIN – – 5 pF DCTCXO mode
Note:
3. APR = PR – initial tolerance – 20-year aging – frequency stability over temperature. Refer to Table 14 for APR with respect to other pull range options.
SiT5157
60 MHz to 220 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Rev 1.05
Page 6 of 34
www.sitime.com
Table 4. Jitter & Phase Noise, -40°C to 85°C
Parameters
Symbol
Unit
Condition
Jitter
RMS Phase Jitter (random)
T_phj
ps
F_nom = 100 MHz, Integration bandwidth = 12 kHz to 20 MHz
RMS Period Jitter
T_jitt_per
ps
F_nom = 100 MHz, population 10 k
Peak Cycle-to-Cycle Jitter T_jitt_cc – 6.6 13.4 ps F_nom = 100 MHz, population 1 k, measured as absolute
value
Phase Noise
1 Hz offset
– -61 -54 dBc/Hz
F_nom = 100 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
10 Hz offset
dBc/Hz
100 Hz offset
dBc/Hz
1 kHz offset
– -128 -124 dBc/Hz
10 kHz offset
dBc/Hz
100 kHz offset
dBc/Hz
1 MHz offset
– -150 -146 dBc/Hz
5 MHz offset
– -157 -151 dBc/Hz
10 MHz offset
dBc/Hz
20 MHz offset
– -159 -152 dBc/Hz
Spurious
T_spur – -91 -86 dBc F_nom = 100 MHz, 1 kHz to 40 MHz offsets
Table 5. Jitter & Phase Noise, -40°C to 105°C
Parameters
Symbol
Unit
Condition
Jitter
RMS Phase Jitter (random)
T_phj
ps
F_nom = 100 MHz, Integration bandwidth = 12 kHz to 20 MHz
RMS Period Jitter
T_jitt_per
ps
F_nom = 100 MHz, population 10 k
Peak Cycle-to-Cycle Jitter T_jitt_cc – 6.6 13.4 ps F_nom = 100 MHz, population 1 k, measured as absolute
value
Phase Noise
1 Hz offset
– -61 -54 dBc/Hz
F_nom = 100 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
10 Hz offset
– -89 -83 dBc/Hz
100 Hz offset
dBc/Hz
1 kHz offset
dBc/Hz
10 kHz offset
– -133 -131 dBc/Hz
100 kHz offset
– -133 -130 dBc/Hz
1 MHz offset
dBc/Hz
5 MHz offset
– -157 -150 dBc/Hz
10 MHz offset
– -157 -150 dBc/Hz
20 MHz offset
dBc/Hz
Spurious
T_spur – -91 -85 dBc F_nom = 100 MHz, 1 kHz to 40 MHz offsets
SiT5157
60 MHz to 220 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Rev 1.05
Page 7 of 34
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Table 6. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part.
Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter Test Conditions Value Unit
Storage Temperature
-65 to 125 °C
Continuous Power Supply Voltage Range (Vdd) -0.5 to 4 V
Human Body Model (HBM) ESD Protection JESD22-A114 2000 V
Soldering Temperature (follow standard Pb-free soldering guidelines)
260
°C
Junction Temperature
[4] 130 °C
Input Voltage, Maximum
Any input pin Vdd + 0.3 V
Input Voltage, Minimum Any input pin -0.3 V
Note:
4. Exceeding this temperature for an extended period of time may damage the device.
Table 7. Thermal Considerations[5]
Package θJA[6] (°C/W) θJC, Bottom (°C/W)
Ceramic 5.0 mm x 3.2 mm 54 15
Note:
5. Measured in still air. Refer to JESD51 for θJA and θJC definitions.
6. Devices soldered on a JESD51 2s2p compliant board.
Table 8. Maximum Operating Junction Temperature[7]
Max Operating Temperature (ambient) Maximum Operating Junction Temperature
70°C
80°C
85°C
95°C
105°C 115°C
Note:
7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 9. Environmental Compliance
Parameter
Test Conditions
Value
Unit
Mechanical Shock Resistance MIL-STD-883F, Method 2002 30000 g
Mechanical Vibration Resistance MIL-STD-883F, Method 2007 70 g
Temperature Cycle
JESD22, Method A104
–
–
Solderability MIL-STD-883F, Method 2003 – –
Moisture Sensitivity Level MSL1 @260°C – –
SiT5157
60 MHz to 220 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Rev 1.05
Page 8 of 34
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Device Configurations and Pin-outs
Table 10. Device Configurations
Configuration Pin 1 Pin 5 I2C Programmable Parameters
TCXO OE/NC NC –
VCTCXO VC NC –
DCTCXO OE/NC A0/NC Frequency Pull Range, Frequency Pull Value, Output Enable control.
Pin-out Top Views
OE/NC
1
2
3
4 5 6
7
8
910
NC
NC
GND
NC
NC
VDD
CLK
NC
NC
Figure 3. TCXO
VC
1
2
3
456
7
8
910
NC
NC
GND
NC
NC
VDD
CLK
NC
NC
Figure 4. VCTCXO
OE / NC
1
2
3
456
7
8
9
10
SCL
NC
GND
NC
NC
VDD
CLK
A0 / NC
SDA
Figure 5. DCTCXO
Table 11. Pin Description
Pin Symbol I/O Internal Pull-up/Pull Down
Resistor Function
1 OE/NC[10]/VC
OE – Input 100 kΩ Pull-Up H[8]: specified frequency output
L: output is high impedance. Only output driver is disabled.
NC – No Connect – H or L or Open: No effect on output frequency or other device functions
VC – Input – Control Voltage in VCTCXO Mode
2 SCL / NC[10]
SCL – Input 200 kΩ Pull-Up I2C serial clock input.
No Connect H or L or Open: No effect on output frequency or other device functions
3 NC[10] No Connect – H or L or Open: No effect on output frequency or other device functions
4 GND Power – Connect to ground
5 A0 / NC[10]
A0 – Input 100 kΩ Pull-Up
Device I2C address when the address selection mode is via the A0 pin.
This pin is NC when the I2C device address is specified in the ordering
code.
A0 Logic Level I2C Address
0 1100010
1 1101010
NC – No Connect – H or L or Open: No effect on output frequency or other device functions.
6 CLK Output – LVCMOS
7 NC[10] No Connect – H or L or Open: No effect on output frequency or other device functions
8 NC[10] No Connect – H or L or Open: No effect on output frequency or other device functions
9 VDD Power – Connect to power supply[9]
10 SDA / NC[10]
SDA – Input/Output 200 kΩ Pull Up I2C Serial Data.
NC – No Connect – H or L or Open: No effect on output frequency or other device functions.
Notes:
8. In OE mode for noisy environments, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use
the NC option.
9. A 0.1 μF capacitor in parallel with a 10 μF capacitor are required between VDD and GND. The 0.1 μF capacitor is recommended to place close to the device,
and place the 10 μF capacitor less than 2 inches away.
10. All NC pins can be left floating and do not need to be soldered down.
SiT5157
60 MHz to 220 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Rev 1.05
Page 9 of 34
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Test Circuit Diagrams for LVCMOS Outputs
9876
1234
510
Power
Supply
VDD Test Point
Vdd
OE Function
CLK
15pF
(including probe
and fixture
capacitance)
10µF
0.1µF
+
-
10µF
0.1µF
+
-
9876
123 4
5
10
Power
Supply
VDD Test Point
Control
Voltage
VC Function
CLK
15pF
(including probe
and fixture
capacitance)
Figure 6. LVCMOS Test Circuit (OE Function)
Figure 7. LVCMOS Test Circuit (VC Function)
9876
1234
5
10
Power
Supply
VDD Test Point
Any state
or floating
NC Function
CLK
15pF
(including probe
and fixture
capacitance)
10µF
0.1µF
+
-
Figure 8. LVCMOS Test Circuit (NC Function)
9 8 7 6
12 3 4
510
Power
Supply
VDD Test Point
Any state
or floating
NC
Function
CLK
SCL
SDA
[11]
15pF
(including probe
and fixture
capacitance)
10µF
0.1µF
+
-
A0/NC
Figure 9. LVCMOS Test Circuit (I2C Control), DCTCXO mode for AC and DC Measurements
Note:
11. SDA is open-drain and may require pull-up resistor if not present in I2C test setup.
SiT5157
60 MHz to 220 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Rev 1.05
Page 10 of 34
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Waveforms
90 % Vdd
50 % Vdd
10 % Vdd
tr tf
High Pulse
(TH)
Low Pulse
(TL)
Period
Figure 10. LVCMOS Waveform Diagram[12]
Note:
12. Duty Cycle is computed as Duty Cycle = TH/Period.
Timing Diagrams
90% Vdd Vdd
Vdd Pin
Voltage
CLK Output
T_start
T_start: Time to start from power-off
HZ
Figure 11. Startup Timing
50% Vdd
Vdd
OE Voltage
CLK Output
T_oe
T_oe: Time to re-enable the clock output
HZ
Figure 12. OE Enable Timing (OE Mode Only)
SiT5157
60 MHz to 220 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Rev 1.05
Page 11 of 34
www.sitime.com
Typical Performance Plots
Figure 13. Duty Cycle (LVCMOS)
Figure 14. IDD DCTCXO (LVCMOS)
Figure 15. IDD TCXO (LVCMOS)
Figure 16. IDD VCTCXO (LVCMOS)
Figure 17. RMS Phase Jitter, DCTCXO, TCXO (LVCMOS)
Figure 18. RMS Period Jitter (LVCMOS)
Figure 19. RMS Phase Jitter, VCTCXO (LVCMOS)
Figure 20. DCTCXO frequency pull characteristic
45
47
49
51
53
55
70 90 110 130 150 170 190 210
Duty cycle (%)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
40
42
44
46
48
50
52
54
56
58
70 90 110 130 150 170 190 210
Current consumption (mA)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
40
42
44
46
48
50
52
54
56
58
70 90 110 130 150 170 190 210
Current consumption (mA)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
46
48
50
52
54
56
58
60
70 90 110 130 150 170 190 210
Current consumption (mA)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
0
100
200
300
400
500
70 90 110 130 150 170 190 210
Phase Jitter (fs RMS
)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
0,50
0,70
0,90
1,10
1,30
1,50
1,70
1,90
70 90 110 130 150 170 190 210
Period Jitter (ps RMS)
Frequency (MHz)
2.5 V 3.3 V
0
100
200
300
400
500
70 120 170 220
Phase Jitter (fs RMS
)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
-6,25
-5
-3,75
-2,5
-1,25
0
1,25
2,5
3,75
5
6,25
-6,25 -5 -3,75 -2,5 -1,25 01,25 2,5 3,75 56,25
Frequency deviation (ppm)
DCTCXO pull (ppm)
SiT5157
60 MHz to 220 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Rev 1.05
Page 12 of 34
www.sitime.com
Architecture Overview
Based on SiTime’s innovative Elite Platform™, the SiT5157
delivers exceptional dynamic performance, i.e. resilience to
environmental stressors such as shock, vibration, and fast
temperature transients. Underpinning the Elite platform are
SiTime’s unique DualMEMS™ temperature sensing
architecture and TurboCompensation™ technologies.
DualMEMS is a noiseless temperature compensation
scheme. It consists of two MEMS resonators fabricated on
the same die substrate. The TempFlat™ MEMS resonator is
designed with a flat frequency characteristic over
temperature whereas the temperature sensing resonator is
by design sensitive to temperature changes. The ratio of
frequencies between these two resonators provides an
accurate reading of the resonator temperature with 20 µK
resolution.
By placing the two MEMS resonators on the same die, this
temperature sensing scheme eliminates any thermal lag and
gradients between resonator and temperature sensor,
thereby overcoming an inherent weakness of legacy quartz
TCXOs.
The DualMEMS temperature sensor drives a state-of-the-
art CMOS temperature compensation circuit. The
TurboCompensation design, with >100 Hz compensation
bandwidth, achieves a dynamic frequency stability that is far
superior to any quartz TCXO. The digital temperature
compensation enables additional optimization of frequency
stability and frequency slope over temperature within any
chosen temperature range for a given system design.
The Elite platform also incorporates a high resolution, low
noise frequency synthesizer along with the industry standard
I2C bus. This unique combination enables system designers
to digitally control the output frequency in steps as low as 5
ppt and over a wide range up to ±3200 ppm.
For more information regarding the Elite platform and its
benefits please visit:
SiTime's breakthroughs section
TechPaper: DualMEMS Temperature Sensing Technology
TechPaper: DualMEMS Resonator TDC
Functional Overview
The SiT5157 is designed for maximum flexibility with an
array of factory programmable options, enabling system
designers to configure this precision device for optimal
performance in a given application.
Frequency Stability
The SiT5157 comes in three factory-trimmed stability
grades.
Table 12. Stability Grades vs. Ordering Codes
Frequency Stability Over Temperature
Ordering Code
±0.5 ppm
K
±1.0 ppm
A
±2.5 ppm
D
Output Frequency and Format
The SiT5157 can be factory programmed for an output
frequency without sacrificing lead time or incurring an
upfront customization cost typically associated with custom-
frequency quartz TCXOs.
Output Frequency Tuning
In addition to the non-pullable TCXO, the SiT5157 can also
support output frequency tuning through either an analog
control voltage (VCTCXO), or I2C interface (DCTCXO). The
I2C interface enables 16 factory programmed pull-range
options from ±6.25 ppm to ±3200 ppm. The pull range can
also be reprogrammed via I2C to any supported pull-range
value.
Refer to Device Configuration section for details.
SiT5157
60 MHz to 220 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Rev 1.05
Page 13 of 34
www.sitime.com
Pin 1 Configuration (OE, VC, or NC)
Pin 1 of the SiT5157 can be factory programmed to support
three modes: Output Enable (OE), Voltage Control (VC), or
No Connect (NC).
Table 13. Pin Configuration Options
Pin 1 Configuration Operating Mode Output
OE TCXO/DCTCXO Active or High-Z
NC TCXO/DCTCXO Active
VC VCTCXO Active
When pin 1 is configured as OE pin, the device output is
guaranteed to operate in one of the following two states:
Clock output with the frequency specified in the part
number when Pin 1 is pulled to logic high
Hi-Z mode with weak pull down when pin 1 is pulled to
logic low.
When pin 1 is configured as NC, the device is guaranteed to
output the frequency specified in the part number at all times,
regardless of the logic level on pin 1.
In the VCTCXO configuration, the user can fine-tune the
output frequency from the nominal frequency specified in the
part number by varying the pin 1 voltage. The guaranteed
allowable variation of the output frequency is specified as pull
range. A VCTCXO part number must contain a valid pull-
range ordering code.
Device Configurations
The SiT5157 supports 3 device configurations – TCXO,
VCTCXO, and DCTCXO. The TCXO and VCTCXO options
are directly compatible with the quartz TCXO and VCTCXO.
The DCTCXO configuration provides performance
enhancement by eliminating VCTCXO’s sensitivity to control
voltage noise with an I2C digital interface for frequency
tuning.
Figure 21. Block Diagram – TCXO
TCXO Configuration
The TCXO generates a fixed frequency output, as shown in
Figure 21. The frequency is specified by the user in the
frequency field of the device ordering code and then factory
programmed. Other factory programmable options include
supply voltage, and pin 1 functionality (OE or NC).
Refer to the Ordering Information section at the end of the
datasheet for a list of all ordering options.
SiT5157
60 MHz to 220 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Rev 1.05
Page 14 of 34
www.sitime.com
VCTCXO Configuration
A VCTCXO, shown in Figure 22, is a frequency control device
whose output frequency is an approximately linear function of
control voltage applied to the voltage control pin. VCTCXOs
have a number of use cases including the VCO portion of a jitter
attenuation/jitter cleaner PLL Loop.
The SiT5157 achieves a 10x better pull range linearity of <0.5%
via a high-resolution fractional PLL and low-noise precision
analog-to-digital converter. By contrast, quartz-based
VCTCXOs change output frequency by varying the capacitive
load of a crystal resonator using varactor diodes, which results
in linearity of 5% to 105%.
Figure 22. Block Diagram – VCTCXO
Note that the output frequency of the VCTCXO is
proportional to the analog control voltage applied to pin
1. Because this control signal is analog and directly
controls the output frequency, care must be taken to
minimize noise on this pin.
The nominal output frequency is factory programmed
per the customer’s request to 6 digits of precision and
is defined as the output frequency when the control
voltage equals Vdd/2. The maximum output frequency
variation from this nominal value is set by the pull range,
which is also factory programmed to the customer’s
desired value and specified by the ordering code. The
Ordering Information section shows all ordering
options and associated ordering codes.
Refer to Appendix 1 Design Considerations with
VCTCXO for more information on critical VCTCXO
parameters including pull range linearity, absolute pull
range, control voltage bandwidth, and KV.